L2P mapping table storage method and device

Abstract

The invention belongs to the technical field of L2P mapping tables, and provides an L2P mapping table storage method, reading method and device.The L2P mapping table storage method is used for an SSD larger than 16 TB and comprises the steps that the L2P mapping table is split, PA [31: 0] is stored in a storage space with a base address starting from AADDR, and PA [N: 32] is stored in a storage space with a base address starting from BADDR; the PA occupies N bits, N is an integer greater than 32, and the address space of the AADDR and the address space of the BADDR are not overlapped. According to the method, PA [N: 0] is separated into PA [N: 32] and PA [31: 0] for respective storage, and compared with a 8Byte alignment mode, the L2P mapping table storage space is saved.

Description

Technical Field

[0001] The present invention relates to the technical field of L2P mapping tables, and in particular to a method and device for storing an L2P mapping table. Background Art

[0002] Solid State Drive (SSD) is a non-volatile storage device composed of a controller and a storage chip. It is widely used in many fields such as industrial control, video surveillance, network terminals, and navigation due to its advantages such as small size, light weight, low power consumption, and fast read and write speed. The reading and writing of data in the storage chip of the solid state drive depends on physical characteristics. The file system cannot directly access or operate the storage chip. It is necessary to use a cache chip such as SRAM or DRAM to store the L2P mapping table to convert the logical address provided by the file system into the physical address of the storage chip. The L2P (logical address to physical address) table is used for the conversion of the logical address (LA, Logic Address) to the physical address (PA, Physical Address).

[0003] If 4KB is used as the logical page, PA is represented by 4Byte, and the theoretical maximum capacity of the SSD is 2 32 ×4KB = 16TB, the size of the L2P table is about one thousandth of the SSD capacity, about 16GB. If the SSD needs to support 32TB, PA needs to be expanded to 8Byte for simple indexing, then the size of the L2P table is about two thousandths of the SSD capacity, about 64GB. This approach not only wastes capacity, but also the storage medium for buffering L2P expression is DDR. In the case of full buffering, the storage of the L2P table alone requires 64GB of capacity, which greatly increases the cost. Summary of the invention

[0004] In view of the defects in the prior art, the present invention provides a L2P mapping table storage method, a reading method and a device to solve the problem that the current L2P mapping table is stored in an integrated manner, resulting in a waste of capacity.

[0005] In a first aspect, the present invention provides an L2P mapping table storage method for an SSD larger than 16 TB, comprising: The L2P mapping table is split, where PA[31:0] is stored in the storage space starting with the base address A_ADDR, and PA[N:32] is stored in the storage space starting with the base address B_ADDR; PA occupies N bits, N is an integer greater than 32, and the address spaces of A_ADDR and B_ADDR do not overlap.

[0006] It can be seen from the above technical solution that the L2P mapping table storage method provided by the present invention divides PA[N:0] into PA[N:32] and PA[31:0] for separate storage, which saves L2P mapping table storage space compared to the 8-Byte alignment method.

[0007] Optionally, every 1K entries constitute a Group, wherein each Group of PA[31:0] occupies 4KB of storage space, and each Group of PA[N:32] occupies (N-32+1)×128B of space.

[0008] Optionally, PA[31:0] Group is stored in DDR and PA[N:32] Group is stored in Cache.

[0009] It can be seen from the above technical solution that PA[N:32] Group is stored in the Cache to avoid frequent read, modify and write operations on the DDR. Compared with the L2P table entry 8Byte solution, there is almost no performance loss, especially for continuous LA read and write operations.

[0010] Optionally, LA[31:10] is used to index a Group, and LA[9:0] is used to index an entry within a Group.

[0011] Optionally, LA[16:10] in LA[31:10] is used to index the tag SRAM and data SRAM.

[0012] Optionally, when storing the L2P mapping table, the L2P mapping table is written based on the following method, including: Get Group Addr1 and Group Index1, write DDR to overwrite PA[31:0]; use LA[16:10] to index tag SRAM and data SRAM at the same time; LA[16:10] indexes the tag SRAM and data SRAM in one clock cycle to determine whether the cache hits. If a hit occurs, the tag SRAM and data SRAM are written directly, and the valid and dirty bits of the tag SRAM are set to 1, and the writing to L2P is completed; If there is no hit, get Group Addr2 and Group Index2, send the write command to DDR, wait for the completion of writing PA[N:32] to DDR, and when the writing of PA[N:32] is completed, the writing of L2P ends.

[0013] Optionally, the address of PA[N:0] is determined according to the following formula: The Group address where PA[31:0] is located, that is, Group Addr1 = A_ADDR + LA[31:10] × 4K; The Group address where PA[N:32] is located, that is, Group Addr2 = B_ADDR + LA[31:10] × ((N-32+1) × 128); The offset of PA[31:0] within the Group, i.e. Group Index1 = LA[9:0] × 4; The offset of PA[N:32] within the Group, that is, Group Index2=LA[9:0]×(N-32+1) / 8.

[0014] It can be seen from the above technical solution that the address conversion is performed directly based on the above formula, which ensures that the LA address processed by the FTL does not need to be changed and establishes a one-to-one mapping relationship with the PA.

[0015] Optionally, when storing the L2P mapping table, the L2P mapping table is read based on the following method, including: Get Group Addr1 and Group Index1, access DDR to get PA[31:0]; use LA[16:10] to index tag SRAM and data SRAM at the same time; LA[16:10] indexes the tag SRAM and data SRAM in one clock cycle to determine whether the cache hits. If it hits, it directly gets PA[N:32] from data SRAM and ends the L2P read after PA[31:0] returns; If there is no hit, get Group Addr2, send the read command to DDR, wait for the return of PA[31:0]; wait for the return of PA[N:32]Group, and take out PA[N:32]Group from PA[N:32]Group according to Group Index2; At the same time, the tag SRAM is indexed again to determine whether dirty is 1; if dirty is 1, the data SRAM is written to DDR, and the written DDR address is calculated using PA[31:17] in the tag SRAM; if dirty is 0, the PA[33:32] Group retrieved from DDR is directly used to overwrite the original data, and the L2P reading is completed.

[0016] In a second aspect, an embodiment of the present invention provides an L2P mapping table storage device, which implements the steps of any one of the methods in the first aspect when executing a computer program.

[0017] In a third aspect, an embodiment of the present invention provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of any of the above methods when executing the computer program.

[0018] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium having computer program instructions stored thereon, which implement the steps of any of the above methods when executed by a processor.

[0019] By adopting the above technical solution, the present application has the following beneficial effects: The present invention provides an L2P mapping table storage method, which divides PA[N:0] into PA[N:32] and PA[31:0] for separate storage, thereby saving L2P mapping table storage space compared to the 8-Byte alignment method. The present invention ensures that the LA address processed by the FTL does not need to be changed through address conversion, and establishes a one-to-one mapping relationship with the PA; The present invention uses PA[N:32] Group Cache to avoid frequent read, modify and write operations on DDR. Compared with the current solution of using 8 Byte for L2P entries, there is almost no performance loss, especially for continuous LA read and write operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for the specific embodiments or the description of the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn according to the actual scale.

[0021] Figure 1 A schematic diagram showing the current storage of the L2P mapping table according to the integrated storage method; Figure 2 A schematic diagram showing a method for storing an L2P mapping table according to an embodiment of the present invention is shown; Figure 3 A schematic diagram showing LA[31:0] indexing PA[31:0] provided by an embodiment of the present invention is shown; Figure 4 A schematic diagram of the PA[33:32] Group Cache provided by an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0022] The following embodiments of the technical solution of the present invention are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and are therefore only used as examples, and cannot be used to limit the protection scope of the present invention. It should be noted that, unless otherwise specified, the technical terms or scientific terms used in this application should have the common meanings understood by those skilled in the art to which the present invention belongs.

[0023] This embodiment specifically describes the principle with a logical page size of 4KB, PA 34bit, LA 32bit, and a DDR full buffer solution. Figure 1 At present, the easiest way to store the L2P table is to store it sequentially, and each entry in the L2P table occupies 8 bytes. Figure 1 As shown in the figure, the advantage of this method is that there is a natural one-to-one correspondence between LA and DDR address. By selecting some bits of LA and shifting 3 bits to the left, the DDR address can be obtained, thereby obtaining the PA value stored in the L2P table entry. The disadvantage of this method is also obvious. Each L2P table entry wastes 30 bits of storage space.

[0024] Based on this, in one embodiment, a L2P mapping table storage method is provided, which is applicable to an SSD larger than 16 TB, including: The L2P mapping table is split, where PA[31:0] is stored in the storage space starting with the base address A_ADDR, and PA[N:32] is stored in the storage space starting with the base address B_ADDR; PA occupies N bits, N is an integer greater than 32, and the address spaces of A_ADDR and B_ADDR do not overlap.

[0025] Specifically, every 1K table entries constitute a Group, wherein each Group of PA[31:0] occupies 4KB of storage space, and each Group of PA[N:32] occupies (N-32+1)×128B of space, so that the L2P mapping table can be managed hierarchically.

[0026] It should be noted that those skilled in the art can understand that PA[31:0] represents bit31, bit30, ..., bit0 of PA, i.e., bit31, bit30, ..., bit0 of PA. PA[N:32] represents bitN, bitN-1, ..., bit32 of PA, i.e., bitN, bitN-1, ..., bit32 of PA. LA[31:0] etc. will not be described in detail below.

[0027] The solution proposed in this embodiment is to store the L2P mapping table separately. Figure 2A schematic diagram showing separate storage of PA[33:0] is shown. Figure 2 PA[31:0] and PA[33:32] are stored separately. Figure 2 In (a), each PA[31:0] occupies 4 bytes, and each Group includes 1K entries, so the size of the PA[31:0] Group is 4KB; Figure 2 In (b), the PA[33:32]Group size is 256B.

[0028] like Figure 3 As shown, when indexing, some bits of LA are extracted as offsets, the group addresses of PA[31:0] and PA[N:32] are first obtained, and then the offsets of PA[31:0] and PA[N:32] within the group are obtained.

[0029] LA[31:10] is used to index the Group, and LA[9:0] is used to index the table items within the Group. The address translation can be performed through the AT (Address Translate) module. The address of PA[N:0] is determined according to the following formula: The Group address where PA[31:0] is located, that is, Group Addr1 = A_ADDR + LA[31:10] × 4K; The Group address where PA[N:32] is located, that is, Group Addr2 = B_ADDR + LA[31:10] × ((N-32+1) × 128); The offset of PA[31:0] within the Group, i.e. Group Index1 = LA[9:0] × 4; The offset of PA[N:32] within the Group, that is, Group Index2=LA[9:0]×(N-32+1) / 8.

[0030] This solves the problem of access from LA to PA. For SSDs larger than 16TB, although storage capacity is saved, when accessing L2P, the access to PA[N:32] is increased, which increases the access latency of L2P and reduces SSD efficiency. The following describes how to reduce the access latency of PA[N:32].

[0031] Taking PA[33:0] as an example, since the PA[33:32] Group occupies a small space of only 256B, it is convenient for cache storage. That is, the PA[31:0] Group can be stored in DDR, and the PA[N:32] Group can be stored in the cache. Through the characteristic of 1 clock cycle delay of SRAM, the access efficiency can be improved and the impact of accessing PA[N:32] can be reduced; thus, a 32KB cache can buffer 128 PA[33:32] Groups, that is, 128K table entries, which can greatly improve the hit rate.

[0032] In one embodiment, when the logical page size is 4KB, PA is 34 bits, and LA is 32 bits, the cache can use 32KB to buffer 128 PA[33:32] Groups, such as Figure 4 shown.

[0033] The cache structure consists of tag SRAM and data SRAM. The tag stores the LA bit, Valid bit and Dirty bit; the data stores the PA[N:32] group.

[0034] Specifically, LA[16:10] in LA[31:10] is used to index the tag SRAM and the data SRAM.

[0035] Whenever L2P is accessed, the cache is directly indexed while sending an access command to DDR. Once the cache hits, the latency caused by accessing PA[N:32] can be saved, improving the access efficiency of L2P. If the cache does not hit, it is necessary to obtain PA[N:32] from DDR and fill it into the cache. The size of the cache can be adjusted according to the size of the PA[N:32] group to achieve a balance of PPA (performance, power, area).

[0036] In one embodiment, when storing the L2P mapping table, the L2P mapping table is written based on the following method, which specifically includes the following steps: S101. When the FTL (Flash Translation Layer) obtains Group Addr1 and Group Index1, it writes DDR to overwrite PA[31:0]; at the same time, it uses LA[16:10] to index the tag SRAM and data SRAM.

[0037] S102.LA[16:10] indexes the tag SRAM and data SRAM within 1 clock cycle to determine whether the cache hits.

[0038] Specifically, after the index tag SRAM and data SRAM are completed, the tag value is read out and then compared with the high bit of LCA. If they are equal, it is a hit, otherwise it is a miss.

[0039] S103a. If a hit occurs, directly write to the tag SRAM and data SRAM, and set the valid and dirty bits of the tag SRAM to 1, and write to L2P ends; S103b. If there is no hit, get Group Addr2 and Group Index2, directly send the write command to DDR, wait for the completion of writing PA[N:32] to DDR, and when the writing of PA[N:32] is completed, the writing of L2P is finished.

[0040] In one embodiment, when the L2P mapping table is stored, the L2P mapping table is read based on the following method, which specifically includes the following steps: S201. When the FTL (Flash Translation Layer) obtains Group Addr1 and GroupIndex1, it accesses DDR to obtain PA[31:0]; at the same time, it uses LA[16:10] to index the tag SRAM and data SRAM.

[0041] S202.LA[16:10] indexes tag SRAM and data SRAM in 1 clock cycle to determine whether the cache hits. S203a. If hit, directly get PA[N:32] from data SRAM, and finish reading L2P after PA[31:0] returns; S203b. If there is no hit, get Group Addr2, send the read command to DDR, wait for the return of PA[31:0]; and wait for the new PA[N:32]Group to return, take out PA[N:32]Group from PA[N:32]Group according to Group Index2; at the same time, index the tag SRAM again to determine whether dirty is 1; if dirty is 1, write the data SRAM to DDR, and the written DDR address is calculated using PA[31:17] in the tag SRAM; if dirty is 0, directly overwrite the original data with PA[33:32]Group retrieved from DDR, and the L2P reading is completed.

[0042] In one embodiment, an L2P mapping table storage device is provided for use in an SSD larger than 16 TB, and is used to implement the method steps provided in the above embodiments when executing a computer program.

[0043] The L2P mapping table storage device provided in the embodiment of the present application and the above-mentioned L2P mapping table storage method adopt the same inventive concept and can achieve the same beneficial effects, which will not be described in detail here.

[0044] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), tape, floppy disk, flash memory or optical memory, etc. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0045] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0046] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A method for storing an L2P mapping table, characterized in that: For SSDs larger than 16TB, including: The L2P mapping table is split, where PA[31:0] is stored in the storage space starting with the base address A_ADDR, and PA[N:32] is stored in the storage space starting with the base address B_ADDR; PA occupies N bits, N is an integer greater than 32, and the address spaces of A_ADDR and B_ADDR do not overlap.

2. The method according to claim 1, characterized in that Every 1K entries is a group, where each group of PA[31:0] occupies 4KB of storage space, and each group of PA[N:32] occupies (N-32+1)×128B of space.

3. The method according to claim 2, characterized in that PA[31:0] Group is stored in DDR, and PA[N:32] Group is stored in Cache.

4. The method according to claim 3, characterized in that LA[31:10] is used to index a group, and LA[9:0] is used to index an entry within a group.

5. The method according to claim 4, characterized in that LA[16:10] in LA[31:10] is used to index tag SRAM and data SRAM.

6. The method according to claim 5, characterized in that When storing the L2P mapping table, the L2P mapping table is written based on the following methods, including: Get Group Addr1 and Group Index1, write DDR to overwrite PA[31:0]; use LA[16:10] to index tag SRAM and data SRAM at the same time; LA[16:10] indexes the tag SRAM and data SRAM in one clock cycle to determine whether the cache hits. If a hit occurs, the tag SRAM and data SRAM are written directly, and the valid and dirty bits of the tag SRAM are set to 1, and the writing to L2P is completed; If there is no hit, get Group Addr2 and Group Index2, send the write command to DDR, wait for the completion of writing PA[N:32] to DDR, and when the writing of PA[N:32] is completed, the writing of L2P ends.

7. The method according to claim 6, characterized in that The address of PA[N:0] is determined according to the following formula: The Group address where PA[31:0] is located, that is, Group Addr1 = A_ADDR + LA[31:10] × 4K; The Group address where PA[N:32] is located, that is, Group Addr2 = B_ADDR + LA[31:10] × ((N-32+1) × 128); The offset of PA[31:0] within the Group, i.e. Group Index1 = LA[9:0] × 4; The offset of PA[N:32] within the Group, that is, Group Index2=LA[9:0]×(N-32+1) / 8.

8. The method according to claim 6, characterized in that When the L2P mapping table is stored, the L2P mapping table is read based on the following methods, including: Get Group Addr1 and Group Index1, access DDR to get PA[31:0]; use LA[16:10] to index tag SRAM and data SRAM at the same time; LA[16:10] indexes the tag SRAM and data SRAM in one clock cycle to determine whether the cache hits. If it hits, it directly gets PA[N:32] from data SRAM and ends the L2P read after PA[31:0] returns; If there is no hit, get Group Addr2, send the read command to DDR, wait for the return of PA[31:0]; wait for the return of PA[N:32] Group, and take out PA[N:32] Group from PA[N:32] Group according to Group Index2; At the same time, the tag SRAM is indexed again to determine whether dirty is 1; if dirty is 1, the data SRAM is written to DDR, and the written DDR address is calculated using PA[31:17] in the tag SRAM; if dirty is 0, the PA[33:32] Group retrieved from DDR is directly used to overwrite the original data, and the L2P read is completed.

9. An L2P mapping table storage device, characterized in that: For use with an SSD larger than 16 TB, the computer program is executed to implement the steps of the method according to any one of claims 1 to 8.

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