Data caching method, device, electronic device, storage medium and program

Abstract

The embodiment of the present invention discloses a data caching method, device, electronic device, storage medium and program, which are applied to a cache component, and the cache component is configured with a target register group, wherein the method includes: receiving a data access request sent by a target processor; determining the type of the data access request according to the configuration information of the target register group; replacing the current cached data with the target data requested to be accessed by the data access request according to the type of the data access request and the configuration information of the target register group; wherein the target register group is configured with multiple registers, each of which is used to store the configuration information of a persistent data address window. The technical solution of the embodiment of the present invention realizes a highly fair data caching strategy that supports data persistence, enriches the data caching function, and reduces the requirements for software and hardware resources in the data caching process.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of data processing technology, and in particular, to a data caching method, device, electronic device, storage medium and program. Background Art

[0002] As a key component in modern computer storage architecture, cache plays a vital role in improving storage performance.

[0003] When the processor tries to access the cache, if the required data is already in the cache, it can be directly obtained from the cache without further access to the next level of storage media, thereby reducing access latency and increasing access bandwidth. However, when the requested data is not in the cache and the cache space is full and cannot store new data, data replacement is required. At this time, the Least Recently Used (LRU) or Pseudo Least Recently Used (PLRU) algorithm is usually used to determine the data to be replaced or to use extended instructions to indicate to the cache the data that needs to be persistently stored.

[0004] In the process of implementing the present invention, the inventors found that the prior art has the following defects: (1) When using the LRU algorithm for data replacement, there is a lack of consideration for data priority, which is difficult to meet the needs in the scenario where the user needs to be able to retain some process data for a long time; (2) The data that needs to be persistently stored is identified by extended instructions, which requires the processor to be able to support extended instructions, which not only limits the choice of processors, but also increases the requirements for software and hardware configuration. Summary of the invention

[0005] The embodiments of the present invention provide a data caching method, device, electronic device, storage medium and program, which implement a highly fair data caching strategy that supports data persistence, enrich the data caching function, and reduce the requirements for software and hardware resources during the data caching process.

[0006] According to one aspect of the present invention, there is provided a data caching method, which is applied to a cache unit, wherein the cache unit is configured with a target register group, and the method comprises:

[0007] receiving a data access request sent by a target processor;

[0008] Determining the type of the data access request according to the configuration information of the target register group;

[0009] Replace the current cache data with the target data requested by the data access request according to the type of the data access request and the configuration information of the target register group;

[0010] The target register group is configured with a plurality of registers, and each of the registers is used to store configuration information of a persistent data address window.

[0011] According to another aspect of the present invention, a cache unit is provided, comprising a data buffer and a target register group; wherein:

[0012] The data buffer includes a first data buffer and a second data buffer; the first data buffer is used to store tag data; the second data buffer is used to store cache data;

[0013] The target register group is configured with a plurality of registers, each of which is used to store configuration information of a persistent data address window;

[0014] The cache component is used for:

[0015] receiving a data access request sent by a target processor;

[0016] Determining the type of the data access request according to the configuration information of the target register group;

[0017] The target data requested by the data access request replaces the current cache data according to the type of the data access request and the configuration information of the target register group.

[0018] According to another aspect of the present invention, there is provided a data cache device, which is configured in a cache unit, wherein the cache unit is configured with a target register group, and the device comprises:

[0019] A data access request receiving module, used for receiving a data access request sent by a target processor;

[0020] A request type determination module, used to determine the type of the data access request according to the configuration information of the target register group;

[0021] A target data cache module, used for replacing the current cached data with the target data requested by the data access request according to the type of the data access request and the configuration information of the target register group;

[0022] The target register group is configured with a plurality of registers, and each of the registers is used to store configuration information of a persistent data address window.

[0023] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0024] at least one processor; and

[0025] A memory communicatively connected to the at least one processor; the memory is communicatively connected to a cache component, wherein:

[0026] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the data caching method described in any embodiment of the present invention.

[0027] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the data caching method described in any embodiment of the present invention when executed.

[0028] According to another aspect of the present invention, a computer program product is provided, including a computer program. When the computer program is executed by a processor, the data caching method described in any embodiment of the present invention is implemented.

[0029] The technical solution of this embodiment receives a data access request sent by a target processor and determines the type of the data access request according to the configuration information of the target register group. Further, the target data requested by the data access request can be replaced with the current cache data according to the type of the data access request and the configuration information of the target register group, solving the problem that the LRU algorithm in the prior art cannot support data persistence caching, realizing a highly fair data caching strategy that supports data persistence, enriching the data caching function, and reducing the requirements for software and hardware resources in the data caching process.

[0030] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 is a flow chart of a data caching method provided by Embodiment 1 of the present invention;

[0033] Figure 2 is a flow chart of a data caching method provided by Embodiment 2 of the present invention;

[0034] Figure 3is a flow chart of a data caching method provided by Embodiment 3 of the present invention;

[0035] Figure 4 is a flow chart of a data caching method provided by Embodiment 4 of the present invention;

[0036] Figure 5 is a schematic diagram of a cache component provided in Embodiment 5 of the present invention;

[0037] Figure 6 is a flow chart of a data caching method of a cache component provided by Embodiment 5 of the present invention;

[0038] Figure 7 is a schematic diagram of a data cache device provided by Embodiment 6 of the present invention;

[0039] Figure 8 A schematic diagram of the structure of an electronic device provided in Embodiment 7 of the present invention. DETAILED DESCRIPTION

[0040] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0041] It should be noted that the terms "target", "first" and "second" in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0042] Embodiment 1

[0043] Figure 1This is a flow chart of a data caching method provided in the first embodiment of the present invention. This embodiment is applicable to the case where data persistent caching is performed in a cache component. The method can be performed by a data caching device, which can be implemented by software and / or hardware and can generally be integrated in an electronic device. The electronic device can be a terminal device or a server device. As long as the data caching method can be performed, the embodiment of the present invention does not limit the specific device type of the electronic device. Accordingly, Figure 1 As shown, the method includes the following operations:

[0044] S110. Receive a data access request sent by a target processor.

[0045] The target processor may be a processor that sends a data access request, and the data access request may be a request for accessing data initiated by the target processor to the cache component.

[0046] In the embodiment of the present invention, the cache component may receive a data access request sent by a target processor so as to perform a replacement operation of cache data according to the data access request.

[0047] S120: Determine the type of the data access request according to the configuration information of the target register group.

[0048] Among them, the target register group can be a set of registers configured in the cache unit. The configuration information of the target register group can be data used to set and describe the characteristics, functions, initial state and working mode of the target register group. Exemplarily, the target register group can be configured with multiple registers, each of which can be used to store the configuration information of a persistent data address window. The embodiment of the present invention does not limit the specific content of the configuration information of the target register group. The types of data access requests may include but are not limited to persistent requests and ordinary requests. A persistent request may be a data request that requires the specific attributes of the accessed data or request to remain valid or be preserved for a long time. A normal request may be a data request that does not require the specific attributes of the accessed data or request to remain valid or be preserved for a long time.

[0049] Correspondingly, after receiving the data access request sent by the target processor, the type of the data access request can be determined according to the configuration information of the target register group.

[0050] S130 . Replace the current cache data with the target data requested by the data access request according to the type of the data access request and the configuration information of the target register group.

[0051] The target data may be data requested to be accessed by the data access request. The current cache data may be data cached in the cache component. The persistent data address window may be a window in the cache component for managing persistent data. The cache component may determine the current cache data to be replaced by the target data requested to be accessed by the data access request based on the configuration information of the persistent data address window.

[0052] Specifically, after receiving a data access request sent by a target processor and determining the type of the data access request, the target data requested by the data access request may replace the current cache data according to the type of the data access request and configuration information of the target register group.

[0053] Since the target register group stores the configuration information of the persistent data address window through the configured register, and the configuration information of each persistent data address window can be flexibly adjusted according to actual needs, the flexibility of the cache component in caching data is improved. At the same time, the traditional LRU algorithm does not consider the priority of data when caching data, while the embodiment of the present invention customizes the configuration information of the persistent data address window to distinguish the priority of data, which can support cache management of multiple persistence levels, realize a highly fair data caching strategy that supports data persistence, and enrich the data caching function. In addition, the data caching method in the embodiment of the present invention does not require the processor to support additional extended instructions, thereby reducing the requirements for software and hardware resources in the data caching process.

[0054] The technical solution of this embodiment receives a data access request sent by a target processor and determines the type of the data access request according to the configuration information of the target register group. Further, the target data requested by the data access request can be replaced with the current cache data according to the type of the data access request and the configuration information of the target register group, solving the problem that the LRU algorithm in the prior art cannot support data persistence caching, realizing a highly fair data caching strategy that supports data persistence, enriching the data caching function, and reducing the requirements for software and hardware resources in the data caching process.

[0055] Embodiment 2

[0056] Figure 2 is a flow chart of a data caching method provided by Embodiment 2 of the present invention. This embodiment is specific based on the above embodiment. In this embodiment, multiple specific optional implementation methods are provided for determining whether a data access request is a persistence request and replacing the current cached data with the target data requested by the data access request. Figure 2 As shown, the method of this embodiment may include:

[0057] S210: Receive a data access request sent by a target processor.

[0058] S220: parse the data access request and determine a request address of the data access request.

[0059] The request address of the data access request may be the address of the target data requested to be accessed by the data access request.

[0060] In an embodiment of the present invention, after receiving a data access request sent by a target processor, the cache component may parse the data access request and determine the address of the target data requested to be accessed by the data access request as a basis for determining the persistence type of the data access request.

[0061] S230. When it is determined that the request address of the data access request hits the address range of the persistent data address window, determine that the data access request is a persistent request; when it is determined that the request address of the data access request does not hit the address range of the persistent data address window, determine that the data access request is a normal request.

[0062] Among them, the configuration information of the persistent data address window may include but is not limited to the window start and end addresses, etc., and the embodiment of the present invention does not limit the specific information included in the configuration information of the persistent data address window. The window start and end addresses can be the starting address and end address of the persistent data address window, and the address range of the window can be determined according to the window start and end addresses. It can be understood that a plurality of registers can be configured in the target register group of the cache component, and each register is used to store the configuration information of a persistent data address window, that is, a plurality of persistent data address windows can be configured in the cache component, and the address ranges of each persistent data address window cannot overlap.

[0063] Optionally, the configuration information of the persistent data address window may further include a preset hit rate and a persistence priority. The preset hit rate may be the ratio of successfully obtaining data from the cache when accessing data. For example, the value range of the preset hit rate may be 0-1. The persistence priority may be the persistence level of each persistent data address window in the cache component. Exemplarily, the persistence priority may include, but is not limited to, strong persistence, weak persistence, and non-persistence, etc. The embodiment of the present invention does not limit the specific level included in the persistence priority. In a specific example, the data persistence function enable may be configured in the register, 0 represents off, and 1 represents on. When the data persistence function enable is 0, the persistence priority of the persistent data address window is non-persistent; when the data persistence function enable is 1, the persistence priority of the persistent data address window is strong persistence or weak persistence. The persistence level of the persistent data address window may also be configured in the register, 0 represents weak persistence, and 1 represents strong persistence. It is understandable that the configuration information of the persistent data address window may be configured before the data caching method is executed.

[0064] Correspondingly, after parsing the data access request to determine the request address of the data access request, it is possible to determine whether the request address of the data access request hits the address range of the persistent data address window. When the request address of the data access request is within the address range of the persistent data address window, it can be considered that the request address of the data access request hits the address range of the persistent data address window. In the case where it is determined that the request address of the data access request hits the address range of the persistent data address window, the data access request is determined to be a persistent request; in the case where it is determined that the request address of the data access request does not hit the address range of the persistent data address window, the data access request is determined to be a normal request. For persistent requests, the number of the persistent data address window hit by the request address of the data access request can be attached to the data access request and sent to the subsequent module for further processing. For normal requests, they can be directly sent to the subsequent module for processing according to the normal process.

[0065] S240: Obtain the persistent storage priority of the current cached data.

[0066] The current cache data may include multiple cache groups, each cache group may include multiple cache ways, and each cache way may include multiple cache lines. The persistent storage priority of the current cache data may be the persistence level of the persistent data address window where the current cache data is located. It is understandable that the persistent storage priorities of cache lines in the same persistent data address window are the same.

[0067] Correspondingly, the target data requested by the data access request replaces the current cache data according to the configuration information of the target register group. First, the persistent storage priority of the current cache data can be obtained as the basis for data caching.

[0068] S250, calculating the actual hit rate of each persistent data address window in real time.

[0069] The actual hit rate of the persistent data address window may be a ratio of successfully obtaining data from the cache during data access, and is real data calculated based on real-time data.

[0070] Specifically, the cache lines in each persistent data address window stored in the cache in the cache component can be counted, and each time a cache line is filled, the corresponding persistent data address window count value is increased by 1, and each time a cache line is eliminated, the corresponding persistent data address window count value is reduced by 1. Through the count value of each persistent data address window, the actual hit rate of each persistent data address window can be calculated in real time.

[0071] S260. Replace the current cached data with the target data requested by the data access request according to the type of the data access request, the persistent storage priority of the current cached data, the preset hit rate of each persistent data address window, and the actual hit rate of each persistent data address window.

[0072] Correspondingly, after obtaining the type of data access request, the persistent storage priority of the current cached data, the preset hit rate of each persistent data address window and the actual hit rate of each persistent data address window, the current cached data can be replaced by the target data requested by the data access request based on the above data.

[0073] The technical solution of this embodiment receives a data access request sent by a target processor, parses the data access request, and determines the request address of the data access request. Furthermore, the type of the data access request can be determined based on whether the request address of the data access request hits the address range of the persistent data address window. Furthermore, the persistent storage priority of the current cached data can be obtained and the actual hit rate of each persistent data address window can be calculated in real time, so that the target data requested by the data access request can be replaced with the current cached data based on the type of data access request, the persistent storage priority of the current cached data, the preset hit rate of each persistent data address window, and the actual hit rate of each persistent data address window. This solves the problem that the LRU algorithm in the prior art cannot support data persistence caching, realizes a highly fair data caching strategy that supports data persistence, enriches the data caching function, and reduces the requirements for software and hardware resources during the data caching process.

[0074] Embodiment 3

[0075] Figure 3 is a flow chart of a data caching method provided by the third embodiment of the present invention. This embodiment is specific based on the above embodiment. In this embodiment, multiple specific optional implementation methods are provided for replacing the current cached data with the target data requested by the data access request according to the type of the data access request, the persistent storage priority of the current cached data, the preset hit rate of each persistent data address window, and the actual hit rate of each persistent data address window. Figure 3 As shown, the method of this embodiment may include:

[0076] S310: Receive a data access request sent by a target processor.

[0077] S320, parse the data access request and determine the request address of the data access request; if it is determined that the request address of the data access request hits the address range of the persistent data address window, determine that the data access request is a persistent request; if it is determined that the request address of the data access request does not hit the address range of the persistent data address window, determine that the data access request is a normal request.

[0078] S330, obtaining the persistent storage priority of the current cached data; and calculating the actual hit rate of each persistent data address window in real time.

[0079] S340, determining whether all cache lines of the cache group corresponding to the data access request in the current cache data are strong persistent cache lines, if so, executing S350, otherwise executing S3130.

[0080] The strongly persistent cache line may be a cache line of a cache group corresponding to a data access request in the current cache data whose persistent storage priority is strongly persistent.

[0081] S350, determine whether the type of the data access request is a persistence request, if so, execute S360, otherwise execute S370.

[0082] S360, determine whether the data access request belongs to a strong persistence window, if so, execute S380, otherwise execute S370.

[0083] The strong persistence window may be a persistent data address window to which the data access request belongs, the persistence priority of which is strong persistence.

[0084] S370: Prohibit the target data requested by the data access request from replacing the current cache data.

[0085] The data access request does not belong to the strong persistence window, which means that the data access request belongs to the non-strong persistence window. The non-strong persistence window may be a persistent data address window to which the data access request belongs, whose persistence priority is non-persistent or weakly persistent.

[0086] Correspondingly, when all cache lines of the cache group corresponding to the data access request in the current cache data are strongly persistent cache lines and the data access request is a non-strong persistence window, it is prohibited to replace the current cache data with the target data requested by the data access request, thereby ensuring the highest priority of strongly persistent data.

[0087] S380. Determine whether there is a target persistent data address window. If so, execute S3100; otherwise, execute S390.

[0088] The target persistent data address window may be a persistent data address window whose actual hit rate is greater than or equal to a preset hit rate. When the actual hit rate is greater than or equal to the preset hit rate, it can be considered that the corresponding persistent data address window meets the hit rate.

[0089] S390: Use the LRU algorithm to replace the target data in the current cache data.

[0090] Accordingly, in the absence of a target persistent data address window, an LRU algorithm may be used to replace the cache line that has not been accessed for the longest time in the current cache data with the target data requested for access by the data access request.

[0091] S3100, determine whether there is a same request window in the target persistent data address window, if so, execute S3110, otherwise execute S3120.

[0092] The same request window may be a persistent data address window hit by a data access request.

[0093] S3110, using the LRU algorithm to replace the target data in the cache line in the same request window.

[0094] Accordingly, when there is a same request window in the target persistent data address window, the LRU algorithm can be used to replace the cache line that has not been accessed for the longest time in the same request window with the target data requested by the data access request.

[0095] S3120: Use the LRU algorithm to replace the target data in the cache line of the target persistent data address window.

[0096] Correspondingly, when there is a target persistent data address window and there is no same request window in the target persistent data address window, the LRU algorithm can be used to replace the cache line that has not been accessed for the longest time in other target persistent data address windows with the target data requested for access by the data access request.

[0097] S3130. Replace the current cached data with the target data requested by the data access request based on the type of the data access request, the persistent storage priority of the current cached data, the preset hit rate of each persistent data address window, and the actual hit rate of each persistent data address window.

[0098] The technical solution of this embodiment receives a data access request sent by a target processor, and parses the data access request to determine the request address of the data access request. Further, the type of the data access request can be determined according to whether the request address of the data access request hits the address range of the persistent data address window. Further, the persistent storage priority of the current cache data can be obtained and the actual hit rate of each persistent data address window can be calculated in real time, so that when the type of the data access request is a persistent request, all cache lines in the current cache data are strong persistent cache lines and the data access request belongs to a strong persistent window, the target data requested by the data access request can be replaced with the current cache data according to the preset hit rate of each persistent data address window and the actual hit rate of each persistent data address window; when all cache lines in the current cache data are strong persistent cache lines and the data access request is a non-strong persistent window, the target data requested by the data access request is prohibited from replacing the current cache data, which solves the problem that the LRU algorithm in the prior art cannot support data persistent caching, realizes a data caching strategy that supports data persistence with high fairness, enriches the data caching function, and reduces the requirements for software and hardware resources in the data caching process.

[0099] Embodiment 4

[0100] Figure 4 This is a flow chart of a data caching method provided by the fourth embodiment of the present invention. This embodiment is specific based on the above embodiment. In this embodiment, multiple specific optional implementation methods are provided for replacing the current cached data with the target data requested by the data access request according to the type of the data access request, the persistent storage priority of the current cached data, the preset hit rate of each persistent data address window, and the actual hit rate of each persistent data address window. Figure 4 As shown, the method of this embodiment may include:

[0101] S410: Receive a data access request sent by a target processor.

[0102] S420, parse the data access request and determine the request address of the data access request; when it is determined that the request address of the data access request hits the address range of the persistent data address window, determine that the data access request is a persistent request; when it is determined that the request address of the data access request does not hit the address range of the persistent data address window, determine that the data access request is a normal request.

[0103] S430, obtaining the persistent storage priority of the current cache data; and calculating the actual hit rate of each persistent data address window in real time.

[0104] S440, determining whether all cache lines of the cache group corresponding to the data access request in the current cache data are strong persistent cache lines, if so, executing S4120, otherwise executing S450.

[0105] S450, determining whether there is a non-persistent cache line in the cache group corresponding to the data access request in the current cache data, if so, executing S460, otherwise executing S470.

[0106] The non-persistent cache line may be a cache line of current cached data whose persistent storage priority is non-persistent.

[0107] S460: Use an LRU algorithm to replace the target data in the non-persistent cache line.

[0108] In an embodiment of the present invention, when all cache lines of the cache group corresponding to the data access request in the current cache data are not strongly persistent cache lines, and there are non-persistent cache lines in the cache line of the cache group corresponding to the data access request in the current cache data, regardless of whether the type of the data access request is a persistent request, the LRU algorithm can be used to replace the non-persistent cache line in the cache component that has not been accessed for the longest time using the target data requested to be accessed by the data access request.

[0109] S470 , determine whether there is a weakly persistent cache line in the target persistent data address window, if so, execute S490 , otherwise execute S480 .

[0110] The weakly persistent cache line may be a cache line of current cached data whose persistent storage priority is weakly persistent.

[0111] S480: Use the LRU algorithm to replace the target data in the weakly persistent cache line.

[0112] Correspondingly, when there is no weakly persistent cache line in the target persistent data address window, the LRU algorithm can be used to replace the weakly persistent cache line that has not been accessed for the longest time among the weakly persistent cache lines that do not meet the hit rate using the target data requested by the data access request.

[0113] S490, determine whether there is a same request window in the target persistent data address window, if so, execute S4100, otherwise execute S4110.

[0114] S4100: Use the LRU algorithm to replace the target data in the cache line of the same request window.

[0115] Correspondingly, when there is a weakly persistent cache line in the target persistent data address window and there is a same request window in the target persistent data address window, the LRU algorithm can be used to replace the weakly persistent cache line that has not been accessed for the longest time in the same request window with the target data requested by the data access request.

[0116] S4110. Use the LRU algorithm to replace the target data in the weakly persistent cache line of the target persistent data address window.

[0117] Correspondingly, when there is a weakly persistent cache line in the target persistent data address window and there is no same request window in the target persistent data address window, the LRU algorithm can be used to replace the weakly persistent cache line that has not been accessed for the longest time in other target persistent data address windows with the target data requested by the data access request.

[0118] S4120. Replace the current cached data with the target data requested by the data access request based on the type of the data access request, the persistent storage priority of the current cached data, the preset hit rate of each persistent data address window, and the actual hit rate of each persistent data address window.

[0119] The technical solution of this embodiment receives a data access request sent by a target processor, parses the data access request, and determines the request address of the data access request. Further, the data access request type can be determined based on whether the request address of the data access request hits the address range of the persistent data address window. Furthermore, the persistent storage priority of the current cache data can be obtained and the actual hit rate of each persistent data address window can be calculated in real time. Therefore, when all cache lines of the cache group corresponding to the data access request in the current cache data are not strongly persistent cache lines and there are non-persistent cache lines in the cache lines of the cache group corresponding to the data access request in the current cache data, the LRU algorithm can be used to replace the target data in the non-persistent cache lines; when all cache lines in the current cache data are not strongly persistent cache lines and there are no non-persistent cache lines in the cache lines in the current cache data, the current cache data is replaced with the target data requested by the data access request according to the preset hit rate of each persistent data address window and the actual hit rate of each persistent data address window, which solves the problem in the prior art that the LRU algorithm cannot support data persistent caching, realizes a highly fair data caching strategy that supports data persistence, enriches the data caching function, and reduces the requirements for software and hardware resources in the data caching process.

[0120] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information are in compliance with the relevant laws and regulations and do not violate public order and good morals.

[0121] It should be noted that any arrangement and combination of the technical features in the above embodiments also falls within the protection scope of the present invention.

[0122] Embodiment 5

[0123] Figure 5 is a schematic diagram of a cache component provided by Embodiment 5 of the present invention, such as Figure 5 As shown, the cache components include:

[0124] The data buffer includes a first data buffer and a second data buffer; the first data buffer is used to store tag data; the second data buffer is used to store cache data;

[0125] Among them, the data buffer can be an area in the cache component for temporarily storing data. The first data buffer can be an area in the cache component for storing tag data. The tag data can include a valid storage bit, a dirty data flag bit, a physical address high segment, and an index field. The valid storage bit can be the number of binary bits that can be used to store valid data in the cache component. The dirty data flag bit can be a binary bit in the cache component used to mark whether the data has been modified but has not yet been updated to the main storage. The physical address high segment can be the address bit of the high-order part of the physical address, which can be used to divide the memory of the cache component into different areas. The index field can be used to store the window number corresponding to the cache line. The cache line and the window can be linked by the index field. Exemplarily, assuming that there are three persistent data address windows, the index field requires 2 bits, 0 represents persistent data address window 0, 1 represents persistent data address window 1, 2 represents persistent data address window 2, and 3 represents not belonging to any window. The second data buffer can be an area for storing cache data.

[0126] The target register group is configured with a plurality of registers, each of which is used to store configuration information of a persistent data address window;

[0127] The cache component is used for:

[0128] receiving a data access request sent by a target processor;

[0129] Determining the type of the data access request according to the configuration information of the target register group;

[0130] The target data requested by the data access request replaces the current cache data according to the type of the data access request and the configuration information of the target register group.

[0131] Optionally, the configuration information of the persistent data address window may include the start and end addresses of the window; the cache component is also used to: parse the data access request and determine the request address of the data access request; when it is determined that the request address of the data access request hits the address range of the persistent data address window, determine that the data access request is a persistent request; when it is determined that the request address of the data access request does not hit the address range of the persistent data address window, determine that the data access request is a normal request.

[0132] Optionally, the configuration information of the persistent data address window also includes a preset hit rate and a persistent priority; the cache component is also used to: obtain the persistent storage priority of the current cached data; calculate the actual hit rate of each persistent data address window in real time; replace the current cached data with the target data requested to be accessed by the data access request based on the type of the data access request, the persistent storage priority of the current cached data, the preset hit rate of each persistent data address window and the actual hit rate of each persistent data address window.

[0133] Optionally, the current cache data includes multiple cache groups, each of which may include multiple cache ways, and each of which may include multiple cache lines; the cache component is also used to: when it is determined that the type of the data access request is a persistent request, all cache lines of the cache group corresponding to the data access request in the current cache data are strongly persistent cache lines, and the data access request belongs to a strong persistent window, replace the current cache data with the target data requested to be accessed by the data access request according to a preset hit rate of each persistent data address window and an actual hit rate of each persistent data address window; when it is determined that all cache lines of the cache group corresponding to the data access request in the current cache data are strongly persistent cache lines, and it is determined that the data access request is a non-strong persistent window, prohibit the current cache data from being replaced with the target data requested to be accessed by the data access request.

[0134] Optionally, the cache component is also used to: filter the persistent data address windows whose actual hit rate is greater than or equal to the preset hit rate as target persistent data address windows; when it is determined that the target persistent data address window does not exist, use the LRU algorithm to replace the target data in the current cache data; when it is determined that there is a same-request window in the target persistent data address window, use the LRU algorithm to replace the target data in the cache line in the same-request window; when it is determined that there is the target persistent data address window and it is determined that the same-request window does not exist in the target persistent data address window, use the LRU algorithm to replace the target data in the cache line of the target persistent data address window; wherein, the same-request window is the persistent data address window hit by the data access request.

[0135] Optionally, the cache component is also used to: when it is determined that not all cache lines of the cache group corresponding to the data access request in the current cache data are strongly persistent cache lines, and when it is determined that there are non-persistent cache lines in the cache lines in the current cache data, use an LRU algorithm to replace the target data in the non-persistent cache lines; when it is determined that not all cache lines of the cache group corresponding to the data access request in the current cache data are strongly persistent cache lines, and when it is determined that there are no non-persistent cache lines in the cache group corresponding to the data access request in the current cache data, replace the current cache data with the target data requested to be accessed by the data access request according to a preset hit rate of each of the persistent data address windows and an actual hit rate of each of the persistent data address windows.

[0136] Optionally, the cache component is also used to: filter the persistent data address windows whose actual hit rate is greater than or equal to the preset hit rate as target persistent data address windows; when it is determined that there is no weakly persistent cache line in the target persistent data address window, use the LRU algorithm to replace the target data in the weakly persistent cache line; when it is determined that there is a weakly persistent cache line in the target persistent data address window and when it is determined that there is a same-request window in the target persistent data address window, use the LRU algorithm to replace the target data in the cache line of the same-request window; when it is determined that there is a weakly persistent cache line in the target persistent data address window and when it is determined that there is no same-request window in the target persistent data address window, use the LRU algorithm to replace the target data in the weakly persistent cache line of the target persistent data address window; wherein, the same-request window is the persistent data address window in which the data access request hits.

[0137] Figure 6 is a flow chart of a data caching method of a cache component provided in Embodiment 5 of the present invention. Figure 6 As shown, after receiving the data access request sent by the target processor, the cache component can determine the persistent storage priority of all ways of the cache group corresponding to the data access request.

[0138] When it is determined that the persistent storage priority of all the ways of the cache group corresponding to the data access request is strongly persistent, the persistent priority of the persistent data address window hit by the data access request can be further judged. When it is determined that the persistent priority of the persistent data address window hit by the data access is strongly persistent, the current cache data can be replaced with the target data requested by the data access request; when the persistent priority of the persistent data address window hit by the data access is not strongly persistent, replacement is prohibited, so that the highest priority of strongly persistent data can be guaranteed. When replacing, first, it can be checked whether there is a cache line that meets the hit rate. If there is no cache line that meets the hit rate, the LRU algorithm can be used to replace the cache line that has not been accessed for the longest time in the current cache data with the target data requested by the data access request; if there is a cache line that meets the hit rate, it can be further judged whether there is a same request window for the cache line that meets the hit rate. If there is a same request window, the LRU algorithm can be used to use the target data requested by the data access request to replace the cache line that has not been accessed for the longest time in the same request window; if there is no same request window, the LRU algorithm can be used to use the target data requested by the data access request to replace the cache line that has not been accessed for the longest time in other request windows.

[0139] When it is determined that the persistent storage priority of all the ways of the cache group corresponding to the data access request is not strongly persistent, replacement is allowed regardless of whether the data access request is a persistent request or a common request, thereby ensuring that there is a non-persistent cache line in a cache group, reserving a certain cache space for other applications. Further, it is possible to judge whether there are non-persistent cache lines in all the ways of the cache group corresponding to the data access request. If it is determined that there are non-persistent cache lines in all the ways of the cache group corresponding to the data access request, the LRU algorithm can be used to replace the non-persistent cache line that has not been accessed for the longest time in the current cache data with the target data requested by the data access request. Thereby, it can be ensured that the priority of persistent data is higher than that of non-persistent data. If it is determined that there are no non-persistent cache lines in all the ways of the cache group corresponding to the data access request, it can be found whether there are weakly persistent cache lines that meet the hit rate. If there is no weakly persistent cache line that meets the hit rate, the LRU algorithm can be used to replace the weakly persistent cache line that has not been accessed for the longest time in the current cache data with the target data requested by the data access request; if there is a weakly persistent cache line that meets the hit rate, it can be further searched for the same request window in the weakly persistent cache line that meets the hit rate. If there is a same request window, the LRU algorithm can be used to replace the weakly persistent cache line that has not been accessed for the longest time in the same request window with the target data requested by the data access request; if there is no same request window, the LRU algorithm can be used to replace the weakly persistent cache line that has not been accessed for the longest time in other request windows with the target data requested by the data access request.

[0140] The technical solution of this embodiment receives a data access request sent by a target processor and determines the type of the data access request according to the configuration information of the target register group. Further, the target data requested by the data access request can be replaced with the current cache data according to the type of the data access request and the configuration information of the target register group, solving the problem that the LRU algorithm in the prior art cannot support data persistence caching, realizing a highly fair data caching strategy that supports data persistence, enriching the data caching function, and reducing the requirements for software and hardware resources in the data caching process.

[0141] Embodiment 6

[0142] Figure 7 is a schematic diagram of a data cache device provided by Embodiment 6 of the present invention, such as Figure 7 As shown, the device is configured in a cache component, and the cache component is configured with a target register group, including: a data access request receiving module 610, a request type determination module 620 and a target data cache module 630, wherein:

[0143] The data access request receiving module 610 is configured to replace the current cached data with the target data requested by the data access request according to the configuration information of the target register group when it is determined that the data access request is a persistence request according to the configuration information of the target register group.

[0144] The request type determination module 620 is configured to determine the type of the data access request according to the configuration information of the target register group.

[0145] The target data cache module 630 is configured to replace the current cached data with the target data requested by the data access request according to the configuration information of the target register group when it is determined that the data access request is a persistence request according to the configuration information of the target register group.

[0146] The target register group is configured with a plurality of registers, and each of the registers is used to store configuration information of a persistent data address window.

[0147] The technical solution of this embodiment receives a data access request sent by a target processor and determines the type of the data access request according to the configuration information of the target register group. Further, the target data requested by the data access request can be replaced with the current cache data according to the type of the data access request and the configuration information of the target register group, solving the problem that the LRU algorithm in the prior art cannot support data persistence caching, realizing a highly fair data caching strategy that supports data persistence, enriching the data caching function, and reducing the requirements for software and hardware resources in the data caching process.

[0148] Optionally, the configuration information of the persistent data address window includes the start and end addresses of the window, and the request type determination module 620 is specifically used to: parse the data access request and determine the request address of the data access request; when it is determined that the request address of the data access request hits the address range of the persistent data address window, determine that the data access request is a persistent request; when it is determined that the request address of the data access request does not hit the address range of the persistent data address window, determine that the data access request is a normal request.

[0149] Optionally, the configuration information of the persistent data address window also includes a preset hit rate and a persistent priority, and the target data cache module 630 is specifically used to: obtain the persistent storage priority of the current cached data; calculate the actual hit rate of each persistent data address window in real time; and replace the current cached data with the target data requested to be accessed by the data access request based on the type of the data access request, the persistent storage priority of the current cached data, the preset hit rate of each persistent data address window, and the actual hit rate of each persistent data address window.

[0150] Optionally, the current cache data includes multiple cache groups, each of the cache groups includes multiple cache ways, each of the cache ways includes multiple cache lines, and the target data cache module 630 is specifically used to: when it is determined that the type of the data access request is a persistent request, all cache lines of the cache group corresponding to the data access request in the current cache data are strongly persistent cache lines, and the data access request belongs to a strong persistent window, replace the current cache data with the target data requested to be accessed by the data access request according to a preset hit rate of each persistent data address window and an actual hit rate of each persistent data address window; when it is determined that all cache lines of the cache group corresponding to the data access request in the current cache data are strongly persistent cache lines, and it is determined that the data access request is a non-strong persistent window, prohibit the target data requested to be accessed by the data access request from replacing the current cache data.

[0151] Optionally, the target data cache module 630 is specifically used to: filter the persistent data address windows whose actual hit rate is greater than or equal to the preset hit rate as the target persistent data address windows; when it is determined that the target persistent data address window does not exist, use the LRU algorithm to replace the target data in the current cache data; when it is determined that there is a same request window in the target persistent data address window, use the LRU algorithm to replace the target data in the cache line in the same request window; when it is determined that there is the target persistent data address window and it is determined that there is no same request window in the target persistent data address window, use the LRU algorithm to replace the target data in the cache line of the target persistent data address window; wherein, the same request window is the persistent data address window hit by the data access request.

[0152] Optionally, the target data cache module 630 is specifically used to: when it is determined that not all cache lines of the cache group corresponding to the data access request in the current cache data are strongly persistent cache lines, and when it is determined that there are non-persistent cache lines in the cache lines in the current cache data, use the LRU algorithm to replace the target data in the non-persistent cache lines; when it is determined that not all cache lines of the cache group corresponding to the data access request in the current cache data are strongly persistent cache lines, and when it is determined that there are no non-persistent cache lines in the cache group corresponding to the data access request in the current cache data, replace the current cache data with the target data requested to be accessed by the data access request according to a preset hit rate of each of the persistent data address windows and an actual hit rate of each of the persistent data address windows.

[0153] Optionally, the target data cache module 630 is specifically used to: filter the persistent data address windows whose actual hit rate is greater than or equal to the preset hit rate as the target persistent data address windows; when it is determined that there is no weakly persistent cache line in the target persistent data address window, use the LRU algorithm to replace the target data in the weakly persistent cache line; when it is determined that there is a weakly persistent cache line in the target persistent data address window and when it is determined that there is a same-request window in the target persistent data address window, use the LRU algorithm to replace the target data in the cache line of the same-request window; when it is determined that there is a weakly persistent cache line in the target persistent data address window and when it is determined that there is no same-request window in the target persistent data address window, use the LRU algorithm to replace the target data in the weakly persistent cache line of the target persistent data address window; wherein, the same-request window is the persistent data address window in which the data access request hits.

[0154] The above data cache device can execute the data cache method provided by any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method. For technical details not described in detail in this embodiment, please refer to the data cache method provided by any embodiment of the present invention.

[0155] Since the data cache device introduced above is a device that can execute the data cache method in the embodiment of the present invention, based on the data cache method introduced in the embodiment of the present invention, the technical personnel in the field can understand the specific implementation of the data cache device of the present embodiment and its various variations, so how the data cache device implements the data cache method in the embodiment of the present invention is not introduced in detail here. As long as the technical personnel in the field implement the device used by the data cache method in the embodiment of the present invention, it belongs to the scope of protection of this application.

[0156] Embodiment 7

[0157] Figure 8 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0158] like Figure 8 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., and the memory is connected to the cache component, wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0159] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0160] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as a data caching method.

[0161] In some embodiments, the data caching method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the data caching method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the data caching method in any other appropriate manner (e.g., by means of firmware).

[0162] Optionally, the data caching method is applied to a cache component, which is configured with a target register group. The method may include: receiving a data access request sent by a target processor; determining the type of the data access request based on the configuration information of the target register group; replacing the current cached data with the target data requested to be accessed by the data access request based on the type of the data access request and the configuration information of the target register group; wherein the target register group is configured with multiple registers, each of which is used to store the configuration information of a persistent data address window.

[0163] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0164] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0165] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0166] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0167] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0168] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0169] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0170] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A data caching method, characterized in that: Applied to a cache unit, the cache unit is configured with a target register group, the method comprises: receiving a data access request sent by a target processor; Determining the type of the data access request according to the configuration information of the target register group; Replace the current cache data with the target data requested by the data access request according to the type of the data access request and the configuration information of the target register group; The target register group is configured with a plurality of registers, and each of the registers is used to store configuration information of a persistent data address window.

2. The method according to claim 1, characterized in that The configuration information of the persistent data address window includes the window start and end addresses; and determining the type of the data access request according to the configuration information of the target register group includes: Parsing the data access request to determine a request address of the data access request; In the case where it is determined that the request address of the data access request hits the address range of the persistent data address window, determining that the data access request is a persistent request; In the case where it is determined that the request address of the data access request does not hit the address range of the persistent data address window, the data access request is determined to be a common request.

3. The method according to claim 2, characterized in that The configuration information of the persistent data address window also includes a preset hit rate and a persistence priority; the replacing the current cache data with the target data requested to be accessed by the data access request according to the type of the data access request and the configuration information of the target register group includes: Obtaining the persistent storage priority of the current cached data; Calculating the actual hit rate of each persistent data address window in real time; According to the type of the data access request, the persistent storage priority of the current cached data, the preset hit rate of each persistent data address window and the actual hit rate of each persistent data address window, the target data requested by the data access request replaces the current cached data.

4. The method according to claim 3, characterized in that in, The current cache data includes a plurality of cache groups, each of the cache groups includes a plurality of cache ways, and each of the cache ways includes a plurality of cache lines; The replacing the current cache data with the target data requested by the data access request according to the type of the data access request, the persistent storage priority of the current cache data, the preset hit rate of each persistent data address window, and the actual hit rate of each persistent data address window includes: When it is determined that the type of the data access request is a persistent request, all cache lines of the cache group corresponding to the data access request in the current cache data are strong persistent cache lines, and the data access request belongs to a strong persistent window, according to a preset hit rate of each persistent data address window and an actual hit rate of each persistent data address window, the current cache data is replaced with the target data requested to be accessed by the data access request; When it is determined that all cache lines of the cache group corresponding to the data access request in the current cache data are strong persistent cache lines, and it is determined that the data access request is a non-strong persistent window, it is prohibited to replace the current cache data with the target data requested by the data access request.

5. The method according to claim 4, characterized in that The replacing the current cache data with the target data requested by the data access request according to the preset hit rate of each persistent data address window and the actual hit rate of each persistent data address window comprises: Filtering the persistent data address windows whose actual hit rate is greater than or equal to the preset hit rate as target persistent data address windows; When it is determined that the target persistent data address window does not exist, replacing the target data in the current cache data using a least recently used (LRU) algorithm; When it is determined that there is a same-request window in the target persistent data address window, replacing the target data in the cache line in the same-request window using the LRU algorithm; When it is determined that the target persistent data address window exists and it is determined that the same request window does not exist in the target persistent data address window, replacing the target data in the cache line of the target persistent data address window by using the LRU algorithm; The same request window is a persistent data address window hit by the data access request.

6. The method according to claim 4, characterized in that The replacing the current cache data with the target data requested by the data access request according to the type of the data access request, the persistent storage priority of the current cache data, the preset hit rate of each persistent data address window, and the actual hit rate of each persistent data address window includes: When it is determined that all cache lines of the cache group corresponding to the data access request in the current cache data are not strongly persistent cache lines, and when it is determined that there are non-persistent cache lines in the cache lines in the current cache data, the target data is replaced in the non-persistent cache lines using an LRU algorithm; When it is determined that all cache lines of the cache group corresponding to the data access request in the current cache data are not strongly persistent cache lines, and when it is determined that there are no non-persistent cache lines in the cache line of the cache group corresponding to the data access request in the current cache data, the current cache data is replaced with the target data requested to be accessed by the data access request based on a preset hit rate of each persistent data address window and an actual hit rate of each persistent data address window.

7. The method according to claim 6, characterized in that The replacing the current cache data with the target data requested by the data access request according to the preset hit rate of each persistent data address window and the actual hit rate of each persistent data address window comprises: Filtering the persistent data address windows whose actual hit rate is greater than or equal to the preset hit rate as target persistent data address windows; When it is determined that there is no weak persistent cache line in the target persistent data address window, replacing the target data in the weak persistent cache line using the LRU algorithm; When it is determined that there is a weak persistent cache line in the target persistent data address window and when it is determined that there is a same request window in the target persistent data address window, the target data is replaced in the cache line of the same request window by using the LRU algorithm; When it is determined that there is a weak persistent cache line in the target persistent data address window and when it is determined that there is no same request window in the target persistent data address window, the target data is replaced in the weak persistent cache line of the target persistent data address window by using the LRU algorithm; The same request window is a persistent data address window hit by the data access request.

8. An electronic device, characterized in that: The electronic device comprises: at least one processor; and A memory communicatively connected to the at least one processor; the memory is communicatively connected to a cache component, wherein: The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the data caching method according to any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the data caching method described in any one of claims 1 to 7 when executed.

10. A computer program product comprising a computer program / instructions, wherein: When the computer program / instruction is executed by a processor, the data caching method according to any one of claims 1 to 7 is implemented.

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