Memory management method, device, equipment and readable storage medium

Abstract

An embodiment of the present invention provides a memory management method, apparatus, device, and readable storage medium. The method includes: obtaining a first memory capacity to be applied for, and determining a first offset sequence corresponding to the first memory capacity; there is a positive correlation between the first memory capacity and the number of offsets in the first offset sequence; starting from the first offset in the first offset sequence, according to the first offset, offset the bit positions of a preset register, and based on the register value before offset and the register value after offset, obtain a register update value; each bit position is used to represent that the corresponding memory area is in an idle state or an occupied state; based on the register update value, continue the next offset until traversing the first offset sequence is completed, and determine a final first register value; perform encoding processing on the first register value to obtain a first memory address corresponding to the first register value. The present invention can improve the efficiency of memory management.

Description

Technical Field

[0001] The present invention relates to the technical field of memory, and in particular, to a memory management method, device, electronic device, and readable storage medium. Background Art

[0002] Dynamic memory management is a technology for memory allocation and release during program execution. Dynamic memory management can handle memory requirements of different sizes and lifecycles, avoiding the rigidity of static memory allocation, improving program performance, and having a greater impact on system stability and performance.

[0003] In related technologies, a dynamic memory allocation mechanism is implemented based on software modules. Moreover, existing various dynamic memory management algorithms, such as the malloc and free functions in the C language, are all implemented at the software level. These functions will apply for memory, allocate memory, and perform other dynamic memory management operations from the operating system.

[0004] However, in related technologies, dynamic memory management is performed through software. Compared with hardware implementation, the dynamic memory allocation mechanism implemented by these software is still slower in processing speed and lower in efficiency. Summary of the Invention

[0005] Embodiments of the present invention provide a memory management method, device, electronic device, and readable storage medium, which can solve the problem of low efficiency of the dynamic memory allocation mechanism implemented by software in related technologies.

[0006] To solve the above problems, embodiments of the present invention disclose a memory management method, including:

[0007] Obtain a first memory capacity to be applied for, and determine a first offset sequence corresponding to the first memory capacity; there is a positive correlation between the first memory capacity and the number of offsets in the first offset sequence; the offsets in the first offset sequence have an increasing relationship;

[0008] Starting from the first offset in the first offset sequence, offset the bit of a preset register according to the first offset, and based on the register value before offset and the register value after offset, obtain a register update value; the register value is determined by multiple bits of the register; each bit is used to represent that the corresponding memory area is in an idle state or an occupied state;

[0009] Based on the register update value, continue the next offset until the first offset sequence is traversed, and determine a final first register value;

[0010] Perform encoding processing on the first register value to obtain a first memory address corresponding to the first register value; the first memory address is the starting address to be allocated.

[0011] On the other hand, an embodiment of the present invention also discloses a memory management device, which includes:

[0012] An application sequence module, configured to obtain a first memory capacity to be applied for, and determine a first offset sequence corresponding to the first memory capacity; there is a positive correlation between the first memory capacity and the number of offsets in the first offset sequence; the offsets in the first offset sequence have an increasing relationship;

[0013] An iterative offset module, configured to start from the first offset in the first offset sequence, offset the bit positions of a preset register according to the first offset, and obtain a register update value based on the register value before offset and the register value after offset; the register value is determined by multiple bit positions of the register; each bit position is used to represent that the corresponding memory area is in an idle state or an occupied state;

[0014] An iterative result module, configured to continue the next offset based on the register update value until the first offset sequence is traversed, and determine a final first register value;

[0015] An address allocation module, configured to perform encoding processing on the first register value to obtain a first memory address corresponding to the first register value; the first memory address is the starting address to be allocated.

[0016] An embodiment of the present invention also discloses an electronic device, which includes a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete communication with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions cause the processor to execute the foregoing memory management method.

[0017] An embodiment of the present invention also discloses a readable storage medium. When the instructions in the readable storage medium are executed by the processor of the electronic device, the electronic device can execute the foregoing memory management method.

[0018] Embodiments of the present invention have the following advantages: Obtain the first memory capacity to be applied for, determine the first offset sequence corresponding to the first memory capacity, start from the first offset in the first offset sequence, offset the bits of a preset register according to the first offset, and based on the register value before offset and the register value after offset, obtain a register update value. Based on the register update value, continue the next offset until the first offset sequence is traversed, and determine the final first register value. Perform encoding processing on the first register value to obtain the starting address to be allocated corresponding to the first register value. It is possible to calculate and determine the free memory corresponding to the first memory capacity and the starting address of the free memory based on the bit offset update of the register, realizing memory application processing at the hardware level. Since the hardware processing speed is fast, the efficiency of memory management is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0020] Figure 1 is a flowchart of steps of a memory management method of the present invention;

[0021] Figure 2 is a flowchart of steps of another memory management method of the present invention;

[0022] Figure 3 is a structural block diagram of a memory management device of the present invention;

[0023] Figure 4 is a structural block diagram of an electronic device for memory management of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0025] In the description and claims of the present invention, terms such as "first" and "second" are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are usually of the same category, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the description and claims is used to describe the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. In the embodiments of the present invention, the term "plurality" refers to two or more, and other quantifiers are similar.

[0026] Dynamic memory refers to a mechanism that dynamically allocates and reclaims memory according to requests during operation. Generally, the application program makes a memory application, specifies the required memory size, the dynamic memory management system finds memory not less than this size in the free memory, returns the starting address to the application layer, and also needs to set the memory to the occupied state; when the application program needs to release a specified memory range, the dynamic memory management system should set this range to the free state to complete the release for subsequent application use.

[0027] Method embodiments

[0028] Figure 1 It is a step diagram of a memory management method of the present invention. The method includes:

[0029] Step 101, obtain the first memory capacity to be applied, and determine the first offset sequence corresponding to the first memory capacity; there is a positive correlation between the first memory capacity and the number of offsets in the first offset sequence.

[0030] In the embodiments of the present invention, the steps of the memory management method can be executed by other controllers outside the processor. The memory can be applied by an application program or a software module of the operating system. For example, the file system applies memory to cache file content and inode; the device driver can also apply memory to temporarily store data received from or sent to the hardware device; when the network driver receives network data packets, it needs to apply memory to store these data packets.

[0031] According to the memory application of the application program or the software module of the operating system, the memory application can carry the required memory size, so as to determine the first memory capacity to be applied based on the memory application.

[0032] Based on the first memory capacity of different sizes, a corresponding first offset sequence can be determined, and the first offset sequence includes at least one or more offsets. The way to determine the first offset sequence can be to perform operations based on the size of the first memory capacity, and can be calculated through the following formula:

[0033] k = log2N

[0034] In the above formula, k represents the number of offsets, N represents the size of the first memory capacity, and log2 is the logarithm operation with base 2.

[0035] In addition, the offsets in the first offset sequence can be increasing in size, for example, they can increase based on powers of two. For example, when the number of offsets in the first offset sequence is 5, the 5 offsets in the first offset sequence are 1, 2, 4, 8, and 16 respectively, and so on. When the first memory capacity is larger, for example, when the number of offsets in the first offset sequence is 7, the 7 offsets are 1, 2, 4, 8, 16, 32, and 64 respectively. The size of the first memory capacity and the first offset sequence are not specifically limited here.

[0036] Step 102, starting from the first offset in the first offset sequence, according to the first offset, offset the bits of the preset register, and based on the register value before the offset and the register value after the offset, obtain the register update value; the register value is determined by multiple bits of the register; each bit is used to represent that the corresponding memory area is in an idle state or an occupied state.

[0037] In the embodiment of the present invention, the first offset sequence may include one or more offsets. Starting from the first offset in the first offset sequence, based on the first offset, offset the bits of the preset register.

[0038] The preset register may have multiple bits, and each bit represents the state of a memory area of a certain size. The states include an idle state and an occupied state. Thus, according to the multiple bits of the register, the states of each memory area in the larger memory can be represented. Among them, a bit being 1 can represent the idle state, a bit being 0 can represent the occupied state, or it can be other representation methods. This is only an example here and is not limited.

[0039] When offsetting the bits of the register according to the offset, whether the entire bits of the register are shifted left or right, the offset will cause some changes in the register value. For example, the register value represented by the bits of the register is "001001110". If the offset is 2 and it is shifted left, the register value after the offset is "100111000". Among them, it should be noted that since it is shifted left, the first two bits "00" are shifted out, and two bits "00" can be shifted in on the right as a supplement.

[0040] After completing one offset, based on the register value before the offset and the register value after the offset, a specific operation such as an AND operation can be performed to obtain a register update value. For example, if the register value before the offset is "001001110" and the register value after the offset is "100111000", then after performing the AND operation, the obtained register update value is "000001000".

[0041] Step 103: Based on the register update value, continue the next offset until traversing the first offset sequence is completed, and determine the final first register value.

[0042] In the embodiment of the present invention, if there is only one offset amount 2 in the first offset sequence, the obtained register update value is "000001000", which is the final first register value.

[0043] If there are multiple offset amounts in the first offset sequence, continue the next offset based on the register update value. The offset process is similar. Based on the bit positions represented by the register update value, perform an offset based on the next offset amount, and similarly obtain the register value before the offset (i.e., the previous register update value) and the register value after the offset, and obtain the next register update value. The specific process will not be elaborated here.

[0044] Completing the traversal of the first offset sequence means that the corresponding bit offsets have been completed based on each offset amount, and the final first register value can be determined.

[0045] Among them, when performing successive offsets based on each offset amount in the first offset sequence, it can be controlled by a clock for each offset. For example, calculate one step of iteration, that is, one offset, at the rising edge of the clock. When there are 7 offset amounts, the overall process can be as follows:

[0046] The 1st clock: F = F&(F<<1)

[0047] The 2nd clock: F = F&(F<<2)

[0048] The 3rd clock: F = F&(F<<4)

[0049] The 4th clock: F = F&(F<<8)

[0050] The 5th clock: F = F&(F<<16)

[0051] The 6th clock: F = F&(F<<32)

[0052] The 7th clock: F = F&(F<<64)

[0053] In the above process, F is a preset register. The first clock indicates that the bits of register F are shifted left by 1 bit (<<1) to obtain the shifted register value (F<<1). The shifted register value (F<<1) is ANDed with the register value before shifting (F) to obtain the register update value, which is then assigned to register F. Then, the shifting process from the second clock to the seventh clock continues.

[0054] Step 104: Perform encoding processing on the first register value to obtain a first memory address corresponding to the first register value; the first memory address is the starting address to be allocated.

[0055] In the embodiment of the present invention, before performing iterative shifting, each bit of the register represents that the corresponding memory area is in an idle state or an occupied state. After completing the iterative shifting, each bit 1 (if 1 represents the idle state) in the first register value can represent the idle memory of the first memory capacity at different positions. The first register value may include multiple 1s, that is, the memory includes multiple idle memories of the first memory capacity.

[0056] Performing encoding processing on the first register value may be to input the first register value into an encoder circuit and encode the first register value of the register into an address, thereby obtaining the first memory address. The first memory address is the starting address of the memory with the size of the first memory capacity required by the application program or other memory requesters.

[0057] Thus, the starting address of the memory to be allocated can be returned to the application program so that the application program can use this memory space to store data.

[0058] It should be noted that the starting address is the starting address of the memory with the size of the first memory capacity in the idle state, that is, starting from the starting address, the consecutive memory with the size of the first memory capacity is idle and available for the memory requester to use. This is because, based on the AND operation between the register value before shifting and the register value after shifting to obtain the register update value, this process is essentially a checking or screening process, aiming to screen out the consecutive idle memory with the size of the first memory capacity.

[0059] For example, since each bit is used to represent whether the corresponding memory area is idle or occupied, if the first bit is 1, it can indicate that the memory area of the first byte in the memory is idle, and if the second bit is 0, it means that the memory area of the second byte in the memory is occupied. Since the first bit is 1 and the second bit is 0, when shifted left by 1 bit, the new first bit is 0. Performing an AND operation with the original first bit 1, the updated first bit obtained is 0. Therefore, this 0 can inversely indicate that the original second bit or the original first bit is 0. Then, the memories corresponding to the original first bit and the second bit are not two consecutive idle areas, so they cannot be used as the memory to be allocated to the memory applicant.

[0060] When 128 bytes of memory are applied for, offsets of 1, 2, 4, 8, 16, 32, and 64 are performed. After 7 offsets with the above offset values, in the final first register value, each bit that is 1 can represent a corresponding consecutive 128-byte idle memory. Then, based on this first register value, the memory address obtained through encoding is the memory address that can be used for allocation, and starting from this memory address, there is 128 bytes of idle memory.

[0061] In addition, it can be understood that the preset register F or the temporary register based on the above iterative offset can only perform arithmetic functions. Additionally, a dedicated memory management register R can be set. The bits of the memory management register R directly represent the idle or occupied state of the corresponding memory. Before starting the offset, set the temporary register F = R, so as to first assign a value to the temporary register, and then complete the iterative offset and arithmetic based on the bits of the already assigned temporary register.

[0062] In summary, in the embodiments of the present invention, the first memory capacity to be applied for is obtained, the first offset sequence corresponding to the first memory capacity is determined. Starting from the first offset value in the first offset sequence, according to the first offset value, the bits of the preset register are offset, and based on the register value before the offset and the register value after the offset, a register update value is obtained. Based on the register update value, continue the next offset until the first offset sequence is traversed, and the final first register value is determined. The first register value is encoded to obtain the starting address to be allocated corresponding to the first register value. It is possible to calculate and determine the idle memory corresponding to the first memory capacity and the starting address of the idle memory based on the offset update of the bits of the register, realizing memory application at the hardware level. Since the hardware processing speed is fast, the efficiency of memory management is improved.

[0063] Figure 2 It is a step diagram of another memory management method provided by the embodiments of the present invention. The method includes:

[0064] Step 201: Obtain the first memory capacity to be applied for, and determine the first offset sequence corresponding to the first memory capacity; there is a positive correlation between the first memory capacity and the number of offsets in the first offset sequence; the offsets in the first offset sequence have an increasing relationship;

[0065] Step 202: Starting from the first offset in the first offset sequence, offset the bits of the preset register according to the first offset, and obtain a register update value based on the register value before offset and the register value after offset; the register value is determined by multiple bits of the register; each bit is used to indicate whether the corresponding memory area is in an idle state or an occupied state;

[0066] Step 203: Based on the register update value, continue the next offset until the first offset sequence is traversed, and determine the final first register value;

[0067] Step 204: Perform encoding processing on the first register value to obtain a first memory address corresponding to the first register value; the first memory address is the starting address to be allocated.

[0068] The specific content of the above steps 201 to 204 can be referred to the above Figure 1 Embodiment, which will not be elaborated here.

[0069] Optionally, after step 204 of performing encoding processing on the first register value to obtain a first memory address corresponding to the first register value, the method further includes:

[0070] Step 205: Perform decoding processing on the first memory address to obtain a second register value corresponding to the first memory address, and set the bits of the register based on the second register value;

[0071] Step 206: Determine a second offset sequence corresponding to the first memory capacity; there is a positive correlation between the first memory capacity and the number of offsets in the second offset sequence; the offsets in the second offset sequence have a decreasing relationship;

[0072] Step 207: Starting from the first offset of the second offset sequence, offset the bits of the register according to the first offset, and obtain a register update value based on the register value before offset and the register value after offset;

[0073] Step 208: Based on the register update value, continue the next offset until the second offset sequence is traversed, and determine the final third register value to set the memory area indicated by the first memory address and the first memory capacity to an occupied state.

[0074] In an embodiment of the present invention, when performing dynamic memory management, when the memory in a specific area has been applied for and allocated, it is necessary to mark the corresponding memory area to accurately track the state of the memory. In dynamic memory management, the memory may be in different states, such as occupied, free, etc. By marking, it is possible to know which memory blocks are being used and which are available for reallocation. Marking the memory can help determine the appropriate location for the next memory allocation. Additionally, if the memory is not marked correctly, it may cause the program to write data to the wrong location or access memory that has already been freed. For example, if a allocated memory block is not marked, the program may accidentally reallocate the memory block, resulting in the loss or overwriting of the data originally stored in it.

[0075] The first memory address for allocation to the memory requester has been determined. Therefore, it is necessary to mark the memory with the first memory capacity corresponding to the first memory address.

[0076] Since in the present invention, the free or occupied state of the memory is represented by the bit positions of a register, the bit positions of the register can be set to set a specific memory as the occupied state to complete the memory marking.

[0077] Perform a decoding process on the first memory address to obtain a second register value corresponding to the first memory address. For example, the first memory address can be 5, and the decoded second register value can be "0b11111011111111...", where 0b represents a binary number, and the ellipsis indicates that the specific number of bits of the second register value is not limited. In the second register value, 0 represents the occupied state, and 1 represents the free state. It should be noted that if the first memory address is 5, the first 5 bit positions of the second register value are 1, and the 6th bit is 0, indicating the occupied state (i.e., the memory is allocated).

[0078] The first memory capacity corresponds to a first offset sequence, and the first offset sequence is used to find the memory with the first memory capacity size that is in the free state. Similarly, based on the first memory capacity, a second offset sequence is determined, and the second offset sequence is used to mark the memory with the first memory capacity size as the occupied state.

[0079] There is also a positive correlation between the first memory capacity and the number of offsets in the second offset sequence. The number of offsets in the second offset sequence can be calculated based on the same formula used to calculate the first offset sequence. However, the offsets in the second offset sequence can be decreasing, or decreasing based on powers of two. For example, if the number of offsets in the second offset sequence is also seven, they can be 64, 32, 16, 8, 4, 2, and 1.

[0080] Similarly, starting from the first offset of the second offset sequence, based on the first offset, the bits of the offset register, and the register values before and after the offset, a register update value is obtained through an AND operation.

[0081] The difference between the memory marking stage and the memory application stage is that the offset is decreasing instead of increasing. A decreasing offset means that the initial offset is based on a larger offset, which can avoid duplication when setting bits to 0 and improve the memory marking efficiency. Additionally, in the memory marking stage, the bit shift can be a right shift, and the value shifted into the left side can be 1. The process of each offset in the memory marking stage will not be elaborated here.

[0082] After traversing the second offset sequence, the memory with the first memory capacity corresponding to the first memory address can be marked as occupied, thus completing the memory marking. Similarly, since the preset register F can be only used for iterative offset and operation, after traversing the second offset sequence, for the preset register F and the memory management register R. Through R = R&F, an AND operation is performed between the register value of the preset register F and the register value of the memory management register R. After traversing the second offset sequence, among the register values of the preset register F, the bits corresponding to the allocated memory are 0. After the AND operation, the corresponding bits of the memory management register R will also be set to 0, thus completing the marking.

[0083] For example, if the first memory address is A and the first memory capacity to be marked is 128 bytes, the following iterative process needs to be completed successively in 7 clock pulses:

[0084] Clock 1: F = F&(F>>64)

[0085] Clock 2: F = F&(F>>32)

[0086] Clock 3: F = F&(F>>16)

[0087] Clock 4: F = F&(F>>8)

[0088] Clock 5: F = F&(F>>4)

[0089] Clock 6: F = F&(F>>2)

[0090] Clock 7: F = F&(F>>1)

[0091] In the above process, for Clock 1, ">>64" means a right shift of 64 bits, (F>>64) is the register value after the right shift, and "F&(F>>64)" means an AND operation between the register value after the offset and the register value before the offset.

[0092] After the 7th clock, all 128 bits of register F starting from position A are set to 0. Finally, let R = R & F, thus completing the memory marking and setting the occupancy status of the corresponding memory.

[0093] Implementing the embodiments of the present invention, decoding the first memory address to obtain a second register value, setting the bits of the register based on the second register value, determining a second offset sequence, starting from the first offset of the second offset sequence, offsetting the bits of the register until traversing the second offset sequence is completed, and determining a final third register value to set the memory area jointly indicated by the first memory address and the first memory capacity to the occupied state. It can realize fast memory marking at the hardware level based on the iterative offset and operation of the bits of the register, thereby improving the memory management efficiency.

[0094] Optionally, the method further includes:

[0095] Step 209, obtaining a second memory address and a second memory capacity to be released, and determining a third offset sequence corresponding to the second memory capacity; there is a positive correlation between the second memory capacity and the number of offsets in the third offset sequence; the offsets in the third offset sequence have a decreasing relationship;

[0096] Step 210, decoding the second memory address to obtain a fourth register value corresponding to the second memory address, and setting the bits of the register based on the fourth register value;

[0097] Step 211, starting from the first offset of the third offset sequence, offsetting the bits of the register according to the first offset, and obtaining a register update value based on the register value before the offset and the register value after the offset;

[0098] Step 212, based on the register update value, continuing the next offset until traversing the third offset sequence is completed, and determining a final fourth register value to set the memory area jointly indicated by the second memory address and the second memory capacity to the free state.

[0099] In the embodiments of the present invention, when an application program or a software module of its operating system has completed the use of a piece of memory and no longer needs to access the data stored in the memory subsequently, it is necessary to release the memory, that is, set the memory to the free state. Releasing the memory can avoid memory leaks and ensure the effective utilization of system resources. If not released in time, it will cause the program to occupy the memory throughout the running period.

[0100] A memory release request generated by an application or other memory user can be obtained. The second memory address and the second memory capacity to be released in the memory release request. The second memory address indicates the starting address of the memory to be released, and the second memory capacity represents the size of the memory to be released starting from the starting address.

[0101] Similarly, a third offset sequence corresponding to the second memory capacity is determined. The determination process of the third offset sequence can be similar to that of the second offset sequence. The offsets in the third offset sequence can be decreasing, and the rest will not be elaborated.

[0102] Based on the second memory address to be released, decoding processing is performed on the second memory address to obtain a fourth register value corresponding to the second memory address.

[0103] Among them, there are some differences between the decoding of the second memory address and the decoding of the first memory address. Since decoding based on the first memory address is for memory marking, if the first memory address is, for example, 5, the register value obtained by decoding can be, for example, "0b1111101111...", where the bit 0 serves to mark the memory as occupied (if 0 represents occupied and 1 represents free). However, the second memory address is used for memory release. Therefore, if the second memory address is 5, the register value obtained by decoding can be, for example, "0b000001000...", where the bit 1 serves to release the memory, that is, set the memory to the free state.

[0104] For example, according to the second memory capacity to be released of 128 bytes, the following calculations need to be completed successively in 7 clock pulses:

[0105] The 1st clock: F = F | (F>>64)

[0106] The 2nd clock: F = F | (F>>32)

[0107] The 3rd clock: F = F | (F>>16)

[0108] The 4th clock: F = F | (F>>8)

[0109] The 5th clock: F = F | (F>>4)

[0110] The 6th clock: F = F | (F>>2)

[0111] The 7th clock: F = F&(F>>1)

[0112] In the above process, the second memory address is A. After the 7th clock, all 128 bits starting from the position A in register F are set to 1. Finally, let register R = R | F, which completes the idle marking to release the memory for the next memory application. Here, "|" is the bitwise OR operator, which is a bitwise operation operator used to perform a logical OR operation on each bit of two operands.

[0113] In an embodiment of the present invention, the second memory address and the second memory capacity to be released are obtained, the third offset sequence is determined, the second memory address is decoded to obtain the fourth register value corresponding to the second memory address, and the bits of the register are set based on the fourth register value. Starting from the first offset of the third offset sequence, the bits of the register are offset until the third offset sequence is traversed, and the final fourth register value is determined to set the memory area jointly indicated by the second memory address and the second memory capacity to the idle state, thereby completing the memory release. It is possible to perform iterative offset and operation based on the bits of the register to achieve fast memory release at the hardware level, and thus improve the memory management efficiency.

[0114] The process of bitwise operation in the above memory application stage, memory marking stage, and memory release stage actually corresponds to the gradual aggregation and expansion of a binary tree with a specific structure, which has the advantages of simple structure and high efficiency. Therefore, it can improve the processing speed of memory application, memory marking, and memory release, and thus improve the memory management efficiency as a whole.

[0115] Optionally, step 201 of obtaining the first memory capacity to be applied and determining the first offset sequence corresponding to the first memory capacity includes:

[0116] Sub-step 2011, determining the mapped memory capacity corresponding to each bit of the register; the mapped memory capacity represents the memory size corresponding to each bit.

[0117] Sub-step 2012, determining the memory application quantity according to the first memory capacity and the mapped memory capacity.

[0118] Sub-step 2013, determining the target offset quantity corresponding to the memory application quantity, and determining the first offset sequence including the target offset quantity of offsets.

[0119] In an embodiment of the present invention, the memory capacity size corresponding to each bit is the same, all being equal mapped memory capacities. For example, each bit corresponds to one byte or multiple bytes. The larger the mapped memory capacity corresponding to each bit, the larger the memory capacity that can be managed. When the mapped memory capacity corresponding to each bit is smaller, although the memory capacity that can be managed is smaller, the management fineness is higher.

[0120] The memory application quantity can be determined based on the first memory capacity and the mapped memory capacity corresponding to each bit. The memory application quantity is also the corresponding number of bits. The memory application quantity indicates how many consecutive bits need to be 1 (if the bit being 1 represents the idle state). For example, if the first memory capacity is 128 bytes and the mapped memory capacity is 1 byte, then the memory application quantity is 128, and 128 consecutive bits that are 1 need to be screened out.

[0121] Therefore, by determining the target offset quantity corresponding to the memory application quantity, a first offset sequence including the target offset quantity of offsets can be determined. For example, if the first memory capacity is 128 bytes, a first offset sequence including 7 offsets, namely 1, 2, 4, 8, 16, 32, and 64, is finally determined.

[0122] By implementing the embodiments of the present invention, by determining the mapped memory capacity corresponding to each bit of the register, determining the memory application quantity according to the first memory capacity and the mapped memory capacity, determining the corresponding target offset quantity, and determining a first offset sequence including the target offset quantity of offsets, the memory application quantity and the first offset sequence can be flexibly determined according to the mapped memory capacity corresponding to the bit. The larger the mapped memory capacity, the larger the memory capacity that can be managed; the smaller the mapped memory capacity, the higher the fineness of memory management, thereby improving the flexibility of memory management.

[0123] Since the offsets in the offset sequence are all obtained based on powers of two, when applying for memory and searching for or screening idle memory, the idle memory also needs to be determined according to powers of two. However, the memory required by the memory applicant does not necessarily exactly conform to powers of two. For example, when applying for 100 bytes, but when determining the available idle memory, in order to meet the requirement of 100 bytes, at least 128 bytes of idle memory need to be determined, so it is easy to cause the problem of memory space waste.

[0124] Optionally, step 201 of obtaining the first memory capacity to be applied and determining the first offset sequence corresponding to the first memory capacity includes:

[0125] Sub-step 2014: Obtain the first memory capacity to be applied, split the first memory capacity into at least two sub-memory capacities, and respectively determine the sub-offset sequences corresponding to each sub-capacity;

[0126] Sub-step 2015: The step of encoding the first register value to obtain the first memory address to be allocated corresponding to the first register value includes:

[0127] Sub-step 2016: Perform encoding processing on the sub-register values corresponding to each sub-offset sequence to obtain sub-memory addresses respectively corresponding to each sub-register value; each sub-memory address is a starting address to be allocated.

[0128] In an embodiment of the present invention, when obtaining the first memory capacity, it can be additionally determined whether the first memory capacity conforms to a power of two, so as to perform the next capacity splitting. For example, if the first memory capacity is 100 bytes, which does not conform to a power of two, 100 bytes can be split into 64 bytes, 32 bytes, and 4 bytes, that is, 4 sub-memory capacities, and each sub-memory capacity conforms to a power of two, thereby avoiding waste of memory space.

[0129] Similarly, based on each sub-memory capacity, determine their respective corresponding sub-offset sequences, and based on the sub-offset sequences, perform offset, and also obtain their respective sub-register values and perform encoding processing to obtain sub-memory addresses corresponding to each sub-memory capacity. Each sub-memory address is a starting address to be allocated. Based on each sub-memory address and the corresponding value memory capacity, memory to be allocated of different sizes can be determined.

[0130] Implementing the embodiments of the present invention, by obtaining the first memory capacity to be applied, splitting the first memory capacity into at least two sub-memory capacities, respectively determining the sub-offset sequences of each sub-capacity, and performing encoding processing on the sub-register values corresponding to each sub-offset sequence to obtain sub-memory addresses respectively corresponding to each sub-register value, it is possible to split the applied first memory capacity, respectively determine different memory to be allocated, avoid or reduce waste of memory space, and improve the accuracy of memory management.

[0131] Optionally, step 204 of performing encoding processing on the first register value to obtain the first memory address to be allocated corresponding to the first register value includes:

[0132] Sub-step 2041: Determine the number of leading zeros of the first register value; the number of leading zeros represents the number of consecutive zeros starting from the highest bit of the first register value;

[0133] Sub-step 2042: Based on the number of leading zeros, determine the first memory address to be allocated corresponding to the first register value.

[0134] In an embodiment of the present invention, performing encoding processing on the first register value can be inputting the first register value into an encoder circuit, and the encoder circuit can be configured to calculate the number of leading zeros of the first register value. The number of leading zeros represents the number of consecutive zeros starting from the highest bit of the first register value. For example, if the first register value is "00001010010", then the number of leading zeros is 4.

[0135] Since each bit that is 1 in the first register value can represent free memory with a first memory capacity, the first memory address can be the number of leading zeros plus 1. For example, if the first register value is "00001010010", the number of leading zeros is 4, and the 5th bit being 1 represents free memory with a first memory capacity, then the first memory address can be 5.

[0136] Optionally, step 205 of decoding the first memory address to obtain a second register value corresponding to the first memory address includes:

[0137] Sub-step 2051: Based on the first memory address, determine a target bit in the register and set the target bit to a first preset value; the target bit being the first preset value indicates that the corresponding memory area is in an occupied state;

[0138] Sub-step 2052: Set the other bits except the target bit to a second preset value to determine the second register value after all the bits in the register are set; the other bits being the second preset value indicates that the corresponding memory area is in a free state.

[0139] In an embodiment of the present invention, when decoding the first memory address, a bit position can be obtained according to the first memory address, and then a target bit in the register is determined, and the target bit is set to the first preset value. Among them, since decoding the first memory address is to mark the memory as occupied, the first preset value can be 0 (a bit being 0 indicates that the memory is in an occupied state).

[0140] Set the other bits except the target bit to a second preset value, for example, 1 (a bit being 1 indicates that the memory is in a free state). After all the bits in the register are set, the second register value can be obtained.

[0141] It can be to input the first memory address into a decoder circuit to obtain the second register value output by the decoder circuit. Additionally, when decoding based on the second memory address, it can be similar to the process of decoding the second memory address. The difference is that the second memory address is an address for releasing memory. Therefore, based on the second memory address, the target bit determined to be the second preset value (for example, 1, indicating a free state) is set, and the other bits except the target bit are set to the first preset value (for example, 0, indicating an occupied state). The specific process is not elaborated here.

[0142] The memory management method of the present invention can perform the aggregation and expansion iteration of a binary tree through a specially designed bit operation structure and process, efficiently complete the search, allocation, and release of free memory, implement dynamic memory management, and can be used to implement complex circuit IP (Intellectual Property).

[0143] In fields such as automobiles and robots, due to the relatively high requirement for real-time performance, high-performance processors and software protocol stacks are usually used to complete communication protocol processing, increasing the hardware cost. Based on the memory management method of the present invention, a high-performance dedicated communication IP can be implemented, combined with a low-cost and low-speed processor, to reduce the overall system cost. It is also possible to develop a Controller Area Network (CAN) IP, which can support dynamic data unpacking and packet unpacking through the memory management method of the present invention, and can also implement an Ethernet-based fieldbus system (EtherCAT, Ethernet for Control Automation Technology) with enhanced hardware functions, supporting the parsing of variable-length data packet groups implemented in hardware.

[0144] It should be noted that for the method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the embodiments of the present invention are not limited by the described action sequence, because according to the embodiments of the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily essential for the embodiments of the present invention.

[0145] Device embodiments

[0146] Figure 3 It is a structural block diagram of a memory management device of the present invention. The device 30 includes:

[0147] An application sequence module 301, configured to obtain a first memory capacity to be applied for, and determine a first offset sequence corresponding to the first memory capacity; there is a positive correlation between the first memory capacity and the number of offsets in the first offset sequence; the offsets in the first offset sequence have an increasing relationship;

[0148] An iterative offset module 302, configured to start from the first offset in the first offset sequence, offset the bit positions of a preset register according to the first offset, and obtain a register update value based on the register value before offset and the register value after offset; the register value is determined by multiple bit positions of the register; each bit position is used to represent that the corresponding memory area is in an idle state or an occupied state;

[0149] The iterative result module 303 is configured to continue the next offset based on the register update value until the first offset sequence is traversed, and determine the final first register value;

[0150] The address allocation module 304 is configured to perform encoding processing on the first register value to obtain a first memory address corresponding to the first register value; the first memory address is the starting address to be allocated.

[0151] Optionally, the device further includes:

[0152] The memory marking module is configured to perform decoding processing on the first memory address to obtain a second register value corresponding to the first memory address, and set the bit of the register based on the second register value;

[0153] The marking sequence module is configured to determine a second offset sequence corresponding to the first memory capacity; there is a positive correlation between the first memory capacity and the number of offsets in the second offset sequence; the offsets in the second offset sequence have a decreasing relationship;

[0154] The first offset module is configured to start from the first offset of the second offset sequence, offset the bit of the register according to the first offset, and obtain a register update value based on the register value before the offset and the register value after the offset;

[0155] The marking completion module is configured to continue the next offset based on the register update value until the second offset sequence is traversed, and determine the final third register value to set the memory area indicated by the first memory address and the first memory capacity to an occupied state.

[0156] Optionally, the device further includes:

[0157] The release application module is configured to obtain a second memory address and a second memory capacity to be released, and determine a third offset sequence corresponding to the second memory capacity; there is a positive correlation between the second memory capacity and the number of offsets in the third offset sequence; the offsets in the third offset sequence have a decreasing relationship;

[0158] The decoding processing module is configured to perform decoding processing on the second memory address to obtain a fourth register value corresponding to the second memory address, and set the bit of the register based on the fourth register value;

[0159] The second offset module is configured to start from the first offset of the third offset sequence, offset the bit of the register according to the first offset, and obtain a register update value based on the register value before the offset and the register value after the offset;

[0160] A memory release module, configured to continue the next offset based on the updated value of the register until traversing the third offset sequence is completed, and determine a final fourth register value to set the memory area jointly indicated by the second memory address and the second memory capacity to an idle state.

[0161] Optionally, the application sequence module includes:

[0162] A mapped memory sub-module, configured to determine the mapped memory capacity corresponding to each bit of the register; the mapped memory capacity represents the memory size corresponding to each bit.

[0163] An application quantity sub-module, configured to determine the memory application quantity according to the first memory capacity and the mapped memory capacity.

[0164] A quantity sequence sub-module, configured to determine a target offset quantity corresponding to the memory application quantity, and determine a first offset sequence including the target offset quantity of offsets.

[0165] Optionally, the application sequence module includes:

[0166] An application splitting sub-module, configured to obtain the first memory capacity to be applied, split the first memory capacity into at least two sub-memory capacities, and respectively determine sub-offset sequences corresponding to each sub-capacity.

[0167] The address allocation module includes:

[0168] An address partitioning sub-module, configured to perform encoding processing on the sub-register values corresponding to each sub-offset sequence to obtain sub-memory addresses respectively corresponding to each sub-register value; each sub-memory address is a starting address to be allocated.

[0169] Optionally, the address allocation module includes:

[0170] A leading zero calculation sub-module, configured to determine the number of leading zeros of the first register value; the number of leading zeros represents the number of consecutive zeros starting from the highest bit of the first register value.

[0171] A leading address sub-module, configured to determine the first memory address to be allocated corresponding to the first register value based on the number of leading zeros.

[0172] Optionally, the memory marking module includes:

[0173] A target bit sub-module, configured to determine a target bit in the register based on the first memory address, and set the target bit to a first preset value; the target bit being the first preset value indicates that the corresponding memory area is in an occupied state.

[0174] An other bit position sub-module, configured to set other bit positions except the target bit position to a second preset value, so as to determine a second register value after all bit positions of the register are set; that the other bit positions are the second preset value indicates that the corresponding memory area is in an idle state.

[0175] For the apparatus embodiments, since they are basically similar to the method embodiments, the description is relatively simple. For related parts, please refer to the partial description of the method embodiments.

[0176] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0177] Regarding the processor in the above embodiments, the specific manners for each module to execute operations have been described in detail in the embodiments related to the method, and will not be elaborated here.

[0178] Referring to Figure 4 , which is a structural block diagram of an electronic device for memory management provided by an embodiment of the present invention. As Figure 4 shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete communication with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions cause the processor to execute the memory management method of the foregoing embodiments.

[0179] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor may also be a combination for implementing a computing function, such as a combination including one or more microprocessors, a combination of a DSP and a microprocessor.

[0180] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The communication bus may be divided into an address bus, a data bus, and a control bus. For the sake of representation, Figure 4 only one line is used in Figure 4 , but it does not mean that there is only one bus or one type of bus.

[0181] The memory may be a ROM (Read Only Memory), or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory), or other types of dynamic storage devices that can store information and instructions. It may also be an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory), magnetic tape, a floppy disk, and optical data storage devices.

[0182] The embodiments of the present invention also provide a non-transitory readable storage medium. When the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), the processor can execute Figure 2 the memory management method shown.

[0183] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0184] Those skilled in the art should understand that the embodiments of the present invention can be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention can take the form of completely hardware embodiments, completely software embodiments, or embodiments combining software and hardware aspects. Moreover, the embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (which may include disk memory, CD-ROM, optical memory) containing computer-usable program code.

[0185] Embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, and the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processors of general-purpose computers, special-purpose computers, embedded processors, or other programmable memory management terminal devices to generate a machine, such that the instructions executed by the processors of the computer or other programmable memory management terminal devices generate means for implementing the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 or multiple blocks.

[0186] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable memory management terminal device to work in a predictive manner, such that the instructions stored in the computer-readable memory generate a manufactured article including instruction means that implement the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 or multiple blocks.

[0187] These computer program instructions can also be loaded onto a computer or other programmable memory management terminal device, such that a series of operation steps are executed on the computer or other programmable terminal device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable terminal device provide means for implementing the functional steps specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 or multiple blocks.

[0188] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications to these embodiments upon learning the basic creative concepts. The appended claims are intended to be construed as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0189] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or terminal device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or terminal device comprising the element.

[0190] The above has introduced in detail a memory management method, device, electronic device and readable storage medium provided by the present invention. Specific examples are used in this text to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A memory management method, characterized in that: The method comprises: Obtain a first memory capacity to be applied for, and determine a first offset sequence corresponding to the first memory capacity; there is a positive correlation between the first memory capacity and the number of offsets in the first offset sequence, and the number of offsets is a logarithm of 2 to the base N, where N is the size of the first memory capacity; there is an increasing relationship between the offsets in the first offset sequence, and they increase from 1; and each offset is a power of two; Starting from the first offset in the first offset sequence, the bits of the preset register are offset according to the first offset, and an AND operation is performed based on the register value before the offset and the register value after the offset to obtain a register update value; the register value is determined by multiple bits of the register; each bit is used to indicate that the corresponding memory area is in an idle state or an occupied state; Based on the register update value, continue the next offset until the first offset sequence is traversed and a final first register value is determined; The first register value is encoded to obtain a first memory address corresponding to the first register value; the first memory address is a starting address to be allocated.

2. The method according to claim 1, characterized in that After the step of encoding the first register value to obtain a first memory address corresponding to the first register value, the method further includes: Decoding the first memory address to obtain a second register value corresponding to the first memory address, and setting a bit of the register based on the second register value; Determine a second offset sequence corresponding to the first memory capacity; there is a positive correlation between the first memory capacity and the number of offsets in the second offset sequence; there is a decreasing relationship between the offsets in the second offset sequence; Starting from a first offset of the second offset sequence, shifting the bits of the register according to the first offset, and obtaining a register update value based on a register value before the shift and a register value after the shift; Based on the register update value, the next offset is continued until the second offset sequence is traversed and completed, and a final third register value is determined to set the memory area indicated by the first memory address and the first memory capacity to an occupied state.

3. The method according to claim 1, characterized in that The method further comprises: Acquire a second memory address and a second memory capacity to be released, and determine a third offset sequence corresponding to the second memory capacity; there is a positive correlation between the second memory capacity and the number of offsets in the third offset sequence; there is a decreasing relationship between the offsets in the third offset sequence; Decoding the second memory address to obtain a fourth register value corresponding to the second memory address, and setting a bit of the register based on the fourth register value; Starting from a first offset of the third offset sequence, shifting the bits of the register according to the first offset, and obtaining a register update value based on a register value before the shift and a register value after the shift; Based on the register update value, the next offset is continued until the third offset sequence is traversed and completed, and a final fourth register value is determined to set the memory area indicated by the second memory address and the second memory capacity to an idle state.

4. The method according to claim 1, characterized in that: The step of obtaining the first memory capacity to be applied for and determining a first offset sequence corresponding to the first memory capacity includes: Determine a mapped memory capacity corresponding to each bit of the register; the mapped memory capacity indicates a memory size corresponding to each bit; Determining a memory application quantity according to the first memory capacity and the mapped memory capacity; A target offset number corresponding to the memory application number is determined, and a first offset sequence including the target offset number of offsets is determined.

5. The method according to claim 1, characterized in that The step of obtaining the first memory capacity to be applied for and determining a first offset sequence corresponding to the first memory capacity includes: Acquire a first memory capacity to be applied for, split the first memory capacity into at least two sub-memory capacities, and respectively determine a sub-offset sequence corresponding to each sub-capacity; The step of encoding the first register value to obtain a first memory address to be allocated corresponding to the first register value includes: The sub-register value corresponding to each sub-offset sequence is encoded to obtain a sub-memory address corresponding to each sub-register value; each sub-memory address is a starting address to be allocated.

6. The method according to claim 1, characterized in that The step of encoding the first register value to obtain a first memory address to be allocated corresponding to the first register value includes: Determine the number of leading zeros of the first register value; the number of leading zeros represents the number of bits that are consecutively zero starting from the most significant bit of the first register value; Based on the number of leading zeros, a first memory address to be allocated corresponding to the first register value is determined.

7. The method according to claim 2, characterized in that The step of decoding the first memory address to obtain a second register value corresponding to the first memory address includes: Based on the first memory address, determine a target bit in the register, and set the target bit to a first preset value; the target bit being the first preset value indicates that the corresponding memory area is in an occupied state; The other bits except the target bit are set to a second preset value to determine a second register value after all the bits of the register are set; the other bits being the second preset value indicates that the corresponding memory area is in an idle state.

8. A memory management device, characterized in that: The device comprises: an application sequence module, configured to obtain a first memory capacity to be applied for, and determine a first offset sequence corresponding to the first memory capacity; a positive correlation exists between the first memory capacity and the number of offsets in the first offset sequence, and the number of offsets is a logarithm of 2 to the base N, where N is the size of the first memory capacity; an increasing relationship exists between the offsets in the first offset sequence, and they increase from 1; and each offset is a power of two; An iterative offset module, used to start from the first offset in the first offset sequence, offset the bits of the preset register according to the first offset, and perform an AND operation based on the register value before the offset and the register value after the offset to obtain a register update value; the register value is determined by multiple bits of the register; each bit is used to indicate that the corresponding memory area is in an idle state or an occupied state; An iteration result module, configured to update the register value, continue the next offset until the first offset sequence is traversed and completed, and determine a final first register value; The address allocation module is used to encode the first register value to obtain a first memory address corresponding to the first register value; the first memory address is a starting address to be allocated.

9. An electronic device, characterized in that: The electronic device comprises a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store executable instructions, and the executable instructions enable the processor to execute the memory management method according to any one of claims 1 to 7.

10. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the processor is enabled to execute the memory management method as described in any one of claims 1 to 7.

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