Clock detection device and method

Abstract

The invention relates to a clock detection device, a clock detection method, electronic equipment and a vehicle. According to a clock detection device, a first clock signal and a second clock signal are input, and the first clock signal serves as an initial system clock signal. The clock detection device comprises a detection module which performs failure detection on a first clock signal according to an internal clock signal and generates a detection flag bit; the switching module is used for determining whether to switch the system clock signal from the first clock signal to the second clock signal according to the detection flag bit; the exception handling module comprises a detection sub-module which is used for performing failure detection on the second clock signal according to the internal clock signal under the condition that the system clock signal is switched to the second clock signal; and the reset sub-module triggers the reset of the signal source of the second clock signal under the condition that the failure of the second clock signal is detected.

Description

Technical Field

[0001] The present disclosure relates to the field of circuits, and in particular to a clock detection device, a clock detection method, an electronic device, a programmable logic device and a vehicle. Background Art

[0002] In some scenarios, a circuit system uses an external crystal oscillator as a clock source to obtain a clock signal and operate. However, when such an external clock source fails, how to keep the circuit system operating becomes a challenge. Summary of the invention

[0003] In view of the above problems, the present disclosure aims to provide a clock detection device, a clock detection method, an electronic device, a programmable logic device and a vehicle.

[0004] The clock detection device of the first aspect of the present disclosure inputs a first clock signal and a second clock signal, wherein the first clock signal is used as an initial system clock signal, and the clock detection device comprises:

[0005] A detection module, which performs failure detection on the first clock signal according to the internal clock signal and generates a detection flag;

[0006] A switching module, which determines whether to switch the system clock signal from the first clock signal to the second clock signal according to the detection flag bit;

[0007] The exception handling module includes: a detection submodule, which performs failure detection on the second clock signal according to the internal clock signal when the system clock signal is switched to the second clock signal; and a reset submodule, which triggers the reset of the signal source of the second clock signal when the failure of the second clock signal is detected.

[0008] According to the clock detection device of some embodiments of the present disclosure, optionally, the exception handling module is further configured to: when the detection module detects that the first clock signal fails and the second clock signal is not sent, wait for a first time period and then perform failure detection on the second clock signal based on the internal clock signal.

[0009] According to the clock detection device of some embodiments of the present disclosure, optionally, the exception handling module is further configured to: after resetting the clock source of the second clock signal, wait for a second time period, and then perform failure detection on the second clock signal based on the internal clock signal.

[0010] According to the clock detection device of some embodiments of the present disclosure, optionally, the exception handling module is further configured to: shut down the operation of the exception handling module when it is detected that the watchdog timer is shut down.

[0011] According to the clock detection apparatus of some embodiments of the present disclosure, optionally, the exception handling module is further configured to: shut down the operation of the exception handling module during a reset operation of the clock source of the second clock signal.

[0012] According to the clock detection device of some embodiments of the present disclosure, optionally, the clock detection device is further configured to: after shutting down the exception handling module, when the watchdog timer works normally and detects that the first clock signal fails, start the exception handling module and trigger the reset of the clock source of the second clock signal.

[0013] According to the clock detection device of some embodiments of the present disclosure, optionally, the switching module includes a selector, and the selector selects one of the first clock signal and the second clock signal as the system clock signal according to the detection flag bit.

[0014] According to the clock detection device of some embodiments of the present disclosure, optionally, the switching module is further configured to: execute switching when a first condition is met, and not execute switching when the first condition is not met.

[0015] According to the clock detection device of some embodiments of the present disclosure, optionally, the clock detection device is arranged in a vehicle, the first condition is a voltage threshold condition, and the switching module is further configured to: perform switching when the bus voltage of the vehicle is lower than the voltage threshold, and not perform switching when the bus voltage of the vehicle is higher than the voltage threshold.

[0016] According to the clock detection device of some embodiments of the present disclosure, optionally, the generation of the detection flag further includes: the detection module samples the first clock signal a corresponding number of times according to the number of edge changes of the internal clock signal, and performs an XOR operation on every two consecutive samples; if the XOR calculation is not set, a cumulative count is performed once; if the XOR calculation is set, the count is cleared to zero; when the count reaches a first preset threshold, the detection flag is flipped to indicate that the first clock signal has failed.

[0017] The clock detection method of the second aspect of the present disclosure, the first clock signal is used as the initial system clock signal, the method comprises: S101: performing failure detection on the first clock signal according to the internal clock signal, and generating a detection flag; S102: determining whether to switch the system clock signal from the first clock signal to the second clock signal according to the detection flag; S103: in the case where the system clock signal is switched to the second clock signal, performing failure detection on the second clock signal according to the internal clock signal; and S104: triggering a reset of the clock source of the second clock signal when failure of the second clock signal is detected.

[0018] According to the clock detection method of some embodiments of the present disclosure, optionally, the method further comprises: when it is detected that the first clock signal fails and the second clock signal is not sent, waiting for a first time period and then performing steps S103 and S104.

[0019] According to the clock detection method of some embodiments of the present disclosure, optionally, the method further includes: after resetting the clock source of the second clock signal, waiting for a second time period, and then performing failure detection on the second clock signal based on the internal clock signal.

[0020] According to the clock detection method of some embodiments of the present disclosure, optionally, the method further includes: when it is detected that the watchdog timer is turned off, not performing steps S103 and S104.

[0021] According to the clock detection method of some embodiments of the present disclosure, optionally, the method further includes: during the reset operation of the clock source of the second clock signal, steps S103 and S104 are not performed.

[0022] According to the clock detection method of some embodiments of the present disclosure, optionally, the method further includes: triggering a reset of a clock source of a second clock signal when a watchdog timer operates normally and detects that the first clock signal fails.

[0023] According to the clock detection method of some embodiments of the present disclosure, optionally, the method further includes: executing step S102 when a first condition is met, and not executing step S102 when the first condition is not met.

[0024] According to the clock detection method of some embodiments of the present disclosure, optionally, step S101 further includes: sampling the first clock signal a corresponding number of times according to the number of edge changes of the internal clock signal, and performing an XOR operation on every two consecutive samples, if the XOR calculation is not set, performing a cumulative count once, if the XOR calculation is set, clearing the count to zero, and when the count reaches a first preset threshold, flipping the detection flag to indicate that the first clock signal has failed.

[0025] The electronic device according to the third aspect of the present disclosure includes a processor and a memory, wherein the memory stores instructions, and when the instructions are executed by the processor, the clock detection method according to any of the above items is implemented.

[0026] A fourth aspect of the present disclosure is a vehicle, which includes a clock detection device according to any of the foregoing embodiments, or includes an electronic device according to any of the foregoing embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A module diagram of a clock detection device 100 according to some embodiments is shown.

[0028] Figure 2 A schematic diagram of the circuit structure of the switching module 120 according to some embodiments is shown.

[0029] Figure 3 A schematic flow chart of a clock detection method according to some embodiments is shown.

[0030] Figure 4 A schematic diagram of state management of an exception handling module according to some embodiments is shown. DETAILED DESCRIPTION

[0031] The following describes some of the various embodiments of the present disclosure, which are intended to provide a basic understanding of the present disclosure, but are not intended to identify the key or decisive elements of the present disclosure or to limit the scope of protection.

[0032] For brevity and illustrative purposes, the principles of the present disclosure are described herein mainly with reference to its exemplary embodiments. However, those skilled in the art will readily recognize that the same principles are equally applicable to and can be implemented in all types of clock detection devices, clock detection methods, electronic devices, programmable logic devices, and vehicles, and any such changes do not depart from the true spirit and scope of the present patent application.

[0033] Moreover, in the following description, reference is made to the accompanying drawings, which illustrate specific exemplary embodiments. Electrical, mechanical, logical and structural changes may be made to these embodiments without departing from the spirit and scope of the present disclosure. In addition, although the features of the present disclosure are disclosed in conjunction with only one of several implementations / embodiments, this feature may be combined with one or more other features of other implementations / embodiments as may be desired and / or advantageous for any given or identifiable function. Therefore, the following description should not be regarded as limiting, and the scope of the present disclosure is defined by the appended claims and their equivalents.

[0034] Terms such as “having” and “including” indicate that in addition to the units (modules) and steps directly and explicitly stated in the specification and claims, the technical solution of the present disclosure does not exclude the situation where it has other units (modules) and steps that are not directly or explicitly stated.

[0035] Figure 11 is a schematic diagram of a clock detection device 100 according to some embodiments of the present disclosure. The clock detection device 100 inputs a first clock signal CLK1 and a second clock signal CLK2, and the first clock signal CLK1 is used as an initial system clock signal. The clock detection device 100 may include a detection module 110, a switching module 120, and an exception handling module 130. The exception handling module 130 may include a detection submodule 132 and a reset submodule 134. Figure 1 , the first clock signal CLK1 is input as the initial system clock signal into the detection module 110 and the switching module 120 in the circuit, and the second clock signal CLK2 is input into the switching module 120 and / or the exception handling module 130, and the switching module 120 selects one of the first clock signal CLK1 and the second clock signal CLK2 (the first clock signal CLK1 is initially selected) as the clock signal used by the functional module. Among them, the functional module may include any module that undertakes one or some functions and needs to input a clock signal, for example, including some programmable logic blocks (such as field programmable gate array FPGA) or sub-blocks or some functional devices / equipment. And among them, the first clock signal CLK1 may be, for example, a stable external clock signal provided by an external crystal oscillator.

[0036] The detection module 110 performs failure detection on the first clock signal CLK1 according to the internal clock signal CLK3, and generates a detection flag D. Among them, the internal clock signal CLK3 is a clock signal provided inside the circuit, which can play a role when all external clock signals are invalid or cannot be provided. The internal clock signal CLK3 has a higher frequency than the first clock signal CLK1 and the second clock signal CLK2, for example, a frequency equivalent to 2-100 times that of the first clock signal CLK1 and the second clock signal CLK2. The detection module 110 can be configured to perform failure detection on the first clock signal CLK1 according to the internal clock signal CLK3, and after detecting that the first clock signal CLK1 fails or does not fail, generate a detection flag to indicate that the first clock signal CLK1 fails or does not fail. For example, the detection module 110 generates a low level "0" to indicate that the first clock signal CLK1 fails, and generates a high level "1" to indicate that the first clock signal CLK1 does not fail. In some examples, the failure of the clock signal may include an irregular shape of the clock signal, such as being at a high level or a low level for a long time, an abnormal duty cycle, and the like.

[0037] The switching module 120 determines whether to switch the system clock signal from the first clock signal CLK1 to the second clock signal CLK2 according to the detection flag D. The switching module 120 can determine whether to switch from the first clock signal CLK1 to the second clock signal CLK2 according to the detection flag D transmitted by the detection module 110. For example, when the detection flag indicates that the first clock signal CLK1 is invalid, the switching module 120 selects the second clock signal CLK2 and outputs it to the functional module, so that the second clock signal CLK2 continues to bear the clock signal input of the functional module (i.e., as the system clock signal). In addition, corresponding to the second clock signal CLK2 from the MCU, for example, it can be multiplied by the phase-locked loop PLL module 140 and then input to the switching module 120. In addition, the clock signal (the first clock signal CLK1 or the second clock signal CLK2) output by the switching module 120 can be further multiplied by the phase-locked loop PLL module 150 and then output to the functional module.

[0038] The exception handling module 130 may at least include the functions of detecting the second clock signal CLK2 and resetting the clock source of the second clock signal CLK2 when the second clock signal CLK2 fails. Among them, the detection submodule 132 performs failure detection on the second clock signal CLK2 according to the internal clock signal CLK3 when the system clock signal is switched to the second clock signal CLK2. When the switching module 120 switches to the second clock signal CLK2, it may transmit a signal to indicate the exception handling module 130 (such as Figure 1 ), the detection submodule 132 can start to perform failure detection on the second clock signal CLK2 based on the internal clock signal CLK3. The failure detection mechanism can be similar to the failure detection mechanism of the detection module 110 on the first clock signal CLK1, but can also be different. The result of the failure detection can be transmitted to the exception handling module 130 or its reset submodule 134 for further processing. In addition, in other examples, the state of the exception handling module 130 performing the failure detection on the second clock signal CLK2 based on the internal clock signal CLK3 can be recorded as state S1.

[0039] The reset submodule 134 resets the clock source of the second clock signal CLK2 when it is detected that the second clock signal CLK2 fails. Wherein, the second clock signal CLK2 can be provided by the main control unit MCU, so the clock source is the MCU in some examples. Thus, the clock source of the second clock signal CLK2 can be reset in time when the second clock signal CLK2 also fails, so that the circuit (such as a functional module) can restore the clock signal input as soon as possible. In addition, in other examples, the state of the exception handling module 130 when the reset operation of the clock source of the second clock signal CLK2 is triggered can be recorded as state S2.

[0040] In some embodiments, the exception handling module 130 or its reset submodule 134 can be further configured to: when the detection module 110 detects that the first clock signal CLK1 is invalid and the second clock signal CLK2 is not sent, wait for the first time period T1, and then perform failure detection on the second clock signal CLK2 according to the internal clock signal CLK3. When the first clock signal CLK1 is invalid, the second clock signal CLK2 may not be sent (for example, because the clock source of the second clock signal CLK2 is still in the power-on stage), so it can wait for a certain time period T1, so that the second clock signal CLK2 is successfully sent or the detection submodule 132 successfully receives the second clock signal CLK2, and then perform failure detection on the second clock signal CLK2. Among them, the time period T1 can be a time period of milliseconds, such as 5-200ms. In this way, it can avoid the result that the detection submodule 132 erroneously detects the failure of the second clock signal CLK2 because the second clock signal CLK2 has not been received by the detection submodule 132. In addition, in some other examples, the state of the abnormality processing module 130 when the detection module 110 detects that the first clock signal CLK1 is invalid and the second clock signal CLK2 is not issued can be recorded as state S0.

[0041] In some embodiments, the exception handling module 130 or its reset submodule 134 may be further configured to: after resetting the clock source of the second clock signal CLK2, wait for a second time period T2, and then perform a failure detection on the second clock signal CLK2 according to the internal clock signal CLK3. In some examples, during the reset period, the clock source of the second clock signal CLK2 cannot normally provide the second clock signal CLK2, so a certain time period T2 may be waited so that the second clock signal CLK2 is normally provided or the detection submodule 132 normally receives the second clock signal CLK2, and then the failure detection on the second clock signal CLK2 is performed. In this way, the result that the detection submodule 132 erroneously detects the failure of the second clock signal CLK2 due to the failure of the second clock signal CLK2 to be normally provided during the reset of the clock source can be avoided. In addition, in other examples, the state of the clock detection device 100 in the second time period T2 waited after the reset of the clock source of the second clock signal CLK2 is triggered can be recorded as state S3.

[0042] In some embodiments, the exception handling module 130 can be further configured to: when the watchdog timer is detected to be turned off (or the watchdog state is turned off), turn off the operation of the exception handling module 130 itself. The watchdog timer can be reset regularly when the circuit or system is operating normally. If the circuit or system fails to reset the timer on time due to some reasons (such as dead loop, infinite waiting, etc.), the timer will automatically trigger a reset after expiration, so that the circuit or system restarts and attempts to resume normal operation. Therefore, the watchdog timer can be used to monitor the operating status of the circuit or ECU / MCU to ensure that it will not fall into a dead loop or a long-term unresponsive state. The watchdog timer can be turned off, for example, because the MCU is performing a flash operation, or because the MCU is in a reset operation period, etc. Therefore, the monitoring and detection of the second clock signal provided by the MCU can be temporarily turned off, or the operation of the entire exception handling module 130 can be temporarily turned off to avoid triggering unnecessary resets due to the detection of clock failure by the detection submodule 132, thereby protecting the flashing process from interference. Furthermore, in some other examples, the state of the exception handling module 130 corresponding to the shutdown operation of the reset submodule 134 and the detection submodule 132 (or the shutdown operation of the exception handling module 130 ) may be recorded as state S4 .

[0043] In some embodiments, the exception handling module 130 can be further configured to shut down the operation of the reset submodule 134 and the detection submodule 132 (or the exception handling module 130 itself) during the reset operation of the clock source of the second clock signal CLK2. The clock source of the second clock signal CLK2 is in the reset operation period, and the second clock signal CLK2 may not be normally issued or provide a normal system clock input for the functional module. Therefore, detecting the second clock signal CLK2 at this time may result in an erroneous failure detection result, or cause the clock source to be reset again unnecessarily. In this way, the effective management of the exception handling module 130 during the reset operation is improved.

[0044] In some embodiments, the clock detection device 100 may be further configured to: after turning off the exception handling module 130, when the watchdog timer works normally and detects that the first clock signal CLK1 fails, start the exception handling module 130 and trigger the reset of the clock source of the second clock signal CLK2. For example, as described above, the watchdog timer being turned off may indicate that the MCU is performing a specific operation such as flashing. When it is detected that the watchdog timer is turned off (or the watchdog state is turned off), the reset submodule 134 and the detection submodule 132 may be turned off (or the exception handling module 130 is turned off). When the watchdog timer is started again (or the watchdog state is turned on), it may indicate that the specific operation has ended and the MCU enters a normal working state. Therefore, in response to the watchdog timer working normally and the first clock signal CLK1 failing, the exception handling module 130 can be started and the reset submodule 134 can re-trigger the reset of the clock source (MCU) of the second clock signal CLK2 as described above. In some examples, after the reset is triggered, the second time period T2 may be waited for similarly, and then the detection submodule 132 may be instructed to perform a failure detection on the second clock signal CLK2 according to the internal clock signal CLK3 .

[0045] In some embodiments, the exception handling module 130 may manage a state machine that manages the aforementioned states S0-S4. Figure 3 Referring to the state machine management diagram shown in the figure, and referring to the contents described above, when the detection module 110 detects that the first clock signal CLK1 fails, or when the switching module 120 performs switching to the second clock signal CLK2, a signal indicating that the first clock signal CLK1 fails or that the operation of switching to the second clock signal CLK2 has been performed can be transmitted to the exception handling module 130, and the exception handling module 130 performs state management based on the signal. If the first clock signal CLK1 fails and the second clock signal CLK2 is not issued, the state S0 is entered. In the state S0, the exception handling module 130 waits for a period of time T1 before performing the next operation (i.e., entering the state S1). Figure 3As shown, if the waiting time is less than T1, the state S0 (arrow S0-1) is maintained continuously, and if the waiting time is equal to T1 (arrow S0-2), the state S1 is entered. In state S1, the second clock signal CLK2 has been successfully sent or successfully received by the exception handling module 130. In this state, the detection submodule 132 can be used to perform failure detection on the second clock signal CLK2. After the failure detection, if the second clock signal CLK2 fails (arrow S1-1), the state S2 can be directly entered, but in another example, it can also be checked whether the number of resets of the clock source (such as MCU) is less than the limit value. If it is less than the limit value (arrow S1-1), the state S2 is entered again to prevent the clock source from being reset too many times. In state S2, the reset submodule 134 triggers the reset operation of the clock source and enters the reset operation period. Therefore, the entire state S2 period corresponds to the reset operation period of the clock source. During this reset operation, the clock source gradually resets its various parts. After the reset operation period ends, the state S3 can wait for a period of time T2 to prevent the detection submodule 132 from performing a failure detection on the second clock signal CLK2 before the clock source is completely reset (or there is a fault in the reset operation, or the second clock signal has not been sent out in time), which may cause an unexpected reset operation and affect the operation of the circuit module. When the waiting time is equal to T2 (arrow S3-1), the state S1 can be entered to continue to perform a failure detection on the second clock signal CLK2.

[0046] State S4 can indicate the state machine state of the exception handling module 130 corresponding to the shutdown operation of the reset submodule 134 and the detection submodule 132 (or the shutdown operation of the exception handling module 130). In state S4, the state machine is shut down and the failure detection of the second clock signal and the reset operation of the clock source are no longer performed. In any state of state S0-S3, if it is detected that the watchdog timer is turned off (or the watchdog state is turned off, corresponding to arrows S0-3, S1-2, S2-2, S3-2), it may be in some specific operation period as described above, at which time the exception handling module 130 enters state S4 and continues to perform the specific operation (arrow S4-1). In addition, in some examples, since state S2 is during the reset operation of the clock source (MCU), state S2 can also trigger entry into state S4 (also shown by arrow S2-2). When a specific operation is completed, or an external circuit (such as an MCU, etc.) indicates that the entire circuit is normal and re-enables the watchdog timer (arrow S4-2), if the first clock signal CLK1 is still in a failed state, the state S4 can be entered into the state S3, and the time period T2 can be waited in S3, and then the failure detection of the second clock signal CLK2 in the state S1 can be entered as described above.

[0047] Therefore, the exception handling module 130 can effectively manage the operation of the entire clock detection device 100 in the case of failure of the first clock signal CLK1 through its detection of the second clock signal CLK2 and the reset management of the clock source. Specifically, the exception handling module 130 can avoid the exception caused by the clock burr in the clock signal switching process. After the first clock signal CLK1 fails, the failure detection of the second clock signal CLK2 can be performed, and some false detection situations are avoided, such as the exception caused by the second clock signal CLK2 not being issued, the situation that is not conducive to the reset operation or the clock signal failure detection operation due to the MCU or other parts of the system still being in a specific operation period such as flashing, etc. In particular, the exception handling module 130 can further manage all the above functions through a state machine and change between states S0-S4, so as to realize the comprehensive management and efficient state switching of the failure detection of the second clock signal CLK2 in the case of failure of the first clock signal CLK1, the reset operation of the clock source, the reset and other specific operation periods, and the state of the watchdog timer. Therefore, the clock signal switching solution disclosed in the present invention has higher stability and robustness, and can also achieve management of various system and circuit problems and subsequent states during the switching process.

[0048] In addition, in some other examples, the exception handling module 130 may further include a synchronization submodule 136, which corresponds to Figure 1 The synchronization module of the functional module in the embodiment (shown in the dotted box). Thus, an internal clock signal can be further provided as a system clock in addition to the first clock signal CLK1 and the second clock signal CLK2 as a redundancy. The synchronization submodule 136 counts the self-synchronization value and transmits the count value to the synchronization module of the functional module for synchronization.

[0049] In some embodiments, the switching module 120 may include a selector configured to select one of the first clock signal CLK1 and the second clock signal CLK2 as the system clock signal according to the detection flag. The selector may include any form of a device for implementing a selection of one input signal from two input signals, such as various types of multiplexers.

[0050] Figure 2 An exemplary circuit structure of a switching module 120 is shown, wherein the first clock signal CLK1 is input at point A, the detection flag signal is input at point B, and the second clock signal CLK2 is input at point C. The inputs of points A and B are connected to an AND gate 121, the inverted signal of the input at point B (via a NOT gate 122) and the input at point C are connected to an AND gate 123, and the outputs of the AND gates 121 and 123 are connected to an OR gate 124, so that the selected clock signal (i.e., the first clock signal CLK1 or the second clock signal CLK2) is output at the OR gate 124. Figure 2 When the input detection flag signal at point B is at a high level or “1”, it indicates that the first clock signal CLK1 is not invalid, and the first clock signal CLK1 is output at the OR gate 124. When the input detection flag signal at point B changes to a low level or “0”, it indicates that the first clock signal CLK1 is invalid, and the second clock signal CLK2 is output at the OR gate 124.

[0051] In some embodiments, the switching module 120 may be further configured to: perform switching when a first condition is satisfied, and not perform switching when the first condition is not satisfied. The first condition may be any prerequisite for setting a switching operation, such as a voltage condition, a current condition, a temperature condition, etc. For example, a certain temperature condition may be set, and when the temperature reaches a threshold temperature (or is lower than a threshold temperature), it is determined that the temperature condition is satisfied, so that the switching operation of the switching module 120 may be performed. In this way, different switching conditions may be set for different circuit module implementations, thereby improving the flexibility of detection and switching.

[0052] Continue to refer Figure 2 , for the setting of the first condition, a signal indicating the first condition can be input at point D, for example, "0" indicates that the first condition is met and "1" indicates that the first condition is not met. The signal indicating the first condition is input from point D to AND gate 127, and the other input of AND gate 127 is the first clock signal CLK1 from point A. In addition, the signal indicating the first condition is input from point D to AND gate 125 via NOT gate 126, and the other input of AND gate 125 is the output from OR gate 124. The output of AND gate 125 and the output of AND gate 127 serve as inputs of OR gate 128. Therefore, the output of OR gate 128 produces the following results: when the first condition is met, if the first clock signal CLK1 is not invalid, the first clock signal CLK1 is output as the system clock signal, and if the first clock signal CLK1 is invalid, the second clock signal CLK2 is output as the system clock signal; when the first condition is not met, the first clock signal CLK1 is output regardless of whether the first clock signal CLK1 is invalid.

[0053] In some embodiments, the clock detection device 100 is arranged in the vehicle, for example, arranged on each electronic control unit or PCB circuit board of the vehicle system. In addition, the above-mentioned first condition is a voltage threshold condition, and the switching module 120 can be further configured to: when the bus voltage of the vehicle is lower than the voltage threshold, the switching is performed, and when the bus voltage of the vehicle is higher than the voltage threshold, the switching is not performed. For example, in electric vehicles, the use of a high-voltage domain (such as 800V high voltage used for motor starting and operation) generally indicates that the vehicle is performing critical activities such as driving tasks, and the bus voltage at this time is relatively high (for example, reaching 800V high voltage), so the switching module 120 can be configured not to perform switching when the bus voltage is high, but can directly prompt or alarm for failure, for example, to avoid the clock signal switching process causing discontinuity or failure of the electronic components of the vehicle that use the clock in critical activities.

[0054] In some embodiments, the generation of the detection flag may further include: the detection module 110 samples the first clock signal CLK1 a corresponding number of times according to the number of edge changes of the internal clock signal CLK3, and performs an XOR operation on every two consecutive samples, if the XOR calculation is not set, a cumulative count is performed once, if the XOR calculation is set, the count is cleared, and when the count reaches a first preset threshold, the detection flag is flipped to indicate that the first clock signal is invalid. For example, assuming that the frequency of the internal clock signal CLK3 is 20 times that of the first clock signal CLK1, then in a normal cycle of the first clock signal CLK1, the internal clock signal CLK3 undergoes 40 edge changes (20 upper edge changes and 20 lower edge changes), so the first clock signal CLK1 can be sampled 40 times. Among them, an XOR operation can be performed every two edge changes (39 XOR operation results are generated after 40 samplings). Once the output result of a certain XOR operation is set (generating level "1"), it means that in the two samples of the XOR operation, the first clock signal CLK1 has jumped (from a high level to a low level, or from a low level to a high level), and thus it can be concluded that the first clock signal CLK1 is not invalid.

[0055] However, it can be understood that the two edge changes in which the XOR operation result is set can be any two consecutive samples in the 40 samples. Some two consecutive samples may be in the period when the first clock signal CLK1 does not jump, and the results of these XOR operations will not be set. Therefore, a first preset threshold can be designed, and the first preset threshold is associated with the frequency ratio of the first clock signal CLK1 and the internal clock signal CLK3. For example, in the above example, the first preset threshold can be set to 39. When the result of the XOR operation is not set, the count is increased by 1, and the sampling and XOR operation are continued. If the count value reaches the first preset threshold 39, it means that the first clock signal CLK1 has not flipped in the 40 samples, so that the first clock signal CLK1 can be determined to be invalid. Of course, in other examples, the first preset threshold is not necessarily set to 39 accurately, and it can also be, for example, 35, 36, 37 or 38 close to 39 to improve the fault tolerance of failure detection. Therefore, it can be understood that if the frequency of the internal clock signal CLK3 is n times that of the first clock signal CLK1 (n is a positive integer greater than or equal to 2), 2n-1 can be used as the first preset threshold, and in order to improve the fault tolerance rate, a value near 2n-1 (for example, 2n-2, 2n-3, 2n-4, 2n... etc.) can also be set as the first preset threshold.

[0056] In another aspect, the present disclosure also provides a clock detection method. Figure 3 , the first clock signal is used as the initial system clock signal, and the clock detection method may include the following steps:

[0057] In step S101, the first clock signal is detected for failure according to the internal clock signal, and a detection flag is generated. Among them, the internal clock signal CLK3 is a clock signal provided inside the circuit, which can play a role when all external clock signals are invalid or cannot be provided. The internal clock signal CLK3 has a higher frequency than the first clock signal CLK1 and the second clock signal CLK2, for example, a frequency equivalent to 2-100 times that of the first clock signal CLK1 and the second clock signal CLK2. The method may include performing a failure detection on the first clock signal CLK1 according to the internal clock signal CLK3, and after detecting that the first clock signal CLK1 fails or does not fail, generating a detection flag to indicate that the first clock signal CLK1 fails or does not fail. For example, a low level "0" can be generated to indicate that the first clock signal CLK1 fails, and a high level "1" can be generated to indicate that the first clock signal CLK1 does not fail. In some examples, the failure of the clock signal may include an irregular shape of the clock signal, such as being at a high level or a low level for a long time, an abnormal duty cycle, and the like.

[0058] In step S102, it is determined whether to switch the system clock signal from the first clock signal to the second clock signal according to the detection flag. The switching module 120 can determine whether to switch from the first clock signal CLK1 to the second clock signal CLK2 according to the detection flag. For example, when the detection flag indicates that the first clock signal CLK1 is invalid, the switching module 120 selects the second clock signal CLK2 and outputs it to the functional module, so that the second clock signal CLK2 continues to serve as the clock signal input of the functional module.

[0059] In step S103, when the system clock signal is switched to the second clock signal, the second clock signal is detected for failure according to the internal clock signal. When the second clock signal CLK2 is switched, the second clock signal CLK2 may be detected for failure based on the internal clock signal CLK3, and the mechanism of such failure detection may be similar to the mechanism of failure detection for the first clock signal CLK1 in step S101, but may also be different.

[0060] In step S104, the reset of the clock source of the second clock signal is triggered when the failure of the second clock signal is detected. The second clock signal CLK2 can be provided by the main control unit MCU, for example, so the clock source is the MCU in some examples. Thus, the clock source of the second clock signal CLK2 can be reset in time when the second clock signal CLK2 also fails, so that the circuit (such as a functional module) can resume the clock signal input as soon as possible.

[0061] In some embodiments, the clock detection method further includes: when it is detected that the first clock signal fails and the second clock signal has not been sent, waiting for a first time period, and then performing the steps S103 and S104. When the first clock signal CLK1 fails, the second clock signal CLK2 may not have been sent (for example, because the clock source of the second clock signal CLK2 is still in the power-on stage), so it is possible to wait for a certain time period T1 so that the second clock signal CLK2 is successfully sent or the second clock signal CLK2 is successfully received, and then the failure detection of the second clock signal CLK2 is performed. Among them, the time period T1 can be a time period of milliseconds, such as 5-200ms. In this way, the result of erroneously detecting the failure of the second clock signal CLK2 in step S103 due to the fact that the second clock signal CLK2 has not been received can be avoided.

[0062] In some embodiments, the clock detection method further includes: after resetting the clock source of the second clock signal, waiting for a second time period, and then performing a failure detection on the second clock signal according to the internal clock signal. In some examples, during the reset period, the clock source of the second clock signal CLK2 cannot normally provide the second clock signal CLK2, so a certain time period T2 can be waited for so that the second clock signal CLK2 is normally provided, and then the failure detection of the second clock signal CLK2 is performed. In this way, the result of erroneously detecting the failure of the second clock signal CLK2 due to the failure of the second clock signal CLK2 to be normally provided during the reset of the clock source can be avoided.

[0063] In some embodiments, the clock detection method further includes: when it is detected that the watchdog timer is turned off, steps S103 and S104 are not performed. The watchdog timer can be reset regularly when the circuit or system is operating normally. If the circuit or system fails to reset the timer on time due to some reasons (such as dead loop, infinite waiting, etc.), a reset will be automatically triggered after the timer expires, so that the circuit or system restarts and attempts to resume normal operation. Therefore, the watchdog timer can be used to monitor the operating status of the circuit or ECU / MCU to ensure that it will not fall into an endless loop or a long-term unresponsive state. The watchdog timer can be turned off, for example, because the MCU is performing a flash operation, or because the MCU is in a reset operation, etc. Therefore, the monitoring and detection of the second clock signal provided by the MCU can be temporarily turned off, that is, the execution of steps S103 and S104 can be temporarily stopped to avoid triggering unnecessary resets due to detection of clock failure, thereby protecting the flashing process from interference.

[0064] In some embodiments, the clock detection method further includes: during the reset operation of the clock source of the second clock signal, the steps S103 and S104 are not performed. The clock source of the second clock signal CLK2 is in the reset operation period, and the second clock signal CLK2 may not be normally issued or provide a normal system clock input for the functional module. Therefore, detecting the second clock signal CLK2 at this time (step S103) may result in an erroneous failure detection, or cause the clock source to be reset again unnecessarily (step S104). In this way, the effective management of the clock signal during the reset operation of the clock source is improved.

[0065] In some embodiments, the clock detection method further includes: triggering the reset of the clock source of the second clock signal when the watchdog timer works normally and detects that the first clock signal fails. For example, as described above, the watchdog timer being turned off may indicate that the MCU is performing a specific operation such as flashing. When the watchdog timer is detected to be turned off (or the watchdog state is turned off), steps S103 and S104 can be suspended. When the watchdog timer is started again (or the watchdog state is turned on), it may indicate that the specific operation has ended and the MCU enters a normal working state. Therefore, in response to the watchdog timer working normally and the first clock signal CLK1 failing, the execution of steps S103 and S104 can be started again and the reset of the clock source (MCU) of the second clock signal CLK2 can be triggered again as described above. In some examples, after triggering the reset, the second time period T2 can also be waited for in the same way, and then the second clock signal CLK2 is detected to fail according to the internal clock signal CLK3.

[0066] In some embodiments, the clock detection method further includes: executing the step S102 when the first condition is met, and not executing the step S102 when the first condition is not met. The first condition may be any prerequisite for setting the switching operation, such as a voltage condition, a current condition, a temperature condition, etc. For example, a certain temperature condition may be set, and when the temperature reaches a threshold temperature (or is lower than the threshold temperature), it is determined that the temperature condition is met, so that the switching operation of step S102 can be performed. In this way, different switching conditions can be set for different circuit module implementations, thereby improving the flexibility of detection and switching.

[0067] In some embodiments, the clock detection method further includes: sampling the first clock signal a corresponding number of times according to the number of edge changes of the internal clock signal, and performing an XOR operation on every two consecutive samples, if the XOR calculation is not set, then performing a cumulative count once, if the XOR calculation is set, the count is cleared, and when the count reaches a first preset threshold, flipping the detection flag to indicate that the first clock signal is invalid. For example, assuming that the frequency of the internal clock signal CLK3 is 20 times that of the first clock signal CLK1, then in a normal cycle of the first clock signal CLK1, the internal clock signal CLK3 undergoes 40 edge changes (20 upper edge changes and 20 lower edge changes), so the first clock signal CLK1 can be sampled 40 times. Among them, an XOR operation can be performed every two edge changes (39 XOR operation results are generated after 40 samplings). Once the output result of a certain XOR operation is set (generating level "1"), it means that in the two samples of the XOR operation, the first clock signal CLK1 has jumped (from a high level to a low level, or from a low level to a high level), and thus it can be concluded that the first clock signal CLK1 is not invalid.

[0068] However, it can be understood that the two edge changes in which the XOR operation result is set can be any two consecutive samples in the 40 samples. Some two consecutive samples may be in the period when the first clock signal CLK1 does not jump, and the results of these XOR operations will not be set. Therefore, a first preset threshold can be designed, and the first preset threshold is associated with the frequency ratio of the first clock signal CLK1 and the internal clock signal CLK3. For example, in the above example, the first preset threshold can be set to 39. When the result of the XOR operation is not set, the count is increased by 1, and the sampling and XOR operation are continued. If the count value reaches the first preset threshold 39, it means that the first clock signal CLK1 has not flipped in the 40 samples, so that the first clock signal CLK1 can be determined to be invalid. Of course, in other examples, the first preset threshold is not necessarily set to 39 accurately, and it can also be, for example, 35, 36, 37 or 38 close to 39 to improve the fault tolerance of failure detection. Therefore, it can be understood that if the frequency of the internal clock signal CLK3 is n times that of the first clock signal CLK1 (n is a positive integer greater than or equal to 2), 2n-1 can be used as the first preset threshold, and in order to improve the fault tolerance rate, a value near 2n-1 (for example, 2n-2, 2n-3, 2n-4, 2n... etc.) can also be set as the first preset threshold.

[0069] According to another aspect of the present disclosure, an electronic device is also provided. The electronic device includes a memory and a processor, the memory stores instructions, and when the instructions are executed by the processor, the clock detection method according to any of the aforementioned embodiments is implemented. According to another aspect of the present disclosure, a computer-readable storage medium storing instructions is also provided, and when the instructions are executed, the clock detection method according to any of the embodiments of the present disclosure is executed.

[0070] The computer-readable storage medium, memory, storage unit, storage module, etc. referred to in this application include various types of computer-readable storage media, which can be any available medium that can be accessed by a general-purpose or special-purpose computer. For example, the computer-readable medium can include RAM, ROM, EPROM, EEPROM, etc. 2 PROM, register, hard disk, removable disk, CD-ROM or other optical disk storage, disk storage or other magnetic storage device, or can be used to carry or store the desired program code unit with instruction or data structure form and can be accessed by general or special computer, or general or special processor any other temporary or non-temporary medium. The above combination should also be included in the protection scope of computer-readable medium. Exemplary storage medium is coupled to processor so that the processor can read and write information from / to the storage medium. In an alternative, storage medium can be integrated into processor. Processor and storage medium can reside in ASIC. ASIC can reside in user terminal. In an alternative, processor and storage medium can reside in user terminal as discrete components.

[0071] According to another aspect of the present disclosure, a vehicle is also provided, which includes a clock detection device according to any embodiment of the present disclosure, or a vehicle including an electronic device or a programmable logic device (such as an FPGA) according to any embodiment of the present disclosure. The vehicle referred to in this application is intended to represent any appropriate vehicle with a drive system, for example, a fuel-powered vehicle, a hybrid vehicle, an electric vehicle, a plug-in hybrid electric vehicle, etc.

[0072] The above mainly describes the clock detection device, clock detection method, electronic device, programmable logic device and vehicle of the present disclosure. Although only some of the specific embodiments of the present disclosure are described, it should be understood by those skilled in the art that the present disclosure can be implemented in many other forms without departing from its subject matter and scope. Therefore, the examples and embodiments shown are regarded as illustrative rather than restrictive, and the present disclosure may cover various modifications and substitutions without departing from the spirit and scope of the present disclosure as defined in the appended claims.

Claims

1. A clock detection device, characterized in that: The clock detection device inputs a first clock signal and a second clock signal, wherein the first clock signal is used as an initial system clock signal, and the clock detection device comprises: A detection module, which performs failure detection on the first clock signal according to an internal clock signal and generates a detection flag; a switching module, which determines whether to switch the system clock signal from the first clock signal to the second clock signal according to the detection flag; The exception handling module includes: a detection submodule, which performs failure detection on the second clock signal according to the internal clock signal when the system clock signal is switched to the second clock signal; and A reset submodule triggers the reset of a signal source of the second clock signal when detecting that the second clock signal fails.

2. The clock detection device according to claim 1, characterized in that: The exception handling module is further configured to: when the detection module detects that the first clock signal fails and the second clock signal is not sent, wait for a first time period and then perform failure detection on the second clock signal according to the internal clock signal.

3. The clock detection device according to claim 1, characterized in that: The exception handling module is further configured to: after resetting the clock source of the second clock signal, wait for a second time period, and then perform failure detection on the second clock signal according to the internal clock signal.

4. The clock detection device according to claim 1, characterized in that: The exception handling module is further configured to: shut down the operation of the exception handling module when it is detected that the watchdog timer is shut down.

5. The clock detection device according to claim 1, characterized in that: The exception handling module is further configured to: during a reset operation of a clock source of the second clock signal, shut down the operation of the exception handling module.

6. A clock detection method, characterized in that: The method comprises the following steps: S101: Performing failure detection on a first clock signal according to an internal clock signal, and generating a detection flag; S102: Determine whether to switch the system clock signal from the first clock signal to the second clock signal according to the detection flag; S103: When the system clock signal is switched to the second clock signal, performing failure detection on the second clock signal according to the internal clock signal; as well as S104: triggering a reset of a clock source of the second clock signal when it is detected that the second clock signal fails, The first clock signal is used as an initial system clock signal.

7. The clock detection method according to claim 6, characterized in that: The method further includes: executing step S102 when a first condition is met, and not executing step S102 when the first condition is not met.

8. The clock detection method according to claim 7, characterized in that: The step S101 further includes: sampling the first clock signal a corresponding number of times according to the number of edge changes of the internal clock signal, and performing an XOR operation on every two consecutive samples, if the XOR calculation is not set, performing a cumulative count once, if the XOR calculation is set, clearing the count to zero, and when the count reaches a first preset threshold, flipping the detection flag to indicate that the first clock signal has failed.

9. An electronic device, characterized in that: The electronic device comprises a processor and a memory, wherein the memory stores instructions, and when the instructions are executed by the processor, the clock detection method according to any one of claims 6 to 8 is implemented.

10. A vehicle, characterized in that: The vehicle comprises a clock detection device according to any one of claims 1-5.

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