DMA controller test system and method

Abstract

The invention relates to the field of storage, in particular to a DMA controller testing system and method. The system comprises a host, a hardware switching device and an FPGA board, the FPGA board simulates a hard disk structure, the host is connected with a serial port module on an FPGA through the hardware switching device, and a DMA is connected with a PCIe interface of the host; a test program is arranged on the host, a detailed operation model is defined for the DMA controller in the test program so as to cover all working modes, and meanwhile, the test system integrates operation models of interactive operation of other hardware components and the DMA controller so as to cover test scenes of interactive operation or parallel operation. Various test commands are generated according to different test requirements, and the functions of the DMA controller can be comprehensively tested; secondly, the tested address is recorded in the database for each test, and the tested address is removed in a test command generation algorithm, so that the coverage degree of the test address is improved;

Description

Technical Field

[0001] The invention relates to the field of storage, and in particular to a DMA controller testing system and method. Background Art

[0002] DMA (Direct Memory Access) is a data transfer technology that exchanges data directly with the system memory without going through the CPU. It can realize data transfer from memory to memory, device to memory, and memory to device, greatly reducing the CPU workload. The DMA controller test mainly performs DMA reading, writing, calculation, comparison, encryption and other tests, focusing on the correctness of data transmission, whether the data path is normal, and data transmission performance. The working process of DMA is implemented by the DMA controller. DMA control data transfer involves two operations: reading and writing. The DMA controller needs to be able to address the memory and modify the address pointer to realize the reading and writing operations of the memory; it can determine the number of bytes transferred by this DMA. The DMA controller initiates the transmission transaction based on the data source address, destination address, and transmission length. The DMA controller test includes test items such as the copy function, encryption function, performance, and error injection of the specified addressing mode.

[0003] During the chip design phase of the SSD hard drive development process, an FPGA board is usually used to simulate a real SSD hard drive. The FPGA board will be equipped with modules such as the CPU, nand flash, and the DMA controller module that are necessary for the SSD hard drive to work. This test method has two problems in terms of test coverage. First, it is difficult to cover all working modes and scenarios. DMA controllers usually have multiple working modes and complex usage scenarios, such as different data transfer sizes, different transfer sources and targets, and different interrupt handling methods. Existing test methods are difficult to fully cover these different modes and scenarios, and may miss some potential problems. Second, it is difficult to find problems in complex system integration. In actual systems, DMA controllers usually work in conjunction with other hardware components and software systems. Existing test methods often find it difficult to fully test DMA controllers in complex system integration environments, and may not be able to find problems that occur when interacting with other components. Summary of the invention

[0004] In view of the defects of the prior art, the present invention provides a DMA controller testing system and method, which can generate various test commands according to different test requirements and can comprehensively test the functions of the DMA controller.

[0005] In order to solve the technical problem, the technical solution adopted by the present invention is: a DMA controller test system, including a host, a hardware adapter and an FPGA board, the FPGA board is equipped with a CPU, a NAND flash, a DMA, a cache, and a serial port module, the CPU, the NAND flash, the DMA, and the cache constitute a hard disk simulation system, the USB interface of the host is connected to the hardware adapter through a data line, the serial port module of the hardware adapter leads out a serial port line and is connected to the serial port module on the FPGA, and the DMA is connected to the PCIe interface of the host; a test program is provided on the host, the test program includes a custom command window, a command generation module, a command transmission module, and a data display and analysis module, the operation type to be tested is set through the custom command window, including the source address range, the destination address range, the address random mode, the test granularity, the test command and the transmission length, the command generation module generates a test command according to the operation type information input in the custom command window, the command transmission module sends the test command to the FPGA board through the hardware adapter, the database display and analysis module receives the information returned by the FPGA, analyzes the test results and displays them.

[0006] Furthermore, the hardware switching device includes a programmable controller and a serial port module. The programmable controller is connected to the USB interface of the host. One end of the serial port module is connected to the programmable controller, and the other end is connected to the serial port module on the FPGA board through a serial port line.

[0007] The present invention also discloses a DMA controller testing method, which is implemented based on the above-mentioned testing system and includes the following steps: S01. Setting a hardware transfer device, the hardware transfer device includes a programmable controller and a serial port module, the programmable controller is connected to a host, the serial port module is connected to an FPGA board, and the hardware transfer device realizes two-way communication between the host and the FPGA board; S02, prepare a host with a PCIe interface and an FPGA board to be tested, the FPGA board to be tested is equipped with a CPU, NAND flash, DMA, cache, and a serial port module, the CPU, NAND flash, DMA, and cache constitute a hard disk simulation system, a test program is provided on the host, the test program includes a custom command window, a command generation module, a command transmission module, and a data display and analysis module, the operation type to be tested is set through the custom command window, including the source address range, the destination address range, the address randomization method, the test granularity, the test command, and the transmission length, the command generation module generates a test command according to the operation type information input in the custom command window, the command transmission module sends the test command to the FPGA board through the hardware adapter, the data display and analysis module receives the information returned by the FPGA, analyzes the test results and displays them; connect the FPGA board to the PCIe interface of the host, connect the serial port line led out of the FPGA board to the serial port module of the hardware adapter, and connect the data line led out of the programmable controller module of the hard disk adapter to the host; S03, the host is turned on, and the control software is run on the host. First, the operation model to be tested is set, including the source address range, the destination address range, the address random method, the test granularity, the test command, and the transmission length, and then the required test command is automatically generated; S04, start the test, the test process is: S41, send a smoke test command, check the command return status in the data display and analysis module of the control software, and confirm whether the FPGA board is working normally. If normal, proceed to the next step; S42, connecting the host to the DMA controller of the FPGA to be tested through the DMA test driver module; S43, sending a test command to the DMA controller of the FPGA board through the command transmission module; S44, collecting command execution results of the DMA controller through a data display and analysis module; S45. Process the command execution result through the data display and analysis module to analyze whether the command processing result meets expectations.

[0008] Furthermore, the test command generation process is: S31. Set command parameters in the custom command window of the control software. The command parameters include the transmission module to be tested, source address range, destination address range, address randomization method, alignment method, test granularity, test command, test data length, and test times. S32, performing address calculation according to the parameter rules in the predefined operation model in the control software, the control software generates an address table according to the selected address range, address randomization mode, granularity, and alignment mode, and ensures that the addresses are aligned according to the selected alignment mode; S33, the control software reads the historical test address table in the database, modifies the address table according to the principle of covering as many test ranges as possible with the same test command, and removes the addresses that have been tested in history; S34, the control software randomly selects a specified number of address range combinations based on the selected test command, address range table, test data length, and test times, and checks whether the address ranges overlap in combination with the data length of each command test; S35, if the address ranges overlap, further modify the address range of the test command according to a pre-set rule; S36. Combine the test command with the address table to generate a test command list.

[0009] Furthermore, the test commands and the address table used therein are recorded in a database and used to cover more test ranges in multiple tests in conjunction with an appropriate address selection algorithm.

[0010] Further, after executing step S35, if a single-core or multi-core operation is specified in the command window, the corresponding parameters in the command are modified.

[0011] Furthermore, the general format of the test command is: tdma -m mode -s source -d dest -ppattern -l pattern_len -z size -n num -u unit -c core_num, where tdma indicates testing the DMA controller; -m mode indicates the transfer mode, which is set in the custom command window of the control software; -s source indicates the source address, which is set in the custom command window of the control software; -d dest indicates the destination address, which is set in the custom command window of the control software; -p pattern indicates the test data content, which is set in the custom command window of the control software or the test data is randomly generated by the control software; -l pattern_len indicates the length of the test data pattern, which is set in the custom command window of the control software; -z size indicates the test data length, which is set in the custom command window of the control software; -n num indicates the number of times a test is performed, which is set in the custom command window of the control software; -u Unit indicates the data length unit, which is set in the custom command window of the control software. -ccore_num indicates that a certain core issues the command, which supports issuing commands on a single core or multiple cores at the same time, which is set in the custom command window of the control software.

[0012] Furthermore, the transmission modes include copy, set, crc, and speed.

[0013] The beneficial effects of the present invention are as follows: firstly, the test command generation module can generate various test commands according to different test requirements, and can comprehensively test the functions of the DMA controller; secondly, the address record database of each test removes the tested addresses in the test command generation algorithm, thereby improving the coverage of the test addresses. The test system of the present invention has a simple structure, low cost, and is easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a functional block diagram of the test system described in Example 1; Figure 2 This is a flow chart of the test method described in Example 2; Figure 3 Flowchart generated for the test command. DETAILED DESCRIPTION

[0015] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0016] Example 1 This embodiment discloses a DAM testing system, such as Figure 1As shown, it includes a host, a hardware adapter and an FPGA board. The FPGA board is equipped with a CPU, a NAND flash, a DMA, a cache and a serial port module. The CPU, the NAND flash, the DMA and the cache constitute a hard disk simulation system. The USB interface of the host is connected to the hardware adapter through a data line. The serial port module of the hardware adapter leads out a serial port line and is connected to the serial port module on the FPGA. The DMA is connected to the PCIe interface of the host. The host is provided with a test program, which includes a custom command window, a command generation module, a command transmission module and a data display and analysis module. The operation type to be tested is set through the custom command window, including the source address range, the destination address range, the address random mode, the test granularity, the test command and the transmission length. The command generation module generates a test command according to the operation type information input in the custom command window. The command transmission module sends the test command to the FPGA board through the hardware adapter. The database display and analysis module receives the information returned by the FPGA, analyzes the test results and displays them.

[0017] In this embodiment, the hardware adapter includes a programmable controller and a serial port module. The programmable controller is connected to the USB interface of the host. One end of the serial port module is connected to the programmable controller, and the other end is connected to the serial port module on the FPGA board through a serial port line.

[0018] The test system described in this embodiment defines a detailed operation model for the DMA controller in the control software to cover all working modes, and the model can accurately reflect the expected behavior of the DMA controller under various input conditions, including different data transfer sizes, transfer sources and destinations, etc. At the same time, the test system integrates the operation model of the interaction between other hardware components and the DMA controller to cover the test scenarios of interactive operation or parallel operation.

[0019] The control software is installed on the host, and the software includes a custom command window, a command generation module, a command transmission module, and a data display and analysis module.

[0020] The host communicates with the hardware adapter through a data line. The device includes a programmable controller and a serial port module. The serial port module is then connected to the FPGA board to enable the host to test the DMA controller on the FPGA board.

[0021] Example 2 This embodiment discloses a DMA controller testing method, such as Figure 2 As shown, the following steps are included: This method is implemented based on the test system described in Example 1 and includes the following steps: S01. Set up a hardware adapter, which includes a programmable controller and a serial port module. The programmable controller is connected to the host, and the serial port module is connected to the FPGA board. The hardware adapter serves as a bridge to achieve two-way communication between the host and the FPGA board.

[0022] S02. Prepare a host with a PCIe interface and an FPGA board to be tested. The FPGA board to be tested is equipped with a CPU, NAND flash, DMA, cache, and a serial port module. The CPU, NAND flash, DMA, and cache constitute a hard disk simulation system. A test program is provided on the host. The test program includes a custom command window, a command generation module, a command transmission module, and a data display and analysis module. The operation type to be tested is set through the custom command window, including the source address range, the destination address range, the address randomization method, the test granularity, the test command, and the transmission length. The command generation module generates a test command according to the operation type information input in the custom command window. The command transmission module sends the test command to the FPGA board through a hardware adapter. The data display and analysis module receives the information returned by the FPGA, analyzes the test results, and displays them. Connect the FPGA board to the PCIe interface of the host, connect the serial port line led out of the FPGA board to the serial port module of the hardware adapter, and connect the data line led out of the programmable controller module of the hard disk adapter to the host.

[0023] In this embodiment, the source address range can be in the buffer or DRAM, and correspondingly, the destination address range can also be in the DRAM or the buffer. In this way, data can be transmitted from the buffer to the DRAM, and data can also be transmitted from the DRAM to the buffer. The buffer and the DRAM are different hardware components, which can reflect the interaction between DMA and other hardware components.

[0024] S03, the host is turned on, and the control software is run on the host. First, the operation model to be tested is set, including the source address range, the destination address range, the address random method, the test granularity, the test command, and the transmission length, and then the required test command is automatically generated.

[0025] S04, start the test, the test process is: S41, send a smoke test command, check the command return status in the data display and analysis module of the control software, and confirm whether the FPGA board is working normally. If normal, proceed to the next step; S42, connecting the host to the DMA controller of the FPGA to be tested through the DMA test driver module; S43, sending a test command to the DMA controller of the FPGA board through the command transmission module; S44, collecting command execution results of the DMA controller through a data display and analysis module; S45. Process the command execution result through the data display and analysis module to analyze whether the command processing result meets expectations.

[0026] like Figure 2 As shown in the figure, the test command generation process is: S31. Set command parameters in the custom command window of the control software. The command parameters include the transmission module to be tested, source address range, destination address range, address randomization method, alignment method, test granularity, test command, test data length, and test times. S32, performing address calculation according to the parameter rules in the predefined operation model in the control software, the control software generates an address table according to the selected address range, address random mode, granularity, and alignment mode, and ensures that the address is aligned according to the selected alignment mode, such as 4k alignment, 4bytes alignment, etc.; S33, the control software reads the historical test address table in the database, modifies the address table according to the principle of covering as many test ranges as possible with the same test command, and removes the addresses that have been tested in history; S34, the control software randomly selects a specified number of address range combinations based on the selected test command, address range table, test data length, and test times, and checks whether the address ranges overlap in combination with the data length of each command test; S35, if the address ranges overlap, further modify the address range of the test command according to a pre-set rule; S36. If a single-core or multi-core operation is specified in the command window, modify the corresponding parameters in the command; S37. Combine the test command with the address table to generate a test command list.

[0027] In this embodiment, the test commands and the address table used by them are recorded in a database, and are used to cover more test ranges in multiple tests in conjunction with an appropriate address selection algorithm.

[0028] The address selection algorithm is used to select test addresses from the address table recorded in the database. It includes random selection algorithm, linear traversal algorithm (with intervals), stratified sampling algorithm, etc. The random selection algorithm simply randomly extracts memory addresses from the address table for testing. The linear traversal algorithm (with intervals) selects addresses according to a certain order and interval. The stratified sampling algorithm divides the memory addresses into different levels or areas (for example, stratified by high-order bytes), first randomly extracts a certain number of levels from the large level, and then randomly selects some addresses in each extracted level for testing. The address selection algorithm of this embodiment preferably adopts the third type, namely the stratified sampling algorithm.

[0029] In this embodiment, the general format of the test command is: tdma -m mode -s source -d dest -ppattern -l pattern_len -z size -n num -u unit -c core_num, and the meanings of the parameters are explained as follows: tdma, means testing the DMA controller; -m mode, indicating the transmission mode, such as copy, set, crc, speed, etc., which is set in the command window of the control software; -s source, indicating the source address, sets the source address range in the command window of the control software; -d dest, indicating the destination address, sets the destination address range in the command window of the control software; -p pattern, which indicates the test data content, can be set in the command window of the control software, or the control software can generate test data randomly; -l pattern_len, which indicates the length of the test data pattern, can be set in the command window of the control software; -z size, which indicates the test data length, can be set in the command window of the control software; -n num, which indicates the number of times a test is performed, that is, how many times the command will be tested in a loop in one test, which can be set in the command window of the control software; -u unit, which indicates the data length unit, including bytes, 4k bytes, etc., which can be set in the command window of the control software; -c core_num, indicating that the command is issued by a certain A55 or M33 core. It can be issued by a single core or multiple cores at the same time, and can be set in the command window of the control software.

[0030] A typical test command is as follows: tdma -m copy -s 0x05010000 -d 0x05040000 -z 4 -u 0 -n 8, this command indicates a copy test, the source address is 0x05010000, the destination address is 0x05040000, the test data length is 4 bytes, and the test is repeated 8 times.

[0031] The above description is only the basic principle and preferred embodiments of the present invention. Improvements and substitutions made by those skilled in the art based on the present invention belong to the protection scope of the present invention.

Claims

1. A DMA controller test system, characterized in that: The invention comprises a host, a hardware adapter and an FPGA board. The FPGA board is equipped with a CPU, a NAND flash, a DMA, a cache and a serial port module. The CPU, the NAND flash, the DMA and the cache constitute a hard disk simulation system. The USB interface of the host is connected to the hardware adapter through a data line. The serial port module of the hardware adapter leads out a serial port line and is connected to the serial port module on the FPGA. The DMA is connected to the PCIe interface of the host. The host is provided with a test program, which comprises a custom command window, a command generation module, a command transmission module and a data display and analysis module. The operation type to be tested is set through the custom command window, including the source address range, the destination address range, the address random mode, the test granularity, the test command and the transmission length. The command generation module generates a test command according to the operation type information input in the custom command window. The command transmission module sends the test command to the FPGA board through the hardware adapter. The database display and analysis module receives the information returned by the FPGA, analyzes the test results and displays them.

2. The DMA controller test system according to claim 1, characterized in that: The hardware switching device includes a programmable controller and a serial port module. The programmable controller is connected to the USB interface of the host. One end of the serial port module is connected to the programmable controller, and the other end is connected to the serial port module on the FPGA board through a serial port line.

3. A DMA controller testing method, characterized in that: This method is implemented based on the test system described in claim 1 or 2, and includes the following steps: S01. Setting a hardware transfer device, the hardware transfer device includes a programmable controller and a serial port module, the programmable controller is connected to a host, the serial port module is connected to an FPGA board, and the hardware transfer device realizes two-way communication between the host and the FPGA board; S02, prepare a host with a PCIe interface and an FPGA board to be tested, the FPGA board to be tested is equipped with a CPU, NAND flash, DMA, cache, and a serial port module, the CPU, NAND flash, DMA, and cache constitute a hard disk simulation system, a test program is provided on the host, the test program includes a custom command window, a command generation module, a command transmission module, and a data display and analysis module, the operation type to be tested is set through the custom command window, including the source address range, the destination address range, the address randomization method, the test granularity, the test command, and the transmission length, the command generation module generates a test command according to the operation type information input in the custom command window, the command transmission module sends the test command to the FPGA board through the hardware adapter, the data display and analysis module receives the information returned by the FPGA, analyzes the test results and displays them; connect the FPGA board to the PCIe interface of the host, connect the serial port line led out of the FPGA board to the serial port module of the hardware adapter, and connect the data line led out of the programmable controller module of the hard disk adapter to the host; S03, the host is turned on, and the control software is run on the host. First, the operation model to be tested is set, including the source address range, the destination address range, the address random method, the test granularity, the test command, and the transmission length, and then the required test command is automatically generated; S04, start the test, the test process is: S41, send a smoke test command, check the command return status in the data display and analysis module of the control software, and confirm whether the FPGA board is working normally. If normal, proceed to the next step; S42, connecting the host to the DMA controller of the FPGA to be tested through the DMA test driver module; S43, sending a test command to the DMA controller of the FPGA board through the command transmission module; S44, collecting command execution results of the DMA controller through a data display and analysis module; S45. Process the command execution result through the data display and analysis module to analyze whether the command processing result meets expectations.

4. The DMA controller testing method according to claim 3, characterized in that: The test command generation process is: S31. Setting command parameters in the custom command window of the control software, the command parameters including the transmission module to be tested, source address range, destination address range, address randomization mode, alignment mode, test granularity, test command, test data length and test times; S32, performing address calculation according to the parameter rules in the predefined operation model in the control software, the control software generates an address table according to the selected address range, address randomization mode, granularity, and alignment mode, and ensures that the addresses are aligned according to the selected alignment mode; S33, the control software reads the historical test address table in the database, modifies the address table according to the principle of covering as many test ranges as possible with the same test command, and removes the addresses that have been tested in history; S34, the control software randomly selects a specified number of address range combinations based on the selected test command, address range table, test data length, and test times, and checks whether the address ranges overlap in combination with the data length of each command test; S35, if the address ranges overlap, further modify the address range of the test command according to a pre-set rule; S36. Combine the test command with the address table to generate a test command list.

5. The DMA controller testing method according to claim 4, characterized in that: The test commands and the address table they use are recorded in a database and used with the address selection algorithm to cover more test ranges in multiple tests.

6. The DMA controller testing method according to claim 4, characterized in that: After executing step S35, if a single-core or multi-core operation is specified in the command window, the corresponding parameters in the command are modified.

7. The DMA controller testing method according to claim 3 or 4, characterized in that: The general format of the test command is: tdma -m mode -s source -d dest -p pattern -l pattern_len -z size -n num -uunit -c core_num, where tdma means testing the DMA controller; -m mode means the transfer mode, which is set in the custom command window of the control software; -s source means the source address, which is set in the custom command window of the control software; -d dest means the destination address, which is set in the custom command window of the control software; -p pattern means the test data content, which is set in the custom command window of the control software or the control software generates the test data randomly; -l pattern_len means the length of the test data pattern, which is set in the custom command window of the control software; -z size means the test data length, which is set in the custom command window of the control software; -n num means the number of times a test is performed, which is set in the custom command window of the control software; -u unit means the data length unit, which is set in the custom command window of the control software; -c core_num indicates that a command is issued by a certain core. It supports issuing commands by a single core or multiple cores at the same time and is set in the custom command window of the control software.

8. The DMA controller testing method according to claim 7, characterized in that: The transmission modes include copy, set, crc, and speed.

Images