A UVM verification system supporting single and dual-port PCIe SSDs

Abstract

The present invention relates to the field of chip verification, and more specifically, is a UVM verification system that supports single- and dual-port PCIe SSDs. The system comprises a UVM component, an adapter, a global configuration manager, and a top-level interface. The UVM component inherits from UVM_env and includes host_env, amba_env, and lcpu_env. The adapter includes a clock generation module and a connector. The global configuration manager is used to control single- and dual-port modes, channel flipping, and polarity inversion. The top-level interface includes a root complex phy, an AXI interface, an APB interface, and an AHB interface. The present invention eliminates the need for macro management to maintain a single- and dual-port environment. Instead, the system utilizes a global configuration manager to achieve multiplexing and flexible configuration of single- and dual-port components. Compared to a macro-managed verification environment, the system eliminates the need for recompilation when testing single- and dual-port PCIe test functions. Port modes can be switched by controlling simulation parameters, enabling single-compilation and multiple simulations, thereby improving verification efficiency.

Description

Technical Field

[0001] The present invention relates to the field of chip verification, in particular to a UVM verification system supporting single- and dual-port PCIe SSDs. Background Art

[0002] With the continuous advancement of solid-state drive (SSD) technology, PCIe-based SSDs, in particular, are becoming increasingly popular in both the consumer and enterprise markets due to their high performance and reliability. Single-port PCIe SSDs, with their uniform specifications and excellent transmission bandwidth, are widely used by high-end users. However, dual-port PCIe SSDs, with their higher reliability, are gradually gaining popularity in the all-flash storage market. The dual-port design enables redundant backup, improves data security, and meets enterprises' requirements for high-availability storage systems.

[0003] Single- and dual-port PCIe SSD chip verification systems typically switch between different modes using macros. Due to the different configurations for single and dual ports, dual verification environments must be managed, reducing verification efficiency. Therefore, developing a stable and reliable verification environment with a simple and efficient switching mechanism is crucial. Such a platform can help reduce verification complexity and improve efficiency, providing reliable support for single- and dual-port PCIe SSD chip verification and driving technological advancements. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a UVM verification system that supports single- and dual-port PCIe SSDs, which does not require macro management to maintain the single- and dual-port environments, and realizes the reuse and flexible configuration of single- and dual-port components through a global configuration manager.

[0005] In order to solve the technical problem, the technical solution adopted by the present invention is: a UVM verification system supporting single and dual-port PCIe SSDs, including UVM components, adapters, global configuration managers and top-level interfaces;

[0006] UVM components include host_env, amba_env, and lcpu_env; host_env inherits from uvm_env and is used to encapsulate components related to the host, root complex, and root complex and host adapter to facilitate environment management. It includes host agent, root complex agent, and host2rc adapter. The host agent is a component used to implement simulated host behavior, including a driver, monitor, and sequencer; the root complex agent is a component used to implement simulated RC behavior, including a root complex driver, monitor, and sequencer. The host2rc adapter is used to adapt to compatibility issues between different hosts and root complexes. When single-port mode is selected, Host_env is only instantiated once; when dual-port mode is selected, Host_env is instantiated twice and runs concurrently; amba_env inherits from uvm_env and is used to encapsulate various protocol environments in amba to facilitate environment management, including Axi_agent, Apb_agent and Ahb_agent. Axi_agent, Apb_agent and Ahb_agent are used to verify whether the AXI, APB and AHB interfaces in the design comply with the relevant protocol specifications to ensure that data transmission, control signals and response mechanisms are correct. Axi_agent, Apb_agent and Ahb_agent all contain corresponding bus agents. The bus agent includes a driver, monitor and sequencer. For the common bus in dual-port mode, the corresponding bus agent is only instantiated once in both single and dual-port modes. For independent buses in dual-port mode, the corresponding bus agent is instantiated twice; lcpu_env inherits from uvm_env and is used to configure relevant registers and handle interrupts during power-on.

[0007] The global configuration manager is connected to the UVM component to control the single and dual port modes;

[0008] The top-level interfaces include the root complex interface, AXI interface, APB interface, and AHB interface;

[0009] The adapter is used to adapt the serial interface interconnection between the root complex and the endpoint device in different port modes and generate a matching reference clock. Host_env is connected to the device under test through the root complex interface and the adapter. amba_env is connected to the device under test through the AXI interface, APB interface, and AHB interface.

[0010] In single-port mode, the verification system forms a 4-channel link with the device under test through the root complex interface and the adapter. In dual-port mode, the verification system forms two independent 2-channel links with the device under test through the root complex interface and the adapter.

[0011] Furthermore, the adapter includes a clock generation module and a connector. The connector is connected between the root complex and the device under test. The clock generation module is used to generate a clock signal and send it to the device under test, and the connector and the clock generation module are connected with a dual-port enable signal and other control signals. In single-port mode, there is only one host and root complex. The host is responsible for initializing the PCIe bus and allocating resources to all devices connected to the bus, such as memory addresses, interrupts, etc. The root complex serves as a bridge between the host and the PCIe bus and is responsible for mapping the host's memory and I / O address space to the PCIe bus. The connector connects the device under test TX0 / TX1 / TX2 / TX3 Connect to the four channels of the root complex RC0 respectively; in dual-port mode, two hosts and root complexes are required. The connector connects TX0 / RX0 and TX1 / RX1 of the root complex RC0 to TX0 / RX0 and TX1 / RX1 of the device under test, and connects TX0 / RX0 and TX1 / RX1 of the root complex RC1 to TX2 / RX2 and TX3 / RX3 of the device under test.

[0012] Furthermore, the clock generation module generates a normal clock and an unstable clock according to requirements.

[0013] Furthermore, other control signals include channel flip signals. After channel flip is enabled, in single-port mode, the adapter reverses the four channels of the root complex RC0 with the four channels of the device under test to realize the verification of the single-port channel flip function point. In dual-port mode, the adapter reverses the two channels of the root complex RC0 and RC1 with the corresponding channels of the device under test to realize the verification of the dual-port channel flip function point.

[0014] Furthermore, other control signals include a polarity reversal signal. When polarity reversal is enabled, the adapter reverses the polarity of the differential signals of TX and RX in each channel, regardless of single-port or dual-port mode.

[0015] Furthermore, the global configuration manager is a class that is instantiated in the UVM_TEST component in UVM and broadcasts the handle to the UVM component through the uvm_config_db mechanism. The UVM component instantiates the components required for single and dual ports and configures the corresponding registers according to the requirements of the global configuration manager.

[0016] Furthermore, the top layer of the verification system is used to instantiate the top-level interface and adapter, and realize the connection between the verification system and the device under test; at the same time, according to different port modes, the corresponding virtual interface is sent to the specified UVM component.

[0017] Furthermore, Apb_agent is a dual-port common configuration interface, and Axi_agent and Ahb_agent are independent buses in dual-port mode.

[0018] The beneficial effects of the present invention include providing a strategy for building a single-port / dual-port PCIe verification system, eliminating the need to maintain a single-port / dual-port environment through macro management, and enabling multiplexing and flexible configuration of single-port / dual-port components through a global configuration manager. For example, the global configuration manager includes a configuration signal for selecting a single-port / dual-port mode. By modifying the port mode in the build_phase in the UVM environment, the uvm_test component in the UVM obtains the configuration information and instantiates one or two host_env, amba_env, and lcpu_env according to the configuration information.

[0019] Compared with the macro management verification environment, there is no need to recompile when testing single-port and dual-port PCIe test functions. The port mode can be switched by controlling the simulation parameters, achieving one-time compilation and multiple simulations, thus improving verification efficiency.

[0020] Provided is an adapter for both single and dual-port PCIe, which can realize automatic connection of single and dual ports and automatic generation of reference clocks, facilitating fast switching of port modes. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a principle block diagram of the present invention;

[0022] Figure 2 This is the principle block diagram of amba_env;

[0023] Figure 3 This is the principle block diagram of the adapter. DETAILED DESCRIPTION

[0024] The present invention will be further described below with reference to the accompanying drawings and specific implementations.

[0025] Example 1

[0026] This embodiment discloses a UVM verification system that supports single and dual-port PCIe SSDs. The present invention is a verification system built based on UVM (Universal Verification Methodology). Figure 1As shown, the system includes UVM components, adapters, a global configuration manager, and top-level interfaces. The top level of the verification system is used to instantiate top-level interfaces and adapters. Top-level interfaces include the root complex (RC) phy, AXI interfaces, APB interfaces, and AHB interfaces, which are used to connect the verification system to the device under test. Simultaneously, based on different port modes, the corresponding virtual interfaces are sent to the specified UVM components using the uvm_config_db mechanism in UVM. In this embodiment, the AXI and AHB interfaces are independent interfaces on ports 0 and 1, while the APB interface is shared by both ports 0 and 1. Instantiating the adapter automatically completes the connection between the verification system TB and the device under test. The global configuration manager connects to UVM components and controls single-port and dual-port modes, channel flipping, polarity inversion, and more. The global configuration manager is a class instantiated in the UVM_TEST component in UVM and broadcasts its handles to the aforementioned UVM components via the uvm_config_db mechanism. Each component instantiates the components required for single and dual ports and configures the corresponding registers based on the global configuration manager's requirements. As mentioned above, when the global configuration manager selects single-port mode, it instantiates one set of AXI, AHB, and APB interfaces and the corresponding Axi_agent, Ahb_agent, and Apb_agent, one root complex (RC) phy, and the corresponding host_env. When the global configuration manager is configured for dual-port mode, it instantiates two sets of AXI, AHB, and APB interfaces and the corresponding Axi_agent and Ahb_agent, one set of APB interfaces and the corresponding Apb_agent, two sets of root complex (RC) phys, and the corresponding host_env.

[0027] UVM components include Host_env, amba_env, and lcpu_env. When single-port mode is selected, these three envs are only instantiated once. When dual-port mode is selected, these three envs are instantiated twice to achieve environment reuse and independent configuration in dual-port mode. Host_env inherits from uvm_env and is used to encapsulate components related to the host, root complex, and root complex and host adapter to facilitate environment management. It includes host agent, root complex agent, and host2rc adapter. Host agent is a component used to implement simulated host-related behaviors, including drivers, monitors, and sequencers. Root complex agent is a component used to implement simulated RC behaviors, including root complex drivers, monitors, and sequencers. The host2rc adapter is used to adapt to compatibility issues between different hosts and root complexes. When single-port mode is selected, Host_env is only instantiated once. When dual-port mode is selected, Host_env is instantiated twice and runs concurrently without interfering with each other. amba_env inherits from uvm_env and is used to encapsulate various protocol environments in amba to facilitate environment management. For example, Figure 2 As shown, the Axi_agent, Apb_agent, and Ahb_agent components are used to verify that the AXI, APB, and AHB interfaces in the design comply with relevant protocol specifications, ensuring correct data transmission, control signals, and response mechanisms. Each of these components includes the corresponding bus agent, which includes a driver, monitor, and sequencer. For common buses in dual-port mode, the corresponding bus agent is instantiated only once in both single- and dual-port modes. For independent buses in dual-port mode, the corresponding bus agent is instantiated twice, and these bus agents execute concurrently. Ahb_agent is the common configuration interface for dual-port mode, while Axi_agent and Apb_agent are independent buses in dual-port mode.

[0028] lcpu_env inherits from uvm_env and is used to configure related registers and handle interrupts during the power-on process.

[0029] The adapter is used to adapt the interconnection between the root complex and the endpoint device serial interface in different port modes and generate a matching reference clock. Host_env is connected to the device under test through the root complex interface and the adapter, and amba_env is connected to the device under test through the AXI interface, APB interface, and AHB interface. In single-port mode, the verification system forms a 4-channel link with the device under test through the root complex interface and the adapter. In dual-port mode, the verification system forms two independent 2-channel links with the device under test through the root complex interface and the adapter.

[0030] like Figure 3 As shown, the adapter includes a clock generation module and a connector. The connector is connected to the root complex and the device under test. The clock generation module is used to generate a clock signal and send it to the device under test, and the connector and the clock generation module are connected with a dual-port enable signal and other control signals. In single-port mode, there is only one host and root complex. The connector connects TX0 / TX1 / TX2 / TX3 of the device under test to the four channels of the root complex RC0 respectively. In dual-port mode, two hosts and root complexes are required. The connector connects TX0 / RX0 and TX1 / RX1 of the root complex RC0 to TX0 / RX0 and TX1 / RX1 of the device under test, and connects TX0 / RX0 and TX1 / RX1 of the root complex RC1 to TX2 / RX2 and TX3 / RX3 of the device under test.

[0031] The clock generation module generates normal clocks and unstable clocks as required. Normal clocks include turning on Pma0_refclk0 and turning off Pma0_refclk1 / Pma1_refclk0 / Pma1_refclk1. Unstable clocks are used to simulate actual usage scenarios.

[0032] Other control signals include channel flip signals. When channel flip is enabled, in single-port mode, the adapter reverses the connection between the four channels of the root complex RC0 and the four channels of the device under test to verify the single-port channel flip function point. In dual-port mode, the adapter reverses the connection between the two channels of the root complex RC0 and RC1 and the corresponding channels of the device under test to verify the dual-port channel flip function point.

[0033] Other control signals include polarity reversal signals. When polarity reversal is enabled, the adapter reverses the polarity of the TX and RX differential signals in each channel, regardless of single-port or dual-port mode.

[0034] This invention provides a strategy for building a single- / dual-port PCIe verification system. This eliminates the need for macro-managed maintenance of single- and dual-port environments, enabling the reuse and flexible configuration of single- and dual-port components through a global configuration manager. Compared to macro-managed verification environments, this eliminates the need for recompilation when testing single- and dual-port PCIe test functions. Simulation parameters can be controlled to switch port modes, enabling multiple simulations with a single compilation, improving verification efficiency. An adapter for single- and dual-port PCIe is provided that automatically connects single and dual ports and generates reference clocks, facilitating rapid switching of port modes.

[0035] The above description is only the basic principle and preferred embodiments of the present invention. Improvements and substitutions made by those skilled in the art based on the present invention fall within the protection scope of the present invention.

Claims

1. A UVM verification system supporting single and dual port PCIe SSDs, characterized by: Includes UVM components, adapters, global configuration manager and top-level interfaces; UVM components include Host_env, amba_env, and lcpu_env; Host_env inherits from uvm_env and is used for encapsulation of host, root complex, and root complex and host adapter components, including host agent, root complex agent, and host2rc adapter. Host agent is a component used to implement simulated host behavior, including driver, monitor, and sequencer; root complex agent is a component used to implement simulated RC behavior, including root complex driver, monitor, and sequencer. Host2rc adapter is used to achieve compatibility between different hosts and root complexes; when single-port mode is selected, Host_env is only instantiated once; when dual-port mode is selected, Host_env is instantiated twice and runs concurrently; amba_env inherits from uvm_env and is used for encapsulation of various protocol environments in amba, including A xi_agent, Apb_agent, and Ahb_agent. Axi_agent, Apb_agent, and Ahb_agent all contain corresponding bus agents, which include drivers, monitors, and sequencers. For the common bus in dual-port mode, the corresponding bus agent is only instantiated once in both single-port and dual-port modes. For the independent bus in dual-port mode, the corresponding bus agent is instantiated twice. lcpu_env inherits from uvm_env and is used for configuring related registers and interrupt processing during the power-on process. The global configuration manager is connected to the UVM component to control the single and dual port modes; The top-level interfaces include the root complex interface, AXI interface, APB interface, and AHB interface; The adapter is used to adapt the serial interface interconnection between the root complex and the endpoint device in different port modes and generate a matching reference clock. Host_env is connected to the device under test through the root complex interface and the adapter. amba_env is connected to the device under test through the AXI interface, APB interface, and AHB interface. In single-port mode, the verification system forms a 4-channel link with the device under test through the root complex interface and the adapter. In dual-port mode, the verification system forms two independent 2-channel links with the device under test through the root complex interface and the adapter.

2. The UVM verification system supporting single and dual port PCIe SSD according to claim 1, wherein: The adapter includes a clock generation module and a connector, the connector is connected between the root complex and the device under test, the clock generation module is used to generate a clock signal and send it to the device under test, and the connector and the clock generation module are connected with a dual-port enable signal and other control signals; In single-port mode, there is only one host and root complex. The host is responsible for initializing the PCIe bus and allocating resources to all devices connected to the bus. The root complex acts as a bridge between the host and the PCIe bus and is responsible for mapping the host's memory and I / O address space to the PCIe bus. The connectors connect the TX0 / TX1 / TX2 / TX3 ports of the device under test to the four channels of the root complex RC0. In dual-port mode, two hosts and root complexes are required. The connectors connect the TX0 / RX0 and TX1 / RX1 ports of the root complex RC0 to the TX0 / RX0 and TX1 / RX1 ports of the device under test, and the TX0 / RX0 and TX1 / RX1 ports of the root complex RC1 to the TX2 / RX2 and TX3 / RX3 ports of the device under test.

3. The UVM verification system supporting single and dual port PCIe SSD according to claim 2, wherein: The clock generation module generates normal clock and unstable clock according to requirements.

4. The UVM verification system supporting single and dual port PCIe SSD according to claim 2, wherein: Other control signals include channel flip signals. When channel flip is enabled, in single-port mode, the adapter reverses the connection between the four channels of the root complex RC0 and the four channels of the device under test to verify the single-port channel flip function point. In dual-port mode, the adapter reverses the connection between the two channels of the root complex RC0 and RC1 and the corresponding channels of the device under test to verify the dual-port channel flip function point.

5. The UVM verification system supporting single and dual port PCIe SSD according to claim 2, wherein: Other control signals include a polarity reversal signal. When polarity reversal is enabled, the adapter reverses the polarity of the TX and RX differential signals in each channel in single-port and dual-port modes.

6. The UVM verification system supporting single and dual port PCIe SSD according to claim 1, wherein: The global configuration manager is a class that is instantiated in the uvm_test component in UVM and broadcasts the handle to the UVM component through the uvm_config_db mechanism. The UVM component instantiates the components required for single and dual ports and configures the corresponding registers according to the requirements of the global configuration manager.

7. The UVM verification system supporting single and dual port PCIe SSD according to claim 1, wherein: The top layer of the verification system is used to instantiate the top-level interface and adapter, and realize the connection between the verification system and the device under test; at the same time, according to different port modes, the corresponding virtual interface is sent to the specified UVM component.

8. The UVM verification system supporting single and dual port PCIe SSD according to claim 1, wherein: Apb_agent is a dual-port public configuration interface, and Axi_agent and Ahb_agent are independent buses in dual-port mode.

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