PCIe device optimization memory allocation method, storage medium, device and system

Abstract

The invention discloses a PCIe (Peripheral Component Interconnect Express) equipment memory allocation optimization method, equipment and system, and a storage medium, and relates to the technical field of PCIe. The method comprises the following steps: configuring an interface by using a memory size, and setting the memory size required by PCIe equipment in a PCIe enumeration process; configuring an interface by utilizing the allocation strategy, and setting a memory allocation strategy of the PCIe equipment; when the memory is allocated, sorting the memory resource requests of the PCIe devices according to a memory allocation strategy, and writing the memory resource requests into a memory request linked list; pCIe controller resources are read, and memory space is allocated according to the sequence in the memory request chain table, the size of the memory needed by the PCIe device and the base address alignment principle. According to the method, the memory demand size of the PCIe equipment can be modified according to the memory space actually used by the PCIe equipment, the memory allocation strategy can be flexibly configured according to the equipment demand, the flexibility is high, the method can adapt to various chip demands, more equipment can be borne in limited resources, and the actual application demand is met.

Description

Technical Field

[0001] The present invention relates to the field of PCIe technology, and in particular to a method, storage medium, device and system for optimizing memory allocation of a PCIe device. Background Art

[0002] The PCIe (Peripheral Component Interconnect Express) bus architecture is a high-speed serial interface used to connect external devices in a computer system. It uses a new serial communication protocol, which has higher bandwidth and lower latency than the traditional PCI bus architecture. The PCIe bus architecture uses a point-to-point connection method, that is, each device is directly connected to the host, avoiding bus contention issues.

[0003] At present, the existing Linux kernel allocates memory space to PCIe devices in a uniform manner according to the principle of allocating memory from large to small according to the PCIe device application in order to reduce memory fragmentation. Figure 1 For example, the current Linux system allocates memory for PCIe devices as follows:

[0004] 1. During the Linux system initialization phase, the PCI bus tree is enumerated to obtain the memory size of all PCI devices (i.e., EP, End Point) in the current PCI bus, that is, the size of the memory resource request; for example, Figure 1 EP0 is 128M, 128M=2 27 , that is, the data width of EP0 is 27bit, EP1 is 64M, and EP2 is 256M;

[0005] 2. During the initialization phase of the CPU PCIe controller (i.e., RC, Root Complex, root endpoint), the memory resources of the current RC are obtained by parsing the device tree file (dts); for example, Figure 1 The RC can allocate 512M memory, which will be allocated to each EP in the PCI bus later;

[0006] 3. If Figure 1 As shown in Figure 1, when allocating memory, the Linux system first writes the memory resource requests of each EP into the memory request linked list in descending order; Figure 1 As shown in , the memory request linked list in process 3 indicates the size of PCIe memory space required by each peripheral, which is arranged in descending order and put into the memory request linked list. Only the request size of each EP is placed in the linked list, and no memory address is actually allocated to the EP at this time;

[0007] 4. If Figure 1As shown in the figure, when actually allocating memory for PCIe devices, the Linux system allocates memory for each EP based on the memory request list and the principle of address alignment (i.e., bit alignment); Figure 1 As shown in , in process 4, each element in the memory request list is taken out and allocated in combination with the RC memory address of the CPU. For example, if the address range of RC is 0x1000,0000 to 0x3000,0000, then according to the 256M space required by EP2, the address allocation is 0x1000,0000 to 0x1fff,ffff.

[0008] However, in practical applications, the current PCIe device memory allocation method still has the following problems:

[0009] 1. When users have multiple PCIe device memory allocation requirements, especially when there is a priority allocation requirement within the limited range of the PCIe controller, the existing Linux kernel cannot configure and adjust the PCIe memory allocation according to user requirements;

[0010] 2. When the memory space actually used by the PCIe device is smaller than the initial hardware setting, its memory requirement size cannot be modified. This may cause the CPU-side RC (i.e. PCIe controller) to be unable to allocate memory for the PCIe device due to limited space, or the allocated memory address cannot meet the PCIe device hardware requirements. Summary of the invention

[0011] The purpose of the present invention is to provide a PCIe device optimized memory allocation method, storage medium, device and system, which can not only modify the memory requirement size according to the memory space actually used by the PCIe device, but also flexibly configure the memory allocation strategy according to the device-side requirements. It has strong flexibility and can adapt to the requirements of various chips. It can carry more devices within limited resources and meet actual application needs.

[0012] To achieve the above objectives, in a first aspect, an embodiment of the present invention provides a method for optimizing memory allocation of a PCIe device, the method comprising:

[0013] The preset memory size configuration interface is used to set the memory size required by the PCIe device during the PCIe enumeration process; the preset allocation strategy configuration interface is used to set the memory allocation strategy of the PCIe device; when allocating memory, the memory resource requests of each PCIe device are sorted according to the memory allocation strategy and written into a memory request linked list; the PCIe controller resources are read, and memory space is allocated to each PCIe device in accordance with the order in the memory request linked list and according to the set memory size required by the PCIe device, combined with the base address alignment principle.

[0014] In combination with the first aspect, in one implementation, using a preset memory size configuration interface, setting the memory size required by the PCIe device during the PCIe enumeration process includes:

[0015] The memory size required by the PCIe device set by the user is obtained through the memory size configuration interface; the original memory size of the PCIe device is obtained from the hardware; when the original memory size in the hardware is different from the memory size required by the PCIe device set by the user, the memory size required by the PCIe device set by the user is saved as the memory size required to be applied for by the PCIe device.

[0016] In combination with the first aspect, in one implementation, the memory allocation strategy includes: priority sorting, sorting from large to small, and sorting from small to large.

[0017] In combination with the first aspect, in one embodiment, when the memory allocation policy of the PCIe device is set to priority sorting, the priority of each PCIe device will be configured according to user needs; wherein, the priority of the PCIe device is indicated by adding specific variables in the Linux standard structure struct pci_dev of the PCIe device.

[0018] In combination with the first aspect, in one implementation, the memory resource requests of each PCIe device are sorted according to the memory allocation strategy and written into a memory request linked list, including:

[0019] If the memory allocation strategy is to sort from large to small, then keep the memory resource requests in a descending order and put them into the memory request linked list;

[0020] If the memory allocation strategy is to sort from small to large, the memory resource request is modified to be put into the memory request linked list in the order from small to large, and the putting method is: loop to judge the newly added memory resource request, if it is smaller than the current linked list head element, insert it to the front of the linked list, otherwise compare it with each linked list element in turn, if it is smaller than the current comparison element, insert it in front of the current comparison element;

[0021] If the memory allocation strategy is priority sorting, an arbitrary sorting method is used to sort according to priority.

[0022] In combination with the first aspect, in one implementation, when the memory size actually used by a certain PCIe device is smaller than the initial hardware setting size thereof and priority allocation is required, the method includes:

[0023] By using a preset memory size configuration interface, the memory size required by a certain PCIe device is set as the memory size actually used by the device during PCIe enumeration; by using a preset allocation strategy configuration interface, the memory allocation strategy is set to priority sorting, and the priority of the certain PCIe device is set to the highest; when allocating memory, the memory resource requests of each PCIe device are sorted according to priority and written into a memory request linked list; the PCIe controller resources are read, and memory space is allocated to each PCIe device in accordance with the order in the memory request linked list, according to the set memory size required by the PCIe device, and in combination with the base address alignment principle.

[0024] In combination with the first aspect, in one implementation, when the memory size actually used by a certain PCIe device is smaller than the initial hardware setting size thereof, and the freed memory thereof can be used by a new PCIe device, the method includes:

[0025] By using a preset memory size configuration interface, the memory size required by a certain PCIe device is set to the memory size actually used by the device during PCIe enumeration; at the same time, the required memory size is set for the new PCIe device; by using a preset allocation strategy configuration interface, the memory allocation strategy of the PCIe device is set; when allocating memory, the memory resource request of the new PCIe device is added, and the memory resource requests of all current PCIe devices are written into a memory request linked list according to the set allocation strategy; the PCIe controller resources are read, and memory space is allocated to each PCIe device in accordance with the order in the memory request linked list and the memory size required by the set PCIe device, combined with the base address alignment principle.

[0026] In a second aspect, an embodiment of the present invention further provides a storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the method in the embodiment of the first aspect.

[0027] In a third aspect, an embodiment of the present invention further provides an electronic device, comprising a processor, a memory, and a PCIe device optimized memory allocation program stored in the memory and executable by the processor, wherein when the PCIe device optimized memory allocation program is executed by the processor, the steps of the method in the embodiment of the first aspect are implemented.

[0028] In a fourth aspect, an embodiment of the present invention further provides a PCIe device optimized memory allocation system based on the method in the embodiment of the first aspect, comprising: a memory size configuration module, an allocation strategy configuration module, a linked list modification module and a memory allocation module;

[0029] The memory size configuration module is used to: use a preset memory size configuration interface to set the memory size required by the PCIe device during the PCIe enumeration process;

[0030] The allocation strategy configuration module is used to: use a preset allocation strategy configuration interface to set a memory allocation strategy for the PCIe device;

[0031] The linked list modification module is used to: when allocating memory, sort the memory resource requests of each PCIe device according to the memory allocation strategy and write them into the memory request linked list;

[0032] The memory allocation module is used to: read PCIe controller resources, allocate memory space to each PCIe device according to the order in the memory request linked list, according to the memory size required by the set PCIe device, and in combination with the base address alignment principle.

[0033] The beneficial effects brought by the technical solution provided by the embodiments of the present application include:

[0034] This embodiment is designed with a memory size configuration interface, which can be used to realize the resetting of the memory size required by the PCIe device. In the case where the memory size actually used by the PCIe device does not match the size initially set by the hardware, the memory size configuration interface can be used to flexibly set the memory size required by the PCIe device, solving the problem that the required memory size cannot be modified in the prior art. In addition, this method of modifying the kernel code instead of modifying the ASIC hardware can also greatly reduce the cost of hardware revision, which has practical economic benefits.

[0035] At the same time, this embodiment is also specially designed with an allocation strategy configuration interface, which can be used to configure the memory allocation strategy of the PCIe device, which can meet various memory allocation needs, has strong flexibility, can adapt to various chip requirements, and can carry more devices within limited resources to meet actual application needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic diagram of a Linux system allocating memory to a PCIe device in the prior art;

[0037] Figure 2 A flowchart of an embodiment of a method for optimizing memory allocation for a PCIe device of the present application;

[0038] Figure 3 A schematic diagram of a scenario in which the PCIe device optimization memory allocation method of the present application is applied in an example;

[0039] Figure 4 A schematic diagram of a scenario in which the PCIe device optimization memory allocation method of the present application is applied in another example;

[0040] Figure 5 This is a schematic diagram of the hardware structure of an embodiment of the electronic device of the present application;

[0041] Figure 6 A schematic diagram of the functional modules of an embodiment of a system for optimizing memory allocation for PCIe devices of the present application. DETAILED DESCRIPTION

[0042] In order to make the technical problems, technical solutions and advantages to be solved by the present invention more clear, the technical solutions of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0043] However, it should be noted that the examples to be introduced below are only some specific examples, and are not intended to limit the embodiments of the present invention to the following specific steps, values, conditions, data, sequences, etc. All other embodiments obtained by ordinary technicians in this field without creative work based on the embodiments in this application are within the scope of protection of this application.

[0044] Embodiment 1

[0045] The present application embodiment provides a method for optimizing memory allocation of a PCIe device. Figure 2 , Figure 2 This is a flow chart of the first embodiment of the PCIe device optimization memory allocation method of this application. Figure 2 As shown, a method for optimizing memory allocation of a PCIe device includes:

[0046] Step A: Use the preset memory size configuration interface to set the memory size required by the PCIe device during the PCIe enumeration process.

[0047] It is understandable that the existing PCIe device memory allocation method cannot modify the PCIe device memory requirement size, and is configured according to the initial hardware setting size. In this embodiment, a Linux kernel-based software interface, the memory size configuration interface, is specially designed to achieve the resetting of the required memory size of the PCIe device. In the case where the actual memory size used by the PCIe device does not match the initial hardware setting size, the memory size configuration interface can be used to flexibly set the required memory size of the PCIe device, solving the problem that the prior art cannot modify the required memory size. In addition, this method of modifying the kernel code instead of modifying the ASIC hardware can also greatly reduce the cost expenditure of hardware revision, which has practical economic benefits.

[0048] Exemplarily, as an optional implementation, in step A, the memory size required by the PCIe device is set during the PCIe enumeration process by using a preset memory size configuration interface, which specifically includes the following operations:

[0049] A1. Obtain the required memory size of the PCIe device (ie, EP) set by the user through the memory size configuration interface. In actual applications, the required memory size of the PCIe device set by the user can be passed as an input parameter to the function of the memory size configuration interface to obtain the required memory size set by the user.

[0050] A2. Use the Pci_size function of the Linux system to obtain the original memory size of the PCIe device from the hardware.

[0051] A3. When the original memory size in the hardware is different from the memory size required by the PCIe device set by the user, the memory size required by the PCIe device set by the user is saved as the memory size required to be applied for by the PCIe device, so that it can be used when the PCIe controller (i.e., RC) allocates memory later. In actual applications, a variable can be set in advance to store the memory size required to be applied for by the PCIe device. For example, the size variable can be added to the Linux standard structure Struct pci_dev of the PCIe device to store the memory size required to be applied for by the PCIe device. When the original memory size in the hardware is different from the memory size required by the PCIe device set by the user, the setting is saved by assigning the memory size required by the PCIe device set by the user to the size variable in the dev structure.

[0052] For example, the pseudo code of the preset memory size configuration interface may be as follows:

[0053]

[0054] Step B: Use the preset allocation strategy configuration interface to set the memory allocation strategy of the PCIe device.

[0055] It is also understandable that the existing Linux kernel cannot configure and adjust PCIe memory allocation according to user needs. In this embodiment, a Linux kernel-based allocation policy configuration interface is specially designed to implement the configuration of the memory allocation policy of the PCIe device, which can meet various memory allocation requirements, has strong flexibility, can adapt to various chip requirements, can carry more devices within limited resources, and meet actual application needs.

[0056] Specifically, the memory allocation strategy described in this embodiment includes priority sorting, large to small sorting, and small to large sorting. Among them, priority sorting refers to the memory allocation principle of the PCIe device being allocated according to the priority order configured by each PCIe device; large to small sorting / small to large sorting refers to the memory allocation principle of the PCIe device being sorted from large to small / small to large according to the memory size required by each PCIe device.

[0057] Further, it is understandable that in actual applications, when the memory allocation strategy of the PCIe device is set to priority sorting, it is necessary to configure the priority of each PCIe device according to user needs. In actual applications, a variable can be set in advance to indicate the priority of each PCIe device. For example, the Linux standard structure Structpci_dev of the PCIe device can be used to indicate the priority of the PCIe device by adding a prio variable. When the priority of the PCIe device set by the user is obtained through the interface, the priority of the PCIe device set by the user is assigned to the prio variable in the dev structure to save the setting for subsequent use when the PCIe controller (ie, RC) allocates memory.

[0058] For example, the pseudo code of the software interface for configuring the priority of each PCIe device may be as follows:

[0059]

[0060] The pseudo code of the preset allocation strategy configuration interface may be as follows:

[0061]

[0062]

[0063] Step C: when allocating memory, sort the memory resource requests of each PCIe device according to the memory allocation strategy and write them into a memory request linked list.

[0064] It can be understood that in this embodiment, the Linux system software will be modified so that when allocating memory, it will not write the memory resource requests of each PCIe device into the memory request linked list in descending order according to the traditional method, but will write the memory resource requests of each PCIe device into the memory request linked list according to the set memory allocation policy.

[0065] Exemplarily, as an optional implementation, in step C, the memory resource requests of each PCIe device are sorted according to the memory allocation strategy and written into the memory request linked list, which specifically includes the following operations:

[0066] C1. If the memory allocation strategy is to sort from large to small, the original allocation principle of the Linux kernel is maintained, that is, the memory resource requests are placed in the memory request linked list in a descending order. The specific placement method is a prior art and will not be described here. It can be understood that since the existing allocation method is to write the memory resource requests of each PCIe device into the memory request linked list in a descending order, when the memory allocation strategy is also set to sort from large to small, the Linux system software does not need to be modified, and the original allocation principle of the Linux kernel can be maintained.

[0067] C2. If the memory allocation strategy is to sort from small to large, then modify the memory resource request and put it into the memory request linked list in the order from small to large. The way of putting it in is: loop to judge the newly added memory resource request. If it is smaller than the current linked list head element, insert it to the front of the linked list. Otherwise, compare it with each linked list element in turn. If it is smaller than the current comparison element, insert it in front of the current comparison element. It can be understood that after sorting the memory request linked list from small to large in this way, the subsequent Linux system will take elements from the linked list head, and then allocate addresses according to the allocatable memory resources, so as to realize the strategy of sorting from small to large.

[0068] C3. If the memory allocation strategy is priority sorting, use any sorting method to sort according to priority.

[0069] For example, the pseudo code for sorting the memory resource requests of each PCIe device according to the memory allocation strategy and writing them into the memory request linked list may be as follows:

[0070]

[0071] In the above pseudo code, struct list_head is the memory request list structure of the Linux kernel, which is a bidirectional linked list. When the memory allocation strategy is to sort from large to small, the original allocation principle of the Linux kernel is maintained; when the memory allocation strategy is to sort from small to large, the memory resource request needs to be modified to be sorted from small to large and put into the memory request list to meet the strategy of sorting from small to large.

[0072] Step D, read the PCIe controller (i.e. RC) resources, and allocate memory space for each PCIe device according to the order in the memory request list, the memory size required by the set PCIe device, and the base address alignment principle. It can be understood that in this step, memory will be allocated to each EP in the memory request list according to the resource range of RC, combined with the address alignment principle. In specific implementation, this part of the implementation code can refer to the original Linux kernel code to align the address of each EP, i.e. 2 nBit alignment, assigning a PCIe physical address to each EP.

[0073] In order to better illustrate the details of implementing various PCIe device memory allocation scenarios in this embodiment and better understand the technical effects of this embodiment, several typical memory allocation scenarios will be described below with reference to the accompanying drawings and specific examples.

[0074] Scenario 1:

[0075] When some EPs (PCIe devices) have special requirements for addresses, or the user wants to ensure that a certain EP is allocated first, the method of this embodiment can be used to set the priority of each EP and allocate memory to certain EPs according to the priority-sorted memory allocation strategy, thereby meeting various memory allocation requirements.

[0076] For example, suppose the initial hardware memory space requirement of EP1 (i.e. the original memory size of the PCIe device in the hardware) is 2 n bit, that is, the address width is n, but in actual use, the address width is only n-2, that is, the actual space requirement is 2 n-2 For the traditional Linux kernel, its memory size cannot be changed. Therefore, for such a situation, the memory size configuration interface of this embodiment can be used to reset the memory size required by the PCIe device during the PCIe enumeration process. However, since its hardware cannot be actually changed, the BAR base address of the allocated memory is 2 n Alignment means that the base address n-1…0 of the BAR needs to be set to 0. Figure 3 For example, assuming that the hardware requirement of EP1 is 256M, that is, 28-bit bit width, the actual usage is 64M, that is, 26-bit bit width, but the address needs to be 28-bit aligned, so the priority is set to EP1>EP0>EP2. The Linux kernel allocates memory to each EP according to the priority and base address alignment principle. The allocation is as follows Figure 3 As shown, it can meet user needs.

[0077] Scenario 2:

[0078] When the RC (PCIe controller) resources are limited but there are many EPs (PCIe devices), and the total EP memory resources are greater than the RC memory resources, the method of this embodiment can be used to adjust the memory size of some EPs, expand the available memory resources, and carry more EPs, under the premise of meeting the hardware data width. For example, assuming that the hardware initial design data width of a certain EP is n, and the actual data width used is n-1, the BAR space size is adjusted to 2 during the PCIe enumeration process through the memory size configuration interface. n-1 , so the extra 2 n-1 The space of that size can be allocated to other EPs.

[0079] For example, Figure 4 For example, when there are 4 EPs, the existing Linux kernel RC resources cannot allocate resources for these 4 EPs (the total memory resources of the 4 EPs is 128+64+256+128=576M, which is greater than the RC memory resources of 512M). Assume that the hardware initial setting memory space of EP2 is 256M, but only 128M is actually used. You can modify its memory size to 128M through the memory size configuration interface, and the free 128M can be allocated to the newly added EP3, such as Figure 4 Therefore, the method of this embodiment can meet the requirement of carrying more EPs when RC resources are limited, and the EPs can also have more CPU selectivity through the method of the embodiment.

[0080] It can be seen from the above content that, compared with the existing PCIe device memory allocation method, this embodiment is designed with a memory size configuration interface, which can be used to realize the resetting of the memory size required for the PCIe device. In the case where the memory size actually used by the PCIe device does not match the size initially set by the hardware, the memory size configuration interface can be used to flexibly set the memory size required by the PCIe device, solving the problem that the prior art cannot modify the required memory size. In addition, this method of replacing the modification of ASIC hardware by modifying the kernel code can also greatly reduce the cost expenditure of hardware revision, which has practical economic benefits. At the same time, this embodiment is also specially designed with an allocation strategy configuration interface, which can be used to realize the configuration of the memory allocation strategy of the PCIe device, which can meet various memory allocation requirements, has strong flexibility, can adapt to various chip requirements, can carry more devices within limited resources, and meet actual application requirements.

[0081] Embodiment 2

[0082] Based on the same inventive concept, an embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, a method for optimizing memory allocation for a PCIe device as provided in any embodiment of the present invention is implemented. The method for optimizing memory allocation for a PCIe device can refer to the various embodiments of the method for optimizing memory allocation for a PCIe device of the present application, and will not be described in detail here.

[0083] The computer storage medium of the embodiment of the present invention can adopt any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to: an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples (non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, a computer-readable storage medium can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it.

[0084] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, which carry computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0085] The program code embodied on the computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0086] Computer program code for performing the operations of the present invention may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0087] Embodiment 3

[0088] Based on the same inventive concept, an embodiment of the present invention further provides an electronic device, which may be a device with data processing function, such as a personal computer (PC), a notebook computer, or a server.

[0089] Reference Figure 5 , Figure 5 Schematic diagram of the hardware structure of the electronic device of the present application. In the embodiment of the present application, the electronic device may include a processor, a memory, a communication interface and a communication bus.

[0090] The communication bus may be of any type and is used to interconnect the processor, the memory, and the communication interface.

[0091] Communication interfaces include input / output (I / O) interfaces, physical interfaces, and logical interfaces, which are used to interconnect devices within electronic devices, as well as interfaces used to interconnect electronic devices with other devices (such as other computing devices or user devices). Physical interfaces can be Ethernet interfaces, optical fiber interfaces, ATM interfaces, etc.; user devices can be display screens (Display), keyboards (Keyboard), etc.

[0092] The memory can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), flash memory, optical storage, hard disk, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), etc.

[0093] The processor may be a general-purpose processor, and the general-purpose processor may call the PCIe device optimized memory allocation program stored in the memory, and execute the PCIe device optimized memory allocation method provided in the embodiment of the present application. For example, the general-purpose processor may be a central processing unit. Among them, the method executed when the PCIe device optimized memory allocation program is called can refer to the various embodiments of the PCIe device optimized memory allocation method of the present application, which will not be repeated here.

[0094] Embodiment 4

[0095] join Figure 6 As shown, based on the same inventive concept, an embodiment of the present invention also provides a PCIe device optimized memory allocation system, which includes a memory size configuration module, an allocation strategy configuration module, a linked list modification module and a memory allocation module.

[0096] Among them, the memory size configuration module is used to: use the preset memory size configuration interface to set the memory size required by the PCIe device during the PCIe enumeration process. The allocation strategy configuration module is used to: use the preset allocation strategy configuration interface to set the memory allocation strategy of the PCIe device. The linked list modification module is used to: when allocating memory, sort the memory resource requests of each PCIe device according to the memory allocation strategy and write them into the memory request linked list. The memory allocation module is used to: read the PCIe controller resources, and allocate memory space to each PCIe device according to the order in the memory request linked list, according to the set memory size required by the PCIe device, and in combination with the base address alignment principle.

[0097] As can be seen from the above content, the system of this embodiment can be used to reset the memory size required for the PCIe device. In the case where the memory size actually used by the PCIe device does not match the size initially set by the hardware, the memory size configuration module of this system can be used to flexibly set the memory size required for the PCIe device, solving the problem that the prior art cannot modify the required memory size. Moreover, this method of modifying the kernel code instead of modifying the ASIC hardware can also greatly reduce the cost expenditure of hardware revision, which has practical economic benefits. At the same time, the system of this embodiment can also be used to configure the memory allocation strategy of the PCIe device, which can meet various memory allocation requirements, has strong flexibility, can adapt to various chip requirements, can carry more PCIe devices within limited resources, and meet actual application needs.

[0098] It should be noted that the various variations and specific examples in the aforementioned method embodiments are also applicable to the system of this embodiment. Through the detailed description of the aforementioned method, those skilled in the art can clearly understand the implementation method of the system in this embodiment, so for the sake of brevity of the specification, they will not be described in detail here.

[0099] Note: The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0100] The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices. The terms "first", "second" and "third" are used to distinguish different objects, etc., and do not represent a sequence, nor do they limit "first", "second" and "third" to different types.

[0101] In the description of the embodiments of the present application, "exemplary", "for example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary", "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary", "for example" or "for example" is intended to present related concepts in a specific way.

[0102] In the description of the embodiments of the present application, unless otherwise specified, “ / ” means or, for example, A / B can mean A or B; the “and / or” in the text is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, “multiple” refers to two or more than two.

[0103] In some processes described in the embodiments of the present application, multiple operations or steps that appear in a specific order are included, but it should be understood that these operations or steps may not be executed in the order in which they appear in the embodiments of the present application or in parallel, and the sequence number of the operation is only used to distinguish the different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed in sequence or in parallel, and these operations or steps may be combined.

[0104] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, disk, CD) as described above, and includes a number of instructions for a terminal device to execute the methods described in each embodiment of the present application.

[0105] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for optimizing memory allocation of a PCIe device, characterized in that: The method includes: Use the preset memory size configuration interface to set the required memory size of the PCIe device during PCIe enumeration; Use the preset allocation strategy configuration interface to set the memory allocation strategy of the PCIe device; When allocating memory, the memory resource requests of each PCIe device are sorted according to the memory allocation strategy and written into the memory request linked list; The PCIe controller resources are read, and memory space is allocated to each PCIe device in accordance with the order in the memory request linked list and the memory size required by the set PCIe device in combination with the base address alignment principle.

2. The PCIe device optimized memory allocation method according to claim 1, characterized in that: Use the preset memory size configuration interface to set the required memory size of the PCIe device during the PCIe enumeration process, including: Obtaining the required memory size of the PCIe device set by the user through the memory size configuration interface; Get the raw memory size of the PCIe device from the hardware; When the original memory size in the hardware is different from the memory size required by the PCIe device set by the user, the memory size required by the PCIe device set by the user is saved as the memory size that needs to be applied for by the PCIe device.

3. The PCIe device optimized memory allocation method according to claim 1, characterized in that: The memory allocation strategies include: priority sorting, sorting from large to small, and sorting from small to large.

4. The PCIe device optimized memory allocation method according to claim 3, characterized in that: When the memory allocation policy of the PCIe device is set to priority sorting, the priority of each PCIe device will be configured according to user needs; wherein, the priority of the PCIe device is indicated by adding a specific variable in the Linux standard structure struct pci_dev of the PCIe device.

5. The PCIe device optimized memory allocation method according to claim 3, characterized in that: The memory resource requests of each PCIe device are sorted according to the memory allocation strategy and written into the memory request linked list, including: If the memory allocation strategy is to sort from large to small, then keep the memory resource requests in a descending order and put them into the memory request linked list; If the memory allocation strategy is to sort from small to large, the memory resource request is modified to be put into the memory request linked list in the order from small to large, and the putting method is: loop to judge the newly added memory resource request, if it is smaller than the current linked list head element, insert it to the front of the linked list, otherwise compare it with each linked list element in turn, if it is smaller than the current comparison element, insert it in front of the current comparison element; If the memory allocation strategy is priority sorting, an arbitrary sorting method is used to sort according to priority.

6. The PCIe device optimized memory allocation method according to claim 3, characterized in that: When the memory size actually used by a PCIe device is smaller than the initial hardware setting size and needs to be allocated first, the method includes: Using a preset memory size configuration interface, during the PCIe enumeration process, the memory size required by the certain PCIe device is set to the memory size actually used by the device; Using a preset allocation strategy configuration interface, setting the memory allocation strategy to priority sorting, and setting the priority of the certain PCIe device to the highest; When allocating memory, the memory resource requests of each PCIe device are sorted by priority and written into the memory request list; The PCIe controller resources are read, and memory space is allocated to each PCIe device in accordance with the order in the memory request linked list and the memory size required by the set PCIe device in combination with the base address alignment principle.

7. The PCIe device optimized memory allocation method according to claim 3, characterized in that: When the memory size actually used by a certain PCIe device is smaller than the initial hardware setting size thereof, and the freed memory thereof can be used by a new PCIe device, the method includes: Using a preset memory size configuration interface, during the PCIe enumeration process, the required memory size of the certain PCIe device is set to the memory size actually used by the device; at the same time, the required memory size is set for the new PCIe device; Use the preset allocation strategy configuration interface to set the memory allocation strategy of the PCIe device; When allocating memory, add the memory resource request of the new PCIe device, and write the memory resource requests of all current PCIe devices into the memory request linked list according to the set allocation policy; The PCIe controller resources are read, and memory space is allocated to each PCIe device in accordance with the order in the memory request linked list and the memory size required by the set PCIe device in combination with the base address alignment principle.

8. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

9. An electronic device, characterized in that: The electronic device includes a processor, a memory, and a PCIe device optimized memory allocation program stored in the memory and executable by the processor, wherein when the PCIe device optimized memory allocation program is executed by the processor, the steps of the PCIe device optimized memory allocation method as described in any one of claims 1 to 7 are implemented.

10. A PCIe device optimized memory allocation system based on the method according to any one of claims 1 to 7, characterized in that: The PCIe device optimized memory allocation system includes a memory size configuration module, an allocation strategy configuration module, a linked list modification module and a memory allocation module; The memory size configuration module is used to: use a preset memory size configuration interface to set the memory size required by the PCIe device during the PCIe enumeration process; The allocation strategy configuration module is used to: use a preset allocation strategy configuration interface to set a memory allocation strategy for the PCIe device; The linked list modification module is used to: when allocating memory, sort the memory resource requests of each PCIe device according to the memory allocation strategy and write them into the memory request linked list; The memory allocation module is used to read PCIe controller resources, allocate memory space to each PCIe device according to the order in the memory request linked list and the memory size required by the set PCIe device in combination with the base address alignment principle.

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