Memory access method and device, computer equipment and storage medium

Abstract

The invention relates to a memory access method and device, computer equipment and a storage medium. The method comprises the following steps: determining a plurality of non-uniform memory access nodes, and allocating resources for the non-uniform memory access nodes; dividing a storage object in the storage system to obtain a plurality of data segments; binding the plurality of data segments with the plurality of non-uniform memory access nodes in sequence; and in response to a received data access request, obtaining a logic block address of the data access request, and determining a target data segment corresponding to the data access request according to the logic block address, so as to perform memory access through a target non-uniform memory access node corresponding to the target data segment. By adopting the method, cross-node access to the memory can be avoided, and meanwhile, the problem that computing resources and memory resources cannot be fully used or a wooden barrel effect exists in the performance of a storage system in an existing scheme is solved.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to a memory access method, device, computer equipment and storage medium. Background Art

[0002] As the number of cores increases, the processor evolves from the SMP (Symmetric Multi-Processor) architecture to the NUMA (Non-Uniform Memory Access) architecture. However, under the NUMA architecture, when the processor core of a NUMA node accesses the memory of another node, it needs to access it through the QPI bus between the nodes, which will result in a large performance difference when the processor accesses the memory of the current node and other nodes.

[0003] In order to solve the I / O processing of the storage system and reduce the memory of the cross-NUMA access control block, the solutions adopted in the prior art are: 1. Bind NUMA nodes according to storage objects. However, if the user only configures one storage object, only the computing and memory resources of one NUMA node will be used during the I / O access process, which will lead to waste of resources of other nodes; 2. Bind NUMA nodes according to modules. However, the functions of each module in the IO stack are different, and the computing amount and memory access times of each module will also be different. This will lead to large differences in the processor busyness and memory access volume of the NUMA node. If the CPU and memory resources of a NUMA node reach a bottleneck, the barrel effect will occur. Summary of the invention

[0004] Based on this, it is necessary to provide a memory access method, apparatus, computer device and storage medium that can solve the performance problems caused by cross-node memory access in response to the above technical problems.

[0005] In one aspect, a memory access method is provided, the method comprising:

[0006] Determine a plurality of non-uniform memory access nodes, and allocate resources to the non-uniform memory access nodes;

[0007] Divide the storage objects in the storage system to obtain multiple data segments;

[0008] Binding the plurality of data segments to the plurality of non-uniform memory access nodes in sequence;

[0009] In response to receiving a data access request, a logical block address of the data access request is obtained, and a target data segment corresponding to the data access request is determined according to the logical block address, so as to perform memory access through a target non-consistent memory access node corresponding to the target data segment.

[0010] In one embodiment, the determining a plurality of non-uniform memory access nodes and allocating resources to the non-uniform memory access nodes respectively includes:

[0011] Determine the number of the non-uniform memory access nodes according to the hardware configuration;

[0012] A corresponding number of thread pools and memory pools are created according to the number of the non-consistent memory access nodes, and the threads in the thread pools and the memories in the memory pools are respectively bound to the processor cores of the corresponding non-consistent memory access nodes.

[0013] In one embodiment, the storage object in the storage system is divided to obtain a plurality of data segments, including:

[0014] Acquire a storage object in the storage system and a storage space of the storage object, wherein the storage space of the storage object is addressed according to a linear space;

[0015] Setting a space granularity, and segmenting the storage space of the storage object according to the space granularity to obtain a plurality of data segments;

[0016] The multiple data segments are linearly numbered in sequence to obtain a segment number of each data segment.

[0017] In one embodiment, before sequentially binding the multiple data segments to the multiple non-uniform memory access nodes, the method further includes:

[0018] Respectively obtain memory device information of the non-uniform memory access node, and determine whether the non-uniform memory access node is valid based on the memory device information;

[0019] An available non-uniform memory access node is determined according to the determination result, and a node number of the available non-uniform memory access node is obtained.

[0020] In one embodiment, the step of sequentially binding the plurality of data segments to the plurality of non-uniform memory access nodes comprises:

[0021] sorting the data segments and the available non-uniform memory access nodes according to the segment numbers and the node numbers respectively to form a data segment sequence and a node sequence;

[0022] Based on the data segment sequence and the node sequence, establishing a mapping relationship between the segment numbers of the data segments and the node numbers of the available non-uniform memory access nodes;

[0023] The multiple data segments are sequentially and cyclically bound to the available non-uniform memory access nodes according to the mapping relationship.

[0024] In one embodiment, in response to receiving a data access request, obtaining a logical block address of the data access request, and determining a target data segment corresponding to the data access request according to the logical block address, so as to perform memory access through a target non-consistent memory access node corresponding to the target data segment, comprises:

[0025] Receiving a data access request, wherein the data access request includes a data write request and a data read request;

[0026] Acquire a logical block address of the data access request, and divide the logical block address of the data access request by the spatial granularity to determine a segment number of a target data segment corresponding to the data access request;

[0027] Determine a target inconsistency memory access node corresponding to the data access request according to a mapping relationship between the segment number and the node number;

[0028] In response to the data access request being a data read request, performing memory access on the target data segment through the target non-uniform memory access node;

[0029] In response to the data access request being a data write request, obtaining a first data amount of the target non-consistent memory access node and a second data amount of the data to be written corresponding to the data write request, wherein the first data amount is a remaining data amount of the corresponding memory;

[0030] comparing the first amount of data with the second amount of data;

[0031] In response to the first data amount being greater than or equal to the second data amount, the data to be written is written into a memory corresponding to the target non-uniform memory access node.

[0032] In one of the embodiments, performing memory access through a target non-consistent memory access node corresponding to the target data segment includes:

[0033] In response to the data access request being a data read request, respectively acquiring computing resources and memory resources from a thread pool and a memory pool corresponding to the target non-consistent memory access node;

[0034] The target data segment is accessed based on the computing resources and the memory resources.

[0035] In another aspect, a memory access device is provided, the device comprising:

[0036] An allocation module, configured to determine a plurality of non-uniform memory access nodes and allocate resources to the non-uniform memory access nodes;

[0037] A partitioning module is used to partition the storage objects in the storage system to obtain multiple data segments;

[0038] A binding module, used for sequentially binding the multiple data segments with the multiple non-uniform memory access nodes;

[0039] An access module is used to obtain a logical block address of the data access request in response to receiving the data access request, and determine a target data segment corresponding to the data access request according to the logical block address, so as to perform memory access through a target non-consistent memory access node corresponding to the target data segment.

[0040] In another aspect, a computer device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the following steps are implemented:

[0041] Determine a plurality of non-uniform memory access nodes, and allocate resources to the non-uniform memory access nodes;

[0042] Divide the storage objects in the storage system to obtain multiple data segments;

[0043] Binding the plurality of data segments to the plurality of non-uniform memory access nodes in sequence;

[0044] In response to receiving a data access request, a logical block address of the data access request is obtained, and a target data segment corresponding to the data access request is determined according to the logical block address, so as to perform memory access through a target non-consistent memory access node corresponding to the target data segment.

[0045] In another aspect, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0046] Determine a plurality of non-uniform memory access nodes, and allocate resources to the non-uniform memory access nodes;

[0047] Divide the storage objects in the storage system to obtain multiple data segments;

[0048] Binding the plurality of data segments to the plurality of non-uniform memory access nodes in sequence;

[0049] In response to receiving a data access request, a logical block address of the data access request is obtained, and a target data segment corresponding to the data access request is determined according to the logical block address, so as to perform memory access through a target non-consistent memory access node corresponding to the target data segment.

[0050] The above-mentioned memory access method, apparatus, computer equipment and storage medium configure NUMA nodes and allocate computing resources and memory resources, and then divide the storage object into multiple data segments according to the storage space, and bind different NUMA nodes respectively. When a data access request is received, the target data segment to be accessed is calculated according to the logical block address, thereby avoiding cross-NUMA node access to memory, and solving the problem that computing resources and memory resources are not fully utilized or there is a barrel effect in the storage system performance in the existing solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 A block diagram of a non-uniform memory access architecture in the prior art;

[0052] Figure 2 A schematic diagram of a storage system I / O stack process in one embodiment;

[0053] Figure 3 A schematic diagram of a flow chart of a memory access method in an embodiment;

[0054] Figure 4 A block diagram of a non-uniform memory access architecture in one embodiment;

[0055] Figure 5 A schematic diagram of storage object space division in one embodiment;

[0056] Figure 6 A schematic diagram of a mapping relationship between data segments and non-consistent memory access nodes in one embodiment;

[0057] Figure 7 is a structural block diagram of a memory access device in one embodiment;

[0058] Figure 8 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0060] like Figure 1As shown, in the traditional technical solution, the processor cores under the NUMA architecture are divided into multiple NUMA nodes, and each node has its own independent memory access controller, memory space and PCIE bus system. When each node accesses its own memory, it uses its own memory access controller and bus system without affecting each other. This can improve the concurrent access capability of the memory and solve the memory access bottleneck problem caused by all processor cores sharing a bus under the SMP architecture. However, under the NUMA architecture, when the processor core of a NUMA node accesses the memory of another node, it needs to access it through the QPI bus between nodes, which will cause the processor to access the memory of this node and other nodes. The performance difference is large, for example, the latency of accessing the memory of this node is 60 to 100ns, while the latency of accessing the memory across nodes is 140 to 200ns. Therefore, under the NUMA architecture, in order to improve system performance, the system and application programs try to use the memory of this node as much as possible during operation to reduce memory access across nodes.

[0061] like Figure 2 As shown in the figure, the IO stack version of a storage system that processes I / O requests includes the following main modules: front-end protocol, which interacts with the host through the storage protocol and parses the I / O requests submitted by the host according to the protocol content; disaster recovery service, which mainly provides disaster recovery services such as snapshot, backup, remote replication, and active-active; cache, which caches hot data to reduce the access latency of the host's I / O requests; storage pool, which virtualizes the storage space of the storage system; RAID (Redundant Array of Independent Disks), which manages storage disks (including mechanical disks and SSD disks) in an array manner, provides redundant protection and multi-disk concurrent processing capabilities; back-end protocol, which manages storage disks and submits I / O requests to the disks through storage protocols for data access.

[0062] An I / O request needs to be passed through the modules at each layer of the I / O stack. Each module needs to generate and save some control information during the processing of the I / O request. This collection of control information is called the I / O request control block. The information in the control block is stored in the memory. Therefore, when an I / O reaches a module, it is necessary to first apply for memory resources to save the control block information. These memories will be accessed during the I / O processing and released after the I / O processing is completed. Therefore, the storage system will have a large number of processors accessing memory during the I / O access process. If these memory accesses involve a large number of cross-node memory accesses, it will have a great impact on performance.

[0063] In one embodiment, Figure 3-6 As shown, a memory access method is provided, comprising the following steps:

[0064] Step S1, determining a plurality of non-uniform memory access nodes, and allocating resources to the non-uniform memory access nodes.

[0065] In an optional implementation, multiple non-consistent memory access nodes are determined, and resources are allocated to the non-consistent memory access nodes respectively, including: determining the number of non-consistent memory access nodes according to the hardware configuration; creating a corresponding number of thread pools and memory pools according to the number of non-consistent memory access nodes, and binding the threads in the thread pool and the memory in the memory pool to the processor cores of the corresponding non-consistent memory access nodes respectively.

[0066] like Figure 4 As shown, when the system is initialized, the number of NUMA nodes of the current system is determined according to the hardware configuration of the system. One NUMA node corresponds to one thread pool and one memory pool, so that the storage system organizes and manages computing resources and memory resources according to the granularity of NUMA nodes, which can better solve the performance problems caused by accessing memory across NUMA nodes under the NUMA architecture.

[0067] Step S2, dividing the storage object in the storage system to obtain multiple data segments.

[0068] In an optional implementation, a storage object in a storage system is divided to obtain a plurality of data segments, including: obtaining a storage object in the storage system and a storage space of the storage object, wherein the storage space of the storage object is addressed according to a linear space; setting a space granularity, and segmenting the storage space of the storage object according to the space granularity to obtain a plurality of data segments; and linearly numbering the plurality of data segments in sequence to obtain a segment number of each data segment.

[0069] The storage objects in the storage system include LUN (logical volume), RAID (disk array) and data disk (mechanical disk or SSD), which are all addressed according to linear space. Figure 2 As shown, the operation object of the front-end protocol, disaster recovery service, cache, and storage pool in the storage I / O stack is LUN (logical volume); the operation object of the RAID module is RAID; and the operation object of the back-end protocol is the data disk.

[0070] like Figure 5 As shown, the space granularity is set to 32MB, and these storage objects are divided into multiple data fragments according to the 32MB space granularity. It can be understood that the space granularity here can be set according to actual needs and is not specifically limited here.

[0071] By segmenting the storage space of the storage object according to a fixed spatial granularity and binding different NUMA nodes to each data segment, the data access path is optimized, the delay caused by cross-node communication is avoided, thereby improving the response speed and throughput of I / O operations, and ensuring that resources are used more evenly among NUMA nodes, which not only reduces the probability of the wooden barrel effect, but also improves the resource utilization of the overall system.

[0072] Step S3, binding the multiple data segments to the multiple non-uniform memory access nodes in sequence.

[0073] In an optional embodiment, before binding multiple data segments to multiple non-consistent memory access nodes in sequence, it also includes: obtaining memory device information of the non-consistent memory access nodes respectively, and judging whether the non-consistent memory access nodes are valid based on the memory device information; determining available non-consistent memory access nodes according to the judgment results, and obtaining node numbers of the available non-consistent memory access nodes.

[0074] Specifically, by judging whether the NUMA node is valid, it is possible to avoid binding data segments to invalid or faulty nodes, greatly reducing the risk of data loss or system crashes due to hardware problems. When it is detected that some NUMA nodes are unavailable, the system can dynamically adjust the binding strategy according to the actual situation and select other available nodes to continue working, thus enhancing the fault tolerance and stability of the system.

[0075] In an optional embodiment, multiple data segments are sequentially bound to multiple non-consistent memory access nodes, including: sorting the data segments and available non-consistent memory access nodes according to the segment numbers and node numbers, respectively, to form a data segment sequence and a node sequence; based on the data segment sequence and the node sequence, establishing a mapping relationship between the segment numbers of the data segments and the node numbers of the available non-consistent memory access nodes; and sequentially binding the multiple data segments to the available non-consistent memory access nodes in a loop according to the mapping relationship.

[0076] like Figure 6 As shown in the figure, taking LUN as a storage object as an example, assuming that there are 4 NUMA nodes in the storage system, LUN 0 is divided into multiple 32MB data segments, where the 1st, 2nd, 3rd, and 4th data segments are bound to the thread pools and memory pools of NUMA nodes 1, 2, 3, and 4 respectively, and the 5th data segment is bound to NUMA node 1 again, and so on. Each data segment is bound to the corresponding NUMA node in a loop according to the segment number to achieve uniform distribution.

[0077] Based on the above steps, a mapping relationship is established between the sorted segment numbers and node numbers. Through loop binding, it is ensured that each data segment can be evenly distributed to each NUMA node, which helps to achieve load balancing of each NUMA node during I / O access, avoiding the situation where some nodes are overloaded while other nodes are idle, thereby improving the resource utilization efficiency of the overall system.

[0078] Step S4, in response to receiving a data access request, obtain a logical block address of the data access request, and determine a target data segment corresponding to the data access request according to the logical block address, so as to perform memory access through a target non-consistent memory access node corresponding to the target data segment.

[0079] In an optional embodiment, in response to receiving a data access request, obtaining a logical block address of the data access request, and determining a target data segment corresponding to the data access request based on the logical block address, so as to perform memory access through a target non-consistent memory access node corresponding to the target data segment, including: receiving a data access request, the data access request including a data write request and a data read request; obtaining a logical block address of the data access request, and dividing the logical block address of the data access request by a spatial granularity to determine a segment number of the target data segment corresponding to the data access request; determining a target non-consistent memory access node corresponding to the data access request based on a mapping relationship between the segment number and the node number; in response to the data access request being a data read request, performing memory access to the target data segment through the target non-consistent memory access node; in response to the data access request being a data write request, obtaining a first data amount of the target non-consistent memory access node, and a second data amount of data to be written corresponding to the data write request, wherein the first data amount is the remaining data amount of the corresponding memory; comparing the first data amount with the second data amount; in response to the first data amount being greater than or equal to the second data amount, writing the data to be written into the memory corresponding to the target non-consistent memory access node.

[0080] Specifically, the logical block address (LBA) of the data access request is first divided by the preset space granularity, for example, 32MB here, to calculate the segment number of the data segment requested for access, and then the modulus is taken by the number of NUMA nodes to calculate the NUMA node to which the data access request belongs. The computing and memory resources required to process the request are applied from the thread pool and memory pool of the corresponding NUMA node.

[0081] Through this solution, the logical block address can be used to determine which NUMA node to obtain the computing and memory resources required to process data access requests, ensuring that each data access request can be evenly distributed to each NUMA node, maximizing the use of existing resources and achieving a more even load distribution.

[0082] In an optional embodiment, in response to the data access request being a data write request, the target non-consistent memory access node is used as the first node, wherein the first node includes the first memory; in response to the first data amount being less than the second data amount, the first memory is determined to be unavailable memory; the distance between the first node and other non-consistent memory access nodes is obtained, and the non-consistent memory access node with the smallest distance to the first node is used as the second node, wherein the second node includes the second memory; the third data amount of the second memory is compared with the second data amount, wherein the third data amount is the remaining data amount of the second memory; in response to the third data amount being greater than or equal to the second data amount, the second memory is determined to be available memory; the data write request is forwarded from the first node to the processor of the second node, and the data to be written is written into the second memory according to the processor of the second node.

[0083] In an optional embodiment, memory access is performed through a target non-consistent memory access node corresponding to a target data segment, including: in response to a data access request being a data read request, computing resources and memory resources are respectively obtained from a thread pool and a memory pool corresponding to the target non-consistent memory access node; and the target data segment is accessed based on the computing resources and the memory resources.

[0084] It should be understood that although Figure 2 The steps in the flowchart are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Moreover, Figure 2 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequentially, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0085] In one embodiment, Figure 7 As shown, a memory access device is provided, including: an allocation module, a partitioning module, a binding module and an access module, wherein:

[0086] An allocation module, used for determining a plurality of non-uniform memory access nodes and allocating resources to the non-uniform memory access nodes;

[0087] A partitioning module is used to partition the storage objects in the storage system to obtain multiple data segments;

[0088] A binding module, used for sequentially binding a plurality of data segments with a plurality of non-uniform memory access nodes;

[0089] The access module is used to obtain the logical block address of the data access request in response to receiving the data access request, and determine the target data segment corresponding to the data access request according to the logical block address, so as to perform memory access through the target non-consistent memory access node corresponding to the target data segment.

[0090] In one embodiment, the allocation module is also used to determine the number of non-consistent memory access nodes based on the hardware configuration; create a corresponding number of thread pools and memory pools based on the number of non-consistent memory access nodes, and bind the threads in the thread pool and the memory in the memory pool to the processor cores of the corresponding non-consistent memory access nodes respectively.

[0091] In one embodiment, the partitioning module is also used to obtain storage objects in the storage system, and the storage space of the storage objects, wherein the storage space of the storage objects is addressed according to the linear space; set the space granularity, and segment the storage space of the storage objects according to the space granularity to obtain multiple data segments; linearly number the multiple data segments in sequence to obtain the segment number of each data segment.

[0092] In one embodiment, a judgment module is also included, which is used to obtain memory device information of non-consistent memory access nodes respectively, and judge whether the non-consistent memory access nodes are valid based on the memory device information; determine the available non-consistent memory access nodes according to the judgment results, and obtain the node numbers of the available non-consistent memory access nodes.

[0093] In one embodiment, the binding module is also used to sort the data segments and available non-consistent memory access nodes according to the segment numbers and node numbers, respectively, to form a data segment sequence and a node sequence; based on the data segment sequence and the node sequence, establish a mapping relationship between the segment numbers of the data segments and the node numbers of the available non-consistent memory access nodes; and according to the mapping relationship, cyclically bind multiple data segments to the available non-consistent memory access nodes in turn.

[0094] In one embodiment, the access module is also used to receive data access requests, which include data write requests and data read requests; obtain the logical block address of the data access request, and divide the logical block address of the data access request by the spatial granularity to determine the segment number of the target data segment corresponding to the data access request; determine the target non-consistent memory access node corresponding to the data access request based on the mapping relationship between the segment number and the node number; in response to the data access request being a data read request, perform memory access to the target data segment through the target non-consistent memory access node; in response to the data access request being a data write request, obtain a first data amount of the target non-consistent memory access node, and a second data amount of data to be written corresponding to the data write request, wherein the first data amount is the remaining data amount of the corresponding memory; compare the first data amount with the second data amount; in response to the first data amount being greater than or equal to the second data amount, write the data to be written into the memory corresponding to the target non-consistent memory access node.

[0095] In one embodiment, the access module is also used to obtain computing resources and memory resources from the thread pool and memory pool corresponding to the target non-consistent memory access node in response to the data access request being a data read request; and access the target data segment based on the computing resources and memory resources.

[0096] For the specific definition of the memory access device, please refer to the definition of the memory access method above, which will not be repeated here. Each module in the above-mentioned memory access device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0097] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Figure 8 As shown. The computer device includes a processor, a memory, a network interface and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store the data segments obtained after the division. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a memory access method is implemented.

[0098] Those skilled in the art will understand that Figure 8The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0099] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the following steps when executing the computer program:

[0100] determining a plurality of non-uniform memory access nodes and allocating resources to the non-uniform memory access nodes;

[0101] Divide the storage objects in the storage system to obtain multiple data segments;

[0102] Binding multiple data segments to multiple non-uniform memory access nodes in sequence;

[0103] In response to receiving a data access request, a logical block address of the data access request is obtained, and a target data segment corresponding to the data access request is determined according to the logical block address, so as to perform memory access through a target non-consistent memory access node corresponding to the target data segment.

[0104] In one embodiment, when the processor executes the computer program, the following steps are also implemented: determining the number of non-consistent memory access nodes according to the hardware configuration; creating a corresponding number of thread pools and memory pools according to the number of non-consistent memory access nodes, and binding the threads in the thread pool and the memory in the memory pool to the processor cores of the corresponding non-consistent memory access nodes respectively.

[0105] In one embodiment, when the processor executes the computer program, the following steps are also implemented: obtaining a storage object in the storage system and a storage space of the storage object, wherein the storage space of the storage object is addressed according to a linear space; setting a spatial granularity, and segmenting the storage space of the storage object according to the spatial granularity to obtain a plurality of data segments; linearly numbering the plurality of data segments in sequence to obtain a segment number of each data segment.

[0106] In one embodiment, when the processor executes the computer program, the following steps are also implemented: respectively obtaining memory device information of the non-consistent memory access nodes, and judging whether the non-consistent memory access nodes are valid based on the memory device information; determining the available non-consistent memory access nodes according to the judgment result, and obtaining the node numbers of the available non-consistent memory access nodes.

[0107] In one embodiment, when the processor executes the computer program, the following steps are also implemented: data segments and available non-consistent memory access nodes are sorted according to segment numbers and node numbers respectively to form data segment sequences and node sequences; based on the data segment sequence and the node sequence, a mapping relationship between the segment numbers of the data segments and the node numbers of the available non-consistent memory access nodes is established; and multiple data segments are sequentially and cyclically bound to the available non-consistent memory access nodes according to the mapping relationship.

[0108] In one embodiment, when the processor executes the computer program, the following steps are also implemented: receiving a data access request, the data access request includes a data write request and a data read request; obtaining a logical block address of the data access request, and dividing the logical block address of the data access request by the spatial granularity to determine the segment number of the target data segment corresponding to the data access request; determining the target non-consistent memory access node corresponding to the data access request based on the mapping relationship between the segment number and the node number; in response to the data access request being a data read request, performing memory access to the target data segment through the target non-consistent memory access node; in response to the data access request being a data write request, obtaining a first data amount of the target non-consistent memory access node, and a second data amount of the data to be written corresponding to the data write request, wherein the first data amount is the remaining data amount of the corresponding memory; comparing the first data amount with the second data amount; in response to the first data amount being greater than or equal to the second data amount, writing the data to be written into the memory corresponding to the target non-consistent memory access node.

[0109] In one embodiment, when the processor executes the computer program, the following steps are also implemented: in response to the data access request being a data read request, computing resources and memory resources are respectively obtained from the thread pool and memory pool corresponding to the target non-consistent memory access node; and the target data segment is accessed based on the computing resources and memory resources.

[0110] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0111] determining a plurality of non-uniform memory access nodes and allocating resources to the non-uniform memory access nodes;

[0112] Divide the storage objects in the storage system to obtain multiple data segments;

[0113] Binding multiple data segments to multiple non-uniform memory access nodes in sequence;

[0114] In response to receiving a data access request, a logical block address of the data access request is obtained, and a target data segment corresponding to the data access request is determined according to the logical block address, so as to perform memory access through a target non-consistent memory access node corresponding to the target data segment.

[0115] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: obtaining a storage object in a storage system and a storage space of the storage object, wherein the storage space of the storage object is addressed according to a linear space; setting a spatial granularity, and segmenting the storage space of the storage object according to the spatial granularity to obtain a plurality of data segments; linearly numbering the plurality of data segments in sequence to obtain a segment number of each data segment.

[0116] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: respectively obtaining memory device information of the non-consistent memory access nodes, and judging whether the non-consistent memory access nodes are valid based on the memory device information; determining the available non-consistent memory access nodes according to the judgment result, and obtaining the node numbers of the available non-consistent memory access nodes.

[0117] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: respectively obtaining memory device information of the non-consistent memory access nodes, and judging whether the non-consistent memory access nodes are valid based on the memory device information; determining the available non-consistent memory access nodes according to the judgment result, and obtaining the node numbers of the available non-consistent memory access nodes.

[0118] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: data segments and available non-consistent memory access nodes are sorted according to segment numbers and node numbers respectively to form data segment sequences and node sequences; based on the data segment sequence and the node sequence, a mapping relationship between the segment numbers of the data segments and the node numbers of the available non-consistent memory access nodes is established; and multiple data segments are sequentially and cyclically bound to the available non-consistent memory access nodes according to the mapping relationship.

[0119] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: receiving a data access request, the data access request includes a data write request and a data read request; obtaining a logical block address of the data access request, and dividing the logical block address of the data access request by the spatial granularity to determine the segment number of the target data segment corresponding to the data access request; determining the target non-consistent memory access node corresponding to the data access request based on the mapping relationship between the segment number and the node number; in response to the data access request being a data read request, performing memory access to the target data segment through the target non-consistent memory access node; in response to the data access request being a data write request, obtaining a first data amount of the target non-consistent memory access node, and a second data amount of the data to be written corresponding to the data write request, wherein the first data amount is the remaining data amount of the corresponding memory; comparing the first data amount with the second data amount; in response to the first data amount being greater than or equal to the second data amount, writing the data to be written into the memory corresponding to the target non-consistent memory access node.

[0120] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: in response to the data access request being a data read request, computing resources and memory resources are respectively obtained from the thread pool and memory pool corresponding to the target non-consistent memory access node; and the target data segment is accessed based on the computing resources and memory resources.

[0121] In one embodiment, a computer product is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0122] determining a plurality of non-uniform memory access nodes and allocating resources to the non-uniform memory access nodes;

[0123] Divide the storage objects in the storage system to obtain multiple data segments;

[0124] Binding multiple data segments to multiple non-uniform memory access nodes in sequence;

[0125] In response to receiving a data access request, a logical block address of the data access request is obtained, and a target data segment corresponding to the data access request is determined according to the logical block address, so as to perform memory access through a target non-consistent memory access node corresponding to the target data segment.

[0126] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: obtaining a storage object in a storage system and a storage space of the storage object, wherein the storage space of the storage object is addressed according to a linear space; setting a spatial granularity, and segmenting the storage space of the storage object according to the spatial granularity to obtain a plurality of data segments; linearly numbering the plurality of data segments in sequence to obtain a segment number of each data segment.

[0127] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: respectively obtaining memory device information of the non-consistent memory access nodes, and judging whether the non-consistent memory access nodes are valid based on the memory device information; determining the available non-consistent memory access nodes according to the judgment result, and obtaining the node numbers of the available non-consistent memory access nodes.

[0128] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: respectively obtaining memory device information of the non-consistent memory access nodes, and judging whether the non-consistent memory access nodes are valid based on the memory device information; determining the available non-consistent memory access nodes according to the judgment result, and obtaining the node numbers of the available non-consistent memory access nodes.

[0129] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: data segments and available non-consistent memory access nodes are sorted according to segment numbers and node numbers respectively to form data segment sequences and node sequences; based on the data segment sequence and the node sequence, a mapping relationship between the segment numbers of the data segments and the node numbers of the available non-consistent memory access nodes is established; and multiple data segments are sequentially and cyclically bound to the available non-consistent memory access nodes according to the mapping relationship.

[0130] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: receiving a data access request, the data access request includes a data write request and a data read request; obtaining a logical block address of the data access request, and dividing the logical block address of the data access request by the spatial granularity to determine the segment number of the target data segment corresponding to the data access request; determining the target non-consistent memory access node corresponding to the data access request based on the mapping relationship between the segment number and the node number; in response to the data access request being a data read request, performing memory access to the target data segment through the target non-consistent memory access node; in response to the data access request being a data write request, obtaining a first data amount of the target non-consistent memory access node, and a second data amount of the data to be written corresponding to the data write request, wherein the first data amount is the remaining data amount of the corresponding memory; comparing the first data amount with the second data amount; in response to the first data amount being greater than or equal to the second data amount, writing the data to be written into the memory corresponding to the target non-consistent memory access node.

[0131] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: in response to the data access request being a data read request, computing resources and memory resources are respectively obtained from the thread pool and memory pool corresponding to the target non-consistent memory access node; and the target data segment is accessed based on the computing resources and memory resources.

[0132] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0133] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0134] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A memory access method, characterized in that: include: Determine a plurality of non-uniform memory access nodes, and allocate resources to the non-uniform memory access nodes; Divide the storage objects in the storage system to obtain multiple data segments; Binding the plurality of data segments to the plurality of non-uniform memory access nodes in sequence; In response to receiving a data access request, a logical block address of the data access request is obtained, and a target data segment corresponding to the data access request is determined according to the logical block address, so as to perform memory access through a target non-consistent memory access node corresponding to the target data segment.

2. The memory access method according to claim 1, characterized in that: The determining of a plurality of non-uniform memory access nodes and respectively allocating resources to the non-uniform memory access nodes comprises: Determine the number of the non-uniform memory access nodes according to the hardware configuration; A corresponding number of thread pools and memory pools are created according to the number of the non-consistent memory access nodes, and the threads in the thread pool and the memory in the memory pool are respectively bound to the processor cores of the corresponding non-consistent memory access nodes.

3. The memory access method according to claim 1, characterized in that: The storage object in the storage system is divided to obtain multiple data segments, including: Acquire a storage object in the storage system and a storage space of the storage object, wherein the storage space of the storage object is addressed according to a linear space; Setting a space granularity, and segmenting the storage space of the storage object according to the space granularity to obtain a plurality of data segments; The multiple data segments are linearly numbered in sequence to obtain a segment number of each data segment.

4. The memory access method according to claim 3, characterized in that: Before sequentially binding the multiple data segments to the multiple non-uniform memory access nodes, the method further includes: Respectively obtain memory device information of the non-uniform memory access node, and determine whether the non-uniform memory access node is valid based on the memory device information; An available non-uniform memory access node is determined according to the determination result, and a node number of the available non-uniform memory access node is obtained.

5. The memory access method according to claim 4, characterized in that: The step of sequentially binding the plurality of data segments to the plurality of non-uniform memory access nodes comprises: sorting the data segments and the available non-uniform memory access nodes according to the segment numbers and the node numbers respectively to form a data segment sequence and a node sequence; Based on the data segment sequence and the node sequence, establishing a mapping relationship between the segment numbers of the data segments and the node numbers of the available non-uniform memory access nodes; The multiple data segments are sequentially and cyclically bound to the available non-uniform memory access nodes according to the mapping relationship.

6. The memory access method according to claim 4, characterized in that: The step of obtaining a logical block address of the data access request in response to receiving the data access request, and determining a target data segment corresponding to the data access request according to the logical block address, so as to perform memory access through a target non-consistent memory access node corresponding to the target data segment, includes: Receiving a data access request, wherein the data access request includes a data write request and a data read request; Acquire a logical block address of the data access request, and divide the logical block address of the data access request by the spatial granularity to determine a segment number of a target data segment corresponding to the data access request; Determine a target inconsistency memory access node corresponding to the data access request according to a mapping relationship between the segment number and the node number; In response to the data access request being a data read request, performing memory access on the target data segment through the target non-uniform memory access node; In response to the data access request being a data write request, obtaining a first data amount of the target non-consistent memory access node and a second data amount of the data to be written corresponding to the data write request, wherein the first data amount is a remaining data amount of the corresponding memory; comparing the first amount of data with the second amount of data; In response to the first data amount being greater than or equal to the second data amount, the data to be written is written into a memory corresponding to the target non-uniform memory access node.

7. The memory access method according to claim 1 or 6, characterized in that: The performing memory access through the target non-consistent memory access node corresponding to the target data segment includes: In response to the data access request being a data read request, respectively acquiring computing resources and memory resources from a thread pool and a memory pool corresponding to the target non-consistent memory access node; The target data segment is accessed based on the computing resources and the memory resources.

8. A memory access device, characterized in that: The device comprises: An allocation module, configured to determine a plurality of non-uniform memory access nodes and allocate resources to the non-uniform memory access nodes; A partitioning module is used to partition the storage objects in the storage system to obtain multiple data segments; A binding module, used for sequentially binding the multiple data segments with the multiple non-uniform memory access nodes; An access module is used to obtain a logical block address of the data access request in response to receiving the data access request, and determine a target data segment corresponding to the data access request according to the logical block address, so as to perform memory access through a target non-consistent memory access node corresponding to the target data segment.

9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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