Data prefetching method, electronic device, apparatus, medium, and product

Abstract

The present disclosure provides a data prefetching method, an electronic device, an apparatus, a medium and a product, comprising: receiving a demand address for a cache by a plurality of entries of a prefetcher, and training based on the demand address to identify streaming data rules and generate a streaming data prefetch request; determining whether there are N entries of the plurality of entries that will generate repeated prefetch addresses based on hit information of the plurality of entries by a multi-hit detector of the prefetcher; determining M selected entries from the N entries based on information of the N entries by the multi-hit detector; generating a null instruction for unselected entries other than the M entries in the N entries by the multi-hit detector, so as to prohibit the unselected entries from generating the streaming data prefetch request, a part of the entries that will generate repeated prefetch addresses can be detected and prohibited, and repeated streaming data prefetch requests are avoided, thereby avoiding power consumption and waste of entry bandwidth caused by repeated prefetching.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a data prefetching method, an electronic device, an apparatus, a medium and a product. BACKGROUND

[0002] Modern multi-issue high-performance CPUs (Central Processing Units) include at least one processor core (CPU Core, or processor core), and each CPU core can include multiple execution units to execute instructions. In existing CPU architectures, program instructions and data are generally stored in DRAM (Dynamic Random Access Memory). The CPU core running frequency is much higher than the DRAM memory running frequency, so it takes hundreds of CPU core clock cycles to obtain data and instructions from the memory, which will inevitably cause the CPU core to idle due to waiting for related instructions and data, resulting in performance degradation. To address this, modern high-performance CPUs use a multi-level cache architecture to store recently accessed data, and use a prefetcher to discover the data access patterns of the CPU to prefetch data and instructions that will be accessed into the cache in advance. How to use the prefetcher to perform efficient and accurate data prefetching is particularly important for providing high-performance processors. SUMMARY

[0003] Embodiments of the present disclosure provide a data prefetching method, an electronic device, an apparatus, a medium and a product, which can detect and disable a part of entries that will generate duplicate prefetch addresses, thereby avoiding waste of power consumption and bandwidth by duplicate prefetch requests and improving prefetch performance and overall operation performance of the device.

[0004] According to an aspect of the present disclosure, a data prefetching method is provided. The method according to the present disclosure is applicable to an electronic device including a prefetcher and a cache, wherein the prefetcher includes a plurality of entries and a multi-hit detector, and the method includes: receiving, by the plurality of entries, demand addresses for the cache, and training based on the demand addresses to identify streaming data patterns and generate streaming data prefetch requests, wherein each entry of the plurality of entries independently trains and generates the streaming data prefetch requests; determining, by the multi-hit detector based on hit information of the plurality of entries, whether there are N entries in the plurality of entries that will generate duplicate prefetch addresses, wherein N is an integer greater than 1; in a case where it is determined that there are N entries, determining, by the multi-hit detector based on information of the N entries, M selected entries from the N entries, wherein M is an integer greater than or equal to 1 and less than N; and generating, by the multi-hit detector, a disable instruction for unselected entries in the N entries other than the M entries, so as to disable the unselected entries from generating the streaming data prefetch requests.

[0005] According to some embodiments of the present disclosure, the multi-way hit detector is implemented as a pipeline, is independent of the multiple entries, and performs multi-way hit detection in parallel with the training and prefetching processes of the multiple entries.

[0006] According to some embodiments of the present disclosure, the demand address is a virtual address corresponding to a load instruction or a store instruction.

[0007] According to some embodiments of the present disclosure, using a multi-way hit detector based on hit information of multiple entries to determine whether there are N entries in the multiple entries that will generate duplicate prefetch addresses includes: when the required address simultaneously hits N entries in the same direction of streaming data and is in prefetch mode, or in training mode, determining that there are N entries that will generate duplicate prefetch addresses; or when the required address simultaneously hits N entries in the same direction of streaming data and is in prefetch mode, or is in prefetch mode, determining that there are N entries that will generate duplicate prefetch addresses.

[0008] According to some embodiments of the present disclosure, M is equal to 1, and using the multi-way hit detector to determine M selected entries from N entries based on information of the N entries includes: determining the entry with the highest confidence parameter from the N entries as the selected entry based on the information of the N entries.

[0009] According to some embodiments of the present disclosure, M is equal to 1, and using the multi-way hit detector to determine M selected entries from N entries based on information of the N entries includes: determining the entry allocated earliest in time from the N entries as the selected entry based on the information of the N entries.

[0010] According to some embodiments of the present disclosure, M is equal to 1, and using a multi-way hit detector to determine M selected entries from N entries based on information of the N entries includes: determining the entry with the smallest or largest entry number from the N entries as the selected entry based on the information of the N entries.

[0011] According to some embodiments of the present disclosure, the prefetcher further includes a prefetch request generator. The data prefetching method according to an embodiment of the present disclosure further includes: generating a streaming data prefetch request based on the M selected entries using the prefetch request generator, the streaming data prefetch request being used to perform a streaming data prefetch process based on the cache.

[0012] According to some embodiments of the present disclosure, a streaming data prefetch request is used to perform a streaming data prefetch process based on a first-level cache, a second-level cache, and a last-level cache of a cache.

[0013] According to another aspect of the present disclosure, an electronic device is provided. The electronic device includes a prefetcher and a cache, the prefetcher is configured to include a plurality of entries and a multi-hit detector, the plurality of entries is configured to: receive a demand address for the cache, and train based on the demand address to identify a streaming data pattern and generate a streaming data prefetch request, wherein each entry of the plurality of entries independently trains and generates the streaming data prefetch request; and the multi-hit detector is configured to: determine whether there are N entries of the plurality of entries that will generate a duplicate prefetch address based on hit information of the plurality of entries, wherein N is an integer greater than 1; in a case where it is determined that there are the N entries, determine M selected entries from the N entries based on information of the N entries, wherein M is an integer greater than or equal to 1 and less than N; and generate an abort instruction for unselected entries of the N entries other than the M selected entries to disable the unselected entries from generating the streaming data prefetch request.

[0014] According to some embodiments of the present disclosure, the multi-hit detector is implemented as a pipeline, is independent of the plurality of entries, and performs the multi-hit detection in parallel with the training and prefetching processes of the plurality of entries.

[0015] According to some embodiments of the present disclosure, the demand address is a virtual address corresponding to a load instruction or a store instruction.

[0016] According to some embodiments of the present disclosure, the multi-hit detector determines whether there are N entries of the plurality of entries that will generate a duplicate prefetch address based on hit information of the plurality of entries includes: in a case where the demand address simultaneously hits N entries of the streaming data in the same direction and in a prefetch mode, or in a training mode, it is determined that there are the N entries that will generate the duplicate prefetch address; or in a case where the demand address simultaneously hits N entries of the streaming data in the same direction and in a prefetch mode, or in a prefetch mode, it is determined that there are the N entries that will generate the duplicate prefetch address.

[0017] According to some embodiments of the present disclosure, M is equal to 1, and the multi-hit detector determines M selected entries from the N entries based on information of the N entries includes one of: determining an entry with the highest confidence parameter as the selected entry from the N entries based on the information of the N entries; determining an entry that is allocated earliest in time as the selected entry from the N entries based on the information of the N entries; or determining an entry with the smallest or largest entry number as the selected entry from the N entries based on the information of the N entries.

[0018] According to some embodiments of the present disclosure, the prefetcher further includes a prefetch request generator configured to: generate a streaming data prefetch request based on the M selected entries, the streaming data prefetch request being used for a streaming data prefetching process based on the cache.

[0019] According to some embodiments of the present disclosure, the streaming data prefetch request is used for a streaming data prefetch process based on a cache level one cache, a cache level two cache, and a cache level last cache.

[0020] According to some embodiments of the present disclosure, the electronic device further includes a read-write unit, wherein the prefetcher is located in the read-write unit of the electronic device, the read-write unit further includes a read-write queue and an arbitrator, wherein the read-write queue is configured to generate a demand access based on information of a read-write operation; the arbitrator is configured to generate a data access request based on the demand access of the read-write queue and the streaming data prefetch request generated by the prefetcher, the data access request corresponds to a demand address, wherein the prefetcher performs training and prefetching based on the demand address.

[0021] According to another aspect of the present disclosure, an electronic device is provided. The electronic device includes a processor and a memory having computer readable code stored therein, which when executed by the processor, causes the processor to perform the steps of the data prefetch method according to embodiments of the present disclosure.

[0022] According to another aspect of the present disclosure, a non-transitory computer readable storage medium is provided, having computer readable instructions stored thereon, which when executed by a processor, causes the processor to perform the steps of the data prefetch method according to embodiments of the present disclosure.

[0023] According to another aspect of the present disclosure, a computer program product is also provided, including a computer program. The computer program, when executed by a processor, causes the processor to perform the steps of the data prefetch method according to embodiments of the present disclosure.

[0024] The data prefetch method, electronic device, apparatus, medium and product provided according to embodiments of the present disclosure utilize multiple entries of the prefetcher to independently perform training and generate streaming data prefetch requests, thereby reducing the requirement for pipeline depth of the entries, on the basis of ensuring fast training of the multiple entries, the hardware implementation area of the multiple entries of the prefetcher can also be controlled. Further, the multiple entries are repeatedly detected in parallel by the multiple-way hit detector of the prefetcher, that is, based on the hit information of the multiple entries, it is determined whether there are entries of the multiple entries that will generate repeated prefetch addresses, and a part of the entries that will generate repeated prefetch addresses are prohibited, so that subsequent prefetch processes no longer repeatedly hit the multiple entries, and the multiple entries will not issue prefetch requests of repeated addresses, thereby avoiding the waste of power consumption and entry bandwidth caused by repeated prefetching, and further improving the prefetching performance of the prefetcher and the overall operation performance of the electronic device. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure and not limit the present disclosure.

[0026] Figure 1 A schematic block diagram of a read-write unit in a processor and its hardware prefetch module is shown;

[0027] Figure 2 A schematic block diagram of a stream data prefetcher is shown;

[0028] Figure 3 A schematic diagram of a stream prefetch entry load is shown;

[0029] Figure 4A A schematic flow diagram of a training process of a stream data prefetcher is shown;

[0030] Figure 4B A schematic flow diagram of a prefetch process of a stream data prefetcher is shown;

[0031] Figure 5 A schematic flow diagram of a data prefetching method according to an embodiment of the present disclosure is shown;

[0032] Figure 6 A flow diagram of a multi-way hit detector according to an embodiment of the present disclosure is shown;

[0033] Figure 7A An example prefetch process diagram in the related art is shown;

[0034] Figure 7B An example prefetch process diagram according to an embodiment of the present disclosure is shown;

[0035] Figure 8A A schematic block diagram of an electronic device according to an embodiment of the present disclosure is shown;

[0036] Figure 8B An example structure diagram of an electronic device according to an embodiment of the present disclosure is shown;

[0037] Figure 9 A schematic block diagram of an electronic device according to an embodiment of the present disclosure is shown;

[0038] Figure 10 An architectural schematic diagram of an example electronic device according to an embodiment of the present disclosure is shown;

[0039] Figure 11 A schematic block diagram of a storage medium according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0040] With reference to the drawings and the embodiments of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, but not all the embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of the present disclosure.

[0041] In addition, as shown in the present disclosure and claims, unless the context clearly indicates otherwise, "one", "a", "an", and / or "the" do not specify a single number, but can also include a plurality. The "first", "second", and similar words used in the present disclosure do not represent any order, quantity, or importance, but are only used to distinguish different components. Similarly, "include" or "contain" and similar words mean that the elements or objects before the word cover the elements or objects listed after the word and their equivalents, and do not exclude other elements or objects. "Connected" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0042] Flowcharts are used in the present disclosure to illustrate the steps of the method according to the embodiments of the present disclosure. It should be understood that the preceding or subsequent steps do not necessarily proceed in sequence. On the contrary, various steps can be processed in reverse order or simultaneously. At the same time, other operations can also be added to these processes.

[0043] First, the terms that may be involved in at least some embodiments of the present disclosure are explained as follows.

[0044] An electronic device generally includes one or more processor cores (CPU Core) and a cache, which can be implemented as a multi-level cache architecture, in which the access speed of the first level (L1) cache memory is the fastest, but the capacity is the smallest, and it is usually set inside the processor core; the last level (LLC, generally the third level) cache memory has the largest capacity and the slowest access speed, and it is usually shared by multiple processor cores; the access speed and capacity of the second level (L2) cache memory are between the L1 cache memory and the LLC cache memory, and it can also be usually set inside the processor core.

[0045] Data Prefetch: In CPU architecture, program instructions and data can be saved in Dynamic Random Access Memory (DRAM). The running frequency of the processor core is much higher than that of the DRAM memory. Therefore, it takes hundreds of processor core clock cycles to obtain data and instructions from the memory, causing the processor core to idle due to waiting for related instructions and data, resulting in performance loss. Therefore, modern high-performance electronic devices all contain multi-level cache architectures to save recently accessed data, and use prefetchers to discover the data access patterns of the CPU to pre-fetch the data and instructions to be accessed into the cache in advance.

[0046] Prefetcher: The prefetcher can be divided into a first-level data prefetcher (i.e., a data prefetcher that prefetches target data into a first-level cache memory (L1 Cache)), a second-level data prefetcher (i.e., a data prefetcher that prefetches target data into a second-level cache memory (L2 Cache)), a last-level data prefetcher (i.e., a data prefetcher that prefetches target data into a last-level cache memory (LLC Cache)), and the like.

[0047] It can be understood that if the prefetcher generates too many inaccurate prefetch requests, it will cause problems such as increased memory access delay and increased cache pollution, which will have a greater negative impact on the performance of the CPU, ultimately leading to a decline in running performance. This problem is more obvious for CPUs that support SMT (Simultaneous Multithreading, also known as concurrent multithreading).

[0048] Prefetch Metrics: Prefetch metrics are standards for evaluating the performance of prefetchers. They can include accuracy, coverage, and lateness. Accuracy is the ratio of the number of correct prefetches to the total number of prefetches. Coverage is the ratio of the number of demand requests (requests generated by memory access instructions in a program) that hit the prefetch data to the total number of demand requests. Lateness is the ratio of the number of correct prefetches that are issued too late to the total number of prefetches. Accuracy and coverage are often difficult to balance at the same time.

[0049] Load-Store Unit (LSU): The load-store unit, also known as the loading and storing unit, is an execution unit in the CPU core that is responsible for processing storage and loading instructions. It usually includes an L1 cache.

[0050] Load-Store Quene (LSQ): It is a queue in LSU to save the information required by Load-Store Operation.

[0051] Cache Line (CL): The minimum granularity of data storage in data cache.

[0052] Miss Status Handling Register (MSHR): It is used to record each uncompleted Cache Miss event, and the information recorded usually includes address, thread identification, etc. The occupancy rate of MSHR can represent the usage rate of memory. If the occupancy rate of MSHR is high, it can reflect that the Cache Miss events of prefetcher are more, i.e. the accuracy of prefetching is decreased, and the usage rate of memory is at a relatively high level.

[0053] Translation Lookaside Buffer (TLB): It can also be called page table cache, address bypass cache, etc. It is a kind of cache of CPU, which is used by memory management unit to improve the speed of virtual address to physical address translation. TLB has a fixed number of space slots, which is used to store the tag page table entry of virtual address mapping to physical address. Its search key is virtual memory address, and its search result is physical address. If the requested virtual address exists in TLB, the Content-Addressable Memory (CAM) will give a very fast matching result, and then the obtained physical address can be used to access the memory. If the requested virtual address does not exist in TLB, the tag page table will be used for virtual-to-physical address translation, and the access speed of tag page table is much slower than that of TLB.

[0054] In the related art, in order to improve the running efficiency of the CPU, a hardware prefetch module (HardWare Prefetcher, HWPF) is usually implemented inside the LSU, which moves the data required by the program stream being executed by the thread into the data cache in advance, so as to improve the speed of data access. In order to achieve this purpose, the hardware prefetch module HWPF needs to predict the addresses that may be accessed in the future according to the address sequence of the current data access. For the HWPF, a common address sequence mode is called "streaming data", that is, the data is read and written to the memory in turn according to the CL granularity, and the virtual address is incremented or decremented. After the streaming data prefetch module identifies such an access sequence in the "training" stage, it enters the "prefetch" state, and according to the sequence increment or decrement direction, it issues the next prefetch request downstream in advance, so as to prefetch the streaming data that may be accessed into the cache in advance.

[0055] In order to identify streaming data with different starting addresses, multiple entries are usually set in the HWPF, and each entry can be trained respectively. The pipeline depth of the training directly affects the hardware area of the prefetch module. In the actual program execution process, for various reasons, such as the memory access order of the program stream itself changing back and forth, modern high-performance processors executing instructions in an out-of-order manner, and the like, the same streaming data may be identified as multiple streaming data and allocated to multiple entries. Therefore, multiple entries will repeat "training" and "prefetching", which will cause waste of power consumption and subsequent storage resources and pipeline bandwidth.

[0056] In view of the technical problems of repeated "training" and "prefetching" existing in the above hardware prefetch module HWPF for streaming data prefetching, the present disclosure provides a data prefetching method for detecting and disabling a part of entries that will generate repeated prefetch addresses, so as to avoid the waste of power consumption and bandwidth of repeated prefetch requests, and improve the prefetch performance and the overall running performance of the device.

[0057] Specifically, using the data prefetching method provided by the embodiment of the present disclosure, for a prefetcher (e.g., HWPF), multiple entries are trained independently and streaming data prefetch requests are generated, thereby reducing the requirements for the pipeline depth of the entries. On the basis of ensuring the rapid training of multiple entries, the hardware implementation area of ​​the multiple entries of the prefetcher can also be controlled. Furthermore, the multi-way hit detector of the prefetcher performs repeated detection on multiple entries in parallel, that is, based on the hit information of multiple entries, it determines whether there are entries in the multiple entries that will generate repeated prefetch addresses, and prohibits some entries that will generate repeated prefetch addresses, ensuring that the subsequent prefetch process no longer repeatedly hits multiple entries. Therefore, multiple entries will not issue prefetch requests for repeated addresses, thereby avoiding the waste of power consumption and entry bandwidth caused by repeated prefetching, thereby improving the prefetch performance (Prefetch Metrics) of the prefetcher and improving the overall operating performance of the electronic device.

[0058] To facilitate understanding of the disclosed solution, before describing in detail the implementation process of the data prefetching method provided by the present disclosure, the implementation process of the hardware prefetch module HWPF in the LSU and the functions involved will be briefly described below with reference to the accompanying drawings. It will be understood that when any component herein appears in more than one drawing, the component is represented by the same or similar reference numeral in each drawing.

[0059] As an example, Figure 1 The following figure shows a schematic block diagram of the load-store unit (LSU) and its hardware prefetch module HWPF in the processor. Figure 1 First, the front end sends information such as load and store operations and addresses (shown as ld / st op) to the LSU, and generates demand access (Demand Access) through the read and write queue (LSQ). After that, these operations enter the data access pipeline (Data access pipe) through the arbiter and start execution.

[0060] Load / Store operations (ld / st op) are address-converted by accessing the TLB, and are compared by accessing the tag array (Tag) to determine whether they hit the L1 cache. For Load operations, if the L1 cache is hit, the corresponding data is read from the data cache and returned; if the L1 cache is not hit, a read request needs to be sent to the downstream L2 cache, and the request is saved in the MSHR; when the data returned by the downstream is backfilled into the L1 cache, the original Load operation is woken up to re-enter the pipeline, and the corresponding data is returned. For Store operations, if the L1 cache is hit and has an exclusive state, the corresponding data is written into the data cache; otherwise, a read request to obtain a writable state needs to be sent to the downstream L2 cache, and the request is saved in the MSHR; when the data returned by the downstream is backfilled into the L1 cache, the original Store operation is woken up to re-enter the pipeline, and the corresponding data is written, for example, in Figure 1

[0061] It can be understood that a hit cache can greatly speed up the completion of Load / Store operations. Therefore, the LSU module can also be configured with a hardware prefetch module HWPF. The HWPF takes the ld / st op information on the pipeline as input, attempts to identify regular memory access address sequences therein. Specifically, as a form of prefetcher, the streaming data prefetcher is responsible for identifying streaming sequences in memory access. When the streaming data prefetcher identifies a streaming sequence through "training", the prefetcher enters the "prefetch" state, and then starts sending prefetch requests. It is assumed that the addresses in the prefetch request are virtual addresses, and the prefetch request, similar to the Load / Store request, also needs to pass through the arbitrator before entering the pipeline, access the TLB for address conversion, and access the tag array (Tag) to determine whether it hits the L1 cache. If the L1 cache is hit, no prefetch is needed. If the L1 cache is not hit, a corresponding request needs to be sent to the downstream L2 cache, and the request is saved in the MSHR; when the data returned by the downstream is backfilled into the L1 cache, the prefetch request is completed.

[0062] As described above, in actual program execution, for various reasons such as the memory access order of the program stream itself jumping back and forth, modern high-performance processors executing instructions in an out-of-order manner, etc., the same streaming data may be identified as multiple streaming data and stored in multiple entries, and thus multiple entries will repeatedly "train" and "prefetch". When the same address prefetch request enters the pipeline, it will cause waste of resources and waste of pipeline bandwidth.

[0063] Next, Figure 2 ​A schematic block diagram of a stream data prefetcher is shown. Next, a general module diagram of the stream data prefetcher is introduced as follows. Figure 2 As shown, the stream data prefetcher can be configured with multiple entries to train multiple streams simultaneously, here with 32 entries as an example (stream entry 0 to stream entry 31). After the memory address (ld / stop) is sent to the input end of the entries, the memory address is sent to the 32 entries simultaneously for matching, and each entry is independent of each other and can simultaneously train and send a prefetch request. Specifically, the stream data prefetcher first works in a "training" stage, and after identifying such a stream access sequence, it will enter a "prefetch" state to send a next prefetch request in advance to the downstream according to the sequence increment or decrement direction, so as to prefetch the stream data that can be accessed in advance to the cache. The prefetch request of each stream entry also needs to pass through a selector (Stream Prefetch Picker) to reach a stream prefetch generation (Stream Prefetch Generation), and finally a stream data prefetch request (Prefetch Request) is sent.

[0064] In addition, each entry of the stream data prefetcher needs to store some information to record the training and prefetch information of the stream data prefetch in order to realize the above training and prefetch process. Illustratively, Figure 3 A schematic diagram of the stream prefetch entry load is shown.

[0065] Figure 3 The meanings of the parameters shown in the above table are as follows:

[0066] Valid: entry valid bit, set to 1 when the entry is allocated;

[0067] Dir: direction bit (Direction), used to identify the increment / decrement direction of the stream data, and this variable is established when the stream mode sequence training is completed;

[0068] Conf: confidence (Confidence), the value range of which can be from 0 to a set maximum value (for example, 3), and when the training is completed, Conf is set from 0 to 1. The greater the confidence, the more times the sequence is hit, so the sequence prefetch accuracy is expected to be higher, and therefore the offset of the prefetch address can also be relatively set to be larger;

[0069] BaseAddr: base address (Base Address), used to identify the starting address of the stream mode sequence, which is updated when the training is completed and the entry is refreshed;

[0070] AccVec: Access Vector, a bit vector, used to track whether a block has been accessed by demand, here in CL granularity, e.g. 64 bits (64B);

[0071] DmdPtr: Demand Pointer, used to track the relative position of the access address and BaseAddr, if the new access address falls behind the current DmdPtr, it will not be changed;

[0072] PfPtr: Prefetch Pointer, based on the above parameters, the next L1 prefetch request address can be represented as (BaseAddr + (L1PfPtr+1) * 64B).

[0073] As a specific implementation example, the present disclosure also provides Figure 4A and Figure 4B wherein Figure 4A shows a schematic flow chart of the training process of the streaming data prefetcher, Figure 4B shows a schematic flow chart of the prefetching process of the streaming data prefetcher. Next, the training process and the prefetching process of the streaming data prefetcher are described.

[0074] As Figure 4A shown, when the demand address enters the streaming data prefetcher (S401), it is compared with the BaseAddr in each entry first to determine whether the entry is hit (S402). If the comparison result of the demand address and the BaseAddr is within a certain range (the range of the training mode and the prefetching mode may be different), it is considered that the entry is hit. Otherwise, if the demand address does not hit the entry, for example, when a certain condition is met (such as being allocated with MSHR), a new entry is allocated for it (S403), and the state of the newly allocated entry is initialized, for example, the valid bit Valid of the newly allocated entry is set to 1, the BaseAddr is set to the demand address, and the Conf is set to 0. At this time, the newly allocated entry enters the training mode.

[0075] Next, in S404, it is determined whether the current entry is in the training state. If it is determined that it is in the training state, the relevant state information can be updated according to the address (S405), for example, according to whether the demand address is within a certain range, for example, [BaseAddr-n, BaseAddr+n] (as an example, assuming n=2), the corresponding access information is recorded by the access vector AccVec. Here, AccVec can be reused, or another hardware resource can be used to record a bit vector.

[0076] Then, in S406, it is determined whether the training of the current entry is completed, when BaseAddr-1, BaseAddr-2 or BaseAddr+1, BaseAddr+2 are all visited, that is, 3 addresses are found to be consecutively accessed in the increment / decrement order, the training of the current entry is considered to be completed, the entry state is updated and the entry enters the prefetch mode (S407). The updating of the entry state here can include: setting the confidence Conf to 1, updating Dir to the corresponding value according to the address increment / decrement rule (for example, 0 represents increment and 1 represents decrement), updating BaseAddr to BaseAddr+ / -2, setting DmdPtr to 0 and setting PfPtr to 0, so that the entry enters the prefetch mode, at this time, the prefetch request can be sent from PfPtr=0, and the request address is BaseAddr+ / -1. If the training of the current entry is not completed, S408 is performed, that is, the training state is updated according to the address.

[0077] For S404, when the current entry is not in the training state, S409 is performed to determine whether the demand address exceeds the range (for example, [BaseAddr-n, BaseAddr+n]), if it exceeds the range, the entry is refreshed and the prefetch state is updated according to the address (S410), if it does not exceed the range, the related state is updated according to the address (S411), and the updating here can be for example, refer to S407.

[0078] Reference Figure 4B Fig. 4 shows a schematic flowchart of the prefetch process of the stream data prefetcher.

[0079] Firstly, in S412, the entry enters the prefetch mode, then in S413, it can be determined whether the parameter PfPtr reaches the current maximum value, if yes, the entry is refreshed or DmdPtr is updated (S414), if no, subsequent S415-S417 are performed, that is, the prefetch request is generated, arbitration is waited and PfPtr is updated.

[0080] When the prefetch request is sent, PfPtr is increased, if the new PfPtr is still within the range, the next prefetch request is continuously sent. The farthest distance of the prefetch request is determined by DmdPtr and Conf: PfPtr

[0081] After an entry enters prefetch mode, the bit vector AccVec can be used to record the state of addresses in the stream sequence being demanded by address requests within a certain observation window; the observation window depth Depth can be implemented differently according to specific designs, and can be a fixed value, can change based on the value of Conf, or can be dynamically adjusted according to the processing of the current memory request during operation. When a prefetch request is generated, if the address corresponding to PfPtr corresponds to an AccVec bit of 1, it means that the address has been accessed, and at this time PfPtr can skip this address and directly prefetch the next one to generate a prefetch request. The search depth of AccVec when generating a prefetch request can vary according to specific implementations, or can remain completely unchanged.

[0082] After an entry enters prefetch mode, DmdPtr records the current farthest demanded address relative to BaseAddr. When DmdPtr exceeds the observation window depth Depth, the entry needs to be refreshed. At this time, the number of bits 1 recorded in the counter AccVec is counted. If the count exceeds a certain threshold, Conf = Conf + 1; if the count is less than a certain threshold, Conf = Conf - 1; otherwise, Conf remains unchanged. If the entry is still in prefetch mode after refreshing, update the other parameters in the entry:

[0083] BaseAddr = BaseAddr + / - Depth

[0084] DmdPtr = DmdPtr - Depth

[0085] PfPtr = PfPtr - Depth

[0086] AccVec = AccVec << Depth

[0087] The various thresholds described above can be implemented differently according to specific designs, and can be a fixed value, can change in size based on the value of Conf, or can be dynamically adjusted according to the processing of the current memory request during operation. When Conf decreases to 0, the entry will fall back to the training mode, and re-enter the prefetch mode after meeting certain conditions through the training process described earlier. When the entry Conf > 0, the entry enters the "prefetch" mode and starts to generate prefetch requests. When multiple entries enter the "prefetch" mode to generate prefetch requests at the same time, a selector is used to select one entry first, and then the corresponding prefetch request is generated according to the information in the entry. When the prefetch request is sent, the PfPtr of the selected entry is updated. The term "sent" refers to the successful reception of the request by the next module, which in this implementation can be a prefetch request queue, or can have other implementation methods.

[0088] As can be seen, each stream mode prefetch entry has an independent training and prefetch process. When a demand address enters the stream data prefetcher, it is sent to each entry at the same time, and training is performed at the same time. In some software scenarios or due to out-of-order emission and execution of the processor, the same stream data can be trained by multiple stream entries at the same time. For multiple entries, the repeated "training" and "prefetch" situation will cause waste of power consumption and subsequent storage resources and pipeline bandwidth when the prefetch request with the same address is pipelined.

[0089] The present disclosure provides a data prefetch method, which can detect and disable a part of entries that will generate repeated prefetch addresses, thereby avoiding the waste of power consumption and bandwidth caused by repeated prefetch requests and improving the prefetch performance and overall operation performance of the device.

[0090] Specifically, by using the data prefetch method provided by the embodiments of the present disclosure, for a prefetcher (for example, HWPF), multiple entries independently perform training and generate stream data prefetch requests, thereby reducing the requirement for the pipeline depth of the entries, and on the basis of ensuring fast training of the multiple entries, the hardware implementation area of the multiple entries of the prefetcher can also be controlled. Further, the multiple-way hit detector of the prefetcher performs repeated detection on the multiple entries in parallel, that is, based on the hit information of the multiple entries, it is determined whether there is an entry that will generate repeated prefetch addresses in the multiple entries, and a part of the entries that will generate repeated prefetch addresses is disabled, so that the subsequent prefetch process no longer repeatedly hits the multiple entries. The multiple entries will not therefore issue repeated address prefetch requests, thereby avoiding the waste of power consumption and entry bandwidth caused by repeated prefetch, and further improving the prefetch performance of the prefetcher and the overall operation performance of the electronic device.

[0091] The data prefetch method of the present disclosure will be described below with reference to the accompanying drawings. In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed description of known functions and known components can be omitted.

[0092] The data prefetch method according to the embodiments of the present disclosure is applicable to an electronic device, which can include a prefetcher and a cache. The prefetcher here can refer to the stream data prefetcher described above in combination with the drawings, which includes multiple entries for stream data prefetch. Further, the prefetcher according to the present disclosure can also be configured with a multiple-way hit detector. As an implementation manner, the multiple-way hit detector can be implemented in the form of a pipeline on hardware, and performs a repeated sequence judgment process in parallel with the entries of the prefetcher to identify the multiple-way hit situation of more than one entry.

[0093] Figure 5 A schematic flowchart of a data prefetch method according to some embodiments of the present disclosure is shown, which includes steps S501-S504.

[0094] Step S501: receiving demand addresses for the cache using a plurality of entries, and training based on the demand addresses to identify streaming data regularity and generate streaming data prefetch requests, wherein each entry of the plurality of entries independently trains and generates the streaming data prefetch requests.

[0095] According to some embodiments of the present disclosure, the demand address is a virtual address corresponding to a load instruction or a store instruction. Specifically, this step S501 can be combined with the description of Figure 2 For example, entries 0 to 31 all receive the ld / st op information, and train in parallel to identify streaming data regularity and generate possible prefetch requests.

[0096] Step S502: determining, using a multi-hit detector, whether there are N entries in the plurality of entries that will generate duplicate prefetch addresses based on hit information of the plurality of entries, wherein N is an integer greater than 1.

[0097] In the scheme according to the present disclosure, a multi-hit detector is added in the streaming data prefetcher to specifically remove duplicate hit entries of the streaming data prefetcher, and the detection and processing of multi-hits are independent of the training and prefetching process of each streaming entry, and do not affect the training and prefetching pipeline of each entry.

[0098] According to some embodiments of the present disclosure, determining, using the multi-hit detector, whether there are N entries in the plurality of entries that will generate duplicate prefetch addresses based on hit information of the plurality of entries includes: in a case where the demand addresses simultaneously hit N entries of the streaming data in the same direction (Dir) and in a prefetch mode, or in a training mode, determining that there are N entries that will generate duplicate prefetch addresses; or in a case where the demand addresses simultaneously hit N entries of the streaming data in the same direction and in a prefetch mode, or in a prefetch mode, determining that there are N entries that will generate duplicate prefetch addresses.

[0099] It can be understood that the judgment conditions of multi-hits can be different in different specific designs. As an example, in some implementations, the multi-hit detector determines whether the demand addresses simultaneously hit multiple entries, and if it is determined that multiple entries are hit, it is determined that there is a multi-hit situation.

[0100] Then, in step S503: determining, using the multi-hit detector, M selected entries from the N entries based on information of the N entries in a case where there are N entries, wherein M is an integer greater than or equal to 1 and less than N.

[0101] As an implementation, M can be equal to 1, i.e., one entry is determined as the selected entry directly from the multiple hit entries, and the other entries in the N entries are determined as the unselected entries. As another implementation, M can be set to a value less than N according to specific situations, for example, in the case of N being 4, two entries can be selected as the selected entries, and the other two entries are determined as the unselected entries.

[0102] As an implementation, M is equal to 1, in which case, determining the M selected entries from the N entries based on the information of the N entries by the multiple hit detector comprises determining the entry with the highest confidence parameter as the selected entry from the N entries based on the information of the N entries. That is, for the N entries with multiple hits, the entry with the highest value of the confidence Conf is determined as the selected entry, and the other entries are determined as the unselected entries.

[0103] As another implementation, M is equal to 1, in which case, determining the M selected entries from the N entries based on the information of the N entries by the multiple hit detector comprises determining the entry allocated earliest in time as the selected entry from the N entries based on the information of the N entries. That is, for the N entries with multiple hits, the selected entry is determined according to the allocation time of the entry.

[0104] As yet another implementation, M is equal to 1, in which case, determining the M selected entries from the N entries based on the information of the N entries by the multiple hit detector comprises determining the entry with the smallest or largest entry number as the selected entry from the N entries based on the information of the N entries. For example, referring to Figure 2 , for the N entries with multiple hits, the selected entry is determined according to the entry number value, for example, the entry with the smallest entry number is determined as the selected entry. Assuming that in step S502, entry 0 and entry 2 are determined as the two entries that will generate duplicate prefetch addresses, in this implementation, entry 0 can be determined as the selected entry, and entry 2 is determined as the unselected entry.

[0105] Next, referring to Figure 5 , in step S504, the multiple hit detector generates a veto instruction for the unselected entries in the N entries other than the M entries, so as to prohibit the unselected entries from generating stream data prefetch requests.

[0106] According to an embodiment of the present disclosure, the multiple hit detector first detects whether there is a hit on multiple entries, and when multiple entry hits occur, the selected entry is determined according to certain rules, and for the unselected entries, an entry invalidation signal, for example, can be sent to stop these repeated entries from generating subsequent prefetch requests, that is, to reduce repeated entries. As an example, these entry resources that receive the invalidation signal will be released for subsequent demand address-based streaming data training and prefetching process. In addition, since the multiple hit detector detects and invalidates multiple entries in the hardware prefetch module, it can intervene before the prefetch request is sent, avoiding the impact of repeated prefetch requests on prefetch training, and avoiding the occupation of pipeline and cache resources by these repeated prefetch requests, which is beneficial to improve the prefetch performance and the overall performance of the processor.

[0107] According to some embodiments of the present disclosure, the prefetcher can further include a prefetch request generator. The data prefetching method according to an embodiment of the present disclosure further includes generating a streaming data prefetch request based on the M selected entries by using the prefetch request generator, and the streaming data prefetch request is used for a streaming data prefetching process based on the cache. That is, for the selected entries, no other operations can be performed, and the subsequent prefetching process can continue according to the original implementation, which is not limited herein.

[0108] According to some embodiments of the present disclosure, the streaming data prefetch request is used for a streaming data prefetching process based on a level one cache, a level two cache, and a last level cache. As described above, according to the cache location where the target data is prefetched, the prefetcher can be divided into an L1-level prefetcher, an L2-level prefetcher, and an LLC-level prefetcher. The data prefetching method according to an embodiment of the present disclosure can be applied to any one of the above L1-level prefetcher, L2-level prefetcher, and LLC-level prefetcher, that is, there is no requirement for the applicable range.

[0109] According to some embodiments of the present disclosure, the multiple hit detector is implemented as a pipeline, independent of the multiple entries, and performs multiple hit detection in parallel with the training and prefetching process of the multiple entries. According to an embodiment of the present disclosure, the processing flow of the multiple hit detector can be a pipeline in actual implementation, and the pipeline of the multiple hit detector and the pipeline of the streaming entries are independent of each other, and the pipeline stages of the two are determined by the timing of their respective specific implementation logic.

[0110] Precisely because the detection process of the multi-way hit detector according to the present disclosure is independent of multiple entries, and multi-way hit detection is performed in parallel with the training and prefetching processes of multiple entries, it is possible to further save the number of pipeline stages of detectors and entries, thereby reducing power consumption. This is because if multi-way hit judgment is added to the training pipeline for each entry, it will cause additional timing pressure. In order to implement the relevant logic, the number of training pipeline stages for each entry needs to be increased, which not only increases hardware resource consumption, but also increases the number of pipeline stages. In addition, it will bring greater prefetch delay. More importantly, in scenarios where multi-way hits do not occur, the increased logic and number of stages will lead to additional power consumption and performance loss.

[0111] Figure 6 FIG. 4 shows an execution flow chart of a multi-way hit detector according to an embodiment of the present disclosure, as shown in FIG. Figure 6 As shown, in step S601, the requested address enters the streaming data prefetcher. Next, a determination is made as to whether the address hits multiple entries (S602). If multiple hits occur, the highest-priority entry is determined from among the multiple entries (S603). For example, the entry with the highest confidence value (Conf) is selected as the selected entry. Then, in S604, the highest-priority entry is retained, and the other unselected entries are discarded. If multiple hits do not occur, the multiple-hit detector performs no further operations (S605).

[0112] Next, combine Figure 7A and Figure 7B A specific example of implementing multi-way hit detection using the data prefetching method disclosed herein is given. Assume that all entries in the streaming data prefetcher are empty, i.e., in the initial state. Next, the input required address sequence is represented as A, A+5, A+1, A+2, A+6, A+7, A+3, A+4, A+8, and A+9. This sequence is a disordered streaming sequence.

[0113] First, refer to Figure 7A The situation shown is that no parallel multi-way hit detection is added. Assume that the hit situation of the above required address sequence is as follows:

[0114] Address A is assigned entry 0; address A+5 is assigned entry 1;

[0115] Afterwards, addresses A+1, A+2 hit entry 0, and entry 0 enters prefetch mode;

[0116] Afterwards, address A+6, A+7 hits entry 0, and entry 0 updates the status AccVec and DmdPtr; at the same time, address A+6, A+7 hits entry 1, and entry 1 enters prefetch mode;

[0117] After that, addresses A+3, A+4 hit entry 0, and entry 0 updates state AccVec;

[0118] After that, addresses A+8, A+9 hit entry 0, and entry 0 updates state AccVec, DmdPtr; meanwhile, addresses A+8, A+9 hit entry 1, and entry 1 updates state AccVec, DmdPtr.

[0119] After the input of the above demand address sequence ends, finally, BaseAddr of entry 0=A+2, DmdPtr=7, and suppose that the confidence of entry 0 Conf=1 and the interval Dist=5; then entry 0 can send a total of 12 prefetch requests, and the address range is A+3~A+14; finally, BaseAddr of entry 1=A+7, DmdPtr=2, and suppose that the confidence of entry 1 Conf=1 and the interval Dist=5; then entry 1 can send a total of 7 prefetch requests, and the address range is A+8~A+14; it can be seen that the prefetch address of entry 1 is completely within the prefetch address range of entry 0, and there is repetition in the prefetch address requests sent by the two entries. Repetitive processing of prefetch requests will inevitably cause waste of bandwidth, power consumption and performance loss of subsequent execution units.

[0120] Next, refer to Figure 7B , which shows the training of the stream data prefetcher after the multi-way hit detector is added, so that the hit situation of the above demand address sequence A, A+5, A+1, A+2, A+6, A+7, A+3, A+4, A+8, A+9 is the same as that shown in Figure 7A , that is:

[0121] Address A is allocated to entry 0; address A+5 is allocated to entry 1;

[0122] After that, addresses A+1, A+2 hit entry 0, and entry 0 enters the prefetch mode;

[0123] After that, addresses A+6, A+7 hit entry 0, and entry 0 updates state AccVec, DmdPtr; meanwhile, addresses A+6, A+7 hit entry 1, and entry 1 enters the prefetch mode;

[0124] Refer to Figure 7B , due to the addition of the multi-way detection process, when the input address A+7 is input, the multi-way hit detector finds the same entry multi-way hit situation, then, for example, entry 0 can be selected to be retained (as the selected entry) and entry 1 can be discarded (as the unselected entry) according to the AccVec count, thereby entry 1 no longer performs the subsequent prefetch process;

[0125] After that, addresses A+3, A+4 hit entry 0, and entry 0 updates state AccVec;

[0126] Afterwards, A+8 and A+9 hit entry 0, which updates the states AccVec and DmdPtr.

[0127] After the required address sequence is input, the final entry 0 has BaseAddr = A+2, DmdPtr = 7, and assuming conf = 1 and Dist = 5; then entry 0 can issue a total of 12 prefetch requests, with addresses A+3 to A+14; entry 1 is no longer valid.

[0128] In addition, it is understandable that because the pipeline of the multi-way hit detector is independent of the training / prefetch pipeline of the streaming data prefetch entry, there may be a certain time window from the entry entering the prefetch mode to the entry being abolished. Before the abolition, entry 1 may issue a partial prefetch request. Figure 7B In the example, it issues at most four prefetch requests, and subsequent sequences will not generate repeated prefetch address requests. The deprecated entry 1 can be freed up for training other required addresses. For example, if the subsequent address received is A+100, it can be assigned to the freed entry 1.

[0129] In summary, according to the data prefetching method provided by the embodiment of the present disclosure, multiple entries of the prefetcher are independently trained and streaming data prefetch requests are generated, thereby reducing the requirements for the pipeline depth of the entries. On the basis of ensuring the rapid training of multiple entries, the hardware implementation area of ​​the multiple entries of the prefetcher can also be controlled. Furthermore, the multi-way hit detector of the prefetcher performs repeated detection on multiple entries in parallel, that is, based on the hit information of multiple entries, it determines whether there are entries in the multiple entries that will generate repeated prefetch addresses, and prohibits some entries that will generate repeated prefetch addresses, ensuring that the subsequent prefetch process no longer repeatedly hits multiple entries, and multiple entries will not issue prefetch requests for repeated addresses, thereby avoiding the waste of power consumption and entry bandwidth caused by repeated prefetching, thereby improving the prefetching performance of the prefetcher and improving the overall operating performance of the electronic device.

[0130] According to another aspect of the present disclosure, an electronic device is provided. Figure 8A 1 shows a schematic block diagram of an electronic device according to an embodiment of the present disclosure. Figure 8A As shown, the electronic device 1000 according to an embodiment of the present disclosure may include a prefetcher 1010 and a cache 1020. The prefetcher 1010 may be configured to include a plurality of entries 1011 and a multi-way hit detector 1012. According to an embodiment of the present disclosure, the prefetcher 1010 may be, for example, the streaming data prefetcher described above, for discovering streaming data access patterns of addresses. The cache 1020 may be the above-mentioned three-level cache architecture, i.e., L1 cache, L2 cache, and LLC cache. The above-mentioned plurality of entries 1011 may have the following structure: Figure 2The illustrated hardware structure is used to independently perform the stream data prefetch and the training process, respectively.

[0131] According to some embodiments of the present disclosure, the plurality of entries 1011 can be configured to receive a demand address for the cache, and perform training based on the demand address to identify a stream data pattern and generate a stream data prefetch request, wherein each entry of the plurality of entries independently performs the training and generates the stream data prefetch request.

[0132] According to some embodiments of the present disclosure, the multiple hit detector 1012 can be configured to determine, based on the hit information of the plurality of entries, whether there are N entries in the plurality of entries that will generate duplicate prefetch addresses, wherein N is an integer greater than 1; in a case where it is determined that there are N entries, determine M selected entries from the N entries based on the information of the N entries, wherein M is an integer greater than or equal to 1 and less than N; and generate an abort instruction for the unselected entries in the N entries other than the M entries, so as to prohibit the unselected entries from generating the stream data prefetch request.

[0133] The specific implementation process of the plurality of entries 1011 and the multiple hit detector according to the embodiments of the present disclosure can refer to the description of the data prefetch method according to the present disclosure above, which will not be described here again.

[0134] According to some embodiments of the present disclosure, the multiple hit detector 1012 is implemented as a pipeline, is independent of the plurality of entries 1011, and performs the multiple hit detection in parallel with the training and prefetch process of the plurality of entries 1011.

[0135] According to some embodiments of the present disclosure, the demand address is a virtual address corresponding to a load instruction or a store instruction. Specifically, the demand address is a virtual address corresponding to a load instruction or a store instruction, such as Figure 2 The entries 0 to 31 in the table 1000 receive the ld / st op information and perform training in parallel to identify a stream data pattern and generate a possible prefetch request.

[0136] According to some embodiments of the present disclosure, the multiple hit detector 1012 determines, based on the hit information of the plurality of entries, whether there are N entries in the plurality of entries that will generate duplicate prefetch addresses, including: in a case where the demand addresses simultaneously hit N entries of the stream data in the same direction and in a prefetch mode or in a training mode, it is determined that there are N entries that will generate duplicate prefetch addresses; or in a case where the demand addresses simultaneously hit N entries of the stream data in the same direction and in a prefetch mode or in a prefetch mode, it is determined that there are N entries that will generate duplicate prefetch addresses.

[0137] According to some embodiments of the present disclosure, M is equal to 1, and the multi-way hit detector 1012 determines M selected entries from the N entries based on information of the N entries includes one of the following: determining an entry with the highest confidence parameter as a selected entry from the N entries based on information of the N entries; determining an entry with the earliest time allocation as a selected entry from the N entries based on information of the N entries; or determining an entry with the smallest or largest entry number as a selected entry from the N entries based on information of the N entries.

[0138] According to some embodiments of the present disclosure, the prefetcher 1010 can further include a prefetch request generator. The prefetch request generator can be configured to generate a streaming data prefetch request based on the M selected entries, wherein the streaming data prefetch request is used for a streaming data prefetch process based on the cache.

[0139] According to some embodiments of the present disclosure, the streaming data prefetch request is used for a streaming data prefetch process based on a level one cache, a level two cache and a last level cache of the cache.

[0140] According to some embodiments of the present disclosure, the electronic device 1000 can further include a load store unit (LSU). The prefetcher 1010 is located in the load store unit, and the load store unit further includes a load store queue (LSQ) and an arbiter (Arbiter). The prefetcher 1010 herein can refer to the hardware prefetch module HWPF in Figure 1 , and the relationship between the LSU and the LSQ can refer to the description in Figure 1 , which will not be repeated here.

[0141] According to some embodiments of the present disclosure, the load store queue LSQ can be configured to generate a demand access based on information of a read or write operation. The arbiter (Arbiter) can be configured to generate a data access request based on the demand access of the load store queue and the streaming data prefetch request generated by the prefetcher, the data access request corresponding to a demand address, wherein the prefetcher performs training and prefetching based on the demand address.

[0142] The electronic device according to the embodiments of the present disclosure can implement the specific execution process of the data access, prefetching and the like, and in addition, the electronic device according to the embodiments of the present disclosure can implement the steps of the data prefetching method according to some embodiments of the present disclosure described above in combination with the drawings, which will not be repeated here. The electronic device according to the embodiments of the present disclosure can perform similar data prefetching process and achieve similar technical effects.

[0143] As an implementation manner, Figure 8B An example structure diagram of an electronic device according to an embodiment of the present disclosure is shown. In combination with the comparison Figure 2 and Figure 8BIt can be seen that the prefetcher according to the embodiments of the present disclosure is further configured with a plurality of hit detectors, which are independent of the entries and can perform repeated detection on a plurality of entries in parallel, that is, based on the hit information of the plurality of entries, it is determined whether there is an entry of a prefetch address that will cause repetition in the plurality of entries, for example, by providing a stall signal to the unselected entries to disable a part of the entries of the prefetch address that will cause repetition, to ensure that the subsequent prefetch process no longer repeatedly hits the plurality of entries, and the plurality of entries thus do not send a prefetch request of a repeated address, thereby avoiding the power consumption and waste of entry bandwidth caused by repeated prefetching, and further improving the prefetch performance of the prefetcher and the overall operation performance of the electronic device.

[0144] According to yet another aspect of the present disclosure, an electronic device is provided. Figure 9 A schematic block diagram of an electronic device according to some embodiments of the present disclosure is shown.

[0145] As Figure 9 shown, the electronic device 2000 can include a processor 2010 and a memory 2020. According to some embodiments of the present disclosure, the memory 2020 stores computer readable code which, when executed by the processor 2010, can perform the steps of the data prefetching method provided according to the embodiments of the present disclosure.

[0146] The processor 2010 can perform various actions and processes according to the programs stored in the memory 2020. Specifically, the processor 2010 can be an integrated circuit with signal processing capability. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor or the like.

[0147] The memory 2020 stores computer readable code which, when executed by the processor 2010, can cause the processor to implement the data prefetching method according to some embodiments of the present disclosure. The memory 2020 can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. It should be noted that the memory described herein can be any suitable type of memory. By executing the computer readable code in the memory 2020, the processor 2010 can implement the steps of the data prefetching method described above in conjunction with the accompanying drawings.

[0148] Figure 10 A schematic architecture diagram of an example electronic device according to embodiments of the present disclosure is shown. It can be understood that, Figure 10 The electronic device shown is merely an example and should not impose any limitation on the functions and scope of use of the embodiments of the present disclosure.

[0149] For example, as Figure 10As shown, in some examples, the electronic device 3000 includes a processing device (e.g., a central processor, a graphics processor, etc.) 3010 that can perform various suitable actions and processes in accordance with programs stored in a Read-Only Memory (ROM) 3020 or loaded from storage 3080 into a Random Access Memory (RAM) 3030. Various programs and data needed in the operation of the computer system are also stored in the RAM 3030. The processing device 3010, the ROM 3020, and the RAM 3030 are in communication with each other by way of a bus 3040. An Input / Output (I / O) interface 3050 is also connected to the bus 3040.

[0150] For example, the following components can be connected to the I / O interface 3050: input devices 3060 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output devices 3070 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 3080 including, for example, a magnetic tape, a hard disk, etc.; and communication devices 3090 including, for example, a LAN card, a modem, etc. The communication devices 3090 can allow the electronic device 3000 to communicate wirelessly or through a wire with other devices to exchange data, perform communication processing via a network such as the Internet. A drive 3100 is also connected to the I / O interface 3050 as necessary. A removable medium 3110, such as a magnetic disk, a magneto-optical disk, a semiconductor memory, etc., is attached to the drive 3100 as necessary, so that a computer program read out therefrom is installed into the storage 3090 as necessary. Although Figure 10 The electronic device 3000 is shown including various devices, but it should be understood that not all of the shown devices are required to be implemented or included. More or fewer devices can alternatively be implemented or included.

[0151] For example, the electronic device 3000 can further include a peripheral interface (not shown in the figure) and the like. The peripheral interface can be various types of interfaces, such as a USB interface, a lighting interface, and the like. The communication device 3090 can communicate with a network and other devices through wireless communication.

[0152] For example, processes described above with reference to the flowcharts can be implemented as a computer software program in accordance with embodiments of the present disclosure. For example, embodiments of the present disclosure include a computer program product including a computer program carried on a non-transitory computer-readable medium.

[0153] According to another aspect of the present disclosure, there is also provided a non-transitory computer-readable storage medium having computer-readable instructions stored thereon, which, when executed by a processor, cause the processor to perform the steps of the data prefetching method according to the present disclosure.

[0154] Figure 11 A schematic block diagram of a storage medium according to an embodiment of the present disclosure is shown. As shown, a computer-readable storage medium 4000 has computer-readable instructions 4010 stored thereon. When the computer-readable instructions 4010 are run by a processor, the steps of the data prefetching method described with reference to the above figures can be performed. Figure 11

[0155] It is noted that the computer-readable storage medium provided by the present disclosure may, for example, be (but is not limited to) an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the above. More specific examples of the computer-readable storage medium can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In an embodiment of the present disclosure, the computer-readable storage medium can be any tangible medium that contains or stores a program used by or in connection with an instruction execution system, apparatus, or device. The above computer-readable medium can be contained in the above electronic device or exist separately from the electronic device.

[0156] In the context of the present disclosure, the machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the above. More specific examples of the machine-readable storage medium can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0157] ​The above description merely illustrates the application of the present disclosure and the principles of the technologies applied. It should be understood by those skilled in the art that the disclosed scope of the present disclosure is not limited to the technical solutions formed by the specific combinations of the technical features described above, and also covers other technical solutions formed by the combinations of the technical features described above or their equivalent features without departing from the technical concepts disclosed above. For example, technical solutions formed by replacing the above-described features with technical features disclosed in the present disclosure (but not limited to) having similar functions.

[0158] In addition, although the present disclosure makes various references to certain units in the electronic device and the electronic apparatus according to the embodiments of the present disclosure, any number of different units can be used and operated on the client and / or server. The units are merely illustrative, and different aspects of the method, electronic device, and electronic apparatus can use different units.

[0159] Those of ordinary skill in the art can understand that all or part of the steps of the above method can be instructed by a computer program to relevant hardware, and the program can be stored in a computer readable storage medium, such as a read-only memory, a magnetic disk, or an optical disk. Alternatively, all or part of the steps of the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiments can be implemented in the form of hardware or in the form of a software functional module. The present disclosure is not limited to any specific form of combination of hardware and software.

[0160] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0161] The above is a description of the present disclosure and should not be considered as a limitation. Although several exemplary embodiments of the present disclosure are described, those skilled in the art will readily understand that many modifications can be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims. It should be understood that the above is a description of the present disclosure and should not be considered as a limitation. It is intended that the disclosed embodiments and other embodiments be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A data prefetching method, characterized in that: The method is applicable to an electronic device, the electronic device including a prefetcher and a cache, wherein the prefetcher includes a plurality of entries and a multi-way hit detector, the method comprising: Receive a request address for the cache using the plurality of entries, and perform training based on the request address to identify streaming data patterns and generate streaming data prefetch requests, wherein each entry in the plurality of entries independently performs the training and generates the streaming data prefetch requests; and Determining, using the multi-way hit detector based on hit information of the plurality of entries, whether there are N entries in the plurality of entries that will generate duplicate prefetch addresses, where N is an integer greater than 1; In a case where it is determined that the N entries exist, using the multi-way hit detector to determine M selected entries from the N entries based on information of the N entries, where M is an integer greater than or equal to 1 and less than N; and The multi-way hit detector is used to generate an invalidation instruction for unselected entries other than the M entries among the N entries, so as to prohibit the unselected entries from generating streaming data prefetch requests.

2. The method according to claim 1, characterized in that The multi-way hit detector is implemented as a pipeline, is independent of the plurality of entries, and performs multi-way hit detection in parallel with the training and prefetching processes of the plurality of entries.

3. The method according to claim 1, characterized in that The required address is a virtual address corresponding to a load instruction or a store instruction.

4. The method according to claim 1, wherein The determining, using the multi-way hit detector based on the hit information of the plurality of entries, whether there are N entries in the plurality of entries that will generate duplicate prefetch addresses comprises: In a case where the demand address simultaneously hits N entries in the same direction of streaming data and in prefetch mode or training mode, determining that there are N entries that will generate duplicate prefetch addresses; or In the case that the demand address simultaneously hits N entries that have the same direction of streaming data and are in prefetch mode or are in prefetch mode, it is determined that there are N entries that will generate duplicate prefetch addresses.

5. The method according to claim 1, wherein M is equal to 1, and determining M selected entries from the N entries based on information of the N entries by using the multi-way hit detector includes: Based on the information of the N entries, an entry with the highest confidence parameter is determined from the N entries as the selected entry.

6. The method according to claim 1, characterized in that M is equal to 1, and determining M selected entries from the N entries based on information of the N entries by using the multi-way hit detector includes: An entry that is allocated earliest in time is determined from the N entries based on information of the N entries as the selected entry.

7. The method according to claim 1, characterized in that M is equal to 1, and determining M selected entries from the N entries based on information of the N entries by using the multi-way hit detector includes: Based on the information of the N entries, an entry with the smallest or largest entry number is determined from the N entries as the selected entry.

8. The method according to claim 1, characterized in that The prefetcher further includes a prefetch request generator, and the method further includes: The prefetch request generator is used to generate a streaming data prefetch request based on the M selected entries, where the streaming data prefetch request is used to perform a streaming data prefetch process based on the cache.

9. The method according to claim 8, characterized in that The streaming data pre-fetch request is used to perform a streaming data pre-fetch process based on the first-level cache, the second-level cache and the last-level cache of the cache.

10. An electronic device, characterized in that: The electronic device includes a prefetcher and a cache, wherein the prefetcher is configured to include a plurality of entries and a multi-way hit detector, wherein: The plurality of entries are configured to: receive a demand address for the cache, and perform training based on the demand address to identify streaming data patterns and generate streaming data prefetch requests, wherein each entry in the plurality of entries independently performs the training and generates the streaming data prefetch requests; and The multi-way hit detector is configured as follows: Determining, based on hit information of the plurality of entries, whether there are N entries in the plurality of entries that will generate duplicate prefetch addresses, where N is an integer greater than 1; In a case where it is determined that the N entries exist, determining M selected entries from the N entries based on information of the N entries, where M is an integer greater than or equal to 1 and less than N; and A disable instruction is generated for unselected entries other than the M entries among the N entries, so that the unselected entries are prohibited from generating streaming data prefetch requests.

11. The electronic device according to claim 10, characterized in that The multi-way hit detector is implemented as a pipeline, is independent of the plurality of entries, and performs multi-way hit detection in parallel with the training and prefetching processes of the plurality of entries.

12. The electronic device according to claim 10, wherein: The required address is a virtual address corresponding to a load instruction or a store instruction.

13. The electronic device according to claim 10, wherein: The multi-way hit detector determines, based on the hit information of the multiple entries, whether there are N entries in the multiple entries that will generate duplicate prefetch addresses, including: In a case where the demand address simultaneously hits N entries in the same direction of streaming data and in prefetch mode or training mode, determining that there are N entries that will generate duplicate prefetch addresses; or In the case that the demand address simultaneously hits N entries that have the same direction of streaming data and are in prefetch mode or are in prefetch mode, it is determined that there are N entries that will generate duplicate prefetch addresses.

14. The electronic device according to claim 10, wherein: M is equal to 1, and the multiple hit detector determines, based on information of the N entries, that M selected entries from the N entries include one of the following: Determining, based on information of the N entries, an entry with the highest confidence parameter from the N entries as the selected entry; Determining, based on information of the N entries, the entry that is allocated earliest in time from the N entries as the selected entry; or Based on the information of the N entries, an entry with the smallest or largest entry number is determined from the N entries as the selected entry.

15. The electronic device according to claim 10, wherein: The prefetcher further includes a prefetch request generator configured to generate a streaming data prefetch request based on the M selected entries, wherein the streaming data prefetch request is used to perform a streaming data prefetch process based on the cache.

16. The electronic device according to claim 15, characterized in that The streaming data pre-fetch request is used to perform a streaming data pre-fetch process based on the first-level cache, the second-level cache and the last-level cache of the cache.

17. The electronic device according to claim 10, wherein: The electronic device further comprises a read-write unit, wherein the prefetcher is located in the read-write unit of the electronic device, and the read-write unit further comprises a read-write queue and an arbitrator, wherein, The read and write queue is configured to: generate demand access based on information of read and write operations; The arbiter is configured to generate a data access request based on the demand access of the read / write queue and the streaming data prefetch request generated by the prefetch, wherein the data access request corresponds to the demand address, wherein the prefetcher performs training and prefetching based on the demand address.

18. An electronic device, characterized in that: The electronic device comprises a processor and a memory, wherein the memory stores computer-readable code, which, when executed by the processor, causes the processor to perform the steps of the method according to any one of claims 1 to 9.

19. A non-transitory computer-readable storage medium having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by a processor, the processor is caused to perform the steps of the method according to any one of claims 1 to 9.

20. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the processor is caused to perform the steps of the method according to any one of claims 1 to 9.

Images