A plug-in universal DMA module for AHB bus

Abstract

The present invention discloses an AHB bus-oriented plug-in universal DMA module, belonging to the field of semiconductor chip design. The present invention comprises a first bus splitting unit, a second bus splitting unit, a third bus splitting unit, a bus interface unit, a bus reading unit, a DMA buffer, a bus writing unit, a first bus multiplexing unit, a second bus multiplexing unit, and a third bus multiplexing unit. The present invention can realize the insertion of a DMA function module without changing the original design, and the inserted DMA is a universal DMA module, which can realize the movement of data of any length on the AHB bus and meet the requirements of aligning any different addresses of the source address and the destination address on the AHB bus.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor chip design, and in particular to an AHB bus-oriented plug-in universal DMA module, which can be used in SoC design scenarios in the semiconductor field, especially in situations where an additional DMA module needs to be inserted in the later stage of design. Background Art

[0002] DMA can automatically move data on the bus, thereby releasing the CPU from the task of data movement and effectively alleviating the pressure on the CPU. Therefore, it is widely used in various SoCs and accelerators. Depending on the application, the DMA module may have different bus interfaces, different bus transfer address alignment requirements, etc.

[0003] Since DMA only realizes a data movement function, it plays a supporting role in SoC design for specific functions. As a result, DMA is often ignored in the early stage of design, but needs to be inserted in the later stage of design. However, how to realize data movement from any source address to any target address and any length by inserting DMA without changing the original design is a problem that has not been solved by the existing technology. Summary of the invention

[0004] In view of this, the present invention proposes a plug-in universal DMA module for AHB bus. The present invention can insert a DMA module without changing the original design, and the designed DMA module is a universal DMA module that supports different address alignment requirements of source address and destination address.

[0005] The technical solution adopted by the present invention is:

[0006] A plug-in universal DMA module for AHB bus, used for being arranged between an accelerator and the AHB bus, so as to realize data movement between the accelerator and other devices on the AHB bus under the control of a CPU; comprising a bus splitting unit 1, a bus splitting unit 2, a bus splitting unit 3, a bus interface unit, a bus read controller, a data buffer, a bus write controller, a bus multiplexer 1, a bus multiplexer 2, and a bus multiplexer 3;

[0007] The bus splitting unit 1 is connected to the bus interface unit, the bus multiplexer 3 and the external CPU bus respectively;

[0008] The bus interface unit is also connected to the bus read controller and the bus write controller respectively;

[0009] The data buffer is connected to the bus read controller and the bus write controller respectively;

[0010] The bus read controller is also connected to the bus splitting unit 2;

[0011] The bus write controller is also connected to the bus splitting unit 3;

[0012] The bus multiplexer 1 is connected to the bus splitting unit 2, the bus splitting unit 3 and the bus multiplexer 3 respectively;

[0013] The bus multiplexer 2 is respectively connected with the bus splitting unit 2, the bus splitting unit 3 and the external accelerator;

[0014] The bus multiplexer 3 is also connected to the outside through the multiplexed bus.

[0015] Furthermore, the data buffer includes a circular buffer composed of a single-slot first-in-first-out unit (FIFO) of D bytes, the head of the circular buffer has a write pointer, and the tail of the circular buffer has a read pointer; the data read from the bus is written into the data buffer and the write pointer is modified; when the bus issues a write request, the data is taken out from the data buffer and sent to the bus;

[0016] The single-slot FIFO has a data register, a data valid flag register Reg, a NOT gate, and an OR gate; the input information of the single-slot FIFO unit includes an input valid flag, input data, and an input ready flag, and the output information includes an output valid flag, output data, and an output ready flag, wherein the input ready flag is generated by the output ready flag and the output valid flag through the following combinational logic:

[0017] Input ready = Output ready || ! Output valid

[0018] In the formula, || is an OR gate and ! is a NOT gate.

[0019] Further, the bus splitting unit 1, the bus splitting unit 2, and the bus splitting unit 3 have the same structure and are collectively referred to as bus splitting units;

[0020] The bus splitting unit includes an address decoding unit and a delay and selection unit. The address decoding unit determines whether the bus enable signals of branch bus 1 and bus 2, namely bus 1 enable and bus 2 enable, are valid according to the address range of the two branch buses split out, namely bus 1 address and bus 2 address. The delay and selection unit first delays the valid read and write signals sent out, and then selects the bus ready signals of the two branches, namely bus 1 ready and bus 2 ready, and the bus read data signals, namely bus 1 read data and bus 2 read data, according to the branch to which the valid read and write signals belong. The bus 1 address and bus 2 address are the same as the bus addresses originally requested.

[0021] Furthermore, bus multiplexer 1, bus multiplexer 2, and bus multiplexer 3 have the same structure and are collectively referred to as bus multiplexers;

[0022] The bus multiplexer includes an arbitrator, a latch and a delay and selection unit; the arbitrator selects one from three branches, including two branch bus applications - bus 1 signal and bus 2 signal - and latched bus applications - latched bus signals, and authorizes downward access; the latch latches the received but unauthorized bus application signal - rejected bus signal - in a register; the delay and selection unit delays the authorized bus signal and indicates to which branch the bus ready signal and bus read data should be sent, that is, whether the bus ready signal and bus read signal should be sent to the bus 1 ready signal and bus 1 read data signal or the bus 2 ready signal and bus 2 read data signal.

[0023] Furthermore, the bus read controller includes a DMA read state machine, a synchronous FIFO unit and a combinational logic unit; the DMA read state machine obtains control information from the bus interface unit, initiates a read request to the bus, and stores the read data into the synchronous FIFO unit, and finally sends it to the data buffer; the size of the synchronous FIFO unit is the data amount of 2 time slots; the combinational logic unit is used to calculate the state of the synchronous FIFO unit and determine whether the synchronous FIFO unit is empty or is becoming empty; after the DMA read state machine initiates the first read request, it can only continue to initiate subsequent read requests if the synchronous FIFO unit is empty or is becoming empty.

[0024] Furthermore, the bus write controller includes a DMA write state machine, a single-slot FIFO unit, a delayer and an AND gate; the DMA write state machine obtains control information from the bus interface unit, initiates a read data request to the data buffer through byte enable, and simultaneously initiates a write request to the bus; the single-slot FIFO unit delays the data read back from the data buffer by one time slot; the delayer samples the valid bus write request and delays it, and the delayed bus write request signal and the bus ready signal pass through the AND gate to form the output ready signal of the single-slot FIFO unit; the output data of the single-slot FIFO is directly used as the bus write data.

[0025] Furthermore, the bus interface unit is used to convert the bus signal of a branch of the bus splitting unit 1 into a register read / write signal to realize the control of the bus read controller and the bus write controller.

[0026] The beneficial effects of the present invention are:

[0027] 1) The original architecture and accelerator design are not changed, and zero modification insertion of the original design is achieved.

[0028] 2) Different address alignment requirements from source address to destination address can be achieved.

[0029] 3) Versatility of DMA function: It can realize data movement of any length from any address to any address.

[0030] 4) Universality of bus interface: DMA configuration bus interface, DMA read data interface, write data interface, interface with CPU, and interface with accelerator are all standard AHB bus interfaces, which are easy to integrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is a schematic diagram of the SoC architecture without DMA;

[0032] Figure 2 This is a schematic diagram of the SoC architecture after DMA is inserted;

[0033] Figure 3 It is a general architecture diagram of an AHB bus-oriented plug-in general DMA module in an embodiment of the present invention;

[0034] Figure 4 yes Figure 3 Schematic diagram of the data buffer part;

[0035] Figure 5 yes Figure 4 Schematic diagram of the structure of the single-slot FIFO unit;

[0036] Figure 6 yes Figure 3 A schematic diagram of the structure of the bus splitting unit;

[0037] Figure 7 yes Figure 3 The structural diagram of the bus multiplexer in the middle;

[0038] Figure 8 yes Figure 3 The structural diagram of the bus read controller;

[0039] Fig. 9 yes Figure 3 Schematic diagram of the structure of the bus write controller. DETAILED DESCRIPTION

[0040] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0041] Figure 1 shows the situation where DMA is ignored in the early stage of design. In Figure 1, there are three accelerators on a CPU bus - accelerator 1, accelerator 2 and accelerator 3. Accelerator 1 is a task-oriented accelerator, and accelerator 2 and accelerator 3 are some general accelerators or peripheral interfaces, such as Ethernet interface, LCD display accelerator, etc. In the later stage of design, due to the need for data movement in accelerator 1, a DMA module needs to be added to realize data movement between accelerator 1 and accelerator 2, accelerator 3 and the main memory controller, that is, to realize Figure 2 To this end, this embodiment proposes a plug-in universal DMA module for the AHB bus, namely Figure 2 The DMA and bus multiplexer in the MCU can realize the data movement of any source address to any target address and any length without changing the original design.

[0042] like Figure 3 As shown, a plug-in universal DMA module for AHB bus includes a bus splitting unit 1, a bus splitting unit 2, a bus splitting unit 3, a bus interface unit, a bus read controller, a data buffer, a bus write controller, a bus multiplexer 1, a bus multiplexer 2, and a bus multiplexer 3;

[0043] The bus splitting unit 1 is connected to the bus interface unit, the bus multiplexer 3 and the external CPU bus respectively;

[0044] The bus interface unit is also connected to the bus read controller and the bus write controller respectively;

[0045] The data buffer is connected to the bus read controller and the bus write controller respectively;

[0046] The bus read controller is also connected to the bus splitting unit 2;

[0047] The bus write controller is also connected to the bus splitting unit 3;

[0048] The bus multiplexer 1 is connected to the bus splitting unit 2, the bus splitting unit 3 and the bus multiplexer 3 respectively;

[0049] The bus multiplexer 2 is respectively connected with the bus splitting unit 2, the bus splitting unit 3 and the external accelerator;

[0050] The bus multiplexer 3 is also connected to the outside through the multiplexed bus;

[0051] Among them, the bus read controller, data buffer, and bus write controller constitute the core part of DMA data movement.

[0052] like Figure 4As shown, the data buffer includes a circular buffer composed of D bytes of single-slot FIFO units, with a write pointer at the head of the circular buffer and a read pointer at the tail of the circular buffer. The data read from the bus is written into the data buffer and the write pointer is modified; when the bus issues a write request, the data is taken out from the data buffer and sent to the bus. Due to the requirement of bus address alignment, the source address of the read data and the destination address of the write data may have different read and write data packet sizes. The data buffer plays a role in adjusting the write and read data packet sizes. For a 32-bit AHB bus, the minimum value of D here is 8, that is, at least 8 single-slot FIFO units are required.

[0053] like Figure 5 As shown, the single-slot FIFO unit has a data register, a data valid flag register Reg, a NOT gate, and an OR gate; the input direction of the single-slot FIFO unit includes three signals: input valid flag, input data, and input ready flag; the output direction includes output data valid flag, output data, and output ready flag; among them, the input ready flag is generated by the output ready flag and the output data valid flag through combinational logic, and their relationship is as follows:

[0054] Input ready = Output ready || ! Output data valid

[0055] Here, || is an OR gate and ! is a NOT gate.

[0056] An important feature of a single-slot FIFO unit is that new data can be input while data is being output.

[0057] like Figure 6 As shown in FIG. 1 , the bus splitting unit includes a bus address decoding unit and a delay and selection unit. The address decoding unit determines whether the bus enable signals of the two branches, Bus 1 and Bus 2, are valid or not, according to the address range of the two branches, Bus 1 and Bus 2. The delay selection unit first delays the valid read / write signals sent out, and then selects the Bus 1 ready signal, Bus 2 ready signal and Bus 1 read data signal, Bus 2 read data signal of the two branches according to the branch to which the valid read / write signals belong.

[0058] like Figure 7As shown in Figure 1, the bus multiplexer includes an arbiter, a latch, and a delay and selection unit. The arbiter selects one from the two branch bus applications and the latched bus application (a total of three branches) and authorizes the downward access. The latch latches the received but unauthorized bus application in the register. The delay selection unit delays the authorized bus application and indicates which way the bus ready and bus read data should be sent. It should be noted here that the latched bus application signal can only belong to one of the two external sources, so the output bus ready and bus read data also have only two outgoing output paths.

[0059] like Figure 8 As shown, the bus read controller includes a DMA read state machine, a synchronous FIFO unit and a combinational logic unit. The DMA read state machine obtains control information from the bus interface unit, initiates a read request to the bus, and stores the read data in the synchronous FIFO unit, and finally sends it to the data buffer. The size of the synchronous FIFO unit is the amount of data for 2 time slots. The combinational logic unit is mainly used to calculate the state of the synchronous FIFO unit. It determines whether the synchronous FIFO unit is empty or is changing to an empty state. After the DMA read state machine initiates the first read request, subsequent read requests can only be initiated if the synchronous FIFO unit is empty or is changing to an empty state.

[0060] like Fig. 9 As shown, the bus write controller includes a DMA write state machine, a single-slot FIFO unit, a delayer, and an AND gate. The DMA write state machine obtains control information from the bus interface unit, initiates a read data request to the DMA buffer, and simultaneously initiates a write request to the bus. Since the write data of the AHB bus is delayed by one clock compared to the write request, the bus write unit uses a single-slot FIFO unit to delay the data read back from the DMA buffer by one time slot. The delayer samples the valid bus write request and delays it. The delayed bus write request signal and the bus ready signal pass through an AND gate to form the output ready signal of the single-slot FIFO unit.

[0061] It should be noted here that the DMA write state machine is the master control machine. It reads data from the DMA buffer and sends a write request to the bus at the same time. However, the write request of the bus will only send a valid write request to the external bus when the read data from the DMA buffer arrives, and can continue to send a write request for the next data packet.

[0062] The DMA module has four operating modes: Figure 3 As shown, they are described as follows:

[0063] Mode 1:

[0064] The DMA module reads data from the multiplexed bus and writes it to the accelerator bus.

[0065] Mode 2:

[0066] The DMA module reads data from the accelerator bus and writes it to the multiplexed bus.

[0067] Mode 3:

[0068] The DMA module reads data from the multiplexed bus and writes data to the multiplexed bus.

[0069] Mode 4:

[0070] The DMA module reads data from the accelerator bus and writes data to the accelerator bus.

[0071] In summary, the present invention can realize the insertion of a DMA function module without changing the original design, and the inserted DMA is a universal DMA module, which can realize the movement of data of any length on the AHB bus and meet the requirements of aligning any different source addresses and destination addresses on the AHB bus.

[0072] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.

Claims

1. A plug-in general DMA module for AHB bus, characterized in that: Used to be set between the accelerator and the AHB bus, so as to realize data movement between the accelerator and other devices on the AHB bus under the control of the CPU; including a first bus splitting unit, a second bus splitting unit, a third bus splitting unit, a bus interface unit, a bus reading unit, a DMA buffer, a bus writing unit, a first bus multiplexing unit, a second bus multiplexing unit, and a third bus multiplexing unit; Wherein, the first bus splitting unit is connected to the bus interface unit, the third bus multiplexing unit and the external CPU respectively; The bus interface unit is also connected to the bus reading unit and the bus writing unit respectively; The DMA buffer is connected to the bus reading unit and the bus writing unit respectively; The bus reading unit is also connected to the second bus splitting unit; The bus write unit is also connected to the third bus splitting unit; The first bus multiplexing unit is respectively connected to the second bus splitting unit, the third bus splitting unit and the third bus multiplexing unit; The second bus multiplexing unit is respectively connected to the second bus splitting unit, the third bus splitting unit and the external accelerator; The third bus multiplexing unit is also connected to an external bus.

2. The AHB bus-oriented plug-in general DMA module according to claim 1, characterized in that: The DMA buffer includes a circular buffer composed of D bytes of single-slot first-in-first-out units, the head of the circular buffer has a write pointer Write_Pointer, and the tail of the circular buffer has a read pointer Read_Pointer; the data read from the bus is written into the DMA buffer and the write pointer Write_Pointer is modified; when the bus issues a write request, the data is taken out of the DMA buffer and sent to the bus; The single-slot FIFO unit has a data register Dat Reg, a data valid flag register VldReg, a NOT gate Not, and an OR gate Or; the input information of the single-slot FIFO unit includes an input valid flag Valid_in, input data Data_in, and an input register available flag Ready_in, and the output information includes an output data valid flag Valid_out, output data Data_out, and an output destination buffer available signal Ready_out, wherein Ready_in is generated by Ready_out and Valid_out through the following combinational logic: Ready_in = Ready_out || !Valid_out In the formula, || is an OR gate and ! is a NOT gate.

3. The AHB bus-oriented plug-in general DMA module according to claim 1, characterized in that: The first bus splitting unit, the second bus splitting unit, and the third bus splitting unit have the same structure; The bus splitting unit includes a bus address decoding unit and a delay selection unit. The address decoding unit determines whether the htrans signal of the branch is valid according to the address range of the two branches split out; the delay selection unit first delays the valid read and write signals sent out, and then selects the ready signals hready and read data signals hrdata of the two branches according to the branches to which the valid read and write signals belong.

4. The AHB bus-oriented plug-in general DMA module according to claim 1, characterized in that: The first bus multiplexing unit, the second bus multiplexing unit and the third bus multiplexing unit have the same structure; The bus multiplexing unit includes an arbiter, a latch and a delay selection unit; the arbiter selects one of the three branches from the two branch bus applications and the latched bus application, and authorizes the downward access; the latch latches the received but unauthorized bus application in the register; the delay selection unit delays the authorized bus application and indicates to which branch hready and read data hrdata should be sent.

5. The AHB bus-oriented plug-in general DMA module according to claim 1, characterized in that: The bus read unit includes a DMA read state machine, a synchronous first-in-first-out unit and a combinational logic unit; the DMA read state machine obtains control information from the bus interface unit, initiates a read request to the bus, and stores the read data in the synchronous first-in-first-out unit, and finally sends it to the DMA buffer; the size of the synchronous first-in-first-out unit is the amount of data in 2 time slots; the combinational logic unit is used to calculate the state of the synchronous first-in-first-out unit and determine whether the synchronous first-in-first-out unit is empty or is becoming empty; after the DMA read state machine initiates the first read request, subsequent read requests can only be initiated if the synchronous first-in-first-out unit is empty or is becoming empty.

6. The AHB bus-oriented plug-in general DMA module according to claim 1, characterized in that: The bus write unit includes a DMA write state machine, a single-slot first-in-first-out unit, a delayer and an AND gate; the DMA write state machine obtains control information from the bus interface unit, initiates a read data request to the DMA buffer, and simultaneously initiates a write request to the bus; the single-slot first-in-first-out unit delays the data read back from the DMA buffer by one time slot; the delayer samples the effective bus write request and delays it, and the delayed bus write request signal and the bus hready signal pass through the AND gate to form the output destination buffer available signal of the single-slot first-in-first-out unit.

7. The AHB bus-oriented plug-in general DMA module according to claim 1, characterized in that: The bus interface unit is used to convert the bus signal of a branch of the first bus splitting unit into a register read / write signal to realize the control of the bus read state machine and the bus write state machine.

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