Simultaneous bidirectional signaling in silicon vias

Abstract

The present disclosure relates to simultaneous bidirectional signaling in silicon vias. A signal transmitter sends a signal onto a bidirectional transmission medium of a TSV. A boost circuit can be used to supplement the signal as needed. A calibration circuit device periodically activates a signal driver of the signal transmitter at time intervals to send a test signal on the bidirectional transmission medium of the TSV. The calibration circuit device then compares the level of the test signal with a range, where different levels within the range correspond to different logic levels. If the level of the test signal is outside the expected range, the boost circuit is activated to bring the level of the test signal into the expected range.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims the benefit of co-pending, commonly assigned U.S. Provisional Patent Application No. 63 / 543,023, filed on October 6, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to multi-layer electronic devices for data transmission and storage that employ ultra-fast and ultra-short-range physical layer transceivers (PHYs) for sending and receiving signals between device layers. More specifically, the present disclosure relates to maintaining signal integrity in bidirectional signaling in chip-to-chip signaling paths such as through silicon vias (TSVs). Background Art

[0004] The background description provided herein is for the purpose of presenting the context of the present disclosure in general. The work of the inventors thereof (to the extent that the work described in this background section) and some aspects of the description which would not have been considered as prior art at the time of filing are neither explicitly nor implicitly admitted to be prior art of the subject matter of the present disclosure.

[0005] In traditional circuit structures, PHY is integrated into the die or positioned in the package laterally relative to other components. The layout of PHY in these structures requires a high level of signal processing to ensure the integrity of the signal delivered to the PHY for remote device reception. By stacking the chip or chiplet with PHY positioned on it on top of the main chip, the distance from the components on the main chip to the PHY is significantly shortened. In the stacked die circuit structure, signals can be transmitted between components on different dies in the stacked die structure. To facilitate such transmission, a structure called silicon through hole (TSV) provides a communication path from one die to another. Conventional stacked die structures use conventional PHYs connected to a synchronous data bus to transfer data between stacked dies, chips or chiplets. Trace matching changes limit the data speed of these conventional PHYs to 3.2Gbps. The data rate may also be limited because the PHY will have to use a lower Nyquist frequency to reduce insertion loss. In the absence of an equalization circuit device, the PHY must operate at a lower data rate to communicate through the channel. Therefore, conventional stacked die circuit structures are currently used only in applications where faster data rates are not critical, and such conventional structures would not be suitable for use with components such as serializer / deserializers (SERDES) or in artificial intelligence or machine learning circuit devices.

[0006] Environmental factors (such as temperature, humidity, etc.) can affect the operation of the signal driver or components of the signal driver. The signal driver can include two field effect transistors (FETs) as its data driver elements. For example, a P-type FET can be responsible for generating a signal representing a logic 1, while an N-type FET can be responsible for generating a signal associated with a logic 0. Changes in environmental and operating conditions can change the output signal level of each FET, resulting in an output level mismatch between the two FETs. Such a mismatch can cause the signal level to fall outside the range of one logic level and fall within the range of a different logic level, causing the receiver of the signal to receive incorrect or corrupted data. Summary of the invention

[0007] This article describes systems, methods, and devices for sending and receiving signals on a bidirectional transmission medium of a silicon through hole (TSV). A signal transmitter sends a signal to the bidirectional transmission medium of the TSV. A boost circuit can be used to supplement the signal as needed. A calibration circuit device periodically activates a signal driver of the signal transmitter at a time interval to send a test signal on the bidirectional transmission medium of the TSV. The calibration circuit device then compares the level of the test signal with a range, and different levels within the range correspond to different logic levels. If the level of the test signal is outside the expected range, the boost circuit is activated to bring the level of the test signal into the expected range.

[0008] In some implementations, the signal driver includes: a P-type transistor configured to send a signal at a first level corresponding to a first logic level; and an N-type transistor configured to send a signal at a second level corresponding to a second logic level different from the first logic level. Then, the calibration circuit device may include: a first comparator configured to compare the first level of the first signal with a first range; and a second comparator configured to compare the second level of the second signal with a second range. The boost circuit may also include: a P-type transistor configured to send a signal at a first level corresponding to the first logic level; and an N-type transistor configured to send a signal at a second level corresponding to the second logic level.

[0009] In some implementations, the calibration circuitry compares the test signal to the range using a comparator. The comparator may be a sample and hold comparator.

[0010] In some implementations, the time intervals at which the calibration process is periodically performed are multiples of the duration of a clock cycle. Each interval may coincide with the start of a clock cycle. In some implementations, the time intervals may be calibrated so that the calibration circuit device activates the signal driver at the start of each clock cycle.

[0011] In some implementations, the calibration circuit device can disable the signal driver after an amount of time that is less than the duration of the clock cycle. This allows the signal transmitter to transmit data onto the bidirectional transmission medium of the TSV during at least a portion of the clock cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Other features of the present disclosure, its nature and various advantages will become apparent from consideration of the following detailed description taken in conjunction with the accompanying drawings, in which like reference numerals refer to like parts throughout, and in which:

[0013] Figure 1 is a schematic representation of an illustrative stacked die circuit structure having TSVs and a respective transceiver at each end of each TSV for transmitting and receiving signals through each respective TSV in accordance with some implementations of the presently disclosed subject matter;

[0014] Figure 2 yes Figure 1 A cross-sectional representation of an illustrative stacked die circuit structure;

[0015] Figure 3 is a cross-sectional representation of a region of an illustrative stacked die structure including TSVs through which bidirectional signaling occurs between layers of the stacked die circuit structure according to some implementations of the disclosed subject matter;

[0016] Figure 4 is a circuit diagram showing an illustrative circuit arrangement for calibrating signal levels of a signal driver to ensure accurate data transmission over a TSV in accordance with some implementations of the presently disclosed subject matter;

[0017] Figure 5 is a circuit diagram showing an illustrative circuit arrangement for comparing a signal level to a range to recover binary data from a received signal in accordance with some implementations of the disclosed subject matter;

[0018] Figure 6 depicts a series of eye diagrams representing a clock signal and signal levels present on a TSV during different phases of the clock signal at times when no data is being transmitted on the TSV, in accordance with some implementations of the presently disclosed subject matter; and

[0019] Figure 7 is a flow chart representing an illustrative process for calibrating a signal driver in accordance with some implementations of the disclosed subject matter. DETAILED DESCRIPTION

[0020] As described above, stacked die circuit structures are generally limited to applications that do not require high-speed data transmission. Therefore, the components of the stacked die circuit structure that rely on communication between stacked dies do not include devices that require high-speed data transmission, such as PHY or SERDES, network switches, storage controllers, AI processors, etc. Instead, these devices are laterally positioned on the same chip, chiplet, or package, and due to the long distances that the signals must travel across the chip, chiplet, or package, a high level of signal processing is required to ensure signal integrity.

[0021] The subject matter of the present disclosure enables bidirectional signal integrity to be maintained in a chip-to-chip signaling path. Although the subject matter of the present disclosure described below focuses on the example of TSV, it is applicable to other chip-to-chip signaling paths, such as 3D face-to-face configurations in which two integrated circuit device chips communicate with each other only through hybrid bonding interconnections. The present disclosure also allows compensation for any mismatch in signal levels between components responsible for sending different logic level signals to the TSV, thereby ensuring that the correct data value is received at the other end of the TSV. This allows the subject matter of the present disclosure to be used in the context of data transmission, storage, and processing, as well as in other contexts in which a large amount of data needs to be sent to and received from a remote device. The transceiver at one end of the TSV sends and receives signals simultaneously. Therefore, the signal present on the transmission medium of the TSV is a combination of a sending signal and a receiving signal. To ensure that any signal sent or received on the TSV is accurate, the signal level representing different logic levels must be calibrated to within an acceptable range.

[0022] By reference Figures 1 to 7 The subject matter of the present disclosure may be better understood.

[0023] Figure 1 1 is a schematic representation of an illustrative stacked die circuit structure with TSVs through which signals can be transmitted between dies according to some implementations of the subject matter of the present disclosure. Die 100 and die 102 form a stacked die circuit structure. TSVs 104a to 104c are formed in die 100 and communicatively connect die 100 and die 102. Transceivers 106, 110, and 114 transmit signals from die 100 to die 102 to corresponding TSVs 104a, 104b, and 104c, while transceivers 108, 112, and 116 transmit signals from die 102 to die 100 to corresponding TSVs 104a, 104b, and 104c. Since TSVs provide a bidirectional transmission path between die 100 and die 102, any transceiver located on die 100 or die 102 can transmit a signal to its corresponding TSV at any time. Therefore, any signal sent onto the TSV may at least partially overlap with a signal sent in the opposite direction.

[0024] Figure 2 is a cross-sectional representation of an illustrative stacked die circuit structure with TSVs in accordance with some implementations of the disclosed subject matter. Figure 2 The stacked die circuit structure is formed by die 200 including wiring layer 202 deposited on device silicon layer 204 and die 206 including wiring layer 208 deposited on device silicon layer 210. TSVs 212a-212i (where Figure 1 The TSVs 104a-104c of FIG. 104 are an illustrative subset) provide a signaling path between die 200 and die 206. At the interface between the TSVs and die 206 are hybrid bonds 214a-214i, through which signals from die 200 are transmitted to die 206 and signals from die 206 are transmitted to the transmission medium of each corresponding TSV through the hybrid bonds. Hybrid bonding, also known as direct bond interconnection (DBI), is a permanent bond that combines dielectric bonding with embedded metal to form an interconnect between two stacked dies. For example, hybrid bond interconnection points can be made on a first die by depositing a dielectric (e.g., silicon oxide) over a metal (e.g., copper) column or other contact structure. The surface of the die can then be planed to remove any dielectric material covering the contacts during deposition and to produce a flat surface for mating with another die. A second die having hybrid bond interconnection points can then be stacked on the first die so that the hybrid bond interconnection points are aligned. The two dies are then bonded together (e.g., using heat) so that both the metal contact structure and the dielectric material are fused together. In one example implementation, die 200 is a memory device (e.g., SRAM) and die 206 is a system on chip (SOC) device. In another example, die 200 is a PHY and die 206 is a SERDES device. In some implementations, the transmission medium is a solid conductor, such as a copper wire formed in a via. However, other types of transmission media may be possible. These stacking and bonding techniques may also be applicable to stacks of more than two dies. For example, a stack of three dies can be stacked and bonded in this manner as long as the middle die has interconnect points on both its top and bottom surfaces.

[0025] Figure 3304. FIG. 306 is a cross-sectional representation of TSVs through which bidirectional signaling occurs between layers of a stacked die circuit structure according to some implementations of the subject matter of the present disclosure. Die 300 has a wiring layer 302 that can communicate with devices on other dies (e.g., die 304) of the stacked die circuit structure. TSVs 306 begin at the wiring layer 302 of die 300 and extend through a device silicon layer 308 of die 300. Hybrid bonding 310 communicatively couples TSVs 306 to die 304, thereby completing a signaling path between die 300 and die 304.

[0026] Figure 4 4 is a circuit diagram showing an illustrative circuit device for calibrating the signal level of a signal driver to ensure accurate data transmission on a TSV according to some implementations of the subject matter of the present disclosure. Signal driver elements 400a and 400b (collectively referred to as driver element 400) are used to transfer data to the TSV. For example, driver element 400a can be responsible for transferring logic 1 to the TSV by pulling the output signal of the signal driver to a first signal level associated with logic 1 (e.g., a more positive voltage level). Driver element 400b can similarly be responsible for transferring logic 0 to the TSV by pulling the output signal of the signal driver to a second signal level associated with logic 0 (e.g., a more negative voltage level). This can be achieved using switches (such as FETs 402 and 404). The activation of each FET causes the output signal to be pulled in the corresponding direction, thereby transferring the associated binary value to TSV 406. In some implementations, the driver element can be at least partially embedded in one or both of the device layers of each die in the interconnect structure (e.g., die 200 and 206).

[0027] Data originating from or passing through the device layer of at least one die is received at connection 408 and provided to driver element 400a. The data also passes through inverter 410 before being provided to driver element 400b. In this way, each driver element is activated for different logic levels. When concurrent signals are transmitted in opposite directions on the TSV, when one signal contains 0 and the other signal contains 1, the TSV signal level will be approximately halfway between the signal level associated with logic 0 and the signal level associated with logic 1. For example, when one signal is at 700mV corresponding to logic 1 and the reverse signal is at 50mV corresponding to logic 0, the voltage of the signal will be 375mV. In another example, the voltage corresponding to logic 1 can be 500mV and the voltage corresponding to logic 0 can be 100mV, resulting in a signal at 300mV. In yet another example, the voltage corresponding to a logical 1 may be 500 mV, while a logical 0 corresponds to ground (i.e., 0 mV), or in some cases, slightly greater than 0 mV (e.g., 5 mV) since ground may not be exactly 0 mV. This results in a test signal voltage of 250 mV. However, if there is a mismatch between the output level or amount of one driver element switch (e.g., FET 402) pulling the signal in the positive direction and the output level or amount of another driver element switch (e.g., FET 404) pulling the signal in the negative direction, the signal present on the TSV may fall outside the threshold range when the reverse signal transmits a different value.

[0028] To compensate for any mismatch in the output levels, the driver elements 400 are periodically activated together, and the resulting signal is compared to a range of signal levels using a comparator 412. When two driver elements are activated simultaneously with appropriately matched signal driver elements, the signal level should be halfway between the signal levels for each logic level. For example, if the signal level for a logic 0 is 50 mV and the signal level for a logic 1 is 700 mV, the test signal generated by activating the two signal drivers should be 375 mV when the signal driver elements are appropriately matched. To account for minor deviations, the transceiver can be configured to read any signal less than 375 mV as a logic 0 and any signal greater than 375 mV as a logic 1. In some implementations, other ranges based on threshold deviations from the expected signal levels for each logic level can be used.

[0029] If the signal driver elements have mismatched output levels, the test signal will not fall precisely between the levels of each logic level (e.g., 375mV). Comparator 412 is used to compare the test signal with the logic value range to determine whether the test signal is at the midpoint between the logic levels. If the signal level of the test signal is too close to the signal level of logic 0, one of boost drivers 416 and 418 (collectively referred to as boost driver 414) is activated to supplement the signal driver elements with lower performance and adjust the signal level toward the midpoint. Similarly, if the signal level of the test signal is too close to the signal level of logic 1, one of boost drivers 414 is activated to supplement the signal driver elements with lower performance and adjust the signal level toward the midpoint. The boost driver 414 activated during the calibration phase is activated when its corresponding signal driver element is activated to transmit the signal to the bidirectional transmission medium of TSV until the next calibration phase occurs.

[0030] Comparator 412 may be a sample and hold comparator. When the two driver elements are activated, comparator 412 samples the signal present on the TSV. When the two driver elements are activated and properly matched, a reference voltage corresponding to the expected signal level is also provided to comparator 412. Then, the signal present on the TSV is compared with the reference voltage. If the signal level does not match the reference voltage, or is not within the threshold range of the reference voltage, no matter which boost driver is required to bring the signal level within the threshold range of the reference voltage, comparator 412 makes the boost enable signal (first boost enable signal 413 or second boost enable signal 415) thereto effective.

[0031] In one example, it may be determined during a first calibration phase that a boost driver is needed to supplement a logic 1 signal driver. When the calibration phase ends and the signal transmission phase begins, the boost driver is activated whenever the logic 1 signal driver is activated in order to successfully transmit a logic 1. The boost driver will remain activated in this manner until a second calibration phase determines if it is still needed or if the output power of the boost driver needs to be adjusted.

[0032] Figure 5 is a circuit diagram showing an illustrative circuit arrangement for comparing a signal level to a range to recover binary data from a received signal according to some implementations of the disclosed subject matter. The received signal may be Figure 4The circuit arrangement depicted is driven. Two separate comparators 500 and 502 are used to determine whether the signal level on the TSV is within a range corresponding to a logical 1 or a logical 0. This produces a window comparator, where a signal at or less than one quarter of the maximum signal level indicates that both dies are transmitting a logical 0, and a signal at or greater than three quarters of the maximum signal level indicates that both dies are transmitting a logical 1. A signal level between one quarter of the maximum signal level and three quarters of the maximum signal level indicates that the two dies are transmitting opposite logic values ​​(i.e., one die transmits a logical 1 and the other die transmits a logical 0). To recover the received data in this case, the logic value transmitted by the die receiving the signal can be subtracted from the received signal.

[0033] Figure 6 A series of eye diagrams according to some implementations of the subject matter of the present disclosure are depicted, representing the clock signal during different phases of the clock signal and the signal levels present on the TSVs at times when no data is being transmitted on the TSVs. A first portion 600 of the clock cycle may be used for signal calibration, leaving a second portion 602 of the clock cycle for data transmission. If calibration is performed at every clock cycle, this will effectively result in half of the maximum data rate that would be possible if calibration was not performed. To avoid such a drastic reduction in data rate, calibration may not be performed at every clock cycle, but rather at some time interval longer than a single clock cycle.

[0034] When calibration is not performed, and when no data is being transmitted, the signal 604 present on the TSV may include a high signal and a low signal generated by a driver element in an idle state. Alternatively, in the absence of a signal on the TSV, the signal channel may remain undriven. During part 600 of the clock cycle, both driver elements are activated at a signal 606 present on the TSV, and signal 606 is an intermediate level signal between a high signal level and a low signal level. If the output signal level of the driver element is properly matched, the intermediate level signal 606 should be halfway between the high signal level and the low signal level. If the intermediate level signal is outside the expected range, the corresponding boost element may be activated to compensate for the intermediate level signal and return it to the expected range. During part 602 of the clock cycle, if no data is to be transmitted, the driver elements return to their idle state. If data is to be transmitted, the driver elements are activated to transmit data, wherein one driver element is valid when transmitting logic 0 and the other driver element is valid when transmitting logic 1. During part 602 of the clock cycle, the boost element may also be activated as needed based on the result of the calibration process performed during part 600 of the clock cycle.

[0035] Figure 7is a flow chart representing an illustrative process for calibrating a signal driver according to some implementations of the disclosed subject matter. At 702, the calibration circuit device initializes or retrieves a value T representing a time interval at which calibration is to occur. The time interval may be the duration of a clock cycle, meaning that calibration will occur at every clock cycle or at some multiple of the duration of a clock cycle. At 704, the calibration circuit device determines whether the interval has elapsed. If not ("No" at 704), the calibration circuit device waits.

[0036] If the time interval has elapsed ("yes" at 704), then at 706, the calibration circuit device activates the signal driver of the signal transmitter to transmit the test signal on the bidirectional transmission medium of the TSV. The transmission of the test signal can be achieved by activating a signal driver element responsible for transmitting a logic 0 and simultaneously activating a second signal driver element responsible for transmitting a logic 1. Therefore, the resulting test signal should have a signal level halfway between the signal level of a logic 0 and the signal level of a logic 1.

[0037] At 708, the calibration circuit device compares the level of the test signal with a range, wherein the level within the range corresponds to a logic level. The level may be a voltage level or a current level. For example, a voltage level of 50mV may correspond to a logic 0, and a voltage level of 700mV may correspond to a logic 1. To account for slight changes in the output level, a threshold deviation, such as 100mV, may be permitted. Therefore, any voltage level between 50mV and 150mV may be considered as a logic 0, and any voltage level between 600mV and 700mV may be considered as a logic 0. Alternatively, any voltage level at or less than 150mV may be considered as a logic 0, and any voltage level at or greater than 600mV may be considered as a logic 1. In another example, the threshold may be a quarter of the difference between the voltage level of logic 0 and the voltage level of logic 1. If logic 0 corresponds to 50mV and logic 1 corresponds to 700mV, a quarter of the difference between the two logic levels is 162.5mV. Thus, any voltage level at or less than 212.5 mV may be considered a logical 0, and any voltage level at or greater than 537.5 mV may be considered a logical 1. The calibration circuitry may compare the voltage level of the test signal to one or more of these thresholds to determine whether the voltage level of the signal is outside of an expected range. In some implementations, the calibration circuitry may determine whether the voltage level of the test signal is greater than a threshold level for a logical 0 (e.g., 212.5 mV) and less than a threshold level for a logical 1 (e.g., 537.5 mV).

[0038] At 710, the calibration circuit device determines whether the level of the test signal is outside of an expected range. For example, the expected range may be greater than a threshold level of a logic 0 and less than a threshold level of a logic 1 (e.g., between 212.5 mV and 537.5 mV). If the level of the test signal is within the expected range ("No" at 710), the calibration circuit device waits for the next calibration cycle.

[0039] If the calibration circuit device determines that the level of the test signal is outside the expected range ("yes" at 710), then at 712, the calibration circuit device activates the boost circuit to bring the level of the test signal into the expected range. For example, if the test signal is within the threshold of logic 0 (e.g., less than 212.5mV), a boost driver configured to increase the voltage level of the test signal is activated. Similarly, if the test signal is within the threshold of logic 1 (e.g., greater than 537.5mV), a boost driver configured to reduce the voltage level of the test signal is activated. The output power of the activated boost driver can be variable and controlled by the calibration circuit device so as to bring the test signal level into the expected range without overshoot.

[0040] Thus, it is seen that a method and system for high-speed data transfer and storage using ultra-short range PHY for performing bidirectional signaling in TSVs has been provided. This allows for reduced power requirements and increased usable area on each die of a stacked die circuit structure. By eliminating the need to include complex signal processing and / or signal compensation circuitry, TSVs can be more densely packed on each die of a stacked die circuit structure.

[0041] As used herein and in the appended claims, the construction "one of A and B" shall mean "A or B."

[0042] It should be noted that the foregoing is only illustrative of the principles of the invention and that the invention may be practiced by embodiments other than those described, which are presented for purposes of illustration and not limitation, and that the invention is limited only by the claims that follow.

Claims

1. A transceiver for sending and receiving signals on a bidirectional transmission medium of a silicon through-hole (TSV), the transceiver comprising: a signal transmitter configured to transmit a signal to the bidirectional transmission medium of the TSV; a boost circuit configured to supplement the signal; as well as A calibration circuit arrangement, the calibration circuit arrangement being configured to: activating a signal driver of the signal transmitter at time intervals to transmit a test signal on the bidirectional transmission medium of the TSV; comparing the level of the test signal to a range, wherein levels within the range correspond to logic levels; as well as In response to determining that the level of the test signal is outside an expected range based on the comparison, the boost circuit is activated to bring the level of the test signal into the expected range.

2. The transceiver according to claim 1, wherein the signal driver of the signal transmitter comprises: a P-type transistor configured to transmit a signal at a first level corresponding to a first logic level; as well as An N-type transistor configured to transmit a signal at a second level corresponding to a second logic level different from the first logic level.

3. The transceiver of claim 2, wherein the calibration circuit device further comprises: a first comparator configured to compare a first level of a first signal with a first range; as well as A second comparator is configured to compare a second level of the second signal with a second range.

4. The transceiver according to claim 1, wherein the boost circuit comprises: a P-type transistor configured to transmit a signal at a first level corresponding to a first logic level; as well as An N-type transistor is configured to transmit a signal at a second level corresponding to a second logic level.

5. The transceiver of claim 1 , wherein the calibration circuit device further comprises a comparator, wherein the calibration circuit device configured to compare the level of the test signal with a range is configured to compare a reference level with the level of the test signal using the comparator.

6. The transceiver according to claim 1, further comprising: a clock having a clock cycle duration, Wherein the time intervals are multiples of the duration of the clock cycle duration, and wherein the start of each interval coincides with the start of a corresponding clock cycle.

7. The transceiver of claim 6, wherein the time interval is calibrated such that the calibration circuit arrangement activates the signal driver of the signal transmitter at the beginning of each clock cycle.

8. The transceiver of claim 6, wherein the calibration circuit device is further configured to: after an amount of time less than the duration of the clock cycle, disable the signal driver of the signal transmitter, so that the signal transmitter can transmit data onto the bidirectional transmission medium of the TSV during at least a portion of the clock cycle.

9. A method for simultaneously bidirectionally transmitting data on a bidirectional transmission medium of a through silicon via (TSV), the method comprising: activating a signal driver of a signal transmitter at time intervals to transmit a test signal on the bidirectional transmission medium of the TSV; comparing the level of the test signal to a range, wherein levels within the range correspond to logic levels; as well as In response to determining that the level of the test signal is outside of an expected range based on the comparison, a boost circuit is activated to bring the level of the test signal into the expected range.

10. The method of claim 9, wherein activating the signal driver of the signal transmitter comprises: activating a P-type transistor of the signal driver to send a signal at a first level, the first level corresponding to a first logic level; as well as The N-type transistor of the signal driver is activated to transmit a signal at a second level corresponding to a second logic level different from the first logic level.

11. The method of claim 10, wherein comparing the level of the test signal to a range comprises: comparing a first level of a first signal to a first range; as well as The second level of the second signal is compared to the second range.

12. The method of claim 9, wherein activating the boost circuit comprises: activating a P-type transistor of the boost circuit to send a signal at a first level, the first level corresponding to a first logic level; as well as The N-type transistor of the boosting circuit is activated to transmit a signal at a second level, the second level corresponding to a second logic level.

13. The method according to claim 9, further comprising: providing the test signal to the comparator, Wherein comparing the level of the test signal with a range is performed using the comparator.

14. The method according to claim 9, further comprising: receiving a clock signal having a duration of a clock cycle, Wherein the time intervals are multiples of the duration of the clock cycle, and wherein the start of each interval coincides with the start of a corresponding clock cycle.

15. The method of claim 14, further comprising setting the time interval so that calibration circuitry activates the signal driver of the signal transmitter at the beginning of each clock cycle.

16. The method according to claim 14, further comprising: After an amount of time less than the duration of the clock cycle, the signal driver of the signal transmitter is deactivated such that the signal transmitter can transmit data onto the bidirectional transmission medium of the TSV during at least a portion of the clock cycle.

17. An apparatus comprising: a host device comprising a first integrated circuit die and a second integrated circuit die stacked on the first integrated circuit die and communicatively coupled to the first integrated circuit die through a plurality of through silicon vias (TSVs); as well as A transceiver for sending and receiving signals on a bidirectional transmission medium of a TSV disposed on at least one of the first integrated circuit die or the second integrated circuit die, the transceiver comprising: a signal transmitter configured to transmit a signal to the bidirectional transmission medium of the TSV; a voltage boost circuit configured to supplement the signal; and A calibration circuit arrangement, the calibration circuit arrangement being configured to: activating a signal driver of the signal transmitter at time intervals to transmit a test signal on the bidirectional transmission medium of the TSV; comparing the level of the test signal to a range, wherein levels within the range correspond to logic levels; and In response to determining that the level of the test signal is outside an expected range based on the comparison, the boost circuit is activated to bring the level of the test signal into the expected range.

18. The apparatus according to claim 17, wherein the signal driver of the signal transmitter comprises: a P-type transistor configured to transmit a signal at a first level corresponding to a first logic level; as well as An N-type transistor configured to transmit a signal at a second level corresponding to a second logic level different from the first logic level.

19. The apparatus of claim 18, wherein the calibration circuit device further comprises: a first comparator configured to compare a first level of a first signal with a first range; as well as A second comparator is configured to compare a second level of the second signal with a second range.

20. The apparatus of claim 17, wherein the voltage boost circuit comprises: a P-type transistor configured to transmit a signal at a first level corresponding to a first logic level; as well as An N-type transistor is configured to transmit a signal at a second level corresponding to a second logic level.

21. A transceiver for sending and receiving signals on a bidirectional transmission medium of a through silicon via (TSV), the transceiver comprising: a first signal driver element configured to transmit a first logic level onto the bidirectional transmission medium of the TSV; a second signal driver element configured to transmit a second logic level different from the first logic level onto the bidirectional transmission medium of the TSV; a first boosting element configured to supplement an output level of the first signal driver; a second boosting element configured to supplement an output level of the second signal driver; as well as A control circuit device, the control circuit device being configured to: determining whether the first logic level or the second logic level is to be transmitted on the bidirectional transmission medium of the TSV; In response to determining that the first logic level is to be sent: activating the first driver element; as well as activating the first voltage boosting element in response to determining during a calibration process that the output level of the first signal driver requires replenishment; as well as In response to determining that the second logic level is to be transmitted: activating the second driver element; as well as In response to determining during the calibration process that the output level of the second driver element requires replenishing, the second boost element is activated.

22. The transceiver of claim 21 , wherein the control circuit device is further configured to: During a first portion of a clock cycle, transmitting at least one logic level onto the bidirectional transmission medium of the TSV; and The calibration process is performed during a second portion of the clock cycle.

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