A method and system for implementing directional configuration of Zynq device FPGA core

Abstract

The present invention discloses a method and system for realizing directional configuration of FPGA core of Zynq device. In the process of testing Zynq device, JTAG daisy chain is cascaded on Zynq device; FPGA core connected to Zynq device is developed, data format of configuration information of FPGA core is obtained based on JTAG daisy chain, operation of daisy chain topology is realized through JTAG daisy chain, thereby realizing directional configuration of FPGA core of Zynq device, and JTAG daisy chain technology can be used to send instructions and receive responses from Zynq device and its connected equipment, thereby performing hardware verification, boundary scan test, troubleshooting, etc. This test method not only improves test efficiency, but also reduces test cost. Through JTAG daisy chain, developers can realize directional configuration of FPGA core in Zynq device. FPGA core can be accurately configured as specific logic function, while maintaining close cooperation with Zynq processor core.

Description

Technical Field

[0001] The present invention belongs to the technical field of Zynq device configuration, implements directional configuration of Zynq device FPGA core through JTAG daisy chain topology based on ATE, and specifically relates to a method and system for implementing directional configuration of Zynq device FPGA core. Background Art

[0002] Zynq-7000 stands for ALL Pogrammable SoC, which is a fully programmable system-on-chip. Fully programmable means software programmable and hardware programmable, including PS (Processing System) and PL (Programming Logic). The essential feature of Zynq is the combination of a dual-core ARM Cortex-A9 processor and a traditional field programmable gate array (FPGA) logic device. This makes it not only have the advantages of ASIC in terms of energy consumption, performance and compatibility, but also has the advantages of FPGA hardware programmability. By perfectly combining the software programmability of the processor with the hardware programmability of the FPGA, it provides unparalleled system performance, flexibility and scalability, while meeting the high performance, low power consumption and multi-core processing capability requirements of complex embedded systems.

[0003] As a hardware programmable device, the FPGA core has fixed pin modes and internal resources after configuration and cannot be changed. The pin and resource modes will be reconfigured until the next power-on reconfiguration. Since the FPGA core device has a rich resource mode and pin attributes, the simplest and most effective way to achieve high coverage testing is to configure multiple times, each time completing different module tests. In order to achieve the highest possible coverage, it is generally necessary to configure more than dozens of times.

[0004] It is usually used in the electronics, semiconductor and other industries to perform automated functional testing and fault detection on products. It is a widely used technical means in chip testing. Zynq devices do not have internal Flash, so the stored data or code needs to be saved in external Flash, which is automatically loaded into the device and starts running after power-on. For the FPGA core with rich internal resources, a single configuration based on external Flash is far from achieving high coverage testing. Therefore, high coverage reliability testing of the FPGA core of the Zynq device has brought great challenges. Summary of the invention

[0005] The purpose of the present invention is to provide a method and system for realizing directional configuration of FPGA core of Zynq device, so as to overcome the drawback that the external Flash in the prior art can only realize single loading. The present invention realizes multiple loading of FPGA in Zynq device through ATE, and the number of times is not limited, and unlimited loading can be realized; through multiple configurations, the coverage rate of FPGA core is greatly improved, which can reach more than 90% at most.

[0006] To achieve the above purpose, the technical solution adopted by the present invention is as follows: A method for implementing a directed configuration of a Zynq device FPGA core comprises the following steps: S1, during the testing of the Zynq device, cascading the JTAG daisy chain on the Zynq device; S2, develop the FPGA core connected to the Zynq device, obtain the data format of the configuration information of the FPGA core based on the JTAG daisy chain, and implement the operation of the daisy chain topology through the JTAG daisy chain, thereby realizing the directional configuration of the FPGA core of the Zynq device.

[0007] Preferably, a JTAG daisy chain connection is implemented on the Zynq device, and multiple devices with JTAG interfaces are connected in series through JTAG lines to form a closed loop or linear chain.

[0008] Preferably, FPGA configuration information received via the JTAG daisy chain is parsed and applied to the FPGA core.

[0009] Preferably, an ARM core and an FPGA core are provided in the Zynq device, the pins of the Zynq device are connected via a JTAG daisy chain, and the Zynq device debugging board and the development software are connected via the JTAG daisy chain.

[0010] Preferably, for the development of FPGA core, Verilog or VHDL language is used for programming, and Bit or Bin file is obtained after compilation.

[0011] Preferably, when configuring the FPGA core on the Zynq device, the generated .bit or .bin file is downloaded to the FPGA via the JTAG interface.

[0012] A directed configuration system for an FPGA core of a Zynq device includes a JTAG daisy chain cascaded with the Zynq device, developing an FPGA core connected to the Zynq device, obtaining a data format of configuration information of the FPGA core based on the JTAG daisy chain, and operating the daisy chain topology through the JTAG daisy chain, thereby achieving directed configuration of the FPGA core of the Zynq device.

[0013] Preferably, a JTAG daisy chain connection is implemented on the Zynq device, and multiple devices with JTAG interfaces are connected in series through JTAG lines to form a closed loop or linear chain.

[0014] Preferably, the FPGA configuration information received through the JTAG daisy chain is parsed and applied to the FPGA core, the Zynq device is provided with an ARM core and an FPGA core, the pins of the Zynq device are connected through the JTAG daisy chain, and the Zynq device debugging board and the development software are connected through the JTAG daisy chain.

[0015] Preferably, when configuring the FPGA core on the Zynq device, the generated .bit or .bin file is downloaded to the FPGA via the JTAG interface.

[0016] Compared with the prior art, the present invention has the following beneficial technical effects: The present invention provides a method for realizing directional configuration of FPGA core of Zynq device. In the process of testing Zynq device, JTAG daisy chain is cascaded on Zynq device; FPGA core connected to Zynq device is developed, data format of configuration information of FPGA core is obtained based on JTAG daisy chain, operation of daisy chain topology is realized through JTAG daisy chain, thereby realizing directional configuration of FPGA core of Zynq device, and JTAG daisy chain technology can be used to send instructions and receive responses from Zynq device and its connected equipment, thereby performing hardware verification, boundary scan test, fault troubleshooting, etc. This test method not only improves test efficiency, but also reduces test cost.

[0017] Preferably, through the JTAG daisy chain, developers can implement targeted configuration of the FPGA core in the Zynq device, and can accurately configure the FPGA core to a specific logic function while maintaining close coordination with the Zynq processor core. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The figure is a flow chart of a method for implementing a directional configuration method of a Zynq device FPGA core in an embodiment of the present invention.

[0019] Figure 2 Schematic diagram of a system for implementing a directional configuration of a Zynq device FPGA core in an embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram of configuration information in an embodiment of the present invention.

[0021] Figure 4 Schematic diagram of cascade codes in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0023] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0024] like Figure 1 As shown, the present invention provides a method for implementing a directional configuration of a Zynq device FPGA core, which specifically includes the following steps: S1, during the testing of the Zynq device, cascading the JTAG daisy chain on the Zynq device; S2, develop the FPGA core connected to the Zynq device, obtain the data format of the configuration information of the FPGA core based on the JTAG daisy chain, and implement the operation of the daisy chain topology through the JTAG daisy chain, thereby realizing the directional configuration of the FPGA core of the Zynq device.

[0025] In the process of testing and developing Zynq devices, the present invention uses JTAG (Joint Test Action Group) daisy chain technology, which is a key and efficient means. As a type of system on chip (SoC) that integrates ARM processor cores and programmable logic (FPGA), the testing and development process of Zynq devices is often complex and sophisticated, and JTAG daisy chain technology provides a flexible interface solution.

[0026] Testing requires the use of a JTAG debugger, test scripts, and a test framework for Zynq devices. Cascade JTAG daisy chain: Implement JTAG daisy chain connections on Zynq devices, connecting multiple devices with JTAG interfaces (which may include Zynq itself and other peripheral chips such as FPGAs, memories, etc.) in series through JTAG lines to form a closed loop or linear chain. This connection method allows the test system to access all devices in the chain through a single JTAG interface. Using the JTAG daisy chain, the test system can send instructions and receive responses from the Zynq device and its connected devices to perform hardware verification, boundary scan testing, troubleshooting, etc. This testing method not only improves test efficiency, but also reduces test costs.

[0027] The FPGA core needs to be configured for specific logic functions. Based on the JTAG daisy chain, the configuration information of the FPGA can be transmitted through a specific data format. This configuration information is usually contained in a bitstream file, which is used to define the logical structure and connections inside the FPGA. The FPGA configuration information received through the JTAG daisy chain is parsed and applied to the FPGA core. This requires the development environment to support the corresponding JTAG protocol and the format of the configuration file to ensure that the configuration process is accurate. The JTAG daisy chain also supports operations on the daisy chain topology, such as dynamically adding or removing devices on the chain, adjusting the order of devices, etc. This flexibility allows the hardware connection to be adjusted as needed during the development process, facilitating debugging and optimization.

[0028] Through the JTAG daisy chain, developers can achieve targeted configuration of the FPGA core in the Zynq device, which means that the FPGA core can be precisely configured to specific logic functions according to application requirements while maintaining close coordination with the Zynq processor core.

[0029] Specifically, in the specific implementation manner of the present application, an ARM core and an FPGA core are provided in the Zynq device, and the pins of the Zynq device are connected through a JTAG daisy chain. The Zynq device debugging board and the development software are connected through the JTAG daisy chain. After scanning, the JTAG daisy chain of the Zynq device is obtained, with Xc7z020_1 as the target device (FPGA core), and the tail device arm_dap_0 (ARM core). For the development of the FPGA core, Verilog or VHDL language is used for programming, and a Bit or Bin file is obtained after compilation. Through the above-mentioned hardware connection method, when the Zynq device and the development software are connected, the data format of the FPGA core configuration information containing the daisy chain information can be obtained, as shown in the following example. Figure 3 shown.

[0030] Specifically, Verilog or VHDL is used to write code to describe the logic circuit inside the FPGA core. The code includes module definitions, signal declarations, and logical operations, which together define the functions that the FPGA will implement.

[0031] Compile and synthesize the code using FPGA development tools such as Xilinx Vivado, Intel Quartus, etc. The compilation process converts the HDL code into gate-level netlists, while synthesis further optimizes these netlists into logic structures that can be implemented by FPGA.

[0032] After compilation and synthesis, the FPGA development tool will generate a file containing FPGA configuration information, usually a binary file with a .bit or .bin suffix. This file contains all the logic configuration of the FPGA core and is the key to downloading it to the FPGA hardware for actual operation.

[0033] For Zynq devices with integrated FPGA cores, the process of configuring the FPGA core should pay attention to its coordination with the Zynq processor core. In the above hardware connection method, the Zynq device is connected to the development software through a specific interface (such as JTAG daisy chain) to transmit configuration information.

[0034] When the configuration information of the FPGA core is transmitted through the JTAG daisy chain, this data contains not only the logical configuration of the FPGA core, but also information about the daisy chain topology. This information is critical to ensure the accuracy and completeness of the configuration process.

[0035] When configuring the FPGA core on a Zynq device, the generated .bit or .bin file is downloaded to the FPGA through the JTAG interface. During this process, the development software parses the configuration file and accurately sends the configuration data to the corresponding part of the FPGA core based on the daisy chain information. After the configuration is completed, a series of verification and debugging steps are usually required to ensure that the FPGA core works as expected. This may include functional testing, performance evaluation, and integration testing with other hardware components.

[0036] like Figure 3As shown in the figure, the data format of the FPGA core configuration information of the daisy chain information is obtained, where the 7th and 9th lines represent the information of the head device, and the 8th and 10th lines represent the information of the tail device. The rest is the configuration information of the FPGA core. In addition to the target device xc7z020_1, there is also a tail device (ARM core), but no head device, so the content of the 7th and 9th lines is empty, which are HIR 0 and HDR0 respectively. The information of the tail device in the 8th and 10th lines is TIR 4 TDI (0f) SMASK (0f) and TDR 1 TDI (00)SMASK (01) respectively. According to the IEEE1149.1 protocol standard, the tail device is placed in the Bypass state.

[0037] The operation of the daisy-chain topology is achieved through the JTAG state machine, which operates the target device (FPGA and) and the tail device (ARM core). Figure 3 In the 8th and 10th lines, TIR 4 TDI (0f) SMASK (0f) and TDR 1 TDI (00) SMASK (01) are the instruction register and data register respectively.

[0038] In the JTAG state machine, the target device and the tail device instruction register and data register need to be cascaded. Take the 8th and 12th lines as an example. The cascaded code should be 3fc9 (14 bits). The principle is as follows Figure 4 shown.

[0039] In another embodiment of the present invention, Figure 2 As shown, a system for implementing a directed configuration of an FPGA core of a Zynq device is provided, including a JTAG daisy chain cascaded with the Zynq device, developing an FPGA core connected to the Zynq device, obtaining a data format of configuration information of the FPGA core based on the JTAG daisy chain, and implementing operations on a daisy chain topology through the JTAG daisy chain, thereby implementing directed configuration of the FPGA core of the Zynq device.

[0040] Preferably, a JTAG daisy chain connection is implemented on the Zynq device, and multiple devices with JTAG interfaces are connected in series through JTAG lines to form a closed loop or linear chain.

[0041] Preferably, the FPGA configuration information received through the JTAG daisy chain is parsed and applied to the FPGA core, the Zynq device is provided with an ARM core and an FPGA core, the pins of the Zynq device are connected through the JTAG daisy chain, and the Zynq device debugging board and the development software are connected through the JTAG daisy chain.

[0042] Preferably, when configuring the FPGA core on the Zynq device, the generated .bit or .bin file is downloaded to the FPGA via the JTAG interface.

[0043] Registers are divided into two categories: data registers (DR) and instruction registers (IR). The instruction register is used to control the data register. Among all the boundary scan chains provided by the chip, a specified boundary scan chain is selected as the current target scan chain and the access object. The data register is connected through the TAP controller, which includes TCK, TMS, TDI, and TDO signal interfaces. All data registers (DR) and instruction registers (IR) provided by the chip can be accessed through the TAP controller. The specific access process is: 1) Select a data register to be accessed through the instruction register (IR); 2) Connect the selected data register between TDI and TDO; 3) Driven by TCK, the required data is input into the selected data register through TDI; at the same time, the data in the selected data register is read out through TDO.

[0044] The TAP controller is a state machine that samples on the rising edge of TCK. It has 16 states, and the transition of these states is controlled by the TMS signal. The svf file records the transition of the TAP state machine and the writing and reading of data instructions in the form of commands.

[0045] After the test vector is entered into the Zynq device through the ATE test equipment, the Bypass state of the ARM core and the directional configuration of the FPGA core can be realized through the JTAG daisy chain. After the corresponding bit files are generated through different Verilog and VHDL configuration languages, the directional configuration of the FPGA core can be realized, and the number of times is not limited. Based on the Zynq device being loaded through external Flash, the present invention uses ATE to realize the directional configuration of the FPGA core through the JTAG daisy chain topology. Through multiple configurations, the coverage rate of the FPGA core can be greatly improved, and the coverage rate can be increased to more than 90%, which solves the disadvantage of low coverage rate caused by single configuration of external Flash.

Claims

1. A method for implementing a directional configuration of a Zynq device FPGA core, characterized in that: The following steps are involved: S1, during the testing of the Zynq device, cascading the JTAG daisy chain on the Zynq device; S2, develop the FPGA core connected to the Zynq device, obtain the data format of the configuration information of the FPGA core based on the JTAG daisy chain, and implement the operation of the daisy chain topology through the JTAG daisy chain, thereby realizing the directional configuration of the FPGA core of the Zynq device.

2. A method for implementing a directional configuration of a Zynq device FPGA core according to claim 1, characterized in that: Implement JTAG daisy chain connection on Zynq device, connect multiple devices with JTAG interface in series through JTAG line to form a closed loop or linear chain.

3. A method for implementing a directional configuration of a Zynq device FPGA core according to claim 1, characterized in that: The FPGA configuration information received via the JTAG daisy chain is parsed and applied to the FPGA core.

4. A method for implementing a directional configuration of a Zynq device FPGA core according to claim 1, characterized in that: The Zynq device is provided with an ARM core and an FPGA core. The pins of the Zynq device are connected through a JTAG daisy chain, and the Zynq device debugging board and the development software are connected through the JTAG daisy chain.

5. A method for implementing a directional configuration of a Zynq device FPGA core according to claim 1, characterized in that: For the development of FPGA core, Verilog or VHDL language is used for programming, and Bit or Bin files are obtained after compilation.

6. A method for implementing a directional configuration of a Zynq device FPGA core according to claim 1, characterized in that: When configuring the FPGA core on a Zynq device, the generated .bit or .bin file is downloaded to the FPGA through the JTAG interface.

7. A directed configuration system for implementing a Zynq device FPGA core, characterized in that: It includes a JTAG daisy chain cascaded with a Zynq device, developing an FPGA core connected to the Zynq device, obtaining a data format of configuration information of the FPGA core based on the JTAG daisy chain, and operating the daisy chain topology through the JTAG daisy chain, thereby realizing directional configuration of the FPGA core of the Zynq device.

8. A directed configuration system for implementing a Zynq device FPGA core according to claim 7, characterized in that: Implement JTAG daisy chain connection on Zynq device, connect multiple devices with JTAG interface in series through JTAG line to form a closed loop or linear chain.

9. A directed configuration system for implementing a Zynq device FPGA core according to claim 7, characterized in that: The FPGA configuration information received through the JTAG daisy chain is parsed and applied to the FPGA core. The Zynq device is equipped with an ARM core and an FPGA core. The pins of the Zynq device are connected through the JTAG daisy chain. The Zynq device debugging board and the development software are connected through the JTAG daisy chain.

10. A directed configuration system for implementing a Zynq device FPGA core according to claim 7, characterized in that: When configuring the FPGA core on a Zynq device, the generated .bit or .bin file is downloaded to the FPGA through the JTAG interface.

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