SYSTEM AND METHOD FOR GENERATING NETWORK-ON-CHIP (NoCs)

Abstract

The present disclosure relates to systems and methods for generating a network-on-chip (NoC). Systems and methods implemented by a generation and synthesis tool for a network, such as a network-on-chip (NoC), are disclosed. The tool receives input from a user, or as a data file, or through a graphical user interface (display). The tool generates the NoC from a set of physical constraints and performance constraints. The tool generates a NoC that includes all elements, which is legal and meets constraints. The tool also receives as input performance scenarios or performance requirements that can be used to convert existing topologies to meet newly added requirements. The resulting output represents a network satisfying the demand, such as a NoC.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application Serial No. 63 / 542,552, filed on October 4, 2023, by Amir CHARIF et al., entitled “SYSTEM AND METHOD FOR GENERATION OF NETWORKS-ON-CHIP(NoC)” and U.S. Patent Application 18 / 907,582, filed on October 6, 2024, the entire disclosures of which are incorporated herein by reference. Technical Field

[0003] The present technology is in the field of electronic design tools and, more specifically, is related to the generation of Network-on-Chip (NoC). Background Art

[0004] Multiprocessor systems have been implemented in systems on chips (SOCs) that communicate through one or more networks on chips (NoCs). The SOC includes instances of intellectual property (IP) that communicate using the NoC. Examples of IP include initiators and targets. The initiator sends data (which may be a transaction) to the target. The transaction is sent from the initiator to one or more targets in the form of a data packet using an industry standard protocol. The initiator, connected to the NoC through a network interface unit (NIU), sends a request transaction to the target, using an address to select the target. The NoC decodes the address and transmits the request from the initiator to the target. The target processes the transaction and sends a response transaction, which is transmitted back to the initiator by the NoC. The NoC is an example of a scalable communication architecture designed for the SOC. When using a NoC in a design application, it is more desirable to eliminate conditions that cause network deadlocks. It is currently known to route messages through an array of data processing nodes to facilitate multiple paths to the destination without messages being delayed by routing deadlocks. An important aspect of designing a dedicated NoC is to achieve more ideal deadlock-free operation using minimal power and area overhead. There are two main types of deadlocks known to occur in NoCs. The first type of deadlock is a routing dependency deadlock. The second type of deadlock is a message dependency deadlock.

[0005] For a given set of performance requirements, such as connectivity and delay between source and destination, frequency of various components, maximum area available for NoC logic, minimum throughput between source and destination, location of components attached to the NoC on the floor plan, creating an optimal NoC that meets all requirements with the least amount of logic and wires is a complex task. It is usually the job of a chip architect or chip designer to create an optimal NoC, which is a difficult and time-consuming task. In addition to this being a difficult task, the design of the NoC is usually modified every time the requirements change, such as a modification of the chip floor plan or a modification that affects the expected performance. Therefore, this task needs to be redone frequently during the design time of the chip. This process is very time-consuming, which leads to production delays. Therefore, a system and method are needed to efficiently generate a NoC from a set of constraints listed as requirements and a set of component inputs. The system needs to produce a NoC that meets the constraints and all of its components are placed on the floor plan of the chip.

[0006] There are currently problems during NoC synthesis of new connections in an existing NoC because reusing existing topology is challenging and the production costs associated with wires are expensive. One problem that exists is verifying that the existing NoC provides enough bandwidth to accommodate the many communication scenarios given as input. Another problem is the lack of tools that can automatically configure the NoC in an optimal way to ensure that it has enough bandwidth to accommodate the many communication scenarios that can be given as input.

[0007] Another problem exists when synthesizing NoC topologies (even if all performance scenarios are known at the beginning), the configuration process cannot guarantee to find a solution that supports running many user-provided performance scenarios. A newly created NoC (generated by topology synthesis, or manually) may not support the load of the scenario generated.

[0008] Another problem is that when designers provide performance requirements to a NoC generation tool or topology synthesis process by defining a set of scenarios (a set of communications occurring in parallel at a given speed) to drive the shape of the topology using performance constraints, the definition is difficult and time consuming, and it is difficult to input all the scenarios required to obtain a specific traffic distribution.

[0009] Another problem that arises when performing environmental NoC synthesis occurs after a specification change. For example, when a new connection is added, the previous results will be overwritten. Therefore, a method for designing a NoC is needed that avoids both routing dependency deadlocks and message dependency deadlocks and is integrated with the topology synthesis phase of the NoC design flow. Considering the deadlock avoidance problem during topology synthesis can achieve a more ideal NoC design compared to traditional methods, in which the deadlock avoidance problem is managed separately. In addition, it is necessary to add new connections without overwriting previous results. Summary of the invention

[0010] According to various embodiments and aspects of the present invention, a system and method for generating a network on chip (NoC) is invented, which uses a set of constraints and inputs to produce or generate a NoC whose all elements satisfy the defined constraints while avoiding deadlock. The elements of the NoC are placed on the floor plan of the chip. The advantage of the present invention is that the design process and the work of the chip architect or designer are simplified. Another advantage is a NoC generation or synthesis method with incremental design, by which the NoC is generated or synthesized one connection at a time. . In particular, a set of nodes of a source-destination pair and each new connection are synthesized by taking the set of existing connections as input. When synthesizing a new connection to define a network route from a source to a destination, new components can be created, including but not limited to switches and / or links. Within the scope of the present invention, the destination includes but is not limited to a list of components to be passed through. In addition, configuring the newly created components, including but not limited to clock and / or data width, is an important aspect when synthesizing new connections. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A shows a logical view of a network on chip (NoC) including various elements that create a NoC;

[0012] Figure 1B shows a NoC with elements placed on a network floor plan;

[0013] Figure 2A A method for generating a NoC description based on a set of constraints according to various aspects and embodiments of the present invention is shown;

[0014] Figure 2B A block diagram of a NoC synthesis tool according to various aspects and embodiments of the present invention is shown;

[0015] Figure 3 A graphical view of a chip floor plan with blocking areas and NoC interface locations according to various aspects and embodiments of the present invention is shown;

[0016] Figure 4 shows a connection table of a NoC according to various aspects and embodiments of the present invention;

[0017] Figure 5 A scenario table with throughput definitions for read transactions and write transactions according to various aspects and embodiments of the present invention is shown;

[0018] Figure 6 shows the creation of a network with 3 traffic classes according to various aspects and embodiments of the present invention;

[0019] Figure 7A method of manufacturing a 3D image processing apparatus having a merger and a splitter according to various aspects and embodiments of the present invention is shown. Figure 6 Decomposition of the network;

[0020] Figure 8 The present invention is shown in various aspects and embodiments Figure 6 A roadmap of the network in a starter's floor plan;

[0021] Fig. 9 The present invention is shown in various aspects and embodiments Figure 6 A roadmap of a target in the floor plan of the network;

[0022] Fig.10 It is shown that according to various aspects and embodiments of the present invention, the master node splitter is decomposed into Figure 8 The roadmap for physically distributed cascade splitters;

[0023] Fig.11 The main node merger is decomposed into Fig. 9 A roadmap of physically distributed cascade combiners;

[0024] Fig.12 An example of two nodes approaching and merging according to various aspects and embodiments of the present invention is shown;

[0025] Fig.13 illustrates a NoC topology on a floor plan with deadlock-free segment and turn networks according to various aspects and embodiments of the present invention;

[0026] Fig.14A illustrates a NoC topology on a plan view with split segments "S" to "D" according to various aspects and embodiments of the present invention;

[0027] Fig. 14B illustrates a NoC topology on a floor plan with a split segment "S" to "D" updated to use two new sub-segments "S" to "N" and "N" to "D" according to various aspects and embodiments of the present invention;

[0028] Fig. 14C Illustrated is a NoC topology on a floor plan with sub-segments "N" and "S" merged into split segments according to various aspects and embodiments of the present invention;

[0029] Fig.14D illustrates a NoC topology on a planar graph having a sub-segment represented by a channel between a node "N" and a node "S" that is bifurcated into split segments according to various aspects and embodiments of the present invention;

[0030] Fig.15 is a flow chart illustrating a method for single-connection NoC topology synthesis processing according to various aspects and embodiments of the present invention;

[0031] Fig.16A illustrates a NoC topology on a planar graph with a request to connect a node "S" to a node "D" according to various aspects and embodiments of the present invention;

[0032] Fig. 16B illustrates an incremental synthesis result with a routing configuration from "S" to "D" according to various aspects and embodiments of the present invention, a NoC topology on a floor plan with a new ingress segment, a new internal segment, and an existing egress segment;

[0033] Fig.17A Illustrated is a NoC topology on a floor plan with a communication strategy 1700 that optimizes wire length with best-effort performance according to various aspects and embodiments of the present invention;

[0034] Fig. 17B illustrates a NoC topology on a floor plan for a communication strategy 1710 for communication with low latency according to various aspects and embodiments of the present invention;

[0035] Fig.18A illustrates an incremental composition mode 1800 for initial setup of a segment connecting from node "S" to node "D" according to various aspects and embodiments of the present invention;

[0036] Fig.18B illustrates an incremental synthesis mode 1810 for physical invariance of segments with minimally varying parameters in accordance with various aspects and embodiments of the present invention;

[0037] Fig. 18C illustrates an incremental synthesis mode 1820 for logical invariance of segments with optimized topology and preserved configured parameters in accordance with various aspects and embodiments of the present invention;

[0038] Fig.18D illustrates an incremental synthesis mode 1830 for network element variability with optimized topology and adapted configured parameters according to various aspects and embodiments of the present invention; and

[0039] Fig.19 The NoC synthesis process based on mesh custom subnet description according to various aspects and embodiments of the present invention is illustrated.

[0040] Fig. 20 A process for checking a NoC configuration according to various aspects and embodiments of the present invention is illustrated.

[0041] Fig.21The configuration process of the NoC according to various aspects and embodiments of the present invention is illustrated.

[0042] Fig. 22 Table illustrating various scenarios for connecting using NoC according to various aspects and embodiments of the present invention.

[0043] Fig.23 The process of physical placement input of a design tool according to various aspects and embodiments of the present invention is illustrated.

[0044] Fig.24 A process with clock constraint input to a design tool according to various aspects and embodiments of the present invention is illustrated.

[0045] Fig.25 The input process of the design tool according to various aspects and embodiments of the present invention is illustrated.

[0046] Fig.26 A portion of a NoC topology between IP blocks sharing a segment is illustrated.

[0047] Fig. 27 The diagram illustrates the changes according to various aspects and embodiments of the present invention. Fig. 20 Steps in the process of sharing segments.

[0048] Fig.28 The diagram illustrates the changes according to various aspects and embodiments of the present invention. Fig. 20 Steps in the process of sharing segments.

[0049] Fig.29 The diagram shows the changes according to various aspects and embodiments of the present invention. Fig. 20 Steps in the process of sharing segments.

[0050] Fig.30 The diagram shows a NoC topology in which a network segment is shared by several initiators to reduce wire costs.

[0051] Fig.31 A graphical user interface of a topology generation tool with shared created and labeled segments according to various aspects and embodiments of the present invention is illustrated.

[0052] Fig.32 A possible scenario of a NoC used by a topology generation tool according to various aspects and embodiments of the present invention is illustrated.

[0053] Fig.33 The diagram illustrates new channels created in the topology of a NoC by a topology generation tool according to various aspects and embodiments of the present invention. DETAILED DESCRIPTION

[0054] The following describes various examples of various aspects and embodiments of the present technology. In general, the examples can use the described aspects in any combination. All statements of the principles, aspects and embodiments and their particular examples herein are intended to cover both their structural equivalents and functional equivalents. Additionally, it is intended that such equivalents include both currently known equivalents and equivalents to be developed in the future, i.e. any element that performs the same function as developed, regardless of structure.

[0055] It should be noted that, as used herein, the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. Throughout the specification, references to "one aspect", "aspects", "some aspects", "various aspects", or similar language mean that a particular aspect, feature, structure, or characteristic described in connection with any embodiment is included in at least one embodiment of the present invention.

[0056] The phrases "according to one or more embodiments," "in an embodiment," "in at least an embodiment," "in an embodiment," "in certain embodiments," and similar language that appear throughout the specification may, but do not necessarily, all refer to the same embodiment or similar embodiments. In addition, the aspects and embodiments of the invention described herein are merely exemplary and should not be construed as limiting the scope or spirit of the invention as understood by those of ordinary skill in the art. The invented invention is effectively made or used in any embodiment including any novel aspect described herein. All statements describing the principles, aspects, and embodiments of the invention herein are intended to cover both structural and functional equivalents thereof. It is intended that such equivalents include both currently known equivalents and equivalents developed in the future.

[0057] As used herein, "initiator" refers to a similar intellectual property (IP) module or unit, and these terms are used interchangeably in the scope and embodiments of the present invention. As used herein, "target" refers to a similar IP module or unit, and these terms are used interchangeably in the scope and embodiments of the present invention. As used herein, a transaction can be a request transaction or a response transaction. Non-limiting examples of request transactions include write requests and read requests.

[0058] As used herein, a node is defined as a distribution point and / or communication endpoint capable of creating, receiving and / or transmitting information through a communication path or channel. A node may refer to any of the following: a switch, a splitter, a combiner, a buffer, and an adapter. As used herein, splitters and combiners are switches; not all switches are splitters or combiners. As used herein, and in accordance with various aspects and embodiments of the present invention, the term "splitter" describes a switch having a single inlet port and multiple outlet ports. As used herein, and in accordance with various aspects and embodiments of the present invention, the term "combiner" describes a switch having a single outlet port and multiple inlet ports.

[0059] In an embodiment, the set of existing connections may be empty. Thus, the NoC will be synthesized from the beginning of the process without existing connections.

[0060] The order in which the connections are implemented can affect the quality of the topology. In an embodiment, the order can be determined based on a variety of mathematical optimization techniques and / or heuristics. For example, the order can be determined by the area of ​​the floor plan spanned by the connections. In another example, the order can be a delay-based communication strategy that is configured to measure the delay for packets to reach the destination and implement more sensitive connections with higher priority. Within the scope of the present invention, the synthesis order is an input to deterministic and incremental physical-aware NoC topology synthesis methods.

[0061] A system configured to automatically generate or synthesize a deadlock-free NoC based on a specification includes: a floor plan, i.e., a physical floor plan of a chip; technical parameters, including but not limited to wire delays and / or logic density; floor plan areas including but not limited to module and / or clock constraints; clock domain crossing (CDC) is the traversal of a signal from a first clock domain to a second clock domain in a synchronous digital circuit; performance requirements; and components having a configuration and location on the floor plan, connectivity requirements between the first component and the second component, and a communication strategy between the first component and the second component.

[0062] A method for converting an existing deadlock-free network-on-chip (NoC) configuration, the existing deadlock-free network-on-chip configuration comprising a plurality of existing physical segments and a set of existing turns allowed between the segments, the plurality of existing physical segments and the set of existing turns forming a plurality of existing routes. The method comprises generating a new NoC configuration by generating and / or synthesizing at least a first new connection into the existing deadlock-free network-on-chip configuration, the first new connection having a source and a destination, the generating creating a first new deadlock-free route from the source to the destination, whereby the new network-on-chip configuration is deadlock-free, and wherein generating the first new deadlock-free route from the source to the destination preserves the existing route.

[0063] The generating includes: for each existing route, converting the route into segments and turns; identifying one or more new connections to be synthesized, each of the multiple new connections having an undefined route, a source, and a destination associated therewith, the one or more new connections being identified along with a synthesis order; for each of the one or more new connections, identifying multiple possible routes from the source to the destination for the new connection based on the order.

[0064] Possible routes include one or more of the following: a new ingress segment connecting the source to an existing deadlock-free NoC configuration; a new egress segment connecting the existing deadlock-free on-chip network configuration to the destination; one or more new internal segments connecting existing segments of the existing deadlock-free on-chip network configuration, whereby the one or more new internal segments connect the source to the destination, wherein the new internal segment is not considered if it would form a circular dependency between segments, thereby causing a deadlock; and existing segments alone.

[0065] Filtering a plurality of possible routes based on one or more criteria, the criteria comprising: a communication policy criterion based on an allowable delay for a route from a source to a destination of a new connection; any one of a plurality of user-defined criteria; selecting one of a plurality of possible routes for synthesis; and / or synthesizing the selected possible route into an existing deadlock-free on-chip network configuration.

[0066] According to one or more embodiments of the invention, the first new deadlock-free route includes at least one of an existing physical segment and a new physical segment.

[0067] According to one or more embodiments of the invention, generating a first new deadlock-free route from a source to a destination preserves all existing routes.

[0068] According to one or more embodiments of the invention, new deadlock-free routes are generated repeatedly and incrementally.

[0069] According to one or more embodiments of the invention, identifying the composition order includes ordering the one or more new connections according to a heuristic.

[0070] According to one or more embodiments of the invention, at least a portion of an existing segment is physically immutable.

[0071] According to one or more embodiments of the present invention, at least a portion of the endpoints of the existing segments are switches. The switches are physically immutable.

[0072] According to one or more embodiments of the invention, any component is logically mutable, causing at least one existing component to be reconfigured in response to a new resulting topology.

[0073] According to one or more embodiments of the invention, selecting one of a plurality of possible routes for synthesis includes selecting a possible route that maximizes usage of an existing deadlock-free network-on-chip configuration, wherein the existing segments are physically immutable except for ingress and egress segments, the switches are physically immutable, and at least one of the network elements is logically immutable.

[0074] According to one or more embodiments of the invention, selecting one of a plurality of possible routes for synthesis includes selecting a possible route that minimizes routing delay.

[0075] According to one or more embodiments of the invention, selecting one of a plurality of possible routes for synthesis includes selecting a possible route that maximizes usage of an existing deadlock-free network-on-chip configuration, wherein existing segments are not physically immutable, switches are allowed to have new connections, and existing network elements are logically immutable, including keeping clock frequencies and other properties unchanged.

[0076] According to one or more embodiments of the invention, selecting one of a plurality of possible routes for synthesis includes selecting when existing segments are not physically immutable, switches are allowed to have new connections, and existing network elements are reconfigurable.

[0077] A method for incremental synthesis and transformation of a deadlock-free on-chip network topology includes receiving an input as a network topology, converting the network topology into an existing segment, reusing the existing segment in a new route, the existing segment being formed by a path between a first node and a second node, recursively splitting the existing segment at any geographic point along the path between the first node and the second node to form a split segment, synthesizing a new route by adding a new segment and a new turn to the split segment in response to the split, and generating a deadlock-free on-chip network topology by routing packets from the turn of the existing segment to the new segment, thereby avoiding deadlock in the network.

[0078] According to one or more embodiments of the invention, identifying the composition order includes ordering the one or more new connections according to a heuristic.

[0079] According to one or more embodiments of the invention, at least a portion of an existing segment is physically immutable.

[0080] According to one or more embodiments of the present invention, at least a portion of the endpoints of the existing segments are switches. The switches are physically immutable.

[0081] According to one or more embodiments of the invention, any component is logically mutable, causing at least one existing component to be reconfigured in response to a new resulting topology.

[0082] A non-transitory computer-readable medium for storing code that, when executed by one or more processors, causes the processor to: receive an input topology of a network on chip (NoC) to determine a source-destination pair and at least one existing connection to be selected for synthesis; transcribe the source-destination pair into a pair of segments; transcribe the at least one existing connection into a pair of existing segments; determine whether the NoC is deadlock-free; in response to determining whether the NoC is deadlock-free, extract the segment pairs that do not have defined routes and sort them using a heuristic method; input the pair of segments and the pair of existing segments into a configuration browser, the configuration browser using Determine a configuration for a route from a source to a destination of a source-destination pair using a communication strategy configured to receive user-defined parameters associated with the source-destination pair, the communication strategy communicating with a configuration filtering module configured to output qualified configurations; select a final configuration to be implemented for connecting the source-destination pair using a configuration selection module; split the pair of existing segments that need to be connected to the pair of segments at points specified by the final configuration; create a new segment determined by the final configuration; activate corresponding turns connecting the pair of existing segments to the pair of segments; and calculate a route from the source to the destination of the source-destination pair.

[0083] Reference now Figure 1A , a network on chip (NoC) 100 according to various aspects and embodiments of the present invention is shown. NoC 100 is an example of a network. According to various aspects and embodiments of the present invention, the network includes a set of nodes and a set of edges, each of which has a model and can be used in the core of the synthesis to perform and implement transformations on the network and converge to the best solution suitable for the specified requirements. NoC 100 includes nodes and endpoints, and uses assembled basic network functions such as: network interface units (NIUs) 102, 104, 106, 108, 110, 112, 130, 132 and 134, nodes / switches 114, 116, 118, 120 and 122; adapters, such as adapter 126; and buffers, such as buffer 124. NoC basic network functions use an internal transmission protocol specific to NoC 100 to communicate with each other, usually based on the transmission of data packets. NIU converts the protocol used by the attached system on chip (SoC) unit (not shown) into the transmission protocol used inside NoC 100. Switches route traffic between sources and destinations. Buffers 124 are used to insert pipeline elements to span long distances, or to store packets to handle rate adaptation between fast senders and slow receivers, or vice versa. Adapters 126 handle various conversions between data width, clock, and power domains.

[0084] Reference now Figure 1B, NoC 150 is shown with various elements, such as NIUs, switches, and blocking areas in the floor plan. NoC 150 includes various connected elements through various switches. According to one aspect of the invention, a set of constraints are used as input to the tool, which will be discussed in more detail below. According to some aspects of the invention, the tool performs a set of sub-steps and produces a description (synthesis) of the resulting NoC (such as NoC 150), with its configured elements and the location of each element on the floor plan. The generated description is used to actually implement the NoC hardware, using the generated physical information to provide guidance for the back-end implementation process.

[0085] Reference now Figure 2A According to some aspects of the invention, a set of constraints (210, 212, 214, 216 and scenarios) are provided to a synthesis tool 220. According to some embodiments and aspects of the invention, the performance and functionality of tool 220 may include third-party ASIC implementation tools, such as logic synthesis, placement and routing back-end tools, etc. A designer or user constructs the set of constraints provided to tool 220. The constraints are captured in a machine-readable form, such as a computer file that captures information using a defined format, and are understood and processed by the tool. According to one aspect of the invention, the format is XML. According to another aspect of the invention, the format is JSON. The scope of the invention is not limited by the specific format used.

[0086] Reference now Figure 2B , the tool reads a file including constraint descriptions and executes the synthesis process. According to some aspects of the invention, the synthesis process is decomposed into multiple steps. Sequencer 250 is responsible for executing each step of the process. According to some aspects of the invention, sequencer 250 of tool 220 executes a set of steps based on the constraints proposed by the user / designer. The scope of the present invention is not limited by the number and type of steps that sequencer 250 can call and execute.

[0087] Reference again Figure 2A and Figure 2BAccording to various aspects of the present invention, a designer of a network provides and defines a set of constraints, such as constraints 210, 212, 214, and 216. Sequencer 250 receives various inputs, including: input 251, including a global merger roadmap with connectivity between initiators and targets, including roadmap creation and information between each initiator and target; input 252, including traffic classification and master switch creation; input 254, including master switch decomposition into mergers and splitters; input 258, including information about the physical distribution of splitters and mergers in the roadmap; input 259, including information about edge clustering; and input 260, including information about performance-aware node clustering. According to one aspect of the present invention, sequencer 250 also receives input 262, which includes information about optimization and network reconstruction. According to one aspect of the present invention, sequencer 250 receives 264, which includes information about routing and legalization. According to various aspects and embodiments of the present invention, sequencer 250 uses all inputs 251-264 to generate a network. According to various aspects and embodiments of the present invention, sequencer 250 generates a network using a combination of inputs 251 - 264 .

[0088] According to various aspects of the invention, input 251 includes input regarding a global merge roadmap. The global merge roadmap includes an integration model that captures a global physical view of the connectivity of the free space of the floor plan and the connectivity across drivers and targets / initiators and targets. The global merge roadmap is modeled by a graph of physical nodes and canonical segments used to locate nodes. (Splitters, mergers, switches, adapters) of the network being built. The global merge roadmap is used to accelerate computation. According to various aspects of the invention, the global merge roadmap is persistent, meaning that it is data that the system exports and re-consumes in incremental synthesis and subsequent runs.

[0089] According to some aspects of the invention, input 259 includes information about edge clustering. Edge clustering is intended to minimize resources and enhance performance goals through appropriate algorithms and techniques. According to some aspects of the invention, edge clustering is combined and applied in conjunction with input 260 (node ​​clustering). Edge clustering and node clustering can be used in combination by mixing, applying them in sequence, or applying them sequentially. The advantage and goal is to expand the scope of synthesis and span a larger solution space for the network.

[0090] According to various aspects of the invention, input 262 includes information about the reconstruction. Reconstruction includes a variety of transformations and capabilities. According to some aspects of the invention, the transformation is logical because the network structure has changed. According to some aspects of the invention, the transformation is physical because there are physical changes in the network, such as moving a node to a new location. Other examples of reconstruction include: breaking up a node into smaller nodes; relocation between nodes; duplication of network subcomponents to avoid deadlock and handle congestion; and physically rerouting links to avoid congested areas or meet time constraints.

[0091] Reference now Figure 3 , according to various aspects of the present invention, a floor plan 300 of a chip on which a NoC is implemented is shown, along with the locations of various initiator interfaces and target interfaces. Physical constraints 210 provide physical information about the design, including: the size of the chip on which the NoC will be implemented; various blocking regions on the floor plan, which are rectangles representing areas of the chip where NoC logic cannot exist or be placed; free space, which is the area of ​​the chip where NoC logic can exist, defined by the area not covered by blocking; and the locations of the interfaces between the SoC units and the NoC, i.e., the locations of the initiator interfaces and the target interfaces, such as NIUs.

[0092] According to various aspects of the present invention, another constraint may also be provided that includes extensions of clock domains and power domains 212. Domains 212 include areas of the chip that allow for placement of logic belonging to a particular domain.

[0093] According to various aspects of the present invention, the capabilities of the logic library to be used to implement the NoC are provided. The information includes the size of the reference logic gates and the time required for the signal to propagate a distance of 1 mm.

[0094] Reference again Figure 2A According to various aspects of the present invention, the SoC includes multiple clock domains and multiple power domains. The clock domain is defined by all logic given a clock input. The clock input is characterized by the frequency of the clock, which is its most important parameter. The power domain is defined by all logic that obtains power from the same power supply. According to various aspects of the present invention, the power is gated, so that a power domain can be turned on or off, or isolated from other power domains. Therefore, the designer provides the set of clock domain and power domain constraints 212 as part of the initial design.

[0095] According to various aspects of the present invention, the initiator and the target are communicatively connected to the NoC. The initiator is a unit that sends requests (usually read commands and write commands). The target is a unit that serves or responds to requests, usually read commands and write commands. Each initiator is connected to or attached to the NoC through an NIU. The NIU attached to the initiator is called an initiator network interface unit (INIU). In addition, each target is attached to the NoC through an NIU. The NIU attached to the target is called a target network interface unit (TNIU). The main function of the NoC is to transmit each request from the initiator to the desired destination target, and if the request requires or expects a response, the NoC transmits the response of each target to the corresponding request initiator. Initiators and targets have many different parameters to characterize them. According to various aspects of the present invention, for each initiator and target, the clock domain and power domain to which they belong are defined. The width of the data bus they use to send write and receive read payloads is several bits. According to various aspects of the present invention, the width of the data bus for the connection (communication path to / from the target) for sending write requests and receiving write responses is also defined. Furthermore, as described herein, the clock and power domain definitions are references to the clock and power domains present in the previously described SoC.

[0096] continue Figure 2A and Figure 2B And refer to Figure 4 , a connection table 400 is shown. According to various aspects of the present invention, table 400 allows traffic to be defined by classification. The tool allows the use of traffic class labels for each connection between an initiator and a target. As shown in table 400, there are three traffic classes: L1, L2, and L3. The traffic class label is an arbitrary label selected by the user or designer. Any number of labels can be defined, and the scope of the present invention is not limited by the number of labels. Each label represents a demand for an independent network resource. If the underlying NoC technology supports it, the present invention will give each label a different subnet, which can be physically different or use a virtual network.

[0097] According to various aspects of the present invention, it is not required that an initiator be able to send requests to all targets or targets connected to the NoC. The precise definition of the targets that can receive requests from the initiator is outlined or set forth in a connection table such as table 400. The connectivity and traffic class labeling information can be represented as a matrix. There is a row for each initiator and a column for each target. If an initiator must be able to send traffic to a target, the traffic class label must appear at the intersection between the initiator row and the target column. If there is no label at the intersection, the tool does not require a connection between the initiator and the target. For example, initiator 1 (M1) communicates connectivity with target 1 (S1) using a defined label 1 (L1), while M1 does not communicate with S2 and therefore there is no label at the intersection of M1 and S2. According to various aspects of the present invention, the actual format used to represent connectivity can be different, as long as each master-slave combination has a precise definition of its traffic class, or there is no classification label if there is no connection.

[0098] Reference now Figure 5 , shows a table 500 according to various aspects of the present invention, including various situations of read (RD) and write (WR) transactions (such as Figure 2A ). Table 500 includes information defining various throughput rates provided to the tool. Scenarios define expected performance in terms of data throughput between initiators and targets. Each scenario describes the expected required read bandwidth and the expected required write bandwidth between each initiator and each target. Throughput is defined in bytes per second (B / s). A typical SoC will have multiple operating modes. As an example, a SoC for a smartphone may have a gaming operating mode, an audio call operating mode, an idle operating mode, etc. These define scenarios that rely on different throughput rates. Therefore, a set of scenarios represents different operating modes supported by the SoC and, accordingly, represents the expected NoC minimum performance in terms of throughput between initiators and targets.

[0099] The scenario can be represented as 2 matrices, one defining the read throughput and one defining the write throughput. According to various aspects of the present invention, the read throughput requirement will be used to determine the size of the response network, which processes the data returned from the target to the initiator. According to various aspects of the present invention, the write throughput requirement will be used to determine the size of the request network, which is the data from the initiator to the target. According to various aspects of the present invention, examples of throughput requirements for various scenarios are shown in Table 500. The actual format used to represent the scenario can be different, as long as each pair (initiator, target) accurately defines the minimum throughput required for reads and writes. In Table 500, a read transaction from M1 to S1 has a minimum performance throughput of 100MB / s. In Table 500, a write transaction from M1 to S1 has a minimum throughput of 50MB / s.

[0100] According to some aspects of the invention, no scenarios are defined for the tool, in which case the tool optimizes the NoC synthesis process for physical cost, such as lowest gate cost and / or lowest wire cost.

[0101] Reference now Figure 6 and Figure 2B , an initial network 600 is created according to various aspects of the present invention. The network 600 implements a connectivity matrix with the following defined parameters or components:

[0102] One network interface unit per initiator,

[0103] One network interface unit per initiator,

[0104] Create one switch for each defined traffic class, called the master switch for that class,

[0105] A switch after each initiator / master NIU to split the traffic to the different master switches that the initiator needs to reach,

[0106] There is a switch before each target / destination NIU that merges traffic from different master switches sending traffic to that target

[0107] The data width of each switch and the clock domain it belongs to is calculated using the data width of each attached interface and its clock domain as input to the tool. According to various aspects of the invention, each step of converting a network that is part of a NoC also performs calculations of the data width and clock domain of the newly created network elements.

[0108] Reference now Figure 7 and Figure 2B , showing Figure 6 A network 600 is provided, wherein the network 600 is transformed by a tool process according to various aspects of the present invention. The sequencer 250 has an input 254, which indicates that the main switch is decomposed into a merger and a splitter. The tool decomposes each main switch of the network 600 into an equivalent implementation having a splitter and a merger. According to various aspects of the present invention, some switches have a single inlet port and multiple outlet ports. According to various aspects of the present invention, some switches have multiple inlet ports and a single outlet port. The inlet port of each main switch is connected to a splitter, and each main switch outlet port is connected to a merger. For the main switches, the splitters and mergers are connected together according to a connection table.

[0109] Reference now Figure 8, a floor plan 800 is shown according to various aspects of the present invention. The sequencer 250 has an input 256 representing the creation of a roadmap between each initiator and a target. The floor plan 800 includes physical paths 802 calculated between a master interface (M0) on the floor plan and each of its connected targets (such as target S0, target S1, target S2, and target S3). Path 802 is referred to as the splitter roadmap of initiator M0; although not shown, each initiator has a splitter roadmap. The tool uses any algorithm suitable for finding a path between a source point and multiple destination points, including an algorithm that minimizes the length of the path.

[0110] Reference now Fig. 9 , the floor plan 800 calculates the physical path 902 between the target interface of the target S0 on the floor plan and each of the initiators connected to it. Path 902 is the merger roadmap of the target S0. Obviously, each target has a merger roadmap. The tool uses any algorithm suitable for finding paths between multiple source points and target points, including algorithms that minimize path length. According to various aspects of the present invention, the tool converts the network in a way that maintains its functionality and adds location information to network elements.

[0111] Reference now Fig.10 , according to various aspects of the present invention, a floor plan 800 with a path 1002 is shown. The sequencer 250 has an input 258 providing the physical distribution of splitters and mergers on the roadmap. Using this tool, each switch is decomposed into mergers and splitters. Using this tool, each splitter in a master switch is further decomposed into cascaded splitters, and each splitter in the cascade is placed at a branch point of the splitter roadmap of the attached master switch. The branch point of the roadmap is defined by the fact that a path is divided into two or more branches.

[0112] Reference now Fig.11, according to various aspects of the present invention, a floor plan 800 with a path 1102 is shown. Using the tool, for each of the combiners in the master switch, the combiner is further decomposed into a cascade of combiners, each combiner of the cascade being placed at a branching point of the combiner roadmap of the attached slave switch. The branching point of the roadmap is defined by the fact that the path is divided into two or more branches. The process of decomposing the splitters in the cascade of splitters retains the functionality of the original splitter, because the number of inputs to the cascade is still 1, and the number of outputs of the cascade is the same as the number of outputs of the original splitter. The process of decomposing the combiners in the cascade of combiners retains the functionality of the original combiner, because the number of outputs of the cascade is still 1, and the number of inputs of the cascade is the same as the number of inputs of the original combiner. According to various aspects of the present invention, the effect of this process is to obtain a set of basic switches, represented by combiners and splitters, which are physically close to the locations where actual connections are required between the switches.

[0113] According to various aspects of the invention, the tool transforms the network so as to reduce the number of wires used between switches that can be achieved while maintaining the performance defined in the scenario, i.e., a set of minimum throughputs required between initiators and targets. According to various aspects of the invention, switches are clustered for performance-aware switching, and mergers and splitters that have been distributed on a roadmap are treated like ordinary switches.

[0114] According to one aspect of the invention, the tool uses an iterative process and will merge switches while still meeting performance requirements until no more switch merges occur. The process used by the tool is described as follows:

[0115] 1) When switch fusion is no longer possible, do the following:

[0116] a) A candidate switch is selected to merge with one of its neighbors. The selection process ensures that all switches in the network are eventually candidate switches.

[0117] b) When a candidate is selected, search for neighbors to merge. The neighbor criteria is based on the evaluation of a cost function. The cost function should return the switch that is the "best fit" to merge with the candidate. The definition of "best fit" is implementation dependent, but the cost function should maximize the gain of the potential fusion of the two switches in at least one metric including: wire length; logic area, power, and performance.

[0118] c) Test whether the performance scenarios will still all meet the minimum throughput requirement if convergence occurs. If not, the two switches cannot be merged. The process performed by the tool searches for another neighbor until either no more neighbors are found, in which case all switches remain unchanged, or a neighbor is found that can be merged with the candidate switch without violating the minimum throughput requirement for all scenarios, in which case the network is modified by merging the candidate switch with that neighbor.

[0119] According to various aspects of the invention, this process can ensure that the switch does not grow beyond a certain size (maximum number of ingress ports, maximum number of egress ports). If the combined switch is above a set threshold, then merging is prevented.

[0120] Reference now Fig.12 , according to various aspects of the present invention, candidate switch SW3 is shown next to switch SW4 for the combiner. The sequencer 250 has an input 260 that provides performance-aware switch clustering. The tool performs a process of merging two switches. When switches are merged, the wires from different switches are simplified to one wire from each connected switch to the combined switch. According to various aspects of the present invention, switches SW3 and SW4 are merged. The connections between SW1 and SW4 and SW3 are merged and replaced by a single connection between SW1 and SW3_4. Therefore, long connections between distant switches are removed and reduced to a minimum, while connections between close switches are removed and completed within the switch.

[0121] Reference again Figure 2B , input 262 to sequencer 250 includes various optimizations that may be performed to further reduce the amount of wire used by the network, the area of ​​the network elements, and the power consumed by the network elements. Examples of such optimizations include: detecting links that may be removed because they are not being used, or their traffic may be rerouted; reducing the width of the link if it is wider than required by the scenario; and performing wire length optimization by finding the best placement of all switch elements that minimizes the total wire length of the network, where the total wire length of the network is the sum of the distance spanned by each connection between network elements multiplied by the width of the connection.

[0122] continue Figure 2B, the input 264 to the sequencer 250 includes generating a legal NoC by modifying the positions of the network elements so that the network elements fit into the allocated free space and do not overlap, and they exist within the corresponding clock and power domain constraints. According to various aspects of the present invention, the area occupied by each network element on the die is calculated using the information provided about the technical capabilities, such as the area of ​​the reference logic gates. The correctness of the placement of each element is then tested (the element has enough free space and no other elements overlap). If the test fails, the element is moved until a suitable position is found where the test passes.

[0123] Formal Methods

[0124] Reference now Fig.13 , the floor plan 1300 illustrates a deadlock-free NoC that can be represented by multiple segments and turns. A segment represents a directed path between two components, for example, "A" 1311 and "B" 1301, "B" 1301 and "C" 1302, "C" 1302 and "D" 1303, and / or "D" 1303 and "A" 1311. The first segment 1304 holds the physical path between "A" 1311 and "B" 1301 in the floor plan, the second segment 1305 holds the physical path between "B" 1301 and "C" 1302 in the floor plan, the third segment 1306 holds the physical path between "C" 1302 and "D" 1303 in the floor plan, and the fourth segment 1307 holds the physical path between "D" 1303 and "A" 1311 in the floor plan, which is the physical coordinate (x i ,y i ). Within the scope of the present invention, a segment has one or more associated cost metrics that can be used during synthesis and / or generation to track the cost of certain routines.

[0125] Turns as a pair of segments can be utilized in a way to avoid deadlock in the network. Given the allowed turns 1308, turns 1309 and turns 1310, the network remains deadlock-free as long as there are no loops between the segments. According to another aspect or embodiment of the present invention, loops can exist between nodes. Turns have dependencies between segments, which is a basic mechanism to ensure that the network is deadlock-free. Within the scope of the present invention, loops exist between nodes to reuse wires without causing deadlock, so that only necessary channels are allocated to prevent node loops. Therefore, this eliminates unnecessary channels and reduces the associated wire costs associated therewith.

[0126] Reference again Fig.13, the presence of the first turn 1308 from the first segment 1304 to the second segment 1305 indicates that the data packet can be routed from the first segment 1304 to the second segment 1305. The presence of the second turn 1309 from the second segment 1305 to the third segment 1306 indicates that the data packet can be routed from the second segment 1305 to the third segment 1306. The presence of the third turn 1310 from the third segment 1306 to the fourth segment 1307 indicates that the data packet can be routed from the third segment 1306 to the fourth segment 1307. With respect to segment splitting, the segment "S1" to "S2" can be routed at any point in its physical route (x i ,y i ) is split, resulting in two new segments. This network is deadlock-free because the turn (D, A) approaching (A, B) does not exist.

[0127] Reference now FIG. 14A to FIG. 14D , showing an embodiment of segment splitting on NoC 1400. Segment 1403 ( Fig.14A ) is defined by node "A" 1401 to node "B" 1402. Segment 1403 can be anywhere in its physical route (x i ,y i ) was split at 1404( Fig.14A )Chengxin Section 1409A( FIG. 14B to FIG. 14D ) and new paragraph 2, 1409B ( FIG. 14B to FIG. 14D ). FIG. 14B to FIG. 14D This split is best depicted by 1404 ( Fig.14A ) results in a newly created node "S" 1408 ( FIG. 14B to FIG. 14D ). The first turn 1405 and the second turn 1406 are shown. FIG. 14B to FIG. 14D ) and the third turn 1407.

[0128] Fig. 14B Illustrated is a segment split of a NoC topology, where the split segment "A" 1401 to "B" 1402 is updated to use two new sub-segments "A" 1401 to "S" 1408 and "S" 1408 to "B" 1402. The newly created node "S" 1408 is a new switch in the NoC. The set of turns involved in the split segment is updated to use the two new sub-segments. A new turn 1406 is added, while turn 1407 is retained.

[0129] A segment that has been split is no longer considered "as is" because the split produces sub-segments with variable routing. This recursive representation is necessary for the increment because it ensures that a segment that was part of an existing route and that may have needed to be split can still be recovered as a series of sub-segments when an existing route is rebuilt. Splitting a segment allows the segment to be connected to a new segment. This produces a new set of turns.

[0130] Fig. 14CDepicted is a new segment 1411 represented by the passage between node “N” 1410 and node “S” 1408 being merged into the split segment, resulting in a new turn 1412 .

[0131] Fig.14D A new segment 1413 represented by the passage between node "N" 1410 and node "S" 1408 is depicted as being forked into the split segment, resulting in a new turn 1414. The added node "N" 1410 may include, but is not limited to, an IP block and / or an initiator.

[0132] According to one aspect and embodiment of the present invention, the system performs a generation and synthesis process, and all existing network routes are converted into segments and turns. In an embodiment, the entire NoC is described as a set of at least one segment defined by, for example, a physical path between two nodes (S, D). According to various aspects and embodiments of the present invention, if the network is not deadlock-free, the system provides a "failure" notification and returns it to the user, because according to one or more aspects of the present invention, the network or NoC must initially be deadlock-free. The system also extracts the group of connections that do not have defined routes and / or connections that need to be synthesized. Given a heuristic, the group of extracted connections is sorted. According to various aspects and embodiments of the present invention, for each connection from a source "S" to a destination "D", a single connection synthesis process includes using a configuration browser, a configuration filtering module, a configuration selection module, splitting, creation, and routing calculation. Each newly created component, switch, and link in the configuration is configured by allocating clock domains and data width settings so that bandwidth requirements are met.

[0133] Fig.15 1500 is a flow chart illustrating a method 1500 of a NoC generator using a topology synthesis process. The input 1503A to be synthesized may be a new connection 1501 and / or the input 1503B may be an existing segment 1502. The new connection 1501 includes creating new components (such as switches and / or links) to define a network route from "S" to "D". The existing segment 1502 may be re-expressed as at least one segment and / or a pair of segments having at least one turn. The existing network has a set of turns that cannot be changed. When a new segment is added, a turn associated with the newly added segment is also added to complete the route from "S" to "D". The added turn does not generate loops and / or deadlocks with the existing turns.

[0134] The configuration browser 1504 receives input 1503A as a new connection 1501 and input 1503B as an existing segment 1502. Since there are multiple ways to connect to segment "S" to "D", the configuration browser 1504 affects the best configuration based on each segment assigned a communication strategy 1506. The configuration browser 1504 uses an exploration of legal configurations 1505 to explore different ways to connect "S" to "D". Legal configurations 1505 are a list of described parameters. The configuration browser 1504 is configured to explore and / or examine and analyze at least one possible configuration indicating a location, traversing the segment to split the segment from a list of meaningful configurations stored in memory. The configuration browser 1504 can have a configuration with a new entry segment for connecting "S" to a segment of the NoC. If "S" is already connected, it already has an entry segment. The configuration browser 1504 can have a configuration with a new exit segment for connection.

[0135] The cost of a given path is updated at each step according to the communication strategy 1506. In an example, moving within an existing segment far from the destination may have more or less cost than creating a new segment that goes directly to the destination, depending on whether the communication strategy 1506 favors wire length and / or delay. It is within the scope of the present invention to use cost updates as a way to efficiently implement several communication strategies, both to explore special segments and to identify potential future segments.

[0136] The main configuration exploration process 1504 can be designed as a specialized version of a general shortest path algorithm, including but not limited to A* and / or Dijkstra. A given step in the shortest path algorithm considers different points that can be reached from the current point. The current point is at least one point along the physical path of the existing segment. The path from the current point to the subsequent point of the current segment needs to be considered.

[0137] In an embodiment, the path may advance one step along the path of the current segment. In an embodiment, if the end of the segment path has been reached, the path may advance to the first point in the path of any next segment, such as a segment directly connected to the current segment, and the current segment can "turn" to that first point.

[0138] In an embodiment, if the destination is not connected, such as if there is no exit segment, the path can jump directly to the destination point. This is equivalent to creating a new exit segment. The new and / or future exit segments are then added to the configuration.

[0139] In yet another embodiment, the path can jump to any point in any segment as long as no circular dependency is created, the two segments have compatible communication strategies and the communication strategies allow the merge. This is equivalent to creating a new internal segment and adding it to the configuration.

[0140] Reference again Fig.15 , the configuration filtering module 1507 has a predetermined list including data, including but not limited to, which configurations are legal, which configurations cause deadlocks, and which configurations are not optimal. The configuration filtering module 1507 filters the configurations given multiple criteria, including but not limited to the criteria based on the communication strategy 1506 and / or any custom criteria, and retains only a subset. In the example of custom criteria, a user (e.g., a programmer) can determine the parameters based on the low latency defined by the shorter length between the routes from "S" to "D". The user can define the maximum length of the path. If the length of the path exceeds a user-defined threshold, the configuration filtering module 1507 of the communication strategy 1506 will remove the route. In another example, the parameter can be based on the use of the minimum number of additional wires. In another example, the parameter can be based on a cost function that tends to have the lowest cost for the route from "S" to "D". The configuration filtering module 1507 can customize the parameters predefined by the user. Users can set their own filters and discard certain types of configurations.

[0141] The first criterion is based on the communication policy 1506. The user can control the way in which new segments are created. The communication policy 1506 is a set of parameters that can be associated with any given connection in the network. The system can define multiple communication policies, and each connection can be associated with a communication policy 1506. The communication policy 1506 has parameters and flags. In the example of the flag, low latency means that the connection should be implemented in a way that minimizes the total path length from the source to the destination. In another example of the flag, enabling serialization means that the links involved in the path from the source to the destination are allowed to use serialization to save wires. For the communication policy 1506 that manages the connection, some configurations of a given connection may be illegal. Qualified configuration 1508 is a filtered version of a legal configuration. In the example, if the connection "S" to "D" is set to have a low latency communication policy, restrictions on the total length of the route and the number of hops or components passed must be applied, and configuration candidates that are not within these restrictions are discarded.

[0142] Reference again Fig.15, after filtering, the configuration filtering module 1507 outputs a qualified configuration 1508. It is desirable to select a qualified configuration performed by a configuration selection module 1509. The selection of the best configuration is achieved using the configuration selection module 1509, which retains only one final configuration as the final synthesis of connecting "S" to "D". Based on the community strategy 1506, the metric used to select the best configuration is configurable and several parameters can be considered. In an embodiment, the communication strategy parameter is the total additional wire length. The length of the additionally created segment creates the wire required to traverse the route. There is also a cost associated with the wire. A more desirable parameter is to minimize the total wire length to reduce the topological cost. In an embodiment, the communication strategy parameter is the total route length. The total length of the route is the sum of the existing segments plus the newly added segments. This parameter focuses primarily on minimizing latency. In another embodiment, the communication strategy parameter is based on bandwidth distribution. This parameter optimizes performance by focusing on the traffic distribution on the segment and the associated congestion level.

[0143] Once the best configuration 1510 is selected, the system implements 1511 the best configuration 1510 by splitting the segments involved and creating 1512 new segments and turns and applying them to the network. It is also within the scope of the present invention that the best configuration is the final configuration. When splitting a segment, the split is performed on all existing segments that need to be connected to the new segment, and the new segment is located at the point specified by the selected configuration. In terms of optimization, if the split point is within a specific distance from one end point of the segment and the end point is a switch, the end point will be reused for the connection instead of creating a new switch. This can reduce the number of switches created. Create 1512 the required new segments indicated by the selected configuration and activate the corresponding turns. The combination of the newly created 1512 segments and turns with the existing 1502 segments and turns is input into the routing tool 1513 that generates the final route 1514. Given the newly created segment, a route from "S" to "D" is calculated. The route is stored in memory. The routing tool 1513 routes the connection on the geographic plan because the segment is defined according to its geographic path following the plan.

[0144] Fig.16A A NoC topology on a floor plan with node "S" 1601 to node "D" 1602 is illustrated. If an existing network exists and a change is requested, such as a request to add a new connection from node "S" 1601 to node "D" 1602, incremental synthesis needs to be performed. IP blocks are examples of restrictions on the floor plan that routing needs to bypass. Existing nodes are connected to each other. It is desirable to create a route for the new connection in the existing network without having to make changes to the existing structure.

[0145] Fig. 16BThe diagram shows the result of incremental synthesis of a routing configuration from "S" 1601 to "D" 1602, a NoC topology on a floor plan with a new ingress segment 1603 (with node "S" 1601 and node 1606), a new internal segment 1604 (with node 1606), and an egress segment 1605. The exploration of legal configurations 1505 is shown in Fig. 16B , where an entry segment 1603 is added if the node is not already connected to the NoC. In an embodiment, the new entry segment 1603 is able to connect "S" 1601 to the segment of the NoC. If "S" 1601 is already connected to the segment of the NoC, it already has an entry segment.

[0146] exist Fig. 16B In the illustration of , egress segment 1605 exists because "D" is already connected to another node. Therefore, if "D" is already connected, it already has an egress segment. A new egress segment can be a configuration option for connecting a segment of the NoC to "D".

[0147] Reference again Fig. 16B , any number of internal segments 1604 are within the scope of the present invention. At least one and / or more new internal segments can connect existing segments in such a way that the entry segment reaches the exit segment. A connection between two existing segments will only be considered if it does not create a circular dependency between the segments, thereby ensuring that only deadlock-free configurations are considered. The synthesis can include calculating the network routing without creating any new switches and / or segments. This is the case if both "S" and "D" are connected to the network and the entry segment can already reach the exit segment given only the existing turns. An important aspect of the present invention is that this configuration can define future segments, whereby no special segments are created in the topology during the exploration phase.

[0148] In an embodiment, the system may preset multiple common communication strategies to make it easier for the user to make a selection. It is more desirable for the user to select from a preset list rather than requiring the user to create a communication strategy. Connections associated with different communication strategies will have physically separate composite routes. During the synthesis, the configuration filter module 1507 ( Fig.15 ) and configuration selection module 1509 ( Fig.15 ) depends on communication policy 1506 ( Fig.15 ) to output the optimal configuration 1510 for implementing 1511 routing.

[0149] Fig.17A A NoC topology on a floor plan is illustrated with a communication strategy 1700 that optimizes wire length for best-effort performance. Fig.17A and Fig. 17B The figure shows how the same connection can result in different implementations based on the communication strategy selected. Fig.17AIn the illustration of FIG. 1 , the focus is on connecting node "S" to node "D" and the parameter of wire length is the main criterion for optimization. The configuration selection module selects the implementation that forms the least additional wire. It is shown that the parameter requirements are met with a short entrance segment 1703 and one turn 1704 activated.

[0150] Fig. 17B A NoC topology on a floor plan with a communication strategy 1710 for low latency communication is illustrated. In this example, there is a preference for a direct connection 1713 between node "S" 1711 and node "D" 1712, rather than traversing several switches. One turn 1714 activated is near "D". Although this configuration requires more additional wires and is more costly, the path chosen by the user from "S" to "D" has the shortest length.

[0151] Figure 1 to Fig. 17B best illustrates the basic method of incrementally synthesizing new connections while reusing existing segments, and Figures 20 to 33 Additional features are shown. According to some embodiments, the tool splits existing segments to fork new segments. At the end of the process, only the newly created components (such as clock and / or data width) are configured while existing components remain unchanged. Fig.15 , existing segments and turns 1502 are controlled by the user at an incremental level to change. The user utilizes communication policies 1506 to control not only the creation and selection of new segments in the network, but also to modify existing topologies or segments. In the example, it may be undesirable to reuse existing segments in new routes due to performance considerations or due to previous optimizations that the user may have implemented, and based on the segments that remain unchanged. When splitting a segment, a hop may be added to traverse multiple routes, which may not be the result we expect. Therefore, the system defines a number of incremental levels or modes that are based on the physical variability of the segments, the physical variability of the switches, and the logical variability of the network elements. In the presence of an existing NoC topology, it is more desirable to capture the user's intent when synthesizing a set of new connections.

[0152] In an alternative embodiment, incremental synthesis mode allows the user to customize how the existing topology is changed.

[0153] Regarding the physical mutability of a segment, by default a segment is mutable. The segment can be split to fork out new segments. For example, if it is not expected to add a switch to an existing route, the user can make the segment immutable.

[0154] Regarding the physical mutability of the switch, if the endpoint is a switch, a new segment can be connected to an existing endpoint of an immutable segment. If it is not desired to modify the physical size of the switch, the switch can be immutable so that no new segments can be connected to the immutable switch.

[0155] Referring now to the logical variability of network elements, by default, existing network elements (including but not limited to data width and / or distributed clocks) are not reconfigured by the incremental synthesis process. Only newly created switches and adapters are configured. This can lead to inefficient configurations, such as insufficient bandwidth and / or excessive clock domain crossings. Any component can be marked as logically variable to allow existing components to be reconfigured, giving new resulting topologies. In an example of how to define preset incremental synthesis modes in a system based on the aforementioned concepts, three preset modes are discussed.

[0156] Fig.18A An incremental synthesis mode 1800 is illustrated for the initial setup of a segment connecting from node "S" 1801 to node "D" 1802. The high bandwidth segment 1803 and the low bandwidth segment 1804 traverse the existing NoC topology routing. During the initial setup, user parameters will determine how to change the existing topology to connect "S" 1801 to "D" 1802.

[0157] Fig.18B An incremental synthesis pattern 1810 of physical invariance of a segment with minimally changed parameters is illustrated. The segment is split 1811 to fork 1812 a new segment, and a U-turn is created in the deadlock-free network to connect "S" 1801 to "D" 1802 with minimal changes. The high bandwidth segment 1803 is unchanged to prevent splitting, and the low bandwidth segment 1804 traverses the existing NoC topology route.

[0158] It is more desirable to preserve the maximum amount of existing topology. All segments are physically immutable except for the ingress and egress segments, as the ingress and egress segments are required to implement new connections. All switches are physically immutable and all network elements are logically immutable. In the example, if a segment from "S" 1801 to "D" 1802 is marked as immutable, it will prevent the splitting of the segment and facilitate routing around existing segments. Therefore, the existing segments remain unchanged.

[0159] Fig. 18C An incremental synthesis pattern 1820 for logical immutability of segments with optimized topology and preserved configuration parameters is illustrated. A low bandwidth 1804 segment is split 1821 and a new segment 1822 is forked, and a new turn is created to connect "S" 1801 to "D" 1802. The high bandwidth is not fully utilized because it is connected to the lower bandwidth and the switches cannot be changed. It is more desirable to change some switches to adapt. This preset allows existing segments to be split and allows switches to have new connections to achieve a more optimized topology. Therefore, better costs can be achieved by reusing existing elements. Existing network elements can be made logically immutable to keep, for example, clock frequencies, clocks assigned to switches, and / or other properties unchanged.

[0160] Fig.18D Illustrated is an incremental synthesis mode 1830 for network element variability with optimized topology and adapted configured parameters. A high bandwidth 1803 segment is split 1831 and a new segment 1832 is forked, and a new turn is created to connect "S" 1801 to "D" 1802. The high bandwidth is fully utilized because after the switch is replaced, it is connected to the higher bandwidth. Greater flexibility in the synthesis process can be achieved when all segments can be split, switches can be connected to new segments, and / or components can be reconfigured if reconfiguring them improves the results, for example, when changing clocks to improve performance.

[0161] Fig.19 The NoC synthesis process based on a mesh custom subnet description is illustrated. First, mesh segments are generated and placed on the requested space in an optimal manner. Second, the new mesh segments, now treated as pre-existing segments by the incremental synthesis process, are opportunistically used to generate the final routes when appropriate. The result is a topology that mixes the automatically generated regular mesh topology with the new optimal synthesized segments. In a fully connected system, each node 1901 of the NoC 1900 is connected to every other node. Zones 1902 are designated for the 3×3 mesh using the XY routing algorithm. As a result of the synthesis process 1903, the NoC 1905 uses the requested mesh segments and the newly synthesized segments. The automatically synthesized local tree 1904 is shown. The mesh is generated and optimally placed within the designated zone 1906.

[0162] According to other aspects of the present invention, an extension of the clock and power domains on a plan view is provided, and each component is tested to ensure that it is within the boundaries of the specified clock and power domains. If the test fails, the component is moved until a suitable position is found where the test passes. Once a suitable position is found for each component, the routing of each connection between the components is completed. The routing process will find a suitable path for a set of wires that connect between the components. After the routing is completed, the cross-distance pipeline element is inserted on the link as needed, based on how long it takes for the signal to transmit a distance of 1mm, using the information provided about the relevant technical capabilities.

[0163] According to some aspects and embodiments of the present invention, the tool generates one or more computer files describing the generated NoC, including:

[0164] List of network elements and their configuration: data width, clock domain.

[0165] The location of each generated network element on the floor plan.

[0166] The set of routes through the network elements that enable connectivity.

[0167] According to aspects of the invention, a route is an ordered list of network elements, one for each pair (initiator, target) and one for each pair (target, initiator). A route indicates how traffic between pairs will flow and through which elements.

[0168] According to various aspects of the present invention, the tool is used to generate metrics about the generated NoC, such as: wire length distribution histogram, number of switches, switch size histogram.

[0169] Reference now Figure 20 to Figure 25 , according to various aspects of the present invention, the tool automatically assigns clock and data widths to each of the network nodes so that all input constraints (performance, physical clock zones, etc.) are met.

[0170] According to various aspects of the invention, the tool is capable of selecting clock and data widths from a range of clock speeds and data widths selected according to input constraints of network parameters. Thus, the automatic selection includes a machine learning model that uses feedback to improve the selection of artificial intelligence.

[0171] Various inputs 2000 are provided to the tool's checker 2010. At step 2020, the checker 2010 determines whether the current configuration is legal. The analysis performed by the checker is outlined herein and includes a review of constraints and parameters to ensure that the configuration is legal.

[0172] Performance scenarios are given at the transaction level (i.e., high-level communication speeds between components). The process automatically converts them into bandwidth requirements for each network segment. For example, according to various aspects of the present invention, the tool machine learning model can identify bandwidth requirements and receive feedback to improve automatic selection. According to various aspects of the present invention, the tool includes a constraint solver 2110 that is used to generate an optimal configuration that adheres to one or more of the following parameters or criteria:

[0173] 1) Cost (wires, energy)

[0174] 2) Number of adapters (clock domain crossing, packet width adapters, etc.)

[0175] According to various aspects of the invention, the tool includes a process for checking whether the existing NoC topology can accommodate a given high-level transaction scenario by verifying that the current configuration is legal in step 2020. According to various aspects of the invention, if the performance check fails, segments without sufficient bandwidth are highlighted so that the designer or user can take action. Information collected from the performance check can also be provided to a machine learning model as feedback to an artificial intelligence (AI) machine implemented as part of the tool.

[0176] According to various aspects of the invention, the tool receives as input a high-level specification of the transactions that constitute running applications (scenarios) to ensure that each application can run individually at a desired speed.

[0177] Special References Fig. 22 According to various aspects of the present invention, the tool interprets scenarios, such as those shown. From the high-level transactions discovered in the scenarios, the tool can infer the actual amount of bandwidth required for each element of each involved network. According to various aspects of the present invention, the tool receives transactions that can be multi-phase and can consume control and / or data BW in multiple networks. According to various aspects of the present invention and as a non-limiting example, a read transaction in a non-consistent scenario generates a request in the requesting network (generally 1, but can also be multiple cycles) and generates multiple data in the responding network (multiple cycles). According to various aspects of the present invention, for each transaction, a list of affected networks is automatically inferred, and the bandwidth requirements of each network component (node ​​and segment) are generated accordingly. According to various aspects of the present invention, the tool performs legal configuration generation. Therefore, for each node, given the bandwidth requirements, current placement, clock physical constraints, the tool:

[0178] 1) Infer the possible configurations (clock + data widths) that may be applied to the node; and

[0179] 2) Expressed as a set of constraints, rather than an exhaustive list.

[0180] According to various aspects of the invention, the tool selects the best configuration. The tool uses a constraint solver when searching for the best legal configuration. The constraint solver is used to minimize the cost using a heuristic method that takes as input the following, including but not limited to at least one or more:

[0181] The cost of clock adapters (e.g., clock domain changes between two nodes) to minimize area;

[0182] Conductor length (lower data width preferred);

[0183] Power consumption (choose a slower clock when legal); and

[0184] Technical parameters,

[0185] According to various aspects of the invention, the tool converts high-level transaction speed requirements into bandwidth annotations for segments in several networks of a NoC. According to various aspects of the invention, the tool considers clock tree propagation constraints (the floor plan regions where a given clock can reside) to filter out illegal configurations. According to various aspects of the invention, the tool uses a constraint solver to not only optimize wire cost and performance, but also reduce the number of required adapters (including clock domain crossings).

[0186] Special References Figure 26 to Figure 29 , according to various aspects of the invention, the tool includes a process for configuring elements of a newly created NoC (generated by topology synthesis or manually created), including clock allocation and data width allocation, to meet performance goals provided by a user in the form of a set of performance scenarios.

[0187] See also Fig.26 , the scenario shown in the figure requires the middle network segment to maintain 6GB / s bandwidth, which is not achievable even if both switches are assigned to the fastest clock in the design. The tool provides an incremental topology synthesis process, which allows the user to provide performance requirements later in the design process, after the topology has been created. To achieve this, the tool includes a method to convert existing topologies to meet the newly added bandwidth requirements.

[0188] According to various aspects of the invention, the tool identifies segments that cannot meet bandwidth requirements. A segment is a segment between two switches, and a segment may already have several channels that include different communications. For each such segment, the tool creates an additional channel for the segment. According to various aspects of the invention, the tool uses a conservative number of channels, such as one channel for each communication traveling through the segment. The tool can optimize the distribution of communications through the network segment (routes) on the new channels so that:

[0189] Each channel will carry as many communication packets as possible and use as much bandwidth as possible;

[0190] Each performance scenario is satisfied with the current routing assignments; and

[0191] New routing packets do not introduce new deadlocks (by merging routes that were previously separated into different existing channels).

[0192] Special References Fig. 27 According to various aspects of the present invention, the tool generates the illustrated route redistribution. Thus, as routes are redistributed across all offending segments, the switch's internal arbiter is changed, sometimes removing the need to maintain the switch. With particular reference to Fig.28 ,The tool detects the real arbitrators inside the remaining switches and splits the switches with multiple disjoint arbitrators or removes the switches that no longer have arbitrators.

[0193] Due to the addition of new channels and the removal / splitting of switches, the shape of the topology has changed, so the current physical placement is no longer considered optimal. According to various aspects of the present invention, the tool calls global placement to find a suitable placement for the newly modified topology. In the non-limiting example provided, Fig.29 The new placement is shown in .

[0194] According to various aspects of the invention, the tool uses the configuration process outlined herein in order to configure the remaining switches. For newly created channels, a valid configuration is guaranteed to be found as long as the scenario provided by the user is valid.

[0195] According to various aspects of the present invention, the tool can incrementally add new channels to the topology (after initial topology synthesis) to maintain specified bandwidth scenarios. According to various aspects of the present invention, the tool can redistribute routes on new channels to minimize the number of required channels without introducing new deadlocks. According to various aspects of the present invention, after route redistribution, the tool can split and delete switches that no longer serve arbitration purposes. According to various aspects of the present invention, the tool can recall data width and clock configuration processes and adjust them as needed. According to various aspects of the present invention, the tool globally adjusts the placement plan on the placement plan. According to various aspects of the present invention, the tool includes a machine learning model that can receive feedback for further training the model.

[0196] According to various aspects of the invention, the tool includes a topology synthesis process, where a topology is initially created by ignoring the provided performance scenarios and focusing on optimizing wire costs, to which the tool applies the above-described topology transformation process to support the performance scenarios in the second phase. This speeds up the NoC generation or topology synthesis process by considering one requirement at a time. In addition, by focusing first on optimizing wire routing and global lengths, the tool ensures that any segments that can be merged have already been merged at the time of initial synthesis, and that only paths that require more bandwidth are ultimately replicated.

[0197] Special References Figure 30 to Figure 33 According to various aspects of the present invention, the tool allows a user to provide performance requirements for the topology synthesis process by defining a set of scenarios, where a scenario is a set of communications occurring in parallel at a given speed. While this makes it possible to use performance constraints to drive the shape of the topology, it can be difficult and time consuming to define and enter all the scenarios required to obtain a specific traffic distribution. To alleviate this problem, the tool introduces a new process that allows the user to select a traffic pattern from a list of predefined patterns and apply it to a set of connections. The tool then automatically generates the scenarios required for the set. According to various aspects of the present invention, a user provides or creates a business class for a set of connections and selects a business model for the business class from a list of predefined business models. The tool generates all scenarios for each business class that has a business model from the set of connections included in the business class.

[0198] Fig.30An example topology is shown in . A topology 3000 is shown that includes a segment 3010 shared between several initiators 3020 to reduce line costs. In one non-limiting example, a user wants to ensure that selected initiators 3020 and targets can communicate at the full available bandwidth at the same time, which is equivalent to having a central crossbar switch in terms of bandwidth.

[0199] Specific reference Fig.31 , showing a screenshot of a table 3100 where a user can simply define traffic classes for these connections. A new traffic class named "CROSSBAR" 3110 is created and set to use the "PreserveBandwidth" traffic mode to ensure that the bandwidth is equal to that of a full crossbar switch. In accordance with some aspects of the invention, the name assigned to the new traffic class can be any name defined by the user. In accordance with various aspects of the invention, the tool then automatically uses the input (i.e., traffic class and bandwidth) to generate a set of scenarios. In accordance with some aspects of the invention, the tool uses a machine learning model to generate the set of scenarios. Each possible set of simulated and simultaneous communications is treated as a separate scenario in which each active input / output pair in the "virtual" crossbar switch communicates at maximum bandwidth, as shown in FIG. Fig.32 As shown in the figure. While there are many different possible scenarios, once these scenarios are defined, the tool performs a topology synthesis process and the tool is able to incrementally modify the topology to maintain the required bandwidth based on a specific scenario (such as scenario 1 or scenario 2). The tool makes changes to the network as needed to achieve the defined performance requirements.

[0200] Fig.33 A topology 3300 is shown that represents topology 3000 and includes channels 3310 for modifying certain segments that were previously shared. According to various aspects of the invention, the tool creates channels 3310 in previously shared segments. Channels 3310 are inserted to meet performance requirements identified by the tool, thereby maximizing the performance of the network using additional channels. According to various aspects of the invention, the tool can apply this process to any set of traffic patterns, not just the crossbar example. According to various aspects of the invention, the tool can receive feedback from a user or input from an adversarial machine learning model that is used to further train the tool's machine learning model.

[0201] According to another aspect of the invention, the tool automatically inserts various adapters and buffers in the network. The tool inserts adapters based on the required adaptation between two elements with different data widths, different clock and power domains. The tool inserts buffers based on scenarios and detected rate mismatches.

[0202] According to some aspects and embodiments, the tool may be used to ensure that multiple iterations of synthesis are performed for incremental optimization of a NoC, including when one of the constraints provided to the tool is information about a previous run.

[0203] After the synthesis process is performed by the software, the result is produced in a machine-readable form, such as a computer file that captures the information using a well-defined format. An example of such a format is XML, and another example of such a format is JSON. The scope of the present invention is not limited by a particular format.

[0204] Some aspects of the present invention employ an incremental approach to network synthesis. This incremental approach is useful in many situations. For example, in some embodiments, the incremental process begins with a standard and clean floor plan. In these and other embodiments, some of which have been discussed above,

[0205] According to some aspects and embodiments, a connection can have a communication policy that specifies, for example, the sensitivity of the connection to latency.

[0206] Certain methods according to various aspects of the present invention may be performed by instructions stored on a non-transitory computer-readable medium. The non-transitory computer-readable medium stores code including instructions that, if executed by one or more processors, will cause a system or computer to perform the steps of the methods described herein. Non-transitory computer-readable media include: rotating magnetic disks, rotating optical disks, flash random access memory (RAM) chips, and other mechanically movable or solid-state storage media. According to various examples, any type of computer-readable medium is suitable for storing code including instructions.

[0207] Certain examples have been described herein, and it will be noted that different combinations of different components from different examples are possible. The highlighted features are for better explanation of the examples; however, it is apparent that certain features may be added, modified and / or omitted without changing the characteristic aspects of the examples described.

[0208] Various examples are methods of using one or a combination of behaviors in a machine. Method examples are complete anywhere in the world where most of the constituent steps appear. For example, according to various aspects and embodiments of the present invention, IP elements or units include: a processor (e.g., a CPU or GPU), a random access memory (RAM-e.g., off-chip dynamic RAM or DRAM), a network interface for wired or wireless connection, such as Ethernet, WIFI, 3G, 4G Long Term Evolution (LTE), 5G and other wireless interface standard radios. The IP may also include various I / O interface devices required for different peripherals, such as touch screen sensors, geolocation receivers, microphones, speakers, Bluetooth peripherals, and USB devices (such as keyboards and mice, etc.). By executing instructions stored in RAM devices, the processor performs the steps of the methods described herein.

[0209] Some examples are one or more non-transient computer-readable media arranged to store such instructions for the methods described herein. Any machine holding a non-transient computer-readable medium including any necessary code can implement the examples. Some examples can be implemented as: a physical device such as a semiconductor chip; a hardware description language representation of the logical or functional behavior of such a device; and one or more non-transient computer-readable media arranged to store such hardware description language representations. The description of the principles, aspects, and embodiments described herein covers both structural equivalents and functional equivalents thereof. The elements described herein as coupled have an effective relationship that can be realized by direct connection or indirectly with one or more other intermediate elements.

[0210] Those skilled in the art will recognize many modifications and variations. Modifications and variations include any relevant combination of the disclosed features. The description of the principles, aspects, and embodiments described herein encompasses both structural equivalents and functional equivalents thereof. Elements described herein as "coupled" or "communicatively coupled" have an effective relationship that can be achieved by direct or indirect connection, using one or more other intermediate elements. Embodiments described herein as "communicating with another device, module, or element" include any form of communication or link, and include effective relationships. For example, a wired connection, wireless protocol, near field protocol, or RFID can be used to establish a communication link.

[0211] To the extent that the terms "including," "includes," "having," "has," "with" or variations thereof are used in the detailed description and claims, such terms are intended to be inclusive in a manner similar to the term "comprising."

[0212] Therefore, the scope of the present invention is not limited to the exemplary embodiments shown and described herein. Rather, the scope and spirit of the present invention is implemented by the appended claims.

Claims

1. A tool for generating a network-on-chip (NoC) topology using performance constraints, wherein the tool comprises a non-transitory computer-readable medium for storing code that, when executed by one or more processors, causes the tool to: receiving traffic classifications identified for a plurality of connections between an initiator and a target; receiving a set of traffic patterns selected from a plurality of predefined traffic patterns; analyzing a set of connections between the initiator and the target to generate a plurality of scenarios based on the set of connections included in the traffic classification; as well as The plurality of scenarios are used to change the NoC using each of the plurality of scenarios to incrementally modify the NoC while maintaining the performance constraints.

2. The tool of claim 1, wherein the plurality of predefined traffic patterns are generated by the tool based on the traffic classification and initiator-to-target pairs.

3. The tool of claim 1 further causing modification of at least one segment of at least one connection selected from the set of connections to include generating parallel communication paths. The tool of claim 1 , wherein the set of connections includes performance requirements for each connection.

5. The tool of claim 1, wherein the performance constraints include clock requirements and bandwidth requirements.

6. The tool according to claim 1, wherein the tool: identifying at least one channel placed in at least one segment; and The NoC is incrementally modified using the at least one channel to produce a legal configuration of the NoC that meets performance requirements.

Images