Low-cost thermal method for vehicle host SOC chip

Abstract

The present invention discloses a low-cost thermal method for a vehicle-mounted host SOC chip, which relates to the technical field of vehicle-mounted chip optimization. The low-cost thermal method includes the following steps: S1: SOC chip analysis: Analyze the SOC chip through a QFD analysis system, identify the key factors that affect the junction temperature of the SOC chip, score each factor in the form of a quality house, and obtain the important proportion of each factor; S2: Key factor screening: Select the top four factors with the most important proportions as the key factors through the data reflected in the quality house, and label the selected key factors respectively; S3: Key factor model design: including DOE simulation model grouping design, removal of insignificant factors, response surface analysis and response optimization. Thus, through experimental design analysis and screening of key factors, multiple groups of experiments are conducted on the key factors, and judgment is made through experimental data and generated charts, so as to obtain the optimal solution that meets various coefficients of the radiator for the purpose of reducing costs.

Description

Technical Field

[0001] The present invention relates to the technical field of vehicle-mounted chip optimization, and in particular to a low-cost thermal method for a vehicle-mounted host SOC chip. Background Art

[0002] With the improvement of the functions and working frequency of the vehicle-mounted host, the thermal power consumption also increases. Therefore, many chips need to be designed with a heat dissipation structure to dissipate heat so that the junction temperature of the chip is lower than the allowed value (or a certain level below). The previous designs were basically for stability and size, which sought to reduce the working junction temperature of the chip to the greatest extent, use a larger heat sink, and a larger heat dissipation area. However, this led to an increase in the overall cost and weight of the product, resulting in a waste of resources and increased costs, and reduced competitiveness. Summary of the invention

[0003] The present invention aims to solve one of the technical problems in the related art at least to a certain extent.

[0004] To this end, the purpose of the present invention is to propose a low-cost thermal method for a vehicle-mounted host SOC chip, analyze and screen key factors through experimental design, conduct multiple groups of experiments on key factors, and make judgments through experimental data and generated charts to obtain the optimal solution that meets various radiator coefficients with the purpose of reducing costs.

[0005] To achieve the above object, the present invention proposes a low-cost thermal method for a vehicle-mounted host SOC chip, and the low-cost thermal method comprises the following steps:

[0006] S1: SOC chip analysis: Analyze the SOC chip through the QFD analysis system, identify the key factors that affect the junction temperature of the SOC chip, score each factor in the form of quality house, and obtain the important proportion of each factor;

[0007] S2: Key factor screening: Based on the data reflected in the quality house, the top four factors with the highest importance ratio are selected as key factors, and the selected key factors are labeled respectively;

[0008] S3: Key factor model design: including DOE simulation model grouping design, removal of insignificant factors, response surface analysis and response optimization;

[0009] DOE simulation model group design: Use Minitab Statistical Software design system to create factor design: "two-level full factorial" + 1 center point for experimental design, and use CAE software for simulation to generate 9 combinations of key factors, thereby obtaining different experimental data;

[0010] The test items include: standard sequence (C1), operating sequence (C2), center point (C3), block group (C4), heat sink width (C5), heat sink thickness (C6), thermal conductivity of thermal conductive silicone (C7) and junction temperature (C8);

[0011] Remove insignificant factors: Generate a bar chart with the above test data, remove insignificant interaction factors one by one through the effect bar chart, analyze the obtained factors and generate a factor analysis chart;

[0012] Generate a bar chart for the test data and perform linear analysis and factor interaction analysis. The linear analysis and factor interaction analysis are analyzed from the aspects of degree of freedom, Adi ss, Adi ms, F value and P value respectively to obtain the regression analysis results of junction temperature (Y). According to the analysis results, it is judged whether it is necessary to add test points. If it is not necessary to add test points, the response surface analysis is directly performed according to the above analysis results. Otherwise, the test points are added to obtain new test data and perform response surface analysis.

[0013] Determine whether the marked line in the factor numerator diagram is bent. If the marked line is not bent, the test ends; if it is bent, the test continues;

[0014] Response surface analysis: Based on the above test, add test points to update the test plan and obtain new test plans and results, and compare the obtained results with the above test. Generate probability graphs and histograms for the test data and combine the main effect graphs and interactions to judge the analysis results of each key factor;

[0015] Modify the original design: add axis points, conduct experiments centered on the surface, generate new bar charts based on the test results, and obtain response surface analysis results by summarizing the model of coded coefficients, variance analysis, regression equations expressed in uncoded units, and fitting diagnostics of abnormal observations;

[0016] Response optimization: Make response optimization adjustments based on costs through the response optimizer.

[0017] The low-cost heat reduction method of the vehicle-mounted host SOC chip of the present invention analyzes and screens key factors through experimental design, conducts multiple groups of experiments on the key factors, and makes judgments through experimental data and generated charts to obtain the optimal solution that meets various coefficients of the radiator with the purpose of reducing costs.

[0018] In addition, the low-cost heating method of the vehicle host SOC chip proposed in the application may also have the following additional technical features:

[0019] Specifically, the four groups of key factors screened out are: heat sink width (X1), heat sink thickness (X2), thermal conductivity of thermal conductive silicone (X3) and thermal conductive silicone thickness (X4).

[0020] Specifically, the test codes for the radiator width (X1), radiator thickness (X2), thermal conductivity of thermal conductive silicone (X3) and thermal conductive silicone thickness (X4) are: A, B, C, D; and the test parameters are: A: 2 levels, B: 2 levels, C: 2 levels, D: 1 level.

[0021] Specifically, the factors grouped by the DOE simulation model include heat sink width (X1), heat sink thickness (X2), and thermal conductivity of thermal conductive silicone (X3), and the minitale design system is a "two-level full factorial" + one center point simulation design.

[0022] Specifically, the confidence level of the test parameter is 0.05, and the P value of the factor is less than 0.05, which is a normal value.

[0023] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0025] Figure 1 This is a block diagram of the low-cost thermal principle of the present invention;

[0026] Figure 2 Design principle block diagram for the key factor model of the present invention;

[0027] Figure 3 Analyze the House of Quality diagram for the QFD system of the present invention;

[0028] Figure 4 is a Pareto diagram of the effect of the present invention;

[0029] Figure 5 A Pareto diagram of the standardized effect of the present invention;

[0030] Figure 6 This is the main effect diagram of junction temperature of the present invention;

[0031] Figure 7 A Pareto diagram of the standardized junction temperature effect of the present invention;

[0032] Figure 8 This is the junction temperature residual diagram of the present invention;

[0033] Fig. 9 This is the main effect diagram of the junction temperature fitting mean of the present invention;

[0034] Fig.10 It is the junction temperature fitting mean interaction diagram of the present invention;

[0035] Fig.11 It is the response optimization diagram of the present invention;

[0036] Fig.12 Create a new response optimization graph for the present invention. DETAILED DESCRIPTION

[0037] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and are not to be construed as limitations of the present invention. On the contrary, embodiments of the present invention include all changes, modifications and equivalents that fall within the spirit and connotation of the appended claims.

[0038] The following describes a low-cost heat reduction method for a vehicle-mounted host SOC chip according to an embodiment of the present invention in conjunction with the accompanying drawings.

[0039] like Figure 1-12 As shown, the low-cost heating method of the vehicle host SOC chip of the embodiment of the present invention comprises the following steps:

[0040] S1: SOC chip analysis: Analyze the SOC chip through the QFD analysis system, identify the key factors that affect the junction temperature of the SOC chip, score each factor in the form of a quality house, and obtain the important proportion of each factor. The quality house is as follows: Figure 3 shown.

[0041] S2: Key factor screening: Based on the data reflected in the quality house, the top four factors with the highest importance ratio are selected as key factors, and the selected key factors are labeled respectively;

[0042]

[0043] S3: Key factor model design: including DOE simulation model grouping design, removal of insignificant factors, response surface analysis and response optimization;

[0044] DOE simulation model group design: Use Minitab Statistical Software design system to create factor design: "two-level full factorial" + 1 center point for experimental design, and use CAE software for simulation to generate 9 combinations of key factors, thereby obtaining different experimental data;

[0045] The test items include: standard sequence (C1), operating sequence (C2), center point (C3), block group (C4), heat sink width (C5), heat sink thickness (C6), thermal conductivity of thermal conductive silicone (C7) and junction temperature (C8);

[0046] Design Summary:

[0047] Factor: 3

[0048] Basic design: 3,8

[0049] Number of trials: 9

[0050] Replicates: 1

[0051] Block: 1

[0052] Center point (total): 1

[0053] Test data table:

[0054]

[0055] Remove insignificant factors: Generate a bar chart with the above test data, remove insignificant interaction factors one by one through the effect bar chart, analyze the obtained factors and generate a factor analysis chart. The analysis chart is as follows: Figure 4 and Figure 5 As shown;

[0056] Furthermore, the project uses the basic structure of V-shaped aluminum plate radiator, the heat dissipation is characterized by area, and the material selection is mainly based on thickness.

[0057] Since the cross section is a regular shape, length is used instead of area to simplify the process. The area change caused by thickness change is too small and therefore ignored.

[0058] ANOVA table:

[0059] source Degrees of Freedom Adj SS Adj MS F-number P-value Model 6 26.0386 4.3398 1735.91 0.001 Linear 3 25.1868 8.3956 3358.24 0.000 Radiator width X1 1 6.6248 6.6248 2649.92 0.000 Radiator thickness X2 1 18.1202 18.1202 7248.08 0.000 Thermal conductivity of thermal conductive silicone 1 0.4418 0.4418 176.72 0.006 Factor Interactions 2 0.1556 0.0778 31.12 0.031 Radiator width X1 Radiator thickness X2 1 0.1458 0.1458 58.32 0.017 Radiator thickness X2 Thermal conductivity of thermal conductive silicone X3 1 0.0098 0.0098 3.92 0.186 bending 1 0.6962 0.6962 278.48 0.004 error 2 0.0050 0.0025 total 8 26.0436

[0060] Factor confirmation: Figure 4 and Figure 5 As shown in , insignificant interaction factors are removed one by one to generate a new analysis graph.

[0061] Generate a bar chart for the test data and perform linear analysis and factor interaction analysis. The linear analysis and factor interaction analysis are analyzed from the aspects of degree of freedom, Adi ss, Adi ms, F value and P value respectively to obtain the regression analysis results of junction temperature (Y). According to the analysis results, it is judged whether it is necessary to add test points. If it is not necessary to add test points, the response surface analysis is directly performed according to the above analysis results. Otherwise, the test points are added to obtain new test data and perform response surface analysis.

[0062] 2-level factor analysis results table:

[0063] source Degrees of Freedom Adj SS Adj MS F-number P-value Model 5 26.0288 5.2058 1055.22 0.000 Linear 3 25.1868 8.3956 1701.81 0.000 Radiator width X1 1 6.6248 6.6248 1342.86 0.000 Radiator thickness X2 1 18.1202 18.1202 3673.01 0.000 Thermal conductivity of thermal conductive silicone 1 0.4418 0.4418 89.55 0.003 Factor Interactions 1 0.1458 0.1458 29.55 0.012 Radiator width X1 Radiator thickness X2 1 0.1458 0.1458 29.55 0.012 bending 1 0.6962 0.6962 141.12 0.001 error 3 0.0148 0.0049 total 8 26.0436

[0064] Through the above 2-level factor analysis result table and Figure 6 The junction temperature (Y) regression analysis is performed on the diagram in Figure 1. After removing the insignificant terms, the result is:

[0065] 1. P value < 0.05, all factors are significant;

[0066] 2. The center point P is less than 0.05. Combined with the factor diagram, X3 may be curved, so it is necessary to add test points and perform response surface analysis.

[0067] Determine whether the marked line in the factor numerator diagram is bent. If the marked line is not bent, the test ends; if it is bent, the test continues;

[0068] The above test shows that there is bending, so the number of tests is increased. The new test plan and results are as follows:

[0069]

[0070] Response surface analysis: Based on the above test, add test points to update the test plan and obtain new test plans and results, and compare the obtained results with the above test. Generate probability graphs and histograms for the test data and combine the main effect graphs and interactions to judge the analysis results of each key factor;

[0071] Response surface analysis conclusion: The model passed the diagnosis

[0072] 1, P value < 0.05, the factor is significant

[0073] 2. R-sq and R-sq (adjusted) are better

[0074] 3. The residual is normal

[0075] Encoded coefficients table:

[0076]

[0077] Model summary table:

[0078] S R-sq R-sq(adjustment) R-sq(prediction) 0.0546214 99.94％ 99.88％ 99.70％

[0079] ANOVA table:

[0080] source Degrees of Freedom Adj SS Adj MS F-number P-value Model 7 33.7827 4.8261 1617.60 0.000 Linear 3 31.8643 10.6214 3560.07 0.000 Radiator width X1 1 8.2992 8.2992 2781.71 0.000 Radiator thickness X2 1 23.0129 23.0129 7713.41 0.000 Thermal conductivity of thermal conductive silicone 1 0.5522 0.5522 185.10 0.000 square 3 1.7725 0.5908 198.04 0.000 Radiator Width Radiator Width 1 0.0901 0.0901 30.21 0.000 Radiator thickness Radiator thickness 1 0.8568 0.8568 287.17 0.001 Thermal conductivity of thermally conductive silicone Thermal conductivity of thermally conductive silicone 1 0.0296 0.0296 9.91 0.000 Factor Interactions 1 0.1458 0.1458 48.87 0.0162 Radiator width X1 Radiator thickness X2 1 0.1458 0.1458 48.87 0.000 error 7 0.0209 0.0030 0.000 total 14 33.8036

[0081] The regression equation expressed in uncoded units:

[0082] Junction temperature (Y) = 124.285-0.478 radiator width-7.993 radiator thickness-0.248 thermal conductivity of thermal conductive silicone + 0.005201 radiator width × radiator width + 1.6034 radiator thickness × radiator thickness + 0.01716 thermal conductivity of thermal conductive silicone × thermal conductivity of thermal conductive silicone + 0.03750 radiator width × radiator thickness.

[0083] Fitting and diagnostics for unusual observations:

[0084] Observations Junction temperature (Y) Fitted values Residual Standardized residuals 1 111.600 111.674 -0.074 -2.01R

[0085] like Figure 8 and Fig. 9 The response surface analysis results are shown as follows:

[0086] 1. Through probability graph and histogram, it basically meets the normal distribution;

[0087] 2. The upper and lower vibration amplitudes of the fitting graph are similar and meet the requirements;

[0088] 3. The sequence diagram has no rules and meets the requirements;

[0089] Conclusion: The residual plot meets the requirements.

[0090] Combining the main effects plot and the interaction plot yields:

[0091] Heat sink width, heat sink thickness and thermal conductivity are negatively correlated with junction temperature;

[0092] The thermal conductivity of thermally conductive silicone has a lower influence on the junction temperature than the heat sink: about 0.5°C;

[0093] The radiator width and radiator thickness are interactively negatively correlated;

[0094] When the heat sink thickness is less than 1.4 mm, the negative correlation has a more significant effect on the junction temperature.

[0095] Modify the original design: add axis points, conduct experiments centered on the surface, generate new bar charts based on the test results, and obtain response surface analysis results by summarizing the model of coded coefficients, variance analysis, regression equations expressed in uncoded units, and fitting diagnostics of abnormal observations;

[0096] Response optimization: Make response optimization adjustments based on costs through the response optimizer.

[0097] Parameter table:

[0098] response Purpose Lower limit Target Upper limit Weight Importance Junction temperature (Y) Minimum 106.3 111.6 1 1

[0099] untie:

[0100] untie Radiator Width Radiator thickness Thermal conductivity of thermal conductive silicone Junction temperature fitting value Composite desirability 1 32 2 7 106.348 0.990964

[0101] Multiple Response Prediction:

[0102]

[0103] Conclusion: The optimal solution is obtained when the radiator width is 32mm, the radiator thickness is 2mm, and the thermal conductivity of the thermal conductive silicone is 7W / m·K.

[0104] Make response optimization adjustments based on cost, and set the junction temperature to no higher than 109℃. The values ​​and descriptions of X1, X2, and X3 are as follows:

[0105] X1- Radiator width = 26mm X2- Radiator thickness = 1.4mm X3- Thermal conductivity of thermal conductive silicone = 2W / m·K

[0106] 1. The thermal conductivity of X3-thermal conductive silicone is selected as 2W / m·K;

[0107] 2. X2-The influence of heat sink thickness on junction temperature is more significant when it is less than 1.4. The closest thickness specification under orientation is 1.2mm

[0108] 3. X1- radiator width. When the junction temperature is 108.9782℃, drag the ruler to get X1 to 25.6157mm, which is rounded to 26mm.

[0109] The low-cost heat treatment method of the vehicle-mounted host SOC chip of the present invention, ... (Beneficial Effects).

[0110] In addition, the low-cost heating method of the vehicle host SOC chip proposed in the application may also have the following additional technical features:

[0111] Specifically, the four groups of key factors screened out are: heat sink width (X1), heat sink thickness (X2), thermal conductivity of thermal conductive silicone (X3) and thermal conductive silicone thickness (X4).

[0112] Specifically, the test codes for the radiator width (X1), radiator thickness (X2), thermal conductivity of thermal conductive silicone (X3) and thermal conductive silicone thickness (X4) are: A, B, C, D; and the test parameters are: A: 2 levels, B: 2 levels, C: 2 levels, D: 1 level.

[0113] Specifically, the factors grouped by the DOE simulation model include heat sink width (X1), heat sink thickness (X2), and thermal conductivity of thermal conductive silicone (X3), and the minitale design system is a "two-level full factorial" + one center point simulation design.

[0114] Specifically, the confidence level of the test parameter is 0.05, and the P value of the factor is less than 0.05, which is a normal value.

[0115] In summary, the low-cost thermal method for the vehicle-mounted host SOC chip of the embodiment of the present invention analyzes and screens key factors through experimental design, conducts multiple groups of experiments on the key factors, and makes judgments based on the experimental data and generated charts to obtain the optimal solution that meets various radiator coefficients with the purpose of reducing costs.

[0116] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and deform the above embodiments within the scope of the present invention.

Claims

1. A low-cost heat reduction method for a vehicle-mounted host SOC chip, characterized in that: The low-cost heating method includes the following steps: S1: SOC chip analysis: Analyze the SOC chip through the QFD analysis system, identify the key factors that affect the junction temperature of the SOC chip, score each factor in the form of quality house, and obtain the important proportion of each factor; S2: Key factor screening: Based on the data reflected in the quality house, the top four factors with the highest importance ratio are selected as key factors, and the selected key factors are labeled respectively; S3: Key factor model design: including DOE simulation model grouping design, removal of insignificant factors, response surface analysis and response optimization; DOE simulation model group design: Through the Minitab Statistical Software design system, create a factor design: "two-level full factorial" + 1 center point for experimental design, and use CAE software for simulation to generate 9 combinations of key factors to obtain different experimental data; The test items include: standard sequence (C1), operating sequence (C2), center point (C3), block group (C4), heat sink width (C5), heat sink thickness (C6), thermal conductivity of thermal conductive silicone (C7) and junction temperature (C8); Remove insignificant factors: Generate a bar chart with the above test data, remove insignificant interaction factors one by one through the effect bar chart, analyze the obtained factors and generate a factor analysis chart; Generate a bar chart for the test data and perform linear analysis and factor interaction analysis. The linear analysis and factor interaction analysis are analyzed from the aspects of degree of freedom, Adi ss, Adi ms, F value and P value respectively to obtain the regression analysis results of junction temperature (Y). According to the analysis results, it is judged whether it is necessary to add test points. If it is not necessary to add test points, the response surface analysis is directly performed according to the above analysis results. Otherwise, the test points are added to obtain new test data and perform response surface analysis. Determine whether the marked line in the factor numerator diagram is bent. If the marked line is not bent, the test ends; if it is bent, the test continues; Response surface analysis: Based on the above test, add test points to update the test plan and obtain new test plans and results, and compare the obtained results with the above test. Generate probability graphs and histograms for the test data and combine the main effect graphs and interactions to judge the analysis results of each key factor; Modify the original design: add axis points, conduct experiments centered on the surface, generate new bar charts based on the test results, and obtain response surface analysis results by summarizing the model of coded coefficients, variance analysis, regression equations expressed in uncoded units, and fitting diagnostics of abnormal observations; Response optimization: Make response optimization adjustments based on costs through the response optimizer.

2. The low-cost heat reduction method for the vehicle-mounted host SOC chip according to claim 1 is characterized in that: The four groups of key factors screened out are: radiator width (X1), radiator thickness (X2), thermal conductivity of thermal conductive silicone (X3) and thermal conductive silicone thickness (X4).

3. The low-cost heat reduction method for the vehicle-mounted host SOC chip according to claim 1 is characterized in that: The test codes for the radiator width (X1), radiator thickness (X2), thermal conductivity of thermal conductive silicone (X3) and thermal conductive silicone thickness (X4) are: A, B, C, D; the test parameters are: A: 2 levels, B: 2 levels, C: 2 levels, D: 1 level.

4. The low-cost heat reduction method for the vehicle-mounted host SOC chip according to claim 1 is characterized in that: The factors grouped by the DOE simulation model include heat sink width (X1), heat sink thickness (X2), and thermal conductivity of thermal conductive silicone (X3), and the minitale design system is a "two-level full factorial" + one center point simulation design.

5. The low-cost heat reduction method for the vehicle-mounted host SOC chip according to claim 1, characterized in that: The confidence level of the test parameter is 0.05, and the P value of the factor is less than 0.05, which is a normal value.

6. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory is used to store a computer program, and when the computer program is executed by the processor, the processor executes a low-cost thermal method for a vehicle-mounted host SOC chip as described in any one of claims 1 to 5.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium is used to store computer instructions. When the computer instructions are executed by a processor, a low-cost thermal method for a vehicle host SOC chip as described in any one of claims 1 to 5 is implemented.

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