Clock detection circuit, clock detection method and display panel

Abstract

This application belongs to the field of display driving technology, and specifically relates to a clock detection circuit, a clock detection method, and a display panel. The clock detection circuit includes: an abnormality detection module for performing abnormality detection on a first clock signal and a second clock signal and outputting corresponding abnormality detection results; a result identification module for identifying the abnormality detection results and outputting a target identification signal to a corresponding memory, so that a timing controller performs single-ended driving or double-ended driving on the display panel according to the target identification signals in all memories. When this application detects that the clock signal on any side of any row is abnormal, it can timely change the double-ended driving mode of all rows in the display panel to the single-ended driving mode at the same time, avoiding abnormal brightness between the normal row and the abnormal row, thereby solving the problem of improving the picture display effect when the clock signal for double-ended driving is abnormal.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of display driving, and particularly relates to a clock detection circuit, a clock detection method, and a display panel. Background Art

[0002] At present, the competition in the in-vehicle product segment of the panel industry is becoming increasingly fierce. Only high resolution and high PPI (Pixels Per Inch, a unit of pixel density) can make products competitive. The in-vehicle products themselves have relatively high requirements for environmental experiments. Therefore, most in-vehicle products in the panel industry use gate IC (gate integrated circuit) for driving, which has good charging effect but relatively high cost. The GDL-driven products are slightly less stable than the gate IC but have lower cost. Therefore, for high-resolution in-vehicle products, dual-end driving using GDL technology can improve pixel charging efficiency and make the image quality better.

[0003] However, in a display panel with dual-end driving using GDL technology, due to various factors, the clock signals of some pixel rows show unilateral anomalies, causing the pixel rows with anomalies to change from dual-end driving to single-end driving, while the other pixel rows are normal dual-end driving. Macroscopically, there are differences in the charging effects between the normal rows and the abnormal rows, and there are light and dark variations in brightness, and equally spaced horizontal stripe anomalies can be seen.

[0004] Therefore, how to improve the picture display effect when the clock signal of dual-end driving is abnormal is the problem to be solved by the current baseband. Summary of the Invention

[0005] The present application provides a clock detection circuit, a clock detection method, and a display panel, which solve the problem of improving the picture display effect when the clock signal of dual-end driving is abnormal.

[0006] In a first aspect, the present application provides a clock detection circuit, which is applied to a display panel with dual-end driving. The clock detection circuit includes: an anomaly detection module, the first input terminal of the anomaly detection module is connected to the first clock signal output terminal, and the second input terminal of the anomaly detection module is connected to the second clock signal output terminal, and is used for performing anomaly detection on the first clock signal and the second clock signal, and outputting corresponding anomaly detection results; a result identification module, the input terminal of the result identification module is connected to the output terminal of the anomaly detection module, the first output terminal of the result identification module is connected to the first memory, the second output terminal of the result identification module is connected to the second memory, and the third output terminal of the result identification module is connected to the third memory, and is used for identifying the anomaly detection results, and outputting target identification signals to the corresponding memories, so that the timing controller performs single-end driving or dual-end driving on the display panel according to the target identification signals in all memories.

[0007] Optionally, the anomaly detection module includes: a first transistor, a control end of the first transistor is connected to the first clock signal output end, and a first end of the first transistor is connected to the second clock signal output end; a second transistor, a control end of the second transistor is connected to the control end of the first transistor, and a first end of the second transistor is connected to a second end of the first transistor; a third transistor, a control end of the third transistor is connected to the first end of the first transistor, a first end of the third transistor is connected to the first end of the second transistor, and a second end of the third transistor is connected to the control end of the second transistor; a fourth transistor, a control end of the fourth transistor is connected to the second end of the second transistor, a first end of the fourth transistor is connected to the first end of the third transistor, and a second end of the fourth transistor is connected to the second end of the third transistor; an inverter, an input end of the inverter is connected to the control end of the third transistor, and an output end of the inverter is connected to the control end of the fourth transistor; wherein, the second end of the first transistor is the output end of the anomaly detection module.

[0008] Optionally, the first transistor and the second transistor have opposite turn-on voltages, the third transistor and the fourth transistor have opposite turn-on voltages, and the first transistor and the third transistor have the same turn-on voltage.

[0009] Optionally, the anomaly detection module further includes: a first resistor, a first end of the first resistor is connected to the second end of the first transistor, and a second end of the first resistor is grounded; a diode, an anode of the diode is connected to the first end of the first resistor; a capacitor, a first end of the capacitor is connected to the cathode of the diode, and a second end of the capacitor is grounded.

[0010] Optionally, the result identification module includes: a fifth transistor, a control end of the fifth transistor is connected to the output end of the anomaly detection module, and a first end of the fifth transistor is connected to a power supply end; a second resistor, a first end of the second resistor is connected to the second end of the fifth transistor, and a second end of the second resistor is grounded; wherein, the second end of the fifth transistor is the first output end of the result identification module.

[0011] Optionally, the result identification module further includes: a comparator, a first input end of the comparator is connected to an output end of the anomaly detection module, and a second input end of the comparator is connected to the power supply terminal; a sixth transistor, a control end of the sixth transistor is connected to an output end of the comparator, a first end of the sixth transistor is connected to the power supply terminal; a seventh transistor, a control end of the seventh transistor is connected to a second end of the fifth transistor, a first end of the seventh transistor is connected to a second end of the sixth transistor; a third resistor, a first end of the third resistor is connected to a second end of the seventh transistor, and a second end of the third resistor is grounded; wherein, the second end of the seventh transistor is a second output end of the result identification module.

[0012] Optionally, the result identification module further includes: an eighth transistor, a control end of the eighth transistor is connected to an output end of the comparator, a first end of the eighth transistor is connected to the power supply terminal; a fourth resistor, a first end of the fourth resistor is connected to a second end of the eighth transistor, and a second end of the fourth resistor is grounded; wherein, the second end of the eighth transistor is a third output end of the result identification module.

[0013] In a second aspect, the present application provides a clock detection method, which is applied to a clock detection circuit. The clock detection method includes: performing anomaly detection on a first clock signal and a second clock signal corresponding to each pixel row to obtain corresponding anomaly detection results; wherein, the anomaly detection results include a first detection result that both the first clock signal and the second clock signal are normal, a second detection result that the first clock signal is normal but the second clock signal is abnormal, and a third detection result that the first clock signal is abnormal but the second clock signal is normal; identifying the anomaly detection results and outputting a target identification signal to a corresponding memory, so that a timing controller performs single-ended driving or double-ended driving on a display panel according to the target identification signals in all memories; wherein, when the first detection result is obtained, the target identification signal is output to a first memory, when the second detection result is obtained, the target identification signal is output to a second memory, and when the third detection result is obtained, the target identification signal is output to a third memory.

[0014] In a third aspect, the present application provides a display panel, which includes: a clock generator for outputting N first clock signals and N second clock signals; a clock detection circuit respectively connected to the first clock signal output terminal and the second clock signal output terminal of the clock generator for performing anomaly detection on the first clock signal and the second clock signal; a first memory connected to the first output terminal of each clock detection circuit for receiving the target identification signals output by each clock detection circuit; a second memory connected to the second output terminal of each clock detection circuit for receiving the target identification signals output by each clock detection circuit; a third memory connected to the third output terminal of each clock detection circuit for receiving the target identification signals output by each clock detection circuit; M cascaded first GDL circuits, each first GDL circuit being respectively connected to the first clock signal output terminal of the clock generator and the first end of the corresponding scan line in the display panel for outputting the corresponding gate driving signal under the action of the first clock signal; M cascaded second GDL circuits, each second GDL circuit being respectively connected to the second clock signal output terminal of the clock generator and the second end of the corresponding scan line in the display panel for outputting the corresponding gate driving signal under the action of the second clock signal; a timing controller respectively connected to the first memory, the second memory, the third memory, the first GDL circuit and the second GDL circuit for controlling the first GDL circuit and the second GDL circuit to be turned on or off according to the target identification signals in all the memories.

[0015] Optionally, controlling the first GDL circuit and the second GDL circuit to be turned on or off according to the target identification signals in all the memories includes: when there are N target identification signals in the first memory, turning on both the first GDL circuit and the second GDL circuit simultaneously; when there is at least one target identification signal in the second memory, turning off the second GDL circuit; and when there is at least one target identification signal in the third memory, turning off the first GDL circuit.

[0016] The technical solution provided by the present application has at least the following beneficial effects:

[0017] In this application, an anomaly detection module is used to detect anomalies in the clock signals at both ends of the display panel, and a result identification module classifies and stores the anomaly detection results in different memories, enabling the timing controller to perform single-ended or double-ended driving of the display panel based on the target identification signals in all memories. Therefore, when this application detects an anomaly in any side clock signal of any row, it can promptly change the double-ended driving mode of all rows in the display panel to the single-ended driving mode simultaneously, avoiding abnormal brightness between the normal rows and the abnormal rows, thereby solving the problem of improving the picture display effect in the case of anomalies in the double-ended driving clock signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings herein are incorporated into and constitute a part of this specification, showing embodiments consistent with the present disclosure and, together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0019] Figure 1 The figure shows a schematic structural diagram of a clock detection circuit provided by an embodiment of this application.

[0020] Figure 2 The figure shows a schematic circuit diagram of a clock detection circuit provided by an embodiment of this application.

[0021] Figure 3 The figure shows a schematic diagram of a signal waveform provided by an embodiment of this application.

[0022] Figure 4 The figure shows another schematic diagram of a signal waveform provided by an embodiment of this application.

[0023] Figure 5 The figure shows yet another schematic diagram of a signal waveform provided by an embodiment of this application.

[0024] Figure 6 The figure shows a schematic flowchart of a clock detection method provided by an embodiment of this application.

[0025] Figure 7 The figure shows a schematic structural diagram of a display panel provided by an embodiment of this application.

[0026] DESCRIPTION OF REFERENCE NUMERALS

[0027] 100, clock detection circuit; 110, anomaly detection module; 120, result identification module; 200, first clock signal output terminal; 300, second clock signal output terminal; 400, first memory; 500, second memory; 600, third memory;

[0028] T1, the first transistor; T2, the second transistor; T3, the third transistor; T4, the fourth transistor; T5, the fifth transistor; T6, the sixth transistor; T7, the seventh transistor; T8, the eighth transistor; R1, the first resistor; R2, the second resistor; R3, the third resistor; R4, the fourth resistor; U1, the inverter; U2, the comparator; D1, the diode; C1, the capacitor; VCC, the power supply terminal; Vo1, the first output terminal; Vo2, the second output terminal; Vo3, the third output terminal. Detailed implementation manners

[0029] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more complete and comprehensive, and will fully convey the concept of the example embodiments to those skilled in the art.

[0030] In addition, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of this application. However, those skilled in the art will realize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of this application.

[0031] The present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted here that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present application and should not be construed as limiting the present application.

[0032] In a first aspect, the present application provides a clock detection circuit, which specifically includes the following embodiments:

[0033] Figure 1 The following shows a schematic structural diagram of a clock detection circuit provided by an embodiment of the present application; as Figure 1As shown in the figure, the clock detection circuit 100 includes: an abnormality detection module 110 and a result recognition module 120; specifically, the first input terminal of the abnormality detection module 110 is connected to the first clock signal output terminal 200, and the second input terminal of the abnormality detection module 110 is connected to the second clock signal output terminal 300, which is used to perform abnormality detection on the first clock signal and the second clock signal and output the corresponding abnormality detection result; optionally, the input terminal of the result recognition module 120 is connected to the output terminal of the abnormality detection module 110. The first output terminal Vo1 of the result recognition module 120 is connected to the first memory 400, the second output terminal Vo2 of the result recognition module 120 is connected to the second memory 500, and the third output terminal Vo3 of the result recognition module 120 is connected to the third memory 600, which is used to recognize the abnormality detection result and output a target recognition signal to the corresponding memory, so that the timing controller performs single-ended driving or double-ended driving on the display panel according to the target recognition signals in all memories.

[0034] In this embodiment, the clock detection circuit 100 is applied to a double-ended driven display panel. Double-ended driving means using two GDL circuits to drive the same scan line in the display panel, and each GDL circuit needs to generate a corresponding gate driving signal according to a clock signal; therefore, the first clock signal can be the clock signal for driving the right side of the scan line, and the second clock signal can be the clock signal for driving the left side of the scan line.

[0035] In addition, it should be noted that according to the GDL cascade relationship, a clock signal can sequentially drive multiple non-adjacent GDL circuits. This application does not elaborate on the corresponding relationship between GDL, scan lines, and clock signals, but only performs abnormality detection on each pair of clock signals (the first clock signal and the second clock signal); under normal circumstances, the waveforms of the first clock signal and the second clock signal should be exactly the same; in addition, for the case of N pairs of clock signals, N clock detection circuits 100 can be used for simultaneous detection, or one clock detection can be used to sequentially detect N pairs of clock signals.

[0036] Here, the abnormality detection process for a pair of clock signals is specifically described: the abnormality detection results in this embodiment include a first detection result that both the first clock signal and the second clock signal are normal, a second detection result that the first clock signal is normal but the second clock signal is abnormal, and a third detection result that the first clock signal is abnormal but the second clock signal is normal; that is to say: when the abnormality detection module 110 detects that both the first clock signal and the second clock signal are normal signals, it outputs the first detection result; when the abnormality detection module 110 detects that the first clock signal is a normal signal while the second clock signal is an abnormal signal, it outputs the second detection result; when the abnormality detection module 110 detects that the first clock signal is an abnormal signal while the second clock signal is a normal signal, it outputs the third detection result.

[0037] Next, the result recognition module 120 recognizes the anomaly detection result and outputs a target recognition signal to the corresponding memory; specifically: if the result recognition module 120 recognizes that the anomaly detection result output by the anomaly detection module 110 is the first detection result, it outputs the target recognition signal to the first memory 400 through the first output terminal Vo1; if the result recognition module 120 recognizes that the anomaly detection result output by the anomaly detection module 110 is the second detection result, it outputs the target recognition signal to the second memory 500 through the second output terminal Vo2; if the result recognition module 120 recognizes that the anomaly detection result output by the anomaly detection module 110 is the third detection result, it outputs the target recognition signal to the third memory 600 through the third output terminal Vo3.

[0038] Finally, the timing controller can perform single-ended driving or double-ended driving on the display panel according to the target recognition signals in all memories; specifically, perform double-ended driving according to the target recognition signal in the first memory 400, perform right-end driving according to the target recognition signal in the second memory 500, or perform left-end driving according to the target recognition signal in the third memory 600.

[0039] It can be seen from this that in this application, the anomaly detection module 110 performs anomaly detection on the clock signals at both ends of the display panel, and the result recognition module 120 classifies and stores the anomaly detection results in different memories, so that the timing controller performs single-ended driving or double-ended driving on the display panel according to the target recognition signals in all memories; therefore, when the clock signal on any side of any row in this application is abnormal, the double-ended driving mode of all rows in the display panel is immediately changed to the single-ended driving mode, avoiding abnormal brightness between the normal row and the abnormal row, thereby solving the problem of improving the picture display effect when the clock signal for double-ended driving is abnormal.

[0040] Figure 2 The figure shows a circuit schematic diagram of a clock detection circuit provided by an embodiment of this application; as Figure 2As shown, the anomaly detection module 110 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and an inverter U1. Among them, the control terminal of the first transistor T1 is connected to the first clock signal output terminal 200, and the first terminal of the first transistor T1 is connected to the second clock signal output terminal 300. The control terminal of the second transistor T2 is connected to the control terminal of the first transistor T1, and the first terminal of the second transistor T2 is connected to the second terminal of the first transistor T1. The control terminal of the third transistor T3 is connected to the first terminal of the first transistor T1, the first terminal of the third transistor T3 is connected to the first terminal of the second transistor T2, and the second terminal of the third transistor T3 is connected to the control terminal of the second transistor T2. The control terminal of the fourth transistor T4 is connected to the second terminal of the second transistor T2, the first terminal of the fourth transistor T4 is connected to the first terminal of the third transistor T3, and the second terminal of the fourth transistor T4 is connected to the second terminal of the third transistor T3. The input terminal of the inverter U1 is connected to the control terminal of the third transistor T3, and the output terminal of the inverter U1 is connected to the control terminal of the fourth transistor T4. The second terminal of the first transistor T1 is the output terminal of the anomaly detection module 110.

[0041] In one embodiment, the turn-on voltages of the first transistor T1 and the second transistor T2 are opposite, the turn-on voltages of the third transistor T3 and the fourth transistor T4 are opposite, and the turn-on voltages of the first transistor T1 and the third transistor T3 are the same. Optionally, the first transistor T1 and the third transistor T3 are P-type MOS transistors, and the second transistor T2 and the fourth transistor T4 are N-type MOS transistors. Optionally, the first transistor T1 and the third transistor T3 are N-type MOS transistors, and the second transistor T2 and the fourth transistor T4 are P-type MOS transistors.

[0042] In one embodiment, the anomaly detection module 110 further includes: a first resistor R1. The first terminal of the first resistor R1 is connected to the second terminal of the first transistor T1, and the second terminal of the first resistor R1 is grounded. Among them, the first resistor R1 functions as a pull-down resistor, so that when the anomaly detection module 110 outputs a low level, the voltage at the output terminal can be pulled down.

[0043] In one embodiment, the anomaly detection module 110 further includes a diode D1 and a capacitor C1. The anode of the diode D1 is connected to the first terminal of the first resistor R1. The first terminal of the capacitor C1 is connected to the cathode of the diode D1, and the second terminal of the capacitor C1 is grounded. Among them, the diode D1 has a rectifying function, and the capacitor C1 has a filtering function, so that the anomaly detection module 110 outputs a stable DC voltage.

[0044] For example: Here, taking the first transistor T1 and the third transistor T3 as P-type MOS transistors, and the second transistor T2 and the fourth transistor T4 as N-type MOS transistors as an example, the working principle of the anomaly detection module 110 will be described in detail with reference to the waveform diagram:

[0045] 1. As Figure 3 shown, when both the first clock signal CKL_R and the second clock signal CKL_L are normal square wave waveforms, the following two cases are described:

[0046] (1) When the high levels in the square waves output by the first clock signal CKL_R and the second clock signal CKL_L are present, high levels are input to the control terminals of the first transistor T1 and the third transistor T3, causing the first transistor T1 and the third transistor T3 to be cut off; at the same time, a high level is input to the control terminal of the second transistor T2, and the second transistor T2 conducts; in addition, the high level of the second clock signal is converted into a low level after passing through the inverter U1, causing the fourth transistor T4 to be cut off and the second terminal of the second transistor T2 to be at a low level, so that the conducting second transistor T2 outputs a low level and the rectifier diode D1 is cut off; that is to say: when both the first clock signal and the second clock signal are at high levels, the abnormality detection module 110 outputs a low level, as Figure 3 the Va waveform in. In addition, it should be noted that since the capacitor C1 has an energy storage function, there is a voltage, but this voltage is small and is equivalent to a low level.

[0047] (2) When the low levels in the square waves output by the first clock signal CKL_R and the second clock signal CKL_L are present, a low level is input to the control terminal of the second transistor T2, causing the second transistor T2 to be cut off; at the same time, low levels are input to the control terminals of the first transistor T1 and the third transistor T3, and the first transistor T1 and the third transistor T3 conduct; in addition, the low level of the second clock signal is converted into a high level after passing through the inverter U1, causing the fourth transistor T4 to conduct, so that the conducting first transistor T1, third transistor T3, and fourth transistor T4 all output low levels; that is to say: when both the first clock signal and the second clock signal are at low levels, the abnormality detection module 110 still outputs a low level, as Figure 3 the Va waveform in.

[0048] 2. As Figure 4As shown, when the first clock signal CKL_R is a normal square wave signal and the second clock signal CKL_L is an abnormal signal; it should be noted that when the sine wave is regarded as an abnormal wave in an embodiment, and the reference starting points of the sine wave and the square wave are the same, both starting from the low level point of the square wave, and the potential of the sine wave is higher than that of the square wave; therefore, when the first clock signal CKL_R is at the normal square wave low level L, the second clock signal CKL_L being an abnormal sine wave is regarded as the high level H; this embodiment is only used as a comparison example, and other waveforms can also be used as abnormal waves as long as they are not the same as the normal square wave signal; thus, it can be seen that when the first clock signal is at the low level L and the second clock signal is at the high level H, the first transistor T1 conducts and outputs a high level. At the same time, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all cut off, so that there is a relatively high potential at the anode end of the diode D1, and the first end of the capacitor C1 outputs a first high level (for example, 4.6V); that is to say: when the first clock signal CKL_R is a normal square wave waveform and the second clock signal CKL_L is an abnormal waveform, the abnormality detection module 110 outputs a first high level H1, as Figure 4 the Va waveform in

[0049] 3. As Figure 5 shown, when the first clock signal CKL_R is an abnormal sine wave and the second clock signal CKL_L is a normal square wave, then when the second clock signal CKL_L is at the low level L and the first clock signal CKL_R is at the high level H, the first transistor T1 is cut off. At the same time, the second transistor T2, the third transistor T3, and the fourth transistor T4 all conduct to output a high level to the anode end of the diode D1, and the conduction of the diode D1 causes the first end of the capacitor C1 to output a second high level (for example, 8.7V); it should be noted that compared with the situation in the above point 2, there is a superposition of two conduction paths at the anode of the diode D1, and the voltage value of the second high level is greater than that of the first high level; that is to say: when the first clock signal CKL_R is an abnormal sine wave and the second clock signal CKL_L is a normal square wave, the abnormality detection module 110 outputs a second high level H2, as Figure 5 the Va waveform in

[0050] In an embodiment, as Figure 2 shown, the result identification module 120 includes: a fifth transistor T5 and a second resistor R2. The control end of the fifth transistor T5 is connected to the output end of the abnormality detection module 110, and the first end of the fifth transistor T5 is connected to the power supply terminal VCC; the first end of the second resistor R2 is connected to the second end of the fifth transistor T5, and the second end of the second resistor R2 is grounded.

[0051] It should be noted that the second terminal of the fifth transistor T5 is used as the first output terminal Vo1 of the result recognition module 120, that is, the output node 1. Specifically, the fifth transistor T5 is a P-type MOS transistor. When the abnormal detection module 110 outputs a low level, the fifth transistor T5 is turned on, causing the output node 1 to output a high level, as shown in the Vo1 waveform in Figure 3 ; in addition, when the abnormal detection module 110 outputs a high level, the fifth transistor T5 is cut off, causing the first output terminal Vo1 to output a low level, as shown in the Vo1 waveforms in Figure 4 and 5 .

[0052] In another embodiment, as shown in Figure 2 , the result recognition module 120 further includes a comparator U2, a sixth transistor T6, a seventh transistor T7, and a third resistor R3. The first input terminal of the comparator U2 is connected to the output terminal of the abnormal detection module 110, and the second input terminal of the comparator U2 is connected to the power supply terminal VCC. The control terminal of the sixth transistor T6 is connected to the output terminal of the comparator U2, and the first terminal of the sixth transistor T6 is connected to the power supply terminal VCC. The control terminal of the seventh transistor T7 is connected to the second terminal of the fifth transistor T5, and the first terminal of the seventh transistor T7 is connected to the second terminal of the sixth transistor T6. The first terminal of the third resistor R3 is connected to the second terminal of the seventh transistor T7, and the second terminal of the third resistor R3 is grounded.

[0053] In one embodiment, the result recognition module 120 further includes an eighth transistor T8 and a fourth resistor R4. The control terminal of the eighth transistor T8 is connected to the output terminal of the comparator U2, and the first terminal of the eighth transistor T8 is connected to the power supply terminal VCC. The first terminal of the fourth resistor R4 is connected to the second terminal of the eighth transistor T8, and the second terminal of the fourth resistor R4 is grounded.

[0054] It should be noted that the second terminal of the seventh transistor T7 is used as the second output terminal Vo2 of the result recognition module 120, that is, the output node 2; the second terminal of the eighth transistor T8 is used as the third output terminal Vo3 of the result recognition module 120, that is, the output node 3.

[0055] Optionally, the comparator U2 is configured to compare the output voltage of the abnormal detection module 110 with a threshold voltage. If the output voltage of the abnormal detection module 110 is greater than the threshold voltage, it outputs a high level; if the output voltage of the abnormal detection module 110 is less than the threshold voltage, it outputs a low level. In this embodiment, the threshold voltage is set to be greater than the first high level and less than the second high level, for example, 5V. Additionally, the voltage output by the power supply terminal VCC is used as the threshold voltage. Optionally, the sixth transistor T6 and the seventh transistor T7 are P-type MOS transistors, and the eighth transistor T8 is an N-type MOS transistor.

[0056] Specifically, when the anomaly detection module 110 outputs a low level and the comparator U2 outputs a low level, the fifth transistor T5 conducts, the sixth transistor T6 conducts, the seventh transistor T7 is cut off, and the eighth transistor T8 is cut off, so that the first output terminal Vo1 outputs a high level, the second output terminal Vo2 outputs a low level, and the third output terminal Vo3 outputs a low level, as Figure 3 the waveforms of Vo1, Vo2, and Vo3 in

[0057] Specifically, when the anomaly detection module 110 outputs a first high level and the comparator U2 outputs a low level, the fifth transistor T5 is cut off, the sixth transistor T6 conducts, the seventh transistor T7 conducts, and the eighth transistor T8 is cut off, so that the first output terminal Vo1 outputs a low level, the second output terminal Vo2 outputs a high level, and the third output terminal Vo3 outputs a low level, as Figure 4 the waveforms of Vo1, Vo2, and Vo3 in

[0058] Specifically, when the anomaly detection module 110 outputs a second high level and the comparator U2 outputs a high level, the fifth transistor T5 is cut off, the sixth transistor T6 is cut off, the seventh transistor T7 conducts, and the eighth transistor T8 conducts, so that the first output terminal Vo1 outputs a low level, the second output terminal Vo2 outputs a low level, and the third output terminal Vo3 outputs a high level, as Figure 5 the waveforms of Vo1, Vo2, and Vo3 in

[0059] Here, the detection results of the above clock signal are summarized in Table 1 as follows:

[0060] Table 1. Detection result table of clock signal

[0061]

[0062] In this embodiment, the high level H output from the first output terminal Vo1, the second output terminal Vo2, or the third output terminal Vo3 is used as the target recognition signal.

[0063] In addition, it should be noted that the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can also be N-type MOS transistors, and the eighth transistor T8 is a P-type MOS transistor; different from the above embodiment, the output logics of the three output terminals of the result recognition module 120 are opposite, so that the subsequent processing logic can be adjusted adaptively, which does not affect the implementation of the solution.

[0064] Second, the present application provides a clock detection method, which specifically includes the following embodiments:

[0065] Figure 6 The following shows a schematic flowchart of a clock detection method provided by an embodiment of the present application; as Figure 6As shown in the figure, the clock detection method specifically includes the following steps:

[0066] Step S100: Perform anomaly detection on the first clock signal and the second clock signal corresponding to each pixel row to obtain corresponding anomaly detection results.

[0067] Among them, the anomaly detection results include a first detection result where both the first clock signal and the second clock signal are normal, a second detection result where the first clock signal is normal but the second clock signal is abnormal, and a third detection result where the first clock signal is abnormal but the second clock signal is normal.

[0068] Step S200: Identify the anomaly detection results, output a target identification signal to the corresponding memory, and enable the timing controller to perform single-ended driving or double-ended driving on the display panel according to the target identification signals in all memories.

[0069] Among them, when it is the first detection result, output the target identification signal to the first memory; when it is the second detection result, output the target identification signal to the second memory; when it is the third detection result, output the target identification signal to the third memory.

[0070] It should be noted that the detection principle of this clock detection method is the same as the working principle of the clock detection circuit in the above embodiment, and will not be elaborated here.

[0071] In a third aspect, the present application provides a display panel, which specifically includes the following embodiments:

[0072] Figure 7 The following shows a schematic structural diagram of a display panel provided by an embodiment of the present application; as Figure 7 shown, the display panel specifically includes:

[0073] A clock generator for outputting N first clock signals and N second clock signals;

[0074] A clock detection circuit, which is respectively connected to the first clock signal output terminal and the second clock signal output terminal of the clock generator, and is used for performing anomaly detection on the first clock signal and the second clock signal;

[0075] A first memory, which is connected to the first output terminal of each clock detection circuit, and is used for receiving the target identification signal output by each clock detection circuit;

[0076] A second memory, which is connected to the second output terminal of each clock detection circuit, and is used for receiving the target identification signal output by each clock detection circuit;

[0077] A third memory, which is connected to the third output terminal of each clock detection circuit, and is used for receiving the target identification signal output by each clock detection circuit;

[0078] M cascaded first GDL circuits ( Figure 7 not shown), each first GDL circuit is respectively connected to the first clock signal output terminal of the clock generator and the first end of the corresponding scan line in the display panel, and is used to output the corresponding gate driving signal under the action of the first clock signal;

[0079] M cascaded second GDL circuits ( Figure 7 not shown), each second GDL circuit is respectively connected to the second clock signal output terminal of the clock generator and the second end of the corresponding scan line in the display panel, and is used to output the corresponding gate driving signal under the action of the second clock signal;

[0080] A timing controller, which is respectively connected to the first memory, the second memory, the third memory, the first GDL circuit and the second GDL circuit, and is used to control the first GDL circuit and the second GDL circuit to be turned on or off according to the target recognition signals in all memories.

[0081] In one embodiment, controlling the first GDL circuit and the second GDL circuit to be turned on or off according to the target recognition signals in all memories specifically includes the following situations:

[0082] (1) When there are N target recognition signals in the first memory, turn on the first GDL circuit and the second GDL circuit at the same time; it should be noted that when there are N target recognition signals in the first memory, it means that all the first clock signals and all the second clock signals are normal signals, so all the first GDL circuits and the second GDL circuits are turned on through the timing controller to realize dual-end driving of the display panel.

[0083] (2) When there is at least one target recognition signal in the second memory, turn off the second GDL circuit; specifically, when there is at least one target recognition signal in the second memory, it means that at least one second clock signal is abnormal, so all the second GDL circuits need to be turned off to realize right-end driving of the display panel.

[0084] (3) When there is at least one target recognition signal in the third memory, turn off the first GDL circuit; specifically, when there is at least one target recognition signal in the third memory, it means that at least one first clock signal is abnormal, so all the first GDL circuits need to be turned off to realize left-end driving of the display panel.

[0085] In addition, it should be noted that generally there will not be target recognition signals in the second memory and the third memory at the same time.

[0086] Therefore, when any side clock signal of any row is detected to be abnormal in this embodiment, the dual-ended driving mode of all rows in the display panel is immediately changed to the single-ended driving mode simultaneously, avoiding abnormal brightness between the normal rows and the abnormal rows, thereby solving the problem of improving the picture display effect when the clock signal of the dual-ended driving is abnormal.

[0087] In summary, when the clock detection circuit is applied to a dual-ended driven display panel, when an abnormal clock signal on either side is detected, the corresponding side gate driving signal is turned off, and if the clock signals on both sides are normal, dual-ended driving is performed. While improving the stability of the display panel, it can improve picture abnormalities, does not affect the customer experience, and increases the service life and profit of the product.

[0088] In addition, terms such as "first", "second", "third", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", "third" may explicitly or implicitly include one or more of such features. In the description of this application, "a plurality" means two or more, unless otherwise specifically defined.

[0089] In the description of this specification, descriptions with reference to terms such as "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0090] Although the embodiments of this application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be construed as limiting this application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and the description of this application shall fall within the scope covered by the patent of this application.

Claims

1. A clock detection circuit, characterized in that: Applicable to a double-ended driven display panel, the clock detection circuit comprises: An abnormality detection module, wherein a first input end of the abnormality detection module is connected to the first clock signal output end, and a second input end of the abnormality detection module is connected to the second clock signal output end, and is used to perform abnormality detection on the first clock signal and the second clock signal, and output corresponding abnormality detection results; A result recognition module, wherein the input end of the result recognition module is connected to the output end of the abnormality detection module, the first output end of the result recognition module is connected to the first memory, the second output end of the result recognition module is connected to the second memory, and the third output end of the result recognition module is connected to the third memory, and is used to recognize the abnormality detection result, output a target recognition signal to the corresponding memory, and enable the timing controller to perform single-end drive or double-end drive on the display panel according to the target recognition signal in all memories; Wherein, the anomaly detection module includes: a first transistor, wherein a control terminal of the first transistor is connected to the first clock signal output terminal, and a first terminal of the first transistor is connected to the second clock signal output terminal; a second transistor, wherein a control terminal of the second transistor is connected to a control terminal of the first transistor, and a first terminal of the second transistor is connected to a second terminal of the first transistor; a third transistor, wherein a control terminal of the third transistor is connected to a first terminal of the first transistor, a first terminal of the third transistor is connected to a first terminal of the second transistor, and a second terminal of the third transistor is connected to a control terminal of the second transistor; a fourth transistor, wherein a control end of the fourth transistor is connected to the second end of the second transistor, a first end of the fourth transistor is connected to the first end of the third transistor, and a second end of the fourth transistor is connected to the second end of the third transistor; an inverter, wherein an input end of the inverter is connected to the control end of the third transistor, and an output end of the inverter is connected to the control end of the fourth transistor; Wherein, the second end of the first transistor is the output end of the abnormality detection module.

2. The clock detection circuit according to claim 1, characterized in that: The turn-on voltages of the first transistor and the second transistor are opposite, the turn-on voltages of the third transistor and the fourth transistor are opposite, and the turn-on voltages of the first transistor and the third transistor are the same.

3. The clock detection circuit according to claim 1 or 2, characterized in that: The anomaly detection module also includes: a first resistor, wherein a first end of the first resistor is connected to a second end of the first transistor, and a second end of the first resistor is grounded; a diode, wherein an anode of the diode is connected to a first end of the first resistor; A capacitor, a first end of the capacitor is connected to the cathode of the diode, and a second end of the capacitor is grounded.

4. The clock detection circuit according to claim 1, characterized in that: The result identification module comprises: a fifth transistor, wherein a control end of the fifth transistor is connected to the output end of the abnormality detection module, and a first end of the fifth transistor is connected to a power supply end; a second resistor, wherein a first end of the second resistor is connected to a second end of the fifth transistor, and a second end of the second resistor is grounded; Wherein, the second end of the fifth transistor is the first output end of the result identification module.

5. The clock detection circuit according to claim 4, characterized in that: The result recognition module also includes: A comparator, wherein a first input terminal of the comparator is connected to the output terminal of the abnormality detection module, and a second input terminal of the comparator is connected to the power supply terminal; a sixth transistor, wherein a control terminal of the sixth transistor is connected to the output terminal of the comparator, and a first terminal of the sixth transistor is connected to the power supply terminal; a seventh transistor, wherein a control terminal of the seventh transistor is connected to the second terminal of the fifth transistor, and a first terminal of the seventh transistor is connected to the second terminal of the sixth transistor; a third resistor, wherein a first end of the third resistor is connected to the second end of the seventh transistor, and a second end of the third resistor is grounded; Wherein, the second end of the seventh transistor is the second output end of the result identification module.

6. The clock detection circuit according to claim 5, characterized in that: The result recognition module also includes: an eighth transistor, wherein a control terminal of the eighth transistor is connected to the output terminal of the comparator, and a first terminal of the eighth transistor is connected to the power supply terminal; a fourth resistor, wherein a first end of the fourth resistor is connected to the second end of the eighth transistor, and a second end of the fourth resistor is grounded; Wherein, the second end of the eighth transistor is the third output end of the result identification module.

7. A clock detection method, characterized in that: Applicable to the clock detection circuit according to any one of claims 1 to 6, the clock detection method comprising: Performing abnormality detection on the first clock signal and the second clock signal corresponding to each pixel row to obtain corresponding abnormality detection results; wherein the abnormality detection results include a first detection result that the first clock signal and the second clock signal are both normal, a second detection result that the first clock signal is normal but the second clock signal is abnormal, and a third detection result that the first clock signal is abnormal but the second clock signal is normal; The abnormal detection result is identified, and a target identification signal is output to a corresponding memory, so that a timing controller performs single-end or double-end driving on the display panel according to the target identification signal in all memories; wherein, if it is a first detection result, the target identification signal is output to a first memory, if it is a second detection result, the target identification signal is output to a second memory, and if it is a third detection result, the target identification signal is output to a third memory.

8. A display panel, characterized in that: The display panel comprises: A clock generator, configured to output N first clock signals and N second clock signals; The clock detection circuit according to any one of claims 1 to 6, wherein the clock detection circuit is respectively connected to a first clock signal output terminal and a second clock signal output terminal of a clock generator, and is used to perform abnormality detection on the first clock signal and the second clock signal; A first memory, connected to a first output terminal of each clock detection circuit, for receiving a target identification signal output by each clock detection circuit; A second memory, connected to the second output terminal of each clock detection circuit, for receiving the target identification signal output by each clock detection circuit; a third memory connected to the third output terminal of each clock detection circuit and configured to receive the target identification signal output by each clock detection circuit; M cascaded first GDL circuits, each of which is respectively connected to a first clock signal output terminal of the clock generator and a first terminal of a corresponding scan line in the display panel, and is used for outputting a corresponding gate drive signal under the action of the first clock signal; M cascaded second GDL circuits, each second GDL circuit is respectively connected to the second clock signal output terminal of the clock generator and the second end of the corresponding scan line in the display panel, and is used for outputting a corresponding gate drive signal under the action of the second clock signal; A timing controller is respectively connected to the first memory, the second memory, the third memory, the first GDL circuit and the second GDL circuit, and is used to control the first GDL circuit and the second GDL circuit to be turned on or off according to the target identification signals in all the memories.

9. The display panel according to claim 8, characterized in that: According to the target identification signals in all memories, controlling the first GDL circuit and the second GDL circuit to be turned on or off includes: When there are N target identification signals in the first memory, the first GDL circuit and the second GDL circuit are turned on simultaneously; When at least one target identification signal exists in the second memory, closing the second GDL circuit; When at least one target identification signal exists in the third memory, the first GDL circuit is turned off.

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