Display device and method for reducing noise

Abstract

The invention provides a display device and a method for reducing noise. The display device comprises a source electrode driving circuit and a display panel. The display panel includes a plurality of data lines and a multiplexer. The multiplexer includes a plurality of control signal lines, a plurality of reverse signal lines, and a plurality of multiplexer circuits. Each multiplexer circuit includes a first transistor and a second transistor. The first transistor has a first end, a second end and a first control end. The first end is coupled to the source driving circuit. The second end is coupled to one of the data lines, and the first control end is coupled to one of the control signal lines. The second transistor has a third end, a fourth end and a second control end. The third end and the fourth end are coupled to one of the reverse signal lines. The second control terminal is coupled to the first terminal of the first transistor.

Description

Technical Field

[0001] The invention relates to a display device and a method for reducing noise applied to the display device. Background Art

[0002] In low temperature polysilicon (LTPS) display products, a multiplexer is usually set up to control switches so that multiple pixel circuits can share the same signal source, thereby reducing the required input contacts and simplifying the design of peripheral circuits. Although the above design can reduce external wiring, due to the high voltage and high frequency characteristics of the multiplexer signal, it will generate parasitic capacitance with the voltage source, forming unnecessary noise and may affect the function of the display.

[0003] For example, when performing electromagnetic interference (EMI) testing on display products, ripples are observed in the signal waveform of the display products. As product specifications and regulations become increasingly stringent, the interference of the above noise may cause the display to fail product inspection. Summary of the invention

[0004] At least one embodiment of the present invention provides a display device and a method for reducing noise. The display device can reduce the interference of noise by executing the method for reducing noise.

[0005] The display device provided by at least one embodiment of the present invention includes a source drive circuit and a display panel. The display panel includes a plurality of data lines and a multiplexer. The multiplexer includes a plurality of control signal lines, a plurality of reverse signal lines and a plurality of multiplexer circuits. Each multiplexer circuit includes a first transistor and a second transistor. The first transistor has a first end, a second end and a first control end. The first end is coupled to the source drive circuit. The second end is coupled to one of the data lines, and the first control end is coupled to one of the control signal lines. The second transistor has a third end, a fourth end and a second control end. The third end and the fourth end are coupled to one of the reverse signal lines. The second control end is coupled to the first end of the first transistor.

[0006] The display device provided by at least one embodiment of the present invention includes a source drive circuit and a display panel. The display panel includes a plurality of data lines and a multiplexer. The multiplexer includes a plurality of control signal lines, a plurality of reverse signal lines and a plurality of multiplexer circuits. Each multiplexer circuit includes a first transistor and a second transistor. The first transistor has a first end, a second end and a first control end. The first end is coupled to the source drive circuit. The second end is coupled to one of the data lines, and the first control end is coupled to one of the control signal lines. The second transistor has a third end, a fourth end and a second control end. The third end and the fourth end are coupled to one of the reverse signal lines. The second control end is coupled to the second end of the first transistor.

[0007] In at least one embodiment of the present invention, the source driving circuit is used to output a first source driving signal and a second source driving signal. In one multiplexer circuit, the first end of the first transistor receives the first source driving signal. In another multiplexer circuit, the first end of the first transistor receives the second source driving signal.

[0008] In at least one embodiment of the present invention, each control signal line is used to transmit a control signal. Each reverse signal line is used to transmit a reverse control signal. Each multiplexer circuit receives one of the control signals and one of the reverse control signals. In each multiplexer circuit, the received reverse control signal is synchronized with and inverted from the received control signal.

[0009] In at least one embodiment of the present invention, in each multiplexer circuit, the first transistor has a first width-to-length ratio and the second transistor has a second width-to-length ratio, and the absolute value of the difference between the second width-to-length ratio and the first width-to-length ratio is less than or equal to 30% of the first width-to-length ratio.

[0010] At least one embodiment of the present invention provides a method for reducing noise, which is applicable to the display device described above. The method for reducing noise includes: a plurality of control signal lines transmit a plurality of control signals respectively; and a plurality of reverse signal lines are synchronized with the plurality of control signal lines respectively to transmit a plurality of reverse control signals, so that in each of the multiplexer circuits, when the first transistor is turned on, the third terminal and the fourth terminal of the second transistor form a capacitor relative to the second control terminal.

[0011] In at least one embodiment of the present invention, the plurality of reverse control signals are respectively inverted with respect to the plurality of synchronous control signals.

[0012] Based on the above, in the display device and the method for reducing noise disclosed in the above embodiments, the cooperation between the capacitor formed by the second transistor and the reverse control signal can reduce the noise generated by the control signal of the multiplexer. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] For a more complete understanding of the embodiments and their advantages, reference is now made to the following description in conjunction with the accompanying drawings, in which:

[0014] Figure 1 is a schematic diagram of a display device according to at least one embodiment of the present invention;

[0015] Figure 2 yes Figure 1 A circuit diagram of a multiplexer of a display device;

[0016] Figure 3 yes Figure 1 A circuit diagram of another multiplexer of a display device;

[0017] Figure 4 is a measurement and schematic diagram of the control terminal of the multiplexer adjacent to the display device; and

[0018] Figure 5 It is a measurement and schematic diagram of the control end of the multiplexer of the control example display device.

[0019] Wherein, the reference numerals are:

[0020] 100: Display device

[0021] 110: Display panel

[0022] 120: Source drive circuit

[0023] 130: Gate drive circuit

[0024] 200A,200B:Multiplexer

[0025] 210A, 210B, 220A, 220B, 230A, 230B, 240A, 240B, 250A, 250B, 260A, 260B: Multiplexer circuit

[0026] 311: First End

[0027] 312: Second End

[0028] 313: The Third End

[0029] 314: The Fourth End

[0030] 410,510: Control signal waveform

[0031] 420,520: Reverse control signal waveform

[0032] 430,530: Noise waveform

[0033] PX: Pixel

[0034] DL1~DL6: Data line

[0035] SL: Scan Line

[0036] S1: First source driving signal

[0037] S2: Second source drive signal

[0038] SW1~SW3: Control signal line

[0039] XSW1~XSW3: Reverse signal line

[0040] T1: First transistor

[0041] T2: Second transistor

[0042] Vpp: The value between the peaks of the voltage

[0043] X,Y: Direction DETAILED DESCRIPTION

[0044] In the following text, in order to clearly present the technical features of the present invention, the dimensions (e.g., length, width, thickness, and depth) of the elements (e.g., layers, films, substrates, and regions, etc.) in the drawings will be enlarged in unequal proportions, and the number of some elements will be reduced. Therefore, the description and explanation of the embodiments below are not limited to the number of elements in the drawings and the dimensions and shapes presented by the elements, but should cover the dimensions, shapes, and deviations thereof caused by the actual process and / or tolerances. For example, the flat surface shown in the drawings may have rough and / or nonlinear features, and the acute angles shown in the drawings may be rounded. Therefore, the elements presented in the drawings of the present invention are mainly for illustration, and are not intended to accurately depict the actual shape of the elements, nor are they intended to limit the scope of the patent application of the present invention.

[0045] Secondly, the words "about", "approximately" or "substantially" that appear in the content of this case not only cover the numerical values ​​and numerical ranges that are clearly recorded, but also cover the permissible deviation range that can be understood by those with ordinary knowledge in the technical field to which the invention belongs, wherein the deviation range can be determined by the error generated during measurement, and the error is caused by the limitations of the measurement system or process conditions. For example, two objects (such as the planes or traces of the substrate) are "substantially parallel" or "substantially perpendicular", wherein "substantially parallel" and "substantially perpendicular" respectively represent that the parallelism and perpendicularity between the two objects may include the non-parallelism and non-perpendicularity caused by the permissible deviation range.

[0046] In addition, "approximately" may mean within one or more standard deviations of the above values, such as ±30%, ±20%, ±10% or ±5%. In this text, the words "approximately", "approximately" or "substantially" may be used to select acceptable deviation ranges or standard deviations according to optical properties, etching properties, mechanical properties or other properties, rather than applying a single standard deviation to all properties such as the above optical properties, etching properties, mechanical properties and other properties.

[0047] The spatially relative terms used in the present invention, such as "below", "under", "above", "on", etc., are for the purpose of facilitating the description of the relative relationship between one element or feature and another element or feature, as shown in the figure. The true meaning of these spatially relative terms includes other orientations. For example, when the figure is flipped up and down 180 degrees, the relationship between one element and another element may change from "below" or "under" to "above" or "on". In addition, the spatially relative descriptions used in the present invention should also be interpreted in the same way.

[0048] In addition, the present invention may be implemented or applied through other different specific embodiments, and the details of the present invention may also be combined, modified and changed in various embodiments based on different viewpoints and applications without departing from the concept of the present invention.

[0049] Figure 1 is a schematic diagram of a display device 100 according to at least one embodiment of the present invention. Figure 2 yes Figure 1 A circuit diagram of a multiplexer 200A of the display device 100 is shown in FIG. Figure 1 and Figure 2 The display device 100 includes a display panel 110, a source driving circuit 120, and a gate driving circuit 130. The display device 100 can be applied to a low-temperature polysilicon display, but is not limited thereto.

[0050] The display panel 110 may be a liquid crystal display panel. The source driving circuit 120 is electrically connected to the display panel 110. Figure 1 and Figure 2 In the example of FIG. 1 , the source driving circuit 120 is used to generate a first source driving signal S1 and a second source driving signal S2, and transmit the first source driving signal S1 and the second source driving signal S2 to the display panel 110. The gate driving circuit 130 is electrically connected to the display panel 110, and is used to generate a gate driving signal and transmit the gate driving signal to the display panel 110.

[0051] The display panel 110 includes a plurality of pixels PX, a plurality of data lines DL1 to DL6, a plurality of scan lines SL, and a multiplexer 200A. The pixels PX are located in the display area and are arranged along directions X and Y. The data lines DL1 to DL6 are sequentially arranged along direction X and coupled to the pixels PX to transmit a first source driving signal S1 and a second source driving signal S2 to the pixels PX, wherein the first source driving signal S1 and the second source driving signal S2 are voltage sources of different positive and negative polarities. For example, when the first source driving signal S1 is a positive voltage source, the second source driving signal S2 is a negative voltage source; when the first source driving signal S1 is a negative voltage source, the second source driving signal S2 is a positive voltage source.

[0052] The scan lines SL are sequentially arranged along the direction Y and are also coupled to the pixels PX to transmit gate driving signals to the pixels PX. The pixels PX are driven by the first source driving signal S1 or the second source driving signal S2 and the gate driving signal to display images.

[0053] The multiplexer 200A is located between these pixels PX and the source driving circuit 120 (i.e., the peripheral area), and is used to selectively transmit the first source driving signal S1 and the second source driving signal S2 to the data lines DL1-DL6, so as to simplify the configuration of the peripheral circuit by sharing the first source driving signal S1 and the second source driving signal S2. The multiplexer 200A includes a plurality of control signal lines SW1-SW3, a plurality of reverse signal lines XSW1-XSW3, and a plurality of multiplexer circuits 210A, 220A, 230A, 240A, 250A, and 260A.

[0054] These control signal lines SW1-SW3 and these reverse signal lines XSW1-XSW3 can be arranged along direction Y. These reverse signal lines XSW1-XSW3 correspond to these control signal lines SW1-SW3 respectively. Further, these control signal lines SW1-SW3 are used to transmit multiple control signals respectively. These reverse signal lines XSW1-XSW3 correspond to these control signal lines SW1-SW3 respectively to transmit multiple reverse control signals respectively, wherein these reverse control signals are synchronized with the corresponding control signals respectively and are inverse to the corresponding control signals. That is, the phase difference between the corresponding control signal and the reverse control signal can be 180 degrees.

[0055] exist Figure 1 and Figure 2In the example of , the number of these data lines DL1 to DL6 is six. The number of these control signal lines SW1 to SW3 is three, and the number of these reverse signal lines XSW1 to XSW3 is three. The number of these multiplexer circuits 210A, 220A, 230A, 240A, 250A, and 260A is six, wherein the multiplexer circuit 210A is the control front end of the multiplexer 200A, and the multiplexer circuit 260A is the control end of the multiplexer 200A. It should be noted that the number of these data lines DL1 to DL6, the control signal lines SW1 to SW3, these reverse signal lines XSW1 to XSW3, and these multiplexer circuits 210A, 220A, 230A, 240A, 250A, and 260A can be adjusted with the size of the display panel 110 without limitation.

[0056] Each of the multiplexer circuits 210A, 220A, 230A, 240A, 250A, 260A includes a first transistor T1 and a second transistor T2. Figure 2 In the example of the first transistor T1 and the second transistor T2, N-type Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET), but not limited thereto. In other embodiments, the first transistor T1 and the second transistor T2 may be P-type Metal-Oxide-Semiconductor Field-Effect Transistor (PMOSFET).

[0057] The first transistor T1 has a first terminal 311, a second terminal 312 and a first control terminal. The first terminal 311 is coupled to the source driving circuit 120 to receive the first source driving signal S1 or the second source driving signal S2. The second terminal 312 is coupled to one of the data lines DL1-DL6. The first control terminal is coupled to one of the control signal lines SW1-SW3. The first terminal 311 and the second terminal 312 can be a source and a drain, respectively.

[0058] The second transistor T2 has a third terminal 313, a fourth terminal 314 and a second control terminal. The third terminal 313 and the fourth terminal 314 are coupled to each other and to one of the reverse signal lines XSW1-XSW3. The second control terminal is coupled to the first terminal 311 of the first transistor T1 and the source driving circuit 120 to receive the first source driving signal S1 or the second source driving signal S2. The third terminal 313 and the fourth terminal 314 can be a source and a drain, respectively.

[0059] In particular, the first transistor T1 has a first width-to-length ratio (i.e., the ratio of the length and width of the gate channel of the first transistor T1), and the second transistor T2 has a second width-to-length ratio (i.e., the ratio of the length and width of the gate channel of the second transistor T2), and the absolute value of the difference between the second width-to-length ratio and the first width-to-length ratio is less than or equal to 30% of the first width-to-length ratio. In other words, the sizes of the first transistor T1 and the second transistor T2 can be the same or similar, so that the performance of the two is similar. For example, the first width-to-length ratio of the first transistor T1 is 120 microns / 4 microns. The second width-to-length ratio of the second transistor T2 can be 120 microns / 4 microns or 130 microns / 4 microns.

[0060] exist Figure 2 In the multiplexer circuits 210A, 220A and 230A, the first terminals 311 of the plurality of first transistors T1 receive the first source drive signal S1. The second terminals 312 of the plurality of first transistors T1 are respectively coupled to the data lines DL1 to DL3. The first control terminals of the plurality of first transistors T1 are respectively coupled to the control signal lines SW1 to SW3. The third terminals 313 (and the fourth terminals 314) of the plurality of second transistors T2 are respectively coupled to the reverse signal lines XSW1 to XSW3. The second control terminals of the plurality of second transistors T2 receive the first source drive signal S1.

[0061] Similarly, in Figure 2 In the multiplexer circuits 240A, 250A and 260A, the first terminals 311 of the plurality of first transistors T1 receive the second source drive signal S2. The second terminals 312 of the plurality of first transistors T1 are respectively coupled to the data lines DL4 to DL6. The first control terminals of the plurality of first transistors T1 are respectively coupled to the control signal lines SW1 to SW3. The third terminals 313 (and the fourth terminals 314) of the plurality of second transistors T2 are respectively coupled to the reverse signal lines XSW1 to XSW3. The second control terminals of the plurality of second transistors T2 receive the second source drive signal S2.

[0062] Figure 3 yes Figure 1 FIG. 1 is a circuit diagram of another multiplexer 200B of the display device 100. Figure 3 , Figure 3 The multiplexer 200B is similar to Figure 2 The multiplexer 200A has the same or similar components with the same reference numerals. Figure 3 In each of the multiplexer circuits 210B, 220B, 230B, 240B, 250B, and 260B of the multiplexer 200B, the second control terminal of the second transistor T2 is coupled to the second terminal 312 of the first transistor T1 and one of the data lines DL1 ˜ DL6 .

[0063] So, in Figure 3In the multiplexer circuits 210B, 220B and 230B, the second control terminals of the plurality of second transistors T2 are respectively coupled to the data lines DL1-DL3. Figure 3 In the multiplexer circuits 240B, 250B and 260B, the second control terminals of the plurality of second transistors T2 are respectively coupled to the data lines DL4 ˜ DL6 .

[0064] See also Figure 2 and Figure 3 The display device 100 can use the multiplexer 200A or 200B to perform a method for reducing noise, which is described as follows. When one of the data lines DL1, DL2 or DL3 needs to receive the first source driving signal S1, one of the control signal lines SW1, SW2 or SW3 can transmit a control signal to the first transistor T1 corresponding to one of the data lines DL1, DL2 or DL3 to turn on the corresponding first transistor T1, so that one of the data lines DL1, DL2 or DL3 can receive the first source driving signal S1 from the turned-on first transistor T1.

[0065] At the same time, one of the reverse signal lines XSW1, XSW2 or XSW3 corresponding to the transmitted control signal lines SW1, SW2 or SW3 also transmits a reverse control signal to the corresponding second transistor T2, so that the third end 313 and the fourth end 314 of the second transistor T2 form a capacitor relative to the second control end.

[0066] Similarly, when one of the data lines DL4, DL5 or DL6 needs to receive the second source drive signal S2, one of the control signal lines SW1, SW2 or SW3 can transmit a control signal to the first transistor T1 corresponding to one of the data lines DL4, DL5 or DL6 to turn on the corresponding first transistor T1, so that one of the data lines DL4, DL5 or DL6 can receive the second source drive signal S2 from the turned-on first transistor T1.

[0067] At the same time, one of the reverse signal lines XSW1, XSW2 or XSW3 corresponding to the transmitted control signal lines SW1, SW2 or SW3 also transmits a reverse control signal to the corresponding second transistor T2, so that the third end 313 and the fourth end 314 of the second transistor T2 form a capacitor relative to the second control end.

[0068] It should be noted that when the first transistor T1 is turned on, the control signal generates noise to the display device 100 (e.g., the common electrode of the system), and when the second transistor T2 forms a capacitor, the reverse control signal also generates reverse noise to the display device 100 (e.g., the common electrode of the system) via the capacitor formed by the second transistor T2, thereby offsetting most of the noise generated by the control signal to reduce the electromagnetic interference caused by the control signal.

[0069] Figure 4 is a measurement and schematic diagram of the control terminal of the multiplexer 200A adjacent to the display device 100. Figure 2 and Figure 4 , measurements are made at the control end of the multiplexer 200A, for example, the control signal is measured at the first control end of the first transistor T1 of the multiplexer circuit 260A, and the reverse control signal is measured at the third end 313 of the second transistor T2. Figure 4 In FIG. 4 , the horizontal axis is time (in microseconds) and the vertical axis is voltage (in volts), wherein the noise waveform 430 is formed by superimposing the control signal waveform 410 and the reverse control signal waveform 420, and the voltage of peak to peak (voltage ofpeak to peak, Vpp) and the voltage of root mean square (voltage of root mean square, Vrms) of the noise waveform 430 can be used to evaluate the size and state of the noise. The voltage of peak to peak of the noise waveform 430 can be used to evaluate the instantaneous disturbance of the noise, and the voltage of root mean square can be used to evaluate the normal distribution of the noise.

[0070] At time 20 microseconds to 24 microseconds, the first source driving signal S1 is 5 volts to 0 volts, and the second source driving signal S2 is -5 volts to 0 volts, and the peak-to-peak value and the root mean square value of the voltage of the noise waveform 430 are 2.0618 volts and 0.9975 volts, respectively. At time 30 microseconds to 34 microseconds, the first source driving signal S1 is 0 volts to 5 volts, and the second source driving signal S2 is 0 volts to -5 volts, and the peak-to-peak value and the root mean square value of the voltage of the noise waveform 430 are 1.2002 volts and 0.99807 volts, respectively.

[0071] Figure 5 The following is a measurement and schematic diagram of the control end of the multiplexer of the control example display device. Figure 4 and Figure 5 The display device of the comparative example is, for example, the display panel of Taiwan Patent Application No. TW109110349. Figure 5 , the horizontal axis is time (in microseconds), and the vertical axis is voltage (in volts), wherein the noise waveform 530 is formed by superimposing the control signal waveform 510 and the reverse control signal waveform 520. At time 20 microseconds to 24 microseconds, the first source driving signal S1 is 5 volts to 0 volts, and the second source driving signal S2 is -5 volts to 0 volts, and the peak-to-peak value and the root mean square value of the voltage of the noise waveform 530 are 3.408 volts and 1.0208 volts, respectively, which are greater than the peak-to-peak value (2.0618 volts) and the root mean square value (0.9975 volts) of the voltage of the noise waveform 430, respectively.

[0072] At time 30 microseconds to 34 microseconds, the first source drive signal S1 is 0 volts to 5 volts, and the second source drive signal S2 is 0 volts to -5 volts, and the peak-to-peak value and root mean square value of the voltage of the noise waveform 530 are 3.1206 volts and 1.0017 volts, respectively, which are greater than the peak-to-peak value (1.2002 volts) and root mean square value (0.99807 volts) of the voltage of the noise waveform 430.

[0073] As can be seen from the above, in each multiplexer circuit of the display device 100 of the present invention, when the first transistor T1 receives a control signal and turns on, the second transistor T2 simultaneously receives a reverse control signal and forms a capacitor. Therefore, when the multiplexer 200A or 200B generates a control signal, the coordination of the capacitor formed by the second transistor T2 and the reverse control signal can offset and reduce the noise generated by the control signal, and both are better than the noise reduction effect of the control example display device (regardless of whether it is instantaneous noise or normal noise distribution). In addition, the display device 100 also has the effect of reducing noise when the voltage of the first source drive signal S1 and the second source drive signal S2 changes.

[0074] The following Tables 1 and 2 are comparisons of the peak-to-peak value (Vpp) and the root mean square value (Vrms) of the voltage of the noise waveform of the display device 100 of the present invention and the comparative display device, when the transistors in the multiplexer are replaced with conventional or variant transistors. Tables 1 and 2 are for considering the influence of the actual manufactured transistors (conventional or variant) on the noise of the display device 100 of the present invention and the comparative display device, wherein the denominator of the percentage is the total amount of the peak-to-peak value (Vpp) or the root mean square value (Vrms) of the voltage of the noise of the comparative display device. For example, the threshold voltage (Vth) of the conventional transistor is 2.0 volts, and the threshold voltage of the variant transistor is 2.0-1.2 volts, or 2.0+1.2 volts. It can be seen from Tables 1 and 2 that even in the case of transistor variants, the display device 100 of the present invention is better than the comparative display device in reducing noise.

[0075] Table 1

[0076]

[0077] Table 2

[0078]

[0079] In summary, in the display device 100 disclosed in the above embodiments and in combination with different multiplexers 200A and 200B, the capacitor formed by the second transistor T2 and the reverse control signal can offset and reduce the noise generated by the control signal, thereby reducing the electromagnetic interference caused by the control signal. Compared with the existing display device (such as the comparative display device), the display device 100 of the present case can achieve a better noise suppression effect.

[0080] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. A person having ordinary knowledge in the technical field to which the present invention belongs may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims

1. A display device, characterized in that: Include: a source driving circuit; and A display panel, comprising: multiple data lines; and A multiplexer, comprising: Multiple control signal lines; Multiple reverse signal lines; and A plurality of multiplexer circuits, each of the multiplexer circuits comprising: a first transistor having a first terminal, a second terminal and a first control terminal, wherein the first terminal is coupled to the source driving circuit, the second terminal is coupled to one of the data lines, and the first control terminal is coupled to one of the control signal lines; and a second transistor having a third terminal, a fourth terminal and a second control terminal, The third terminal and the fourth terminal are coupled to one of the reverse signal lines, and the second control terminal is coupled to the first terminal of the first transistor.

2. The display device according to claim 1, wherein: The source driving circuit is used to output a first source driving signal and a second source driving signal; wherein in one of the multiplexer circuits, the first end of the first transistor receives the first source driving signal; In another one of the multiplexer circuits, the first end of the first transistor receives the second source driving signal.

3. The display device according to claim 1, wherein: Each of the control signal lines is used to transmit a control signal, and each of the reverse signal lines is used to transmit a reverse control signal; Each of the multiplexer circuits receives one of the control signals and one of the reverse control signals; In each of the multiplexer circuits, the received reverse control signal is synchronized with and inverted from the received control signal.

4. The display device according to claim 1, wherein: wherein in each of the multiplexer circuits, the first transistor has a first width-to-length ratio, and the second transistor has a second width-to-length ratio; An absolute value of a difference between the second aspect ratio and the first aspect ratio is less than or equal to 30% of the first aspect ratio.

5. A display device, characterized in that: Include: a source driving circuit; and A display panel, comprising: multiple data lines; and A multiplexer, comprising: Multiple control signal lines; Multiple reverse signal lines; and A plurality of multiplexer circuits, each of the multiplexer circuits comprising: a first transistor having a first terminal, a second terminal and a first control terminal, wherein the first terminal is coupled to the source driving circuit, the second terminal is coupled to one of the data lines, and the first control terminal is coupled to one of the control signal lines; and a second transistor having a third terminal, a fourth terminal and a second control terminal, The third terminal and the fourth terminal are coupled to one of the reverse signal lines, and the second control terminal is coupled to the second terminal of the first transistor.

6. The display device according to claim 5, characterized in that Wherein the source driving circuit is configured to output a first source driving signal and a second source driving signal; wherein in one of the multiplexer circuits, the first end of the first transistor receives the first source driving signal; In another one of the multiplexer circuits, the first end of the first transistor receives the second source driving signal.

7. The display device according to claim 5, characterized in that Each of the control signal lines is used to transmit a control signal, and each of the reverse signal lines is used to transmit a reverse control signal; Each of the multiplexer circuits receives one of the control signals and one of the reverse control signals; In each of the multiplexer circuits, the received reverse control signal is synchronized with and inverted from the received control signal.

8. The display device according to claim 5, characterized in that wherein in each of the multiplexer circuits, the first transistor has a first width-to-length ratio, and the second transistor has a second width-to-length ratio; An absolute value of a difference between the second aspect ratio and the first aspect ratio is less than or equal to 30% of the first aspect ratio.

9. A method for reducing noise, characterized in that: The display device according to claim 1 or 5, wherein the method for reducing noise comprises: The control signal lines transmit a plurality of control signals respectively; and The reverse signal lines are respectively synchronized with the control signal lines to transmit a plurality of reverse control signals, so that in each of the multiplexer circuits, when the first transistor is turned on, the third terminal and the fourth terminal of the second transistor form a capacitor relative to the second control terminal.

10. The method according to claim 9, characterized in that The reverse control signals are respectively in phase with the synchronous control signals.

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