Compact in-pixel memory display architecture

Abstract

The present disclosure relates to compact in-pixel memory display structures. Pixels and compact in-pixel memory displays (e.g., implemented in a fully depleted semiconductor-on-insulator processing technology platform) are disclosed. An electronic component block for a pixel includes a memory cell array, a drive circuit for an LED, and a logic circuit connected between the memory cell array and the drive circuit. The memory cell array is located above a P-well, the drive circuit is located above an adjacent N-well, and the logic circuit includes a P-type transistor located on the N-well and an N-type transistor located on the P-well. The pixel array is located above alternating P-wells and N-wells, with a single buried N-well below. Specifically, each column of pixels is located above adjacent elongated P-wells and N-wells, and within each column, adjacent pixels have a mirrored layout. In addition, pixels of adjacent columns are located above two elongated wells of one type and a shared elongated well of the opposite type therebetween, and adjacent columns have a mirrored layout.

Description

Technical Field

[0001] The present disclosure relates to memory-in-pixel displays and, more particularly, to embodiments of compact memory-in-pixel display structures. Background Art

[0002] In a memory-in-pixel display, each pixel includes a light emitting diode (LED) (e.g., ultra-LED (uLED)), an embedded memory to store data, and logic circuits connecting the embedded memory and the LED. The use of embedded memory provides significant power savings. However, for full grayscale resolution, each pixel requires a relatively large number of memory cells (also referred to herein as bit cells). For example, each pixel may require an array of up to twelve static random access memory (SRAM) cells or even more, thereby increasing the area consumption of each pixel and making it difficult to meet the target area specifications of competitive products. Summary of the invention

[0003] An embodiment of a structure (e.g., an electronic component block for a pixel) is disclosed herein. The block may include an array of memory cells located on an insulator layer above a P-well in a semiconductor substrate. The structure may also include a light emitting diode (LED) driver circuit located on the insulator layer above an N-well in the semiconductor substrate. The N-well may be positioned laterally adjacent to the P-well, and the LED driver circuit may be connected to an anode of the LED. The structure may also include a logic circuit located on the insulator layer and connected to the array of memory cells and the LED driver circuit. The logic circuit may include a P-type transistor located on the insulator layer above the N-well and an N-type transistor located on the insulator layer above the P-well.

[0004] Also disclosed herein is an embodiment of a structure (e.g., a memory-in-pixel display structure). The structure may include a semiconductor substrate. The substrate may include a P-well located within the semiconductor substrate and an N-well located laterally adjacent to the P-well. The structure may include an insulator layer located on the semiconductor substrate and above the P-well and the N-well. The structure may also include a plurality of electronic component blocks for a plurality of pixels, respectively (e.g., at least one column of electronic component blocks for a column of pixels). Each electronic component block for a pixel may include an array of memory cells located on the insulator layer above the P-well. Each block may also include an LED drive circuit located on the insulator layer above the N-well and connected to an anode of an LED. Each block may also include a logic circuit located on the insulator layer and connected to the array of memory cells and the drive circuit. The logic circuit may include a P-type transistor located on the insulator above the N-well and an N-type transistor located on the insulator layer above the P-well.

[0005] In some embodiments, the memory-in-pixel display structure may include a semiconductor substrate having alternating P-wells and N-wells. The structure may also include an insulator layer located on the semiconductor substrate and above the alternating P-wells and N-wells. The structure may also include an array of electronic component blocks for a pixel array. The array of electronic component blocks includes at least two columns of the electronic component blocks for at least two columns of pixels. The two columns of electronic component blocks may have a mirrored column layout aligned above two wells of one type of conductivity and a common well of the opposite type of conductivity therebetween (e.g., a P-well between N-wells or an N-well between P-wells). In any case, each electronic component block for a pixel may include an array of memory cells located on the insulator layer above one P-well. Each block may include an LED driver circuit located on the insulator layer above the N-well adjacent to the P-well and connected to the anode of the LED. Each block may also include a logic circuit located on the insulator layer and connected to the array of memory cells and the LED driver circuit. The logic circuit may include a P-type transistor on the insulator layer over the same N-well as the LED driver circuit and an N-type transistor on the insulator layer over the same P-well as the array of memory cells.

[0006] It should be noted that all aspects, examples and features of the disclosed embodiments mentioned in the above summary of the invention can be combined in any technically possible manner. That is, two or more aspects of any disclosed embodiment, including those described in the summary of the invention, can be combined to form an embodiment not specifically described herein. The details of one or more embodiments are set forth in the drawings and the following description. Other features, objects and advantages will be apparent from the specification and drawings and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure may be better understood by reference to the following detailed description with reference to the accompanying drawings, which are not necessarily drawn to scale, and in which:

[0008] Figure 1 is a schematic diagram illustrating an embodiment of a compact in-pixel memory display structure;

[0009] Figure 2A is a cross-sectional view showing an example of a portion of a compact in-pixel memory display structure;

[0010] Figure 2B It is an instruction Figure 2B A table of threshold voltage types and example backbiasing conditions for transistors on P-wells and N-wells of FIG. 1 ;

[0011] Figures 3A-3C It is shown that it can be incorporated into Figure 1 A schematic diagram of an example of electronic component blocks of a pixel in a display structure of FIG.

[0012] Figures 4A-4C is an example of a timing diagram associated with the operation of the disclosed display structure; and

[0013] Figure 5 is a diagram showing an example of a layout for the disclosed display structure. DETAILED DESCRIPTION

[0014] As described above, in a memory-in-pixel display, each pixel includes a light emitting diode (LED) (e.g., an ultra-LED (uLED)), an embedded memory for storing data, and logic circuits connecting the embedded memory and the LED. The use of embedded memory provides significant power savings. However, for full grayscale resolution, a relatively large number of memory primitives (also referred to herein as bit primitives) are required for each pixel. For example, each pixel may require an array of up to twelve or even more static random access memory (SRAM) primitives, thereby increasing the area consumption of each pixel and making it difficult to meet the target area specifications of competitive products.

[0015] In view of the above, embodiments of pixels with embedded memory and compact display structures containing arrays of such pixels (i.e., compact in-pixel memory display structures) are disclosed herein. The disclosed embodiments are implemented using a fully depleted semiconductor-on-insulator processing technology platform (e.g., a fully depleted silicon-on-insulator (FDSOI) processing technology platform). In the disclosed embodiments, each electronic component block for a pixel may be located above an insulator layer on a semiconductor substrate, and may include a memory cell array, a drive circuit for a light-emitting diode (LED), and a logic circuit connected between the memory cell array and the drive circuit. The memory cell array may be aligned above a P-well in a semiconductor substrate, the drive circuit may be aligned above an adjacent N-well in a semiconductor substrate, and the logic circuit may include a combination of a P-type transistor located above the N-well and an N-type transistor located above the P-well. The electronic component blocks for a pixel may be arranged in an array of columns and rows, and may be aligned above alternating elongated P-wells and N-wells, with a single buried N-well below. Each column of blocks can be aligned over adjacent elongated P-wells and N-wells, and within each column, adjacent blocks can have a mirrored layout. In addition, within the array, adjacent columns of blocks can be aligned over three wells (including two elongated wells of one type of conductivity, and a common elongated well of the opposite type of conductivity therebetween), and adjacent columns can have a mirrored layout. The biasing of the alternating P and N-wells over the buried N-well can be performed in a manner that enables pixel operation while still ensuring that the diodes created at the interface between each P-well and the adjacent N-wells to its sides and below are continuously negatively biased. By performing the layout and back biasing as described, no interruptions are required between the wells (e.g., no isolation regions are required), so that the electronic component blocks for the pixels and arrays of such blocks can be relatively compact and can meet the target area specifications of competitive products.

[0016] Figure 1 1 is a schematic diagram showing an embodiment of a compact in-pixel memory display structure 100 (also referred to herein as display structure 100 or structure 100), and also showing an embodiment of an electronic component block 101 for a pixel therein. Display structure 100 may include control circuit 180, at least a first portion 191 including electronic component block 101 for a pixel (wherein block 101 communicates with control circuit 180), and a second portion 192 including optical components, in particular, LED 140 for the pixel. Within display structure 100, the two portions 191-192 may be stacked, and the electrical and optical components thereon may be electrically connected, as discussed in detail below.

[0017] More specifically, the second portion 192 may include LEDs 140 (e.g., uLEDs) for pixels arranged in an array across the substrate. The array may include one LED 140 for each pixel in the display structure 100. Each LED 140 may include an anode and a cathode. In response to a forward bias, in particular, in response to a positive voltage signal received at the anode of the LED 140 of the pixel from the drive circuit 130 in the electronic component block 101 for the pixel in the first portion 191, as described below, the LED 140 may become conductive (i.e., a forward current may pass through) and may emit a visible light signal at the cathode.

[0018] In the disclosed embodiments (as discussed in more detail below), multi-bit in-pixel memory can be used to implement different forward bias conditions on the LED, thereby respectively implementing emitted light signals with different grayscale resolutions over the entire range of possible grayscale resolutions from dark to bright (as the forward current increases). Various different structural configurations of LEDs (including ultra-LEDs (uLEDs)) on substrates are well known in the art, and therefore, the present disclosure omits their details in order to allow the reader to focus on the salient aspects of the disclosed embodiments related to the electronic components of the display structure 100 in the first portion 191.

[0019] For the purpose of illustration, the disclosed display structure 100 is described herein and shown in the accompanying drawings as a monochrome display. In this case, the forward bias condition on the LED of the pixel can be selectively adjusted so that the light signal emitted from the LED is at a specific grayscale resolution ranging from dark gray to white (e.g., a smaller forward current results in a relatively dark light signal, and vice versa). When the LED is turned off, the pixel is black. However, it should be understood that the present disclosure is not intended to be limiting, and alternatively, the features described herein for the pixels of the monochrome display can be applied to each of the red, blue and green pixels of the color pixels of the color display. That is, for a color display, each color pixel can include a group of pixels: a red pixel with a red filter thereon, a blue pixel with a blue filter thereon, and a green pixel with a green filter thereon. Given a combination of the emitted light signals from each of the red, blue and green pixels, different colors and their chromaticities can be achieved by the color pixels. In this case, the forward bias condition on the LED of the red pixel in the color pixel can be selectively adjusted so that the light signal emitted from the LED is at a specific red grayscale resolution (e.g., from dark red to white). The forward bias condition on the LED of the blue pixel in the color pixel can be selectively adjusted so that the light signal emitted from the LED is at a specific blue grayscale resolution (e.g., from dark blue to white). The forward bias condition on the LED of the green pixel in the color pixel can be selectively adjusted so that the light signal emitted from the LED is at a specific green grayscale resolution (e.g., from dark green to white). If the LEDs of the red, blue, and green pixels are all turned off, the color pixel will be black.

[0020] The first portion 191 of the display structure 100 and the optional control circuit 180 may be implemented in a fully depleted semiconductor-on-insulator process technology platform (eg, a FDSOI process technology platform). Figure 2A As shown, the structure may include a semiconductor substrate 201 and a first portion 191 located on the semiconductor substrate 201. The semiconductor substrate 201 may be, for example, a single crystal silicon substrate or a substrate of any other suitable single crystal semiconductor material (e.g., silicon germanium, etc.). The semiconductor substrate 201 may also include a semiconductor-on-insulator region (e.g., an SOI region).

[0021] Each semiconductor-on-insulator region may include an insulator layer 202 located on a semiconductor substrate 201. The insulator layer 202 may be, for example, a thin silicon dioxide layer or a relatively thin layer of any other suitable insulator material. Each semiconductor-on-insulator region may include a thin semiconductor layer 206 located on the insulator layer 202. The semiconductor layer 206 may be, for example, a single crystal silicon layer or a layer of any other suitable single crystal semiconductor material (e.g., silicon germanium, etc.).

[0022] The semiconductor substrate 201 may also include a plurality of well regions (wells) 151-153. For the purposes of the present disclosure, a well region or well refers to a region of semiconductor material that is doped (e.g., via a dopant implantation process or any other suitable doping process) to have a specific conductivity type (i.e., P-type conductivity or N-type conductivity). The well regions (wells) may, for example, include a P-well 151 (i.e., a P-type well region) and an N-well 152 (i.e., an N-type well region) located in an upper portion of the semiconductor substrate 201 (e.g., at the top surface of the semiconductor substrate 201 adjacent to the insulator layer 202). The P-well 151 and the N-well 152 may be alternately elongated (e.g., strips) and positioned laterally adjacent to each other across the semiconductor substrate 201 or a portion thereof. The well region may also include an additional N-well, in particular, a buried N-well 153 within the semiconductor substrate 201, which is located below the upper portion of the semiconductor substrate 201, in particular below the P-well 151 and the N-well 152 (without interruption), and above the lower portion of the semiconductor substrate 201 (e.g., a certain distance from the bottom surface of the semiconductor substrate 201). It should be noted that each P-well 151 may be laterally surrounded by an N-well 152 extending vertically to the buried N-well 153, thereby electrically isolating the P-well 151 from the lower portion of the underlying semiconductor substrate 201, as long as the PN junction diode formed between each P-well 152 and the adjacent N-well 152-153 remains reverse biased. Those skilled in the art will recognize that a reverse biased diode does not conduct due to a negative voltage on the anode and a positive voltage on the cathode, while a forward biased diode conducts due to a positive voltage on the anode and a negative voltage on the cathode.

[0023] The semiconductor substrate 201 may also include body regions (also referred to as mixed regions). These regions may not have an insulator layer 202, but may include a P-well contact region 155 (also referred to herein as a P-tap) and an N-well contact region 156 (also referred to herein as an N-tap) located on the semiconductor substrate 201 and adjacent to the P-well 151 and the N-well 152, respectively, and electrically isolated from the active device region of the transistor (e.g., by an isolation structure 205). The well contact regions 155, 156 may, for example, include an epitaxially grown single crystalline semiconductor layer (e.g., an epitaxially grown silicon layer or an epitaxially grown layer of any other suitable semiconductor material) located on the top surface of the semiconductor substrate 201 and adjacent to the P-well 151 and the N-well 152, respectively. Each P-well contact region 155 may be doped (e.g., in-situ doped or subsequently implanted) to have P-type conductivity, optionally at a higher conductivity level than the underlying P-well 151. Each N-well contact region 156 may be doped (eg, in-situ or subsequently implanted) to have N-type conductivity, optionally at a higher conductivity level than the underlying N-well 152. Optionally, contact regions 155-156 may also include a silicide layer (not shown) thereon.

[0024] In each semiconductor-on-insulator region, the semiconductor layer 206 may further include an isolation structure 205. The isolation structure 205 may, for example, be a shallow trench isolation (STI) structure including a trench that vertically extends through the semiconductor layer 206 to or through the insulator layer 202, is filled with one or more layers of isolation material (e.g., silicon dioxide, silicon nitride, silicon oxynitride, or any other suitable isolation material), and defines the boundaries of the front-end-of-line (FEOL) device region and provides isolation between the FEOL device regions. The FEOL device region may, for example, include an active device region for a transistor (e.g., a field effect transistor (FET)), including a P-type transistor (e.g., a P-channel field effect transistor) and an N-type transistor (e.g., an N-channel field effect transistor (NFET)).

[0025] Each FET may further include a channel region (C) located between a source region and a drain region (S / D) within its active device region. In a PFET, the source / drain region may have a relatively high conductivity level of P-type conductivity (e.g., may be a P+ source / drain region), and the channel region may be intrinsic (i.e., undoped) or may have a relatively low conductivity level of N-type conductivity (e.g., may be an N-channel region). In an NFET, the source / drain region may have a relatively high conductivity level of N-type conductivity (e.g., may be an N+ source / drain region), and the channel region may be intrinsic (i.e., undoped) or may have a relatively low conductivity level of P-type conductivity (e.g., may be a P-channel region).

[0026] Each FET may also include a main gate (also referred to herein as a front gate) adjacent to the active device region at the channel region (e.g., located above and immediately adjacent to the active device region). Those skilled in the art will recognize that in a field effect transistor (FET), a gate (also referred to as a gate structure) may include a gate dielectric layer (including one or more layers of gate dielectric material) immediately adjacent to the channel region and a gate conductor layer (including one or more layers of gate conductor material) located on the gate dielectric layer. In each FET, the main gate may include at least a relatively thin gate dielectric layer immediately adjacent to the top surface of the semiconductor layer 206 at the channel region and a gate conductor layer located on the gate dielectric layer. The main gate may be any of a gate-first polysilicon gate structure, a gate-first high-K metal gate (HKMG) structure, a gate-last HKMG structure (also referred to as a replacement metal gate (RMG) structure), or any other suitable type of gate structure. Optionally, the main gate of the PFET may include a different gate material than the main gate of the NFET and may therefore have a different work function. Gate sidewall spacers may be positioned laterally adjacent to the sidewalls of the main gate (e.g., to electrically isolate the gate structure from adjacent S / D regions). Such gate structures are well known in the art, and therefore, details thereof are omitted from the specification to allow the reader to focus on the salient aspects of the disclosed embodiments.

[0027] Each FET may also include a secondary gate (also referred to herein as a back gate) adjacent to the active device region (e.g., located below and immediately adjacent to the active device region) opposite the main gate. The secondary gate may include an adjacent portion of the insulator layer 202 and the underlying well region 151 or 152.

[0028] Those skilled in the art will recognize that one advantage of a fully depleted semiconductor-on-insulator (e.g., FDSOI) technology processing platform is that NFETs and PFETs can be formed on an insulator layer above an N-well or P-well to implement different types of NFETs or PFETs with different threshold voltages (VT). For example, for a super low threshold voltage (SLVT) or low threshold voltage (LVT) FET, an NFET can be formed above the N-well 152, and a PFET can be formed above the P-well 151. For a normal threshold voltage (RVT) or high threshold voltage (HVT) FET, an NFET can be formed above the P-well 151, and a PFET can be formed above the N-well 152. Typically, a circuit block will include all SLVT (or LVT) FETs with NFETs above the N-well and PFETs above the P-well, or all RVT (or HVT) FETs with NFETs above the P-well and PFETs above the N-well. Those skilled in the art will recognize that whether a FET is a SLVT or LVT FET, or whether a FET is a RVT or HVT FET, will depend on the design (eg, device size, etc.) and process specifications (eg, dopant concentration, etc.).

[0029] Another advantage of the fully depleted semiconductor-on-insulator (e.g., FDSOI) technology processing platform is that back-gate biasing (referred to as back biasing) can be used to fine-tune the FET VT. Forward back biasing (FBB) refers to applying a gate bias voltage to the back gate (particularly, to its well region) to reduce the VT of the FET, thereby increasing the switching speed. Typically, for PFETs, FBB is achieved by applying 0 volts (i.e., ground voltage) or a negative gate bias voltage to the well region; while for NFETs, FBB is achieved by applying a positive gate bias to the well region. Reverse back biasing (RBB) specifically refers to applying a gate bias voltage to the back gate (particularly, to its well region) to increase the VT of the FET, thereby reducing the switching speed and reducing leakage current. Typically, for PFETs, RBB is achieved by applying a positive gate bias voltage to the well region; while for NFETs, RBB is achieved by applying a negative gate bias voltage to the well region. Figure 2B is a table showing possible back bias conditions that may be used without forward biasing the PN junction diode between the P-well and adjacent N-well 152 - 153 .

[0030] The first portion 191 may also include middle of the line (MOL) layers and back end of the line (BEOL) layers stacked above the FEOL devices. The MOL and BEOL layers may include one or more layers of interlayer dielectric (ILD) material, as well as MOL contacts and other interconnects (BEOL lines and / or vias) within the ILD material to provide electrical connections between FEOL devices and / or to optical components in the second portion 192. Such MOL and BEOL layers including MOL contacts and BEOL interconnects are well known in the art. Therefore, these MOL and BEOL features have been omitted from the drawings, and their details have been further omitted from the description, to avoid clutter in the drawings and to allow the reader to focus on the salient aspects of the disclosed embodiments.

[0031] In the first part 191, blocks 101 each having electronic components for a pixel may be arranged in columns (C0-C1). x ) and row (R0-R y ). For ease of illustration, the columns (C0-C x ) are shown as being oriented in the X direction (ie, from left to right across the page), while rows (R0-R y ) is shown as being oriented in the Y direction (i.e., from top to bottom across the page). In any case, each column will have y blocks and each row will have x blocks. Each block 101 may include an array 110 of memory cells, logic circuitry 120, and drive circuitry 130.

[0032] Figures 3A-3C is a circuit diagram showing components of the first portion 191 and control circuitry connected thereto (eg, pixel-specific PWM generation logic 185 ). Figures 4A-4C is with Figures 3A-3C The components shown and a timing diagram associated with the operation of the LED 140 of the second portion 192.

[0033] like Figure 3A As shown, within each block 101, memory cells 3000-300 n The array 110 of memory cells may be located on the insulator layer 202, specifically above the P-well 151 in the semiconductor substrate 201. The array 110 of memory cells may include memory cells 3000-300 n A single column (c0) and multiple rows (r0-r n ), each row having a single memory cell (ie, r0 includes memory cell 3000, and so on). For ease of illustration, memory cells 3000-300 nA single column (c0) of is shown as being oriented in the X direction (i.e., from left to right across the page). The array 110 may also include a first write bit line 301 (e.g., a true bit line (BLT)) and a second write bit line 302 (e.g., a complementary bit line (BLC)) that are electrically connected to all memory cells 300-300 in the column. n The array 110 may also include a read bit line 303 that is electrically connected to all memory cells 3000-3000 in the column. n , to read from memory cell 3000-300 during a read operation n The array 110 may further include word line pairs for rows. Specifically, the array 110 may include a plurality of write word lines and a plurality of read word lines. For each row, the word lines include corresponding write word lines 3040-304 n (It is connected to the control circuit 180 to receive the corresponding write word line signal (WWL0-WWL n )) and read word lines 3050-305 n (It is connected to the control circuit 180 to receive the read word line selection signal (RWL0-RWL n ). For a given row, the corresponding write and read word lines can each be electrically connected to one memory cell within the given row. In some embodiments, array 110 may include a total of twelve memory cells (i.e., twelve rows of single memory cells in a column) for full grayscale resolution. As discussed in more detail below with respect to read operations and as described in Figure 4A As shown in the timing diagram, RWL0-RWL n may be received from the control circuit 180 and may have a gradually increasing pulse width. That is, the RWL on the read word line for a row in the memory cell array for a pixel will have different pulse widths, more specifically, RWL0-RWL n The pulse width will be between row r0 and row r n Each memory cell is incremented row by row. n A data value of "1" or "0" may be stored. It should be noted that the control circuit 180 may be on the same substrate as the first portion 191, but located at a different position.

[0034] For example, each memory cell 3000-300 nIt may be an eight-transistor static random access memory (8T-SRAM) cell. The 8T-SRAM cell may include a first inverter including a first pull-up transistor 311 (PFET) and a first pull-down transistor 312 (NFET) connected in series between a positive power supply voltage (VDD) rail and ground. The first inverter may also include a first storage node 314 (ST) and a first common gate node 315, the first storage node 314 being located at a junction between the first pull-up transistor 311 and the first pull-down transistor 312, and particularly being located at an electrical connection between the first pull-up and pull-down transistors 311-312, the first common gate node 315 being electrically connected to the gates of the first pull-up and pull-down transistors 311-312. The 8T-SRAM cell may also include a second inverter including a second pull-up transistor 321 (PFET) and a second pull-down transistor 322 (NFET) connected in series between the VDD rail and ground. The second inverter may further include a second storage node 324 (SC) and a second common gate node 325, wherein the second storage node 324 is located between the second pull-up transistor 321 and the second pull-down transistor 322, and in particular, is located at the electrical connection between the second pull-up and pull-down transistors 321-322, and the second common gate node 325 is electrically connected to the gates of the second pull-up and pull-down transistors 321-322. The first and second inverters may also be cross-coupled. That is, the first storage node 314 may be electrically connected to the second common gate node 325, and the second storage node 324 may be electrically connected to the first common gate node 315.

[0035] Each 8T-SRAM cell may also include a pair of transmission gate transistors (NFETs), in particular, a first transmission gate transistor 313 and a second transmission gate transistor 323. The first transmission gate transistor 313 may be connected between the first write bit line 301 (BLT) and the first storage node 314 (ST), and may also have a gate connected to the write word line for the corresponding row. The second transmission gate transistor 323 may be connected between the second write bit line 302 (BLC) and the second storage node 324 (SC), and may also have a gate connected to the write word line 304.

[0036] Each 8T-SRAM cell may further include two additional pull-down transistors 331-332 (NFETs) electrically connected in series between the read bit line 303 and ground. The gates of the two additional pull-down transistors 331-332 are connected to the read word line for the corresponding row and the first storage node 314, respectively.

[0037] As described above, the array 110 is specifically located on the insulator layer 202 above the P-well 151. Therefore, in each 8T-SRAM cell, the first and second pull-up transistors 311 and 321 are LVT (or SLVT) PFETs. In addition, the first and second pull-down transistors 312 and 322, the first and second transmission gate transistors 313 and 323, and the two additional pull-down transistors 331-332 are RVT (or HVT) NFETs.

[0038] It should be understood that the memory cells 3000-300 n The array 110 (particularly, various bit lines and word lines) of the memory cell will be electrically connected to the control circuit 180 (including but not limited to a column address decoder and a row address decoder in communication with the controller) to facilitate the write operation of storing data on the first storage node 314 (ST) of the memory cell, and further facilitate the read operation of reading out the stored data so that the LED 140 generates a light signal with a specific grayscale resolution. In general, the control circuit of the SRAM structure is well known in the art. Therefore, except for the following description (for example, with respect to RWL0-RWL with gradually increasing pulse widths) n , and pixel-specific PWM generation logic 185), the details of the control circuit 180 have been omitted from the present specification and the drawings so that the reader can focus on the significant aspects of the disclosed embodiments and avoid confusing the drawings. In any case, like conventional 6T-SRAM, each 8T-SRAM primitive can operate in three different modes: standby, write, and read. In standby mode, the primitive is in an idle state. In write mode, a data value can be written (i.e., stored) on the first storage node 314 (ST). For example, if a data value "1" (i.e., a high data value) is to be written to the first storage node 314 (ST), the control circuit 180 can cause the first write bit line 301 (BLT) to be precharged and the second write bit line 302 (BLC) to be discharged to ground. Then, the control circuit 180 can cause WWL on the write word line to be pulsed to a high voltage level to turn on the first and second transfer gate transistors 313 and 323, thereby storing the data value "1" on the first storage node 314 (ST). Conversely, if a data value of "0" (i.e., a low data value) is to be written to the first storage node 314 (ST), the control circuit 180 may cause the first write bit line 301 (BLT) to be discharged to ground and the second write bit line 302 (BLC) to be precharged. The control circuit 180 may then cause WWL on the write word line to be pulsed to a high voltage level to turn on the first and second transfer gate transistors 313, 323, thereby storing the data value "0" on the first storage node 314 (ST).

[0039] like Figure 3BAs shown, each block 101 may further include a driving circuit 130 and a logic circuit 120 . The driving circuit 130 is electrically connected to the anode of the LED 140 , and the logic circuit 120 is electrically connected between the array 110 and the driving circuit 130 .

[0040] Logic circuit 120 may have an input node 309 electrically connected to a read bit line 303 of array 110, and may also include a combination of a P-type transistor (PFET) and an N-type transistor (NFET). Specifically, logic circuit 120 may also include a P-type transistor (PFET) 341, in particular, a reset pull-up transistor, electrically connected between the VDD rail and input node 309, and having its gate electrically connected to reset line 306. Reset line 306 may be electrically connected to receive a reset control signal (RESETB) (e.g., from control circuit 180). Those skilled in the art will recognize that if reset line 306 is discharged to ground (i.e., if RESETB is low), reset pull-up transistor 341 will turn on and pull the voltage on read bit line 303 up to VDD, and if reset line 206 is charged (i.e., if RESETB is high), reset pull-up transistor 341 will turn off.

[0041] The logic circuit 120 may also include a keeper circuit 350. The keeper circuit 350 may be a latch that stores a data value previously read from one of the SRAM cells in the memory array 110 until RESETB is asserted low. The latch may include a plurality of P-type transistors (PFETs) (e.g., three PFETs 351-353) electrically connected in series between the VDD rail and an intermediate node 359 (which is electrically connected to the input node 309). The latch may also include a plurality of N-type transistors (NFETs) (e.g., three NFETs 354-356) electrically connected in series between the intermediate node 359 and ground. Finally, the latch may include an inverter 360. The inverter 360 may include a P-type transistor (PFET) 361 and an N-type transistor (NFET) 362 electrically connected in series between the VDD rail and ground. Inverter 360 may also include an inverter input terminal 363, in particular, a common gate node, which is electrically connected to the intermediate node 359 and the gates of PFET 361 and NFET 362. Inverter 360 may also include an inverter output terminal 364 located at the junction between the drain regions of PFET 361 and NFET 362 (i.e., located at the electrical connection). Inverter output terminal 364 may output a latch signal (LATCH) and may be further electrically connected to keeper circuit 350 in a feedback loop. Specifically, inverter output terminal 364 may be electrically connected to the common gate node of the gates of PFETs 351-353, and also electrically connected to the common gate node of the gates of NFETs 354-356. Therefore, the states of PFETs 351-353 and NFETs 354-356 are controlled by LATCH.

[0042] The logic circuit 120 may also include a NAND gate 370 (which effectively functions as a pulse width controller for the driver circuit 130, as described below). The NAND gate 370 may include a pair of P-type transistors (PFETs) 371-372 connected in parallel between the VDD rail and a NAND gate output node 379. The NAND gate 370 may also include a pair of N-type transistors (NFETs) 373-374 electrically connected in series between the NAND gate output node 379 and ground. The NAND gate 370 may also have a first NAND gate input node 378 electrically connected to the inverter output terminal 364 to receive LATCH, and further electrically connected to the gates of the PFET 371 and the NFET 373. The NAND gate 370 may also have a second NAND gate input node that is electrically connected to receive a pulse width modulated signal (PWM) 307 (from the pixel-specific PWM generation logic 185, as discussed in more detail below), and further electrically connected to the gates of the PFET 372 and the NFET 374. Such a NAND gate 370 may operate according to a conventional NAND gate truth table. That is, the output signal (PB) at the NAND gate output node 379 will only be pulled to a low voltage level (i.e., a logic "0") when the voltage level at the inverter output terminal 364 of the inverter 360 is high and PWM is high. Otherwise, the PB at the NAND gate output node 379 will be at a high voltage level (i.e., a logic "1").

[0043] In this logic circuit 120, all of the PFETs 341, 351-353, 361, and 371-372 may be located on the insulator layer 202 and aligned over the N-well 152, which is laterally located adjacent to the P-well 151 in which the array 110 is located. In addition, in the logic circuit 120, the NFETs 354-356, 362, and 373-374 may be located on the insulator layer 202 and aligned over the same P-well 151 in which the array 110 is located. Therefore, in the logic circuit 120, the PFETs may all be RVT (or HVT) PFETs, and the NFETs may all be RVT (or HVT) NFETs.

[0044] The driver circuit 130 may include two additional P-type transistors (PFETs) 381-382 that are electrically connected in series between the VDD rail and a driver circuit output node 389. The driver circuit output node 389 may be electrically connected (e.g., through a combination of interconnects including, but not limited to, MOL contacts, BEOL vias and / or wiring, and through substrate vias (TSVs)) to the anode of a corresponding LED 140 in the second portion 192. In this driver circuit 130, the gates of the PFETs 381-382 may be connected to receive PB from the NAND gate output node 379, and also connected to receive another gate bias voltage (VB) 308 (i.e., a driver circuit enable signal from the control circuit 180, for example). In operation, when both PB and VB are low, the LED 140 will become forward biased and a visible light signal will be emitted at the cathode. However, the length of time that PB is low (i.e., the pulse width of PB between the falling edge and the rising edge) will be a function of the pulse width (between the rising edge and the falling edge) of the PWM generated by the pixel-specific PWM generation logic 185, and the specific grayscale resolution of the emission light signal from the LED 140 will vary depending on the pulse width. For example, if the pulse width of the PWM, and thus the pulse width of the PB, is relatively short during the forward bias of the LED 140, the specific grayscale resolution of the emission light signal from the LED 140 will be relatively low (e.g., dark gray). If the PWM, and thus the PB, has a minimum pulse width, the specific grayscale resolution of the emission light signal from the LED 140 may be at a minimum level (e.g., at the darkest gray level). If the pulse width of the PWM, and thus the pulse width of the PB, is relatively long during the forward bias of the LED 140, the specific grayscale resolution of the emission light signal from the LED 140 will be relatively high (e.g., light gray). If PWM, and thus PB, has a maximum pulse width, a particular grayscale resolution of the emission light signal from LED 140 may be at a maximum level (eg, white).

[0045] In this driver circuit 130, all PFETs 381-382 may be located on the insulator layer 202 and aligned over the same N-well 152 as the PFETs of the logic circuit 120. Thus, in the driver circuit 130, the PFETs may all be RVT (or HVT) PFETs.

[0046] As described above, the memory cells 3000-300 n (ie, SRAM cells) can store data values ​​"1" or "0". In addition, the memory cells 3000-300 are electrically connected to the memory cells 3000-300 n RWL0-RWL nIt can be received from the control circuit 180 and can have a gradually increasing pulse width. For each pixel, RWL0-RWL n It can also be electrically connected to the corresponding pixel specific PWM generation logic 185 (e.g., Figure 3C Pixel specific PWM generation logic 185 can be configured to monitor RWL0-RWL n and adjust the PWM accordingly. For example, the pixel-specific PWM generation logic 185 may include an OR gate 391 that is electrically connected to receive RWL0-RWL n Each of RWL0-RWL1 is used as an input. OR gate 391 can be configured to output an intermediate output signal 392 according to a conventional OR gate truth table. That is, when RWL0-RWL n When all are low (ie, at logic "0"), the intermediate output signal 392 may be at logic "0", and when RWL0-RWL n When any of is high (i.e., at logic "1"), the intermediate output signal 392 can be at logic "1". The pixel-specific PWM generation logic 185 can also include a delay component 393 (e.g., including four inverters 394a-394d connected in series), which is electrically connected to receive the intermediate output signal 392 from the OR gate 391 and output a delayed output signal 395. The pixel-specific PWM generation logic 185 can also include an AND gate 396, which is electrically connected to receive the delayed output signal 395 from the delay component 393 and an enable signal (EN) (e.g., from the control logic) as inputs. The AND gate 396 can be configured to output PWM to the NAND gate 370 of the logic circuit 120 according to a conventional AND gate truth table. That is, when both the delayed output signal 395 from the delay component 393 and the EN signal are high (i.e., at logic "1"), the PWM will be high (i.e., at logic "1"). Otherwise, the PWM will be low.

[0047] In memory primitives 3000-300 n During a read operation of a selected memory cell, EN will be toggled high, RWL0-RWL n One of them will be pulsed so that the memory cell 3000-300 n The selected memory cell in the reads the stored data. n When one of the EN is high, the intermediate output signal 392 will be high, and the delayed output signal 395 from the delay component 393 will become high. When the delayed output signal 395 and EN are high, the PWM output from the AND gate 396 will be high. Therefore, if Figure 4AAs shown, if the memory cell 3000 is selected for the read operation, RWL0 having the shortest pulse width will be pulsed, and PWM will remain high for a relatively short period of time, whereas if the memory cell 3000 is selected for the read operation, RWL0 having the shortest pulse width will be pulsed, and PWM will remain high for a relatively short period of time. n is selected for the read operation, the RWL with the shortest pulse width n will be pulsed, and PWM will remain high for a relatively long period of time.

[0048] More specifically, Figure 4B 341 is a timing diagram showing various signals in the in-pixel memory during a first read cycle of the memory cell 3000 when the memory cell 3000 stores a data value of "0", and during a second read cycle of the memory cell 3000 when the memory cell 3000 stores a data value of "1". As described above, the pulse width of RWL0 is relatively short, and therefore, PWM will be relatively short. At the beginning of the first read cycle of the memory cell 3000 when the memory cell 3000 stores a data value of "0" (i.e., when ST is low), RESETB is pulsed low to turn on PFET 341, thereby pulling up / resetting the voltage level on the read bit line 303. RWL0 is pulsed high. Since BLT is low, BLC is high, ST is low, and SC is high, RBL will be pulled low and cause LATCH to be pulled high. Then, when PWM is pulsed high (for a short period of time) and LATCH is high, the PB output from the NAND gate 370 will be low. As a result, PFET 381 of driver circuit 130 will turn on, and LED 140 will be turned on for a period of time set by the relatively short PWM pulse width (e.g., for a dark gray light signal). At the beginning of the second read cycle of memory cell 3000 when memory cell 3000 stores a data value of "1" (i.e., when ST is high), RESETB is pulsed low to turn on PFET 341, thereby pulling up / resetting the voltage level on read bit line 303. RWL0 is pulsed high. Since BLT is high, BLC is low, ST is high, and SC is low, RBL will remain high and cause LATCH to be low. If LATCH is low, the PB output from NAND gate 370 will be high (regardless of the pulse width of PWM), and LED 140 will remain off.

[0049] Figure 4C is shown when the memory cell 300 n Memory cell 300 when storing data value "0" n During the first read cycle, and when the memory cell 300 n Memory cell 300 when storing data value "1" n The timing diagram of various signals in the pixel memory during the second read cycle of FIG. As described above, RWLn The pulse width is relatively long, so the PWM will be relatively long. n Memory cell 300 storing a data value of "0" (ie, when ST is low) n At the beginning of the first read cycle, RESETB is pulsed low to turn on PFET 341, thereby pulling up / resetting the voltage level on read bit line 303. n is pulsed high. Since BLT is low, BLC is high, ST is low, and SC is high, RBL will be pulled low and cause LATCH to be pulled high. Then, when PWM is pulsed high (for a long period of time) and LATCH is high, the PB output from NAND gate 370 will be low. As a result, PFET 381 of driver circuit 130 will turn on, and LED 140 will turn on for a period of time set by the relatively long PWM pulse width (e.g., for a white light signal). When memory cell 300 is turned on, the LED 140 will be turned on for a period of time set by the relatively long PWM pulse width (e.g., for a white light signal). n At the beginning of the second read cycle of the memory cell 3000 storing a data value of "1" (ie, when ST is high), RESETB is pulsed low to turn on PFET 341, thereby pulling up / resetting the voltage level on the read bit line 303. n Since BLT is high, BLC is low, ST is high, and SC is low, RBL will remain high and cause LATCH to be low. If LATCH is low, the PB output from NAND gate 370 will be high (regardless of the pulse width of PWM), and LED 140 will remain off.

[0050] As described above, in the first portion 191, the blocks 101 each having electronic components for a pixel may be arranged in columns (C0-C1). x ) and row (R0-R y ) array. Figure 5 is a diagram showing an example of a layout (also referred to herein as a floor plan) that may be employed to achieve a compact display structure. For ease of explanation, Figure 5 The layout diagram of FIG. 1 shows four columns (C0-C3) and four rows (R0-R3) of block 101. It should be understood that Figure 5It is not intended to be limiting, and alternatively, such an array may include any number of one or more columns and one or more rows. In any case, as shown, each column may be aligned above an elongated P-well 151 and an elongated N-well 152 positioned laterally adjacent to the elongated P-well 151. Each block 101 of electronic components for a pixel may cover a P-well to N-well interface, wherein the entire memory array 110 and the NFETs 354-356, 362, and 373-374 of the logic circuit 120 are located above the P-well 151, and the entire drive circuit 130 and the PFETs 341, 351-353, 361, and 371-372 of the logic circuit are located above the N-well 152. For ease of illustration, each block 101 is shown as including one P-well contact region 155 (i.e., one P tap) and one N-well contact region 156 (i.e., one N tap). It should be noted that the number of taps in each well region should be sufficient to ensure that the entire well region is adequately biased. Thus, for example, each block 101 may require more than one P-tap and more than one N-tap, or only one P-tap and one N-tap may be required every several blocks 101. The number of taps will be determined based on the design rules of the technology node in question.

[0051] It should be noted that in order to achieve the required compact structure, in particular, in order to use the chip area more effectively, a buried N-well (not shown) can be located below all the elongated P-wells and N-wells 151-152 without any interruption (i.e., without any isolation region). In addition, adjacent elongated P-wells and N-wells 151-152 can each include a wide portion and a narrow portion having an interlocking step shape (in contrast to the case where the adjacent P-well or N-well is simply a relatively wide elongated rectangular shape). As shown in the figure, the wide portion of the P-well can be adjacent to the narrow portion of the N-well, and vice versa, to accommodate the placement of various P-type and N-type transistors of the block 101 thereon as described above. In addition, adjacent electronic component blocks 101 in each column can have a mirror block layout. That is, as shown in the figure, the array 110 of the memory cells of the block can be arranged in line across the elongated P-well. However, in the same column, the first and second blocks 101 will have adjacent driver circuits 130 on the wide portion of the N-well, the second and third blocks will have adjacent logic circuits 120 over the interface between the wide portion of the P-well and the narrow portion of the N-well, and so on. Finally, adjacent columns of blocks 101 may have mirrored column layouts aligned over three different wells (including two wells of one type of conductivity and a common well of the opposite type of conductivity therebetween) (e.g., over two P-wells and a common N-well therebetween, or over two N-wells and a common P-well therebetween). For example, as Figure 5As shown, adjacent columns C0 and C1 of block 101 have a mirrored column layout aligned over two P-wells and a common N-well therebetween; adjacent columns C1 and C2 of block 101 have a mirrored column layout aligned over two N-wells and a common P-well therebetween; and, adjacent columns C2 and C3 of block 101 have a mirrored column layout aligned over two P-wells and a common N-well therebetween.

[0052] It should be understood that in the above structures and methods, semiconductor materials refer to materials whose conductive properties can be changed by doping with impurities. Such semiconductor materials include, for example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, silicon germanium carbide, silicon carbide, etc.) and III-V compound semiconductors (i.e., compounds obtained by combining III-group elements such as aluminum (Al), gallium (Ga) or indium (In) with V-group elements such as nitrogen (N), phosphorus (P), arsenic (As) or antimony (Sb)) (e.g., GaN, InP, GaAs or GaP). Pure semiconductor materials, more specifically, semiconductor materials that are not doped with impurities to increase conductivity (i.e., undoped semiconductor materials) are referred to in the art as intrinsic semiconductors. Semiconductor materials doped with impurities to increase conductivity (i.e., doped semiconductor materials) are referred to in the art as non-intrinsic semiconductors and will be more conductive than intrinsic semiconductors made from the same substrate. That is, non-intrinsic silicon is more conductive than intrinsic silicon; non-intrinsic silicon germanium is more conductive than intrinsic silicon germanium; and so on. In addition, it should be understood that different impurities (i.e., different dopants) can be used to achieve different conductivity types (e.g., P-type conductivity and N-type conductivity), and the dopants can vary depending on the different semiconductor materials used. For example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, etc.) are typically doped with Group III dopants such as boron (B) or indium (In) to achieve P-type conductivity, while silicon-based semiconductor materials are typically doped with Group V dopants such as arsenic (As), phosphorus (P), or antimony (Sb) to achieve N-type conductivity. Gallium nitride (GaN)-based semiconductor materials are typically doped with magnesium (Mg) to achieve P-type conductivity, and doped with silicon (Si) or oxygen to achieve N-type conductivity. Those skilled in the art will also recognize that different conductivity levels depend on the relative concentration levels of (one or more) dopants in a given semiconductor region. In addition, when a semiconductor region or layer is described as being at a higher conductivity level than another semiconductor region or layer, its conductivity is higher (lower resistance) than the other semiconductor region or layer; and when a semiconductor region or layer is described as being at a lower conductivity level than another semiconductor region or layer, its conductivity is lower (higher resistance) than the other semiconductor region or layer.

[0053] It should be understood that the terms used herein are used to describe the disclosed structures and methods and are not intended to be limiting. For example, as used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. In addition, as used herein, the terms "comprises", "comprising", "includes", and / or "including" specify the presence of the features, wholes, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts, and / or groups thereof. In addition, as used herein, when oriented and shown in the figures, terms such as "right", "left", "vertical", "horizontal", "top", "bottom", "upper", "lower", "below", "under", "underlying", "above", "overlying", "parallel", "vertical", etc. are intended to describe relative positions (unless otherwise specified), and terms such as "touching", "direct contact", "adjacent", "directly adjacent", "immediately adjacent", etc. are intended to indicate that at least one element is in physical contact with another element (no other elements separate the elements). The term "laterally" is used herein to describe the relative position of elements and, more specifically, to indicate that one element is to the side of another element, rather than above or below the other element, when the elements are oriented and shown in the figures. For example, an element positioned laterally adjacent to another element will be to the side of the other element, an element positioned laterally next to another element will be directly to the side of the other element, and an element laterally surrounding another element will be adjacent to and bordering the outer sidewall of the other element. The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the following claims are intended to include any structure, material, or act for performing a function in combination with other claimed elements as specifically claimed.

[0054] The description of the various disclosed embodiments is given for the purpose of illustration, but is not intended to be exhaustive or limiting. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosed embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications or technical improvements to technologies found on the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure comprising: An array of memory cells located on an insulator layer above a P-well in a semiconductor substrate; a drive circuit located on the insulator layer above an N-well in the semiconductor substrate, wherein the N-well is located laterally adjacent to the P-well, and wherein the drive circuit is connected to an anode of a light emitting diode; and A logic circuit located on the insulator layer and connected to the array of memory cells and the drive circuit, wherein the logic circuit includes a P-type transistor located on the insulator layer above the N-well and an N-type transistor located on the insulator layer above the P-well.

2. The structure according to claim 1, further comprising: A P-well contact region, which is located on the P-well; An N-well contact region, which is located on the N-well; as well as An additional N-well is located in the semiconductor substrate and below the N-well and the P-well.

3. The structure according to claim 1, wherein: The array of memory cells comprises: A single column and multiple rows, where each row has a single memory cell; a first write bit line, a second write bit line, and a read bit line connected to all of said memory cells in said single column; and Write word lines and read word lines include: for each row, a write word line and a read word line connected to the single memory cell in the row.

4. The structure according to claim 3, wherein: The single rank includes twelve memory cells.

5. The structure according to claim 3, wherein: Each memory cell is an eight-transistor static random access memory cell consisting of: a first inverter including a first pull-up transistor and a first pull-down transistor connected in series, and a first storage node at a connection between the first pull-up transistor and the first pull-down transistor; a second inverter comprising a second pull-up transistor and a second pull-down transistor connected in series, and a second storage node at a connection between the second pull-up transistor and the second pull-down transistor, wherein the first inverter and the second inverter are cross-coupled; a first pass-gate transistor connected between the first write bit line and the first storage node, wherein a gate of the first pass-gate transistor is connected to the write word line; a second pass-gate transistor connected between the second write bit line and the second storage node, wherein a gate of the second pass-gate transistor is connected to the write word line; and Two additional pull-down transistors are connected in series between the read bit line and ground, wherein gates of the two additional pull-down transistors are connected to the read word line and the first storage node, respectively.

6. The structure according to claim 3, in, The logic circuit comprises: an input node connected to the read bit line; Reset line; a P-type transistor connected between the positive supply voltage rail and the input node; three P-type transistors connected in series between the positive supply voltage rail and the input node; three N-type transistors connected in series between the input node and ground; an inverter connected between the input node and the output node, wherein the P-type transistor has a gate connected to the reset line, wherein the three P-type transistors and the three N-type transistors have gates connected to the output node; and a NAND gate having an input connected to the output node and configured to receive a pulse width modulated signal, wherein a pulse width of the pulse width modulated signal depends on a pulse width of a read word line select signal connected to a read word line of a memory cell during a read operation for the memory cell, and Wherein, the pulse width of the read word line selection signal on the read word line increases row by row.

7. The structure according to claim 6, wherein: The drive circuit includes two additional P-type transistors connected in series between the positive supply voltage rail and the anode of the light emitting diode, wherein one of the two additional P-type transistors has a gate connected to the output of the NAND gate and the other of the two additional P-type transistors has a gate connected to receive a gate bias voltage.

8. The structure according to claim 1, wherein: The P-well and the N-well have interlocked step shapes.

9. A structure comprising: A semiconductor substrate comprising a P-well and an N-well adjacent to the P-well; an insulator layer located on the semiconductor substrate and above the P-well and the N-well; as well as Electronic component blocks for each pixel, wherein each block comprises: an array of memory cells located on the insulator layer above the P-well; a driving circuit located on the insulator layer above the N-well and connected to an anode of a light emitting diode; and A logic circuit is located on the insulator layer and connected between the array of memory cells and the drive circuit, wherein the logic circuit includes a P-type transistor located on the N-well and an N-type transistor located on the P-well.

10. The structure according to claim 9, further comprising: A P-well contact region, which is located on the P-well; An N-well contact region, which is located on the N-well; as well as An additional N-well is located in the semiconductor substrate and below the N-well and the P-well, wherein the additional N-well isolates the P-well from a lower portion of the semiconductor substrate.

11. The structure according to claim 9, wherein: The array of memory cells in each block comprises: a single column of said memory primitives and a plurality of rows, each row having a single memory primitive; a first write bit line, a second write bit line, and a read bit line connected to all of said memory cells in said single column; and Write word lines and read word lines, for each row, include write word lines and read word lines connected to the individual memory cells in the row.

12. The structure according to claim 11, wherein: The single column of memory cells includes twelve memory cells.

13. The structure according to claim 11, wherein: Each memory cell is an eight-transistor static random access memory cell consisting of: a first inverter including a first pull-up transistor and a first pull-down transistor connected in series, and a first storage node at a connection between the first pull-up transistor and the first pull-down transistor; a second inverter comprising a second pull-up transistor and a second pull-down transistor connected in series, and a second storage node at a connection between the second pull-up transistor and the second pull-down transistor, wherein the first inverter and the second inverter are cross-coupled; a first pass-gate transistor connected between the first write bit line and the first storage node, wherein a gate of the first pass-gate transistor is connected to the write word line; a second pass-gate transistor connected between the second write bit line and the second storage node, wherein a gate of the second pass-gate transistor is connected to the write word line; and Two additional pull-down transistors are connected in series between the read bit line and ground, wherein gates of the two additional pull-down transistors are connected to the read word line and the first storage node, respectively.

14. The structure according to claim 11, wherein: The logic circuit comprises: an input node connected to the read bit line; Reset line; a P-type transistor connected between the positive supply voltage rail and the input node; three P-type transistors connected in series between the positive supply voltage rail and the input node; three N-type transistors connected in series between the input node and ground; an inverter connected between the input node and the output node, wherein the P-type transistor has a gate connected to the reset line, and wherein the three P-type transistors and the three N-type transistors have gates connected to the output node; and a NAND gate having an input connected to the output node and configured to receive a pulse width modulated signal, wherein a pulse width of the pulse width modulated signal depends on a pulse width of a read word line select signal connected to a read word line of a memory cell during a read operation for the memory cell, and Wherein, the pulse width of the read word line selection signal on the read word line increases row by row.

15. The structure according to claim 14, wherein: The drive circuit includes two additional P-type transistors connected in series between the positive supply voltage rail and the anode of the light emitting diode, wherein one of the two additional P-type transistors has a gate connected to the output of the NAND gate and the other of the two additional P-type transistors has a gate connected to receive a gate bias voltage.

16. The structure according to claim 9, wherein: The P-well and the N-well have interlocked step shapes.

17. A structure comprising: A semiconductor substrate comprising alternating P-wells and N-wells; an insulator layer located on the semiconductor substrate and above the alternating P-wells and N-wells; as well as an array of electronic component blocks respectively for an array of pixels, The array of electronic component blocks includes at least two columns of electronic component blocks. wherein the at least two columns of electronic component blocks have a mirror image column layout aligned over two wells of one type of conductivity and a common well of the opposite type of conductivity therebetween, and Each electronic component block for each pixel includes: an array of memory cells located on the insulator layer above the P-well; a driving circuit located on the insulator layer above the N-well and connected to an anode of a light emitting diode; and A logic circuit is located on the insulator layer and connected between the array of memory cells and the drive circuit, wherein the logic circuit includes a P-type transistor located on the N-well and an N-type transistor located on the P-well.

18. The structure of claim 17, further comprising: A P-well contact region, which is located on the P-well; An N-well contact region, which is located on the N-well; as well as An additional N-well is located in the semiconductor substrate and below the N-well and the P-well, wherein the additional N-well isolates the P-well from a lower portion of the semiconductor substrate.

19. The structure of claim 17, wherein: The array of memory cells comprises: a single column of said memory primitives and a plurality of rows, each row having a single memory primitive; a first write bit line, a second write bit line, and a read bit line connected to all of said memory cells in said single column; and Write word lines and read word lines, for each row, include write word lines and read word lines connected to the individual memory cells in the row.

20. The structure according to claim 19, in, The logic circuit in each block includes: an input node connected to the read bit line; Reset line; a P-type transistor connected between the positive supply voltage rail and the input node; three P-type transistors connected in series between the positive supply voltage rail and the input node; three N-type transistors connected in series between the input node and ground; and an inverter connected between the input node and the output node, wherein the P-type transistor has a gate connected to the reset line, and wherein the three P-type transistors and the three N-type transistors have gates connected to the output node; and a NAND gate having an input connected to the output node and configured to receive a pulse width modulated signal, wherein a pulse width of the pulse width modulated signal depends on a pulse width of a read word line select signal connected to a read word line of a memory cell during a read operation for the memory cell, and The pulse width of the read word line selection signal on the read word line increases row by row, and wherein the drive circuit comprises two additional P-type transistors connected in series between the positive supply voltage rail and the anode of the light emitting diode, wherein one of the two additional P-type transistors has a gate connected to the output of the NAND gate, and the other of the two additional P-type transistors has a gate connected to receive a gate bias voltage.

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