Display device and driving method thereof

Abstract

A display device and a driving method thereof are disclosed. Each of sub-pixels in the display device includes a light emitting element, a driving element, a first switching element, a second switching element, a third switching element, and a fourth switching element. The gate signal includes a first-first scan signal applied to the gate electrode of the fourth switching element, a first-second scan signal applied to the gate electrode of the third switching element, a second scan signal applied to the gate electrode of the second switching element, and a light emission control signal applied to the gate electrode of the first switching element. The pulse of the first-first scan signal has the same pulse width as the pulse of the first-second scan signal and is prior to the pulse of the first-second scan signal.

Description

Technical Field

[0001] The present disclosure relates to a display device and a driving method thereof, and more particularly, for example but not limited to, to a display device and a driving method thereof capable of reducing the size of a gate driving circuit and improving image quality in a low-power driving mode. Background Art

[0002] The organic light-emitting display device includes an organic light-emitting diode (hereinafter referred to as "OLED"), which emits light itself and has the advantages of fast response speed, high luminous efficiency, high brightness and wide viewing angle. The organic light-emitting display device has a fast response speed and excellent luminous efficiency, brightness and viewing angle, and has excellent contrast and color reproducibility because it can express black grayscale in full black.

[0003] Due to process deviations and device characteristic deviations caused by the panel manufacturing process, the electrical characteristics of the driving element may be different from pixel to pixel. The electrical characteristic deviation of the pixel may increase as the driving time of the pixel elapses. In order to compensate for the electrical characteristic deviation of the driving element for each pixel, an internal compensation circuit may be used to implement the pixel circuit of the organic light-emitting display device. The internal compensation circuit can compensate for the gate voltage of the driving element by sampling the threshold voltage of the driving element. The internal compensation circuit requires adding transistors to the pixel circuit and requires a gating signal to control these transistors, which increases the size of the gating drive circuit provided on the display panel. This limits the narrow frame design that reduces the non-display area outside the display device.

[0004] Various studies are being conducted to reduce the power consumption of organic light emitting display devices. For example, an organic light emitting display may reduce the driving frequency of pixels to reduce power consumption under certain conditions. In such cases, a viewer may experience, for example, flickering of an image reproduced on a display panel.

[0005] The description provided in the description of the prior art section should not be considered as prior art merely because it is mentioned in the description of the prior art section or is associated with the description of the prior art section. The description of the prior art section may include information describing one or more aspects of the subject technology, and the description in this section does not limit the present invention. Summary of the invention

[0006] The present disclosure has been made in an effort to address the above-mentioned needs and / or disadvantages.

[0007] The present disclosure provides a display device and a driving method thereof that can reduce the size of a gate driving circuit and improve image quality in a low-power driving mode.

[0008] The problems to be solved by the present disclosure are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0009] A display device according to an exemplary embodiment of the present disclosure includes: a display panel, on which a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of sub-pixels are arranged; a data driver, the data driver is configured to supply a data voltage to the data line; and a gate driver, the gate driver is configured to supply a gate signal to the gate line. Each of the plurality of sub-pixels includes: a light-emitting element; a driving element, the driving element includes a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node, and the driving element is configured to drive the light-emitting element; a first switching element, the first switching element is configured to supply a pixel driving voltage to the second node; a second switching element, the second switching element is configured to supply the data voltage to the second node; a third switching element, the third switching element is configured to connect the first node to the third node; and a fourth switching element, the fourth switching element is configured to supply an initialization voltage to the first node. The gating signal includes: a first-first scan signal applied to the gate electrode of the fourth switching element, a first-second scan signal applied to the gate electrode of the third switching element, a second scan signal applied to the gate electrode of the second switching element, and a light emitting control signal applied to the gate electrode of the first switching element. The pulse of the first-first scan signal has the same pulse width as the pulse of the first-second scan signal and is before the pulse of the first-second scan signal.

[0010] The gating driver may include: a first shift register, which is configured to output a pulse of the first-first scanning signal and then output a pulse of the first-second scanning signal; a second shift register, which is configured to output a pulse of the second scanning signal; and a third shift register, which is configured to output a pulse of the light emitting control signal.

[0011] Each of the sub-pixels may also be connected to a capacitor between the pixel drive voltage and the first node.

[0012] The first switching element may include a gate electrode to which the light emitting control signal is applied, a first electrode to which the pixel driving voltage is applied, and a second electrode connected to the second node. The second switching element may include a gate electrode to which the second scanning signal is applied, a first electrode connected to the data line, and a second electrode connected to the second node. The third switching element may include a gate electrode to which the first-second scanning signal is applied, a first electrode connected to the first node, and a second electrode connected to the third node. The fourth switching element may include a gate electrode to which the first-first scanning signal is applied, a first electrode connected to the first node, and a second electrode to which the initialization voltage is applied. The light emitting element may include an anode connected to the third node and a cathode to which a cathode voltage is applied.

[0013] During the initialization period, the third switching element and the fourth switching element may be turned on to apply the initialization voltage to the first node and the third node. During the sampling period, the second switching element and the third switching element may be turned on so that the data voltage is applied to the second node and the first node is electrically connected to the third node. During the light emission period, the first switching element may be turned on.

[0014] Each of the sub-pixels may further include: a fifth switching element, which is configured to supply a second compensation voltage to the second node; a sixth switching element, which is configured to apply a third compensation voltage to the fourth node; and a seventh switching element, which is configured to connect the third node to the fourth node in response to the light emitting control signal.

[0015] The gate signal may further include a third scan signal applied to a gate electrode of each of the fifth switching element and the sixth switching element.

[0016] Each of the sub-pixels may also include a first capacitor, which is connected between the pixel driving voltage and the first node. The fifth switching element may include a gate electrode to which the third scan signal is applied, a first electrode connected to the second node, and a second electrode to which the second compensation voltage is applied. The sixth switching element may include a gate electrode to which the third scan signal is applied, a first electrode connected to the fourth node, and a second electrode to which the third compensation voltage is applied. The seventh switching element may include a gate electrode to which the light emitting control signal is applied, a first electrode connected to the third node, and a second electrode connected to the fourth node. The light emitting element may include an anode connected to the fourth node and a cathode to which a cathode voltage is applied.

[0017] Each of the sub-pixels may further include a second capacitor connected between a gate line to which the third scan signal is applied and the first node.

[0018] The low power mode may include: a refresh frame, in which a data voltage is applied to the sub-pixel through the data line; and a hold frame, in which a first compensation voltage is applied to the sub-pixel through the data line. The refresh frame may include a first on-bias period, a first initialization period, a second initialization period, a sampling period, a second on-bias period, and a light-emitting period. During the first on-bias period of the refresh frame, the fifth switching element and the sixth switching element may be turned on to apply the second compensation voltage to the second node and the third compensation voltage to the fourth node. During the first initialization period of the refresh frame, the fourth switching element may be turned on to apply the initialization voltage to the first node. During the second initialization period of the refresh frame, the third switching element and the fourth switching element may be turned on to apply the initialization voltage to the first node and the third node. During the sampling period of the refresh frame, the second switching element may be turned on to apply the data voltage to the second node. During the second on-bias period of the refresh frame, the fifth switching element and the sixth switching element may be turned on to apply the second compensation voltage to the second node and the third compensation voltage to the fourth node. During the light emission period of the refresh frame, the first switching element and the seventh switching element may be turned on.

[0019] The display device may further include a switching element configured to apply the first compensation voltage to the data line during the holding frame. No data voltage may be output from the data driver in the holding frame.

[0020] The holding frame may include a third on-bias period, a fourth on-bias period, and a light-emission period. During each of the third on-bias period and the fourth on-bias period of the holding frame, the fifth switching element and the sixth switching element may be turned on to apply the second compensation voltage to the second node and the third compensation voltage to the fourth node. During the light-emission period of the holding frame, the first switching element and the seventh switching element may be turned on.

[0021] The refresh frame may further include a first floating period between the first on-bias period and the first initialization period, a second floating period between the sampling period and the second on-bias period, and a third floating period between the second on-bias period and the light-emitting period of the refresh frame. The hold frame may further include a fourth floating period between the third on-bias period and the fourth on-bias period, and a fifth floating period between the fourth on-bias period and the light-emitting period of the hold frame. The first to seventh switching elements may be in an off state in each of the first to fifth floating periods.

[0022] A voltage of the second compensation voltage may be smaller in the refresh frame than in the hold frame.

[0023] The gating driver may include: a first shift register, which is configured to output a pulse of the first-first scanning signal and then output a pulse of the first-second scanning signal; a second shift register, which is configured to output a pulse of the second scanning signal; a third shift register, which is configured to output a pulse of the third scanning signal; and a fourth shift register, which is configured to output a pulse of the light emitting control signal.

[0024] The second shift register may include: a plurality of odd-numbered signal transmission units, the plurality of odd-numbered signal transmission units being configured to sequentially output pulses of odd-numbered scan signals; and a plurality of even-numbered signal transmission units, the plurality of even-numbered signal transmission units being configured to sequentially output pulses of even-numbered scan signals.

[0025] A carry signal may be transmitted between the odd-numbered signal transmission parts and the even-numbered signal transmission parts adjacent to each other.

[0026] The method of driving a display device according to an exemplary embodiment of the present disclosure includes the following steps: supplying a gate signal to a plurality of gate lines connected to a pixel circuit during a refresh frame period and a hold frame period; supplying a data voltage to a plurality of data lines during the refresh frame period, and supplying the data voltage, a second compensation voltage, and a third compensation voltage to the pixel circuit; and supplying a first compensation voltage to the data lines during the hold frame period, and supplying the first compensation voltage, the second compensation voltage, and the third compensation voltage to the pixel circuit. The gate signal includes: a pulse of a first-first scan signal and a pulse of a first-second scan signal sequentially output from a first shift register, a pulse of a second scan signal sequentially output from a second shift register, and a pulse of a light emitting control signal sequentially output from a third shift register. The pulse of the first-first scan signal is generated, and then the pulse of the first-second scan signal is generated. The pulse of the first-first scan signal has the same pulse width as the pulse of the first-second scan signal and is before the pulse of the first-second scan signal.

[0027] According to another exemplary embodiment of the present disclosure, a method for driving a display device includes the following steps: supplying a gate signal to a plurality of gate lines connected to a pixel circuit during a refresh frame period and a hold frame period; supplying a data voltage to a plurality of data lines during the refresh frame period, and supplying the data voltage, a second compensation voltage, and a third compensation voltage to the pixel circuit; and supplying a first compensation voltage to the data lines during the hold frame period, and supplying the first compensation voltage, the second compensation voltage, and the third compensation voltage to the pixel circuit. The gate signal includes: a pulse of a first-first scan signal and a pulse of a first-second scan signal sequentially output from a first shift register, a pulse of a second scan signal sequentially output from a second shift register, a pulse of a third scan signal sequentially output from a third shift register, and a pulse of a light emitting control signal sequentially output from a fourth shift register. Generate a pulse of the first-first scan signal, and then generate a pulse of the first-second scan signal. The pulse of the first-first scan signal has the same pulse width as the pulse of the first-second scan signal and is before the pulse of the first-second scan signal.

[0028] Some periods of pulses of the first-first scanning signal overlap with pulses of the first-second scanning signal.

[0029] According to the present disclosure, it is possible to drive a display device with low power by driving pixels by maintaining data voltages stored in a refresh frame and a hold frame.

[0030] According to the present disclosure, the difference in brightness characteristics of pixels in a refresh frame and a hold frame may be reduced or minimized by applying a compensation voltage to the pixels in a low-power driving mode, thereby improving image quality.

[0031] According to the present disclosure, more gate signals can be output than the number of shift registers outputting gate signals in the gate driver. Therefore, according to the present disclosure, the size of the gate driver circuit can be reduced, thereby reducing the size of the gate driver disposed on the display panel.

[0032] The effects of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned can be apparently understood by those skilled in the art from the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0034] Figure 1 is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure;

[0035] Figure 2 It is shown Figure 1 A cross-sectional view of the cross-sectional structure of the display panel shown;

[0036] Figure 3 is a diagram schematically showing a display device of a mobile terminal;

[0037] Figure 4 is a diagram schematically showing a shift register in a gate driver according to an exemplary embodiment of the present disclosure;

[0038] Figure 5 is a circuit diagram showing a pixel circuit according to an exemplary embodiment of the present disclosure;

[0039] Figure 6 is shown applied to Figure 5 Waveform diagram of the gate signal and data voltage of the pixel circuit shown;

[0040] FIG. 7A to FIG. 7C It is shown Figure 5 A circuit diagram of the phased operation of the pixel circuit shown;

[0041] Figure 8 is shown for output applied to Figure 5 A diagram of a gate driver for a gate signal of a pixel circuit shown;

[0042] Fig. 9A and Fig. 9Bis a circuit diagram showing a pixel circuit according to another exemplary embodiment of the present disclosure;

[0043] FIG. 10A to FIG. 10E is a waveform diagram showing brightness characteristics according to a driving frequency and a compensation voltage of a pixel;

[0044] Fig.11 is a waveform diagram showing a strobe signal and a data voltage generated during a refresh frame;

[0045] Fig. 12A is a circuit diagram illustrating the operation of a pixel circuit during a first on-bias period of a refresh frame;

[0046] Fig. 12B is a circuit diagram illustrating the operation of a pixel circuit during a first initialization period of a refresh frame;

[0047] Fig. 12C is a circuit diagram illustrating the operation of a pixel circuit during an initialization period of a refresh frame;

[0048] Fig.12D is a circuit diagram illustrating the operation of a pixel circuit during a sampling period of a refresh frame;

[0049] Fig.12E is a circuit diagram illustrating operation of a pixel circuit during a second on-bias period of a refresh frame;

[0050] Fig.12F is a circuit diagram illustrating the operation of a pixel circuit during a light emission period of a refresh frame;

[0051] Fig.13 is a waveform diagram showing a strobe signal and a first compensation voltage generated during a hold frame;

[0052] Fig.14A is a circuit diagram showing the operation of a pixel circuit during an on-bias period of a hold frame;

[0053] Fig. 14B is a circuit diagram showing the operation of a pixel circuit during a floating period of a hold frame;

[0054] Fig. 14C is a circuit diagram illustrating the operation of a pixel circuit during a light emission period of a refresh frame;

[0055] Fig.15 is a waveform diagram showing an example of compensation voltage variation;

[0056] Fig.16 is shown for output applied to Fig. 9A and Fig. 9B A diagram of a gate driver for a gate signal of a pixel circuit shown;

[0057] Fig.17 It shows the input to Fig.16 The waveform diagram of the clock and start pulse of the shift register shown; and

[0058] Fig.18 is a diagram illustrating a compensation voltage generator according to an exemplary embodiment of the present disclosure.

[0059] Throughout the drawings and detailed description, unless otherwise specified, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the relative sizes and descriptions of these elements may be exaggerated. DETAILED DESCRIPTION

[0060] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be shown in the accompanying drawings. In the following description, detailed descriptions of known functions or configurations associated with this document will be omitted when it is determined that they unnecessarily obscure the main points of the inventive concept. The described progression of processing steps and / or operations is an example; however, except that the steps and / or operations must occur in a particular order, the order of the steps and / or operations is not limited to the order set forth herein and may be changed as known in the art. The names of the various elements used in the following description are selected solely for ease of writing the specification and may therefore differ from the names used in the actual product.

[0061] According to the exemplary embodiments described below with reference to the accompanying drawings, the advantages and features of the present disclosure and the methods for implementing the present disclosure will be more clearly understood. However, the present disclosure is not limited to the following exemplary embodiments, but can be implemented in various different forms. On the contrary, the exemplary embodiments will make the disclosure of the present disclosure complete and allow those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is only limited within the scope of the appended claims.

[0062] The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings used to describe the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout this specification, the same reference numerals generally represent the same elements. In addition, when describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0063] Terms such as "include," "comprising," "having," and "containing" used herein are generally intended to allow the addition of other components unless the terms are used with the term "only." Any reference to the singular may include the plural unless explicitly stated otherwise.

[0064] Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations.

[0065] Even if not explicitly stated, the components are interpreted as including the ordinary error range.

[0066] When describing the position or interconnection relationship between two components, such as "on top of," "above," "above," "below," "immediately adjacent," "connected or coupled to," "crossing," "intersecting," etc., one or more other components may be interposed between them, unless "immediately" or "directly" is used. In other words, one or more other components may be disposed between the two components. For example, when one element or layer is disposed on another element or layer, a third element or layer may be interposed between the one element or layer and the other element or layer.

[0067] When describing a temporal sequence such as “after,” “subsequently,” “next,” “before,” etc., it may not be continuous on a temporal basis unless “just,” “immediately,” or “directly” is used.

[0068] The terms "first", "second", "A", "B", "(a)", "(b)", etc. may be used to distinguish elements from each other, but the function or structure of a component is not limited by the sequence number or component name preceding the component. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.

[0069] The following exemplary embodiments may be partially or completely combined or combined with each other, and may be technically linked and operated in various ways. The exemplary embodiments may be performed independently or in association with each other.

[0070] The pixel circuit and the gate drive circuit of the display device may include a plurality of transistors. The transistor may be implemented as a thin film transistor (TFT). The transistor may be implemented as an oxide thin film transistor (TFT) including an oxide semiconductor, a low temperature polysilicon TFT (LTPS TFT) including low temperature polysilicon, etc. For example, the oxide semiconductor material may be formed of any one of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO), but is not limited thereto.

[0071] A transistor is basically a three-electrode element including a gate, a source, and a drain. The source is an electrode through which carriers are supplied to the transistor. The transistor of the present disclosure can be implemented with a four-terminal element to which a back gate bias is applied to shift the threshold voltage to a desired voltage. In a transistor, carriers flow from the source. The drain is the electrode through which carriers leave the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n-channel transistor, since the carriers are electrons, the source voltage is a voltage lower than the drain voltage, so that electrons can flow from the source to the drain. An n-channel transistor has a direction of current flowing from the drain to the source. In the case of a p-channel transistor (p-channel metal oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of the transistor are not fixed. For example, the source and drain can be changed according to the applied voltage. Therefore, the present disclosure is not limited to the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as the first electrode and the second electrode.

[0072] The gating pulse can swing between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to be higher than the threshold voltage of the transistor. The gate-off voltage is set to be lower than the threshold voltage of the transistor. The transistor is turned on in response to the gate-on voltage and turned off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate high voltage VGH and the gate-off voltage may be a gate low voltage VGL. In the case of a p-channel transistor, the gate-on voltage may be a gate low voltage VGL and the gate-off voltage may be a gate high voltage VGH.

[0073] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. For the convenience of description, the scale of each element shown in the drawings is different from the actual scale, and is therefore not limited to the scale shown in the drawings.

[0074] Figure 1 is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure. Figure 2 It is shown Figure 1 A cross-sectional view of the cross-sectional structure of the display panel shown. Figure 3 is a diagram schematically showing a display device of a mobile terminal.

[0075] Reference Figures 1 to 3According to an exemplary embodiment of the present disclosure, the display device may include a display panel 100 for displaying an image, a display panel driving circuit for writing pixel data into pixels 101 of the display panel 100, and a power supply 140 for generating power required to drive the pixels and the display panel driving circuit, but the present disclosure is not limited thereto. For example, the image may include an electronic image, a digital image, a still image, a video or a moving image, etc.

[0076] The display panel 100 may be made of a plastic substrate, a thin glass substrate, a metal substrate, or a flexible polymer film substrate, etc. The pixel 101 is implemented on the display panel 100. For example, the flexible polymer film may be made of any one of polyethylene terephthalate (PET), polycarbonate (PC), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polyether sulfone (PES), cyclic olefin copolymer (COC), triacetyl cellulose (TAC) film, polyvinyl alcohol (PVA) film, polyimide (PI) film, and polystyrene (PS), and the above material is only an example and is not necessarily limited thereto.

[0077] The display panel 100 may be, but is not limited to, a panel of a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display panel 100 may include a display area AA and a non-display area BZ outside the display area AA. The display area AA of the display panel 100 includes a pixel array for displaying an input image thereon. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels 101 arranged in a matrix form. The display panel 100 may also include a power line commonly connected to the pixel 101. The power line is connected to a constant voltage node of the pixel circuit, and a constant voltage required to drive the pixel 101 is supplied to the pixel 101.

[0078] Each pixel 101 can be divided into a plurality of sub-pixels such as red sub-pixels, green sub-pixels and blue sub-pixels for color realization, but is not limited thereto. Each of the plurality of sub-pixels can also include a white sub-pixel. Each sub-pixel includes a pixel circuit for driving a light-emitting element. Each of the pixel circuits is connected to wiring such as a data line, a gate line and a power line. Hereinafter, "pixel" can be interpreted as having the same meaning as "sub-pixel".

[0079] The pixels may be arranged in the form of real color pixels and pentile pixels. The pentile pixels may achieve a higher resolution than real color pixels by driving two sub-pixels with different colors as one pixel 101 using a preset pixel rendering algorithm. The pixel rendering algorithm may compensate for the insufficient color representation in each pixel with the color of light emitted from its neighboring pixels.

[0080] The pixel array may include a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln includes a row of pixels arranged in the row direction (X-axis direction) along the gate line direction in the pixel array of the display panel 100. The pixels arranged in one pixel row may share the gate line 103, but the present invention is not limited thereto. Sub-pixels arranged in the column direction (Y) along the data line direction may share the same data line 102, but the present disclosure is not limited thereto. One horizontal period is the time obtained by dividing one frame period by the total number of pixel rows L1 to Ln.

[0081] The display panel 100 may be implemented with a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device in which an image is displayed on a screen and an actual object in the background is visible. The display panel 100 may be made into a flexible display panel. The display panel 100 may be a liquid crystal display panel, but the embodiments of the present disclosure are not limited thereto. For example, the display panel 100 may be a light-emitting display panel, an electrophoretic display panel, a micro-light-emitting diode display panel, an electrowetting display panel, a quantum dot light-emitting display panel, etc.

[0082] The cross-sectional structure of the display panel 100 may be as follows: Figure 2 The figure includes a circuit layer CIR, a light emitting element layer EMIL and a packaging layer ENC stacked on a substrate SUBS.

[0083] The circuit layer CIR may include a thin film transistor (TFT) array including pixel circuits connected to conductive lines such as data lines, gate lines, and / or power lines, a demultiplexer array 112, and a gate driver 120. The circuit layer CIR includes a plurality of metal layers and semiconductor material layers insulated with insulating layers interposed therebetween.

[0084] The light-emitting element layer EMIL may include a light-emitting element driven by a pixel circuit. The light-emitting element EL may include a plurality of light-emitting elements such as a light-emitting element of a red sub-pixel, a light-emitting element of a green sub-pixel, and a light-emitting element of a blue sub-pixel, but is not limited thereto. For example, sub-pixels emitting light of other colors (e.g., magenta, cyan, or yellow) are also possible. In another embodiment, the light-emitting element layer EMIL may also include a light-emitting element and a color filter of a white sub-pixel. The light-emitting element layer EMIL in each of the sub-pixels may have a structure in which a light-emitting element and a color filter are stacked. The light-emitting element EL in the light-emitting element layer EMIL may be covered by a plurality of protective layers including an organic film and an inorganic film.

[0085] The encapsulation layer ENC may cover the light emitting element layer EMIL to seal the circuit layer CIR and the light emitting element layer EMIL. The encapsulation layer ENC may also have a multi-insulating film structure in which organic films and inorganic films are alternately stacked. The inorganic film blocks the penetration of moisture and oxygen. The organic film flattens the surface of the inorganic film. When the organic film and the inorganic film are stacked in multiple layers, the movement path of moisture and oxygen becomes longer compared to a single layer, so that the penetration of moisture and oxygen that affects the light emitting element layer EMIL can be effectively blocked.

[0086] A touch panel (or touch sensor layer) (not shown) disposed on or embedded in the display panel 100 may be formed on the encapsulation layer ENC, and a polarizer or color filter layer may be disposed on the touch panel. The touch sensor layer may include a capacitive touch sensor that senses a touch input based on a change in capacitance before and after the touch input. The touch sensor layer may include an insulating film and a metal line pattern that form a capacitance of the touch sensor. The insulating film may insulate the portion where the metal line pattern intersects, and may flatten the surface of the touch sensor layer. The polarizer may improve visibility and contrast by converting the polarization of external light reflected by the metal of the touch sensor layer and the circuit layer. The polarizer may be implemented as a polarizer or a circular polarizer combined with a linear polarizer and a phase delay film. The cover glass may be adhered to the polarizer. The color filter layer may include a plurality of different color filters, such as a red filter, a green filter, and a blue filter, but is not limited thereto. For example, a color filter that filters light of other colors (e.g., magenta, cyan, or yellow) is also possible. The color filter layer may further include a black matrix pattern. The color filter layer may replace a polarizer by absorbing a portion of the wavelength of light reflected from the circuit layer and the touch sensor layer, and improve the color purity of an image reproduced in the pixel array.

[0087] The power supply 140 generates a constant voltage (or direct current (DC) voltage) required to drive the pixel array and the display panel driving circuit of the display panel 100 using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply 140 may adjust the level of the DC input voltage applied from the host system 200 to output constant voltages such as a gamma reference voltage, a gate high voltage, a gate low voltage, a pixel driving voltage, a cathode voltage, and an initialization voltage. The gamma reference voltage is supplied to the data driver 110. The dynamic range of the data voltage output from the data driver 110 is determined by the voltage range of the gamma reference voltage. The dynamic range of the data voltage is the range of the voltage between the highest grayscale voltage and the lowest grayscale voltage.

[0088] The gate high voltage and the gate low voltage are supplied to the level shifter 150 and the gate driver 120. Constant voltages such as a pixel driving voltage, a cathode voltage, and an initialization voltage are supplied to the pixels 101 through power lines connected to the pixels 101 in common.

[0089] The pixel driving voltage may be output from a main power source of the host system 200 and supplied to the display panel 100. In this case, the power source 140 does not need to output the pixel driving voltage.

[0090] The display panel driving circuit writes pixel data of the input image into the pixels of the display panel 100 under the control of the timing controller 130. The display panel driving circuit may include a data driver 110 and a gate driver 120, but is not limited thereto. In addition, the display panel driving circuit may further include a demultiplexer array 112 disposed between the data driver 110 and the data line 102.

[0091] The demultiplexer array 112 sequentially supplies data voltages output from the channels of the data driver 110 to the data lines 102 using a plurality of demultiplexers (DEMUX). The demultiplexer may include a plurality of switching elements disposed on the display panel 100. When the demultiplexer is disposed between the output terminal of the data driver 110 and the data lines 102, the number of channels of the data driver 110 may be reduced. The demultiplexer array 112 may be omitted or may be simply provided.

[0092] The display panel driving circuit may further include a touch sensor driver for driving the touch sensor. Figure 1 The touch sensor driver is omitted. The data driver 110 and the touch sensor driver may be integrated into one driver IC (integrated circuit). In a mobile terminal or a wearable terminal, the timing controller 130, the power supply 140, the level shifter 150, the data driver 110, the touch sensor driver, the compensation voltage generator, etc. may be integrated into one driver IC (DIC), such as Figure 3 shown.

[0093] The data driver 110 receives pixel data of an input image received as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 converts the pixel data of the input image into a gamma compensation voltage using a digital-to-analog converter (DAC) to output the data voltage. The gamma reference voltage (VGMA) is divided into a gamma compensation voltage for each grayscale by a voltage divider circuit in the data driver 110, and the gamma compensation voltage is supplied to the DAC. The DAC generates a data voltage as a gamma compensation voltage corresponding to the grayscale value of the pixel data. The data voltage from the DAC can be output to the data line 102 from the corresponding channel of the data driver 110 through the output buffer, or can be output to the data line 102 through the demultiplexer array 112.

[0094] The gate driver 120 may be formed in a circuit layer CIR on the display panel 100 together with the TFT array and conductive lines of the pixel array. The gate driver 120 may be disposed in a non-display area BZ outside the display area AA in the display panel 100, or at least a portion of the gate driver 120 may be disposed in the display area AA.

[0095] The gate driver 120 may include a plurality of shift registers for sequentially shifting pulses of a gate signal. The gate driver 120 may be disposed in a left non-display area BZ or a right non-display area BZ outside the display area AA in the display panel 100 to supply a gate signal to the gate line 103 in a single feeding method. In the single feeding method, the gate signal is applied to one end of the gate line. The gate driver 120 may be disposed in a left non-display area BZ and a right non-display area BZ in the display panel 100 to apply a gate signal to the gate line 103 in a dual feeding method. In the dual feeding method, the gate signal is simultaneously applied to both ends of the gate line 103. At least some circuits of the gate driver 120 may be disposed in the display area AA.

[0096] The gate driver 120 sequentially outputs pulses of the gate signal to the gate line 103 under the control of the timing controller 130. The gate driver 120 can sequentially supply the gate signal to the gate line 103 by shifting the pulses of the gate signal using a shift register. The gate driver 120 can use a plurality of shift registers to output a plurality of gate signals having different phases, pulse widths, etc. In the organic light emitting display device, the gate signal may include various gate pulses such as a scan signal and a light emitting control signal (hereinafter referred to as an "EM signal").

[0097] The timing controller 130 receives the digital video data of the input image and the timing signal synchronized with the data from the host system 200. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE, etc. Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The data enable signal DE has an interval of one horizontal period (1H).

[0098] The timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, a MUX control signal for controlling the operation timing of the demultiplexer array 112, and a gate timing control signal for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system 200. The timing controller 130 synchronizes the data driver 110, the demultiplexer array 112, the touch sensor driver, and the gate driver 120 by controlling the operation timing of the display panel driving circuit.

[0099] The gate timing control signal generated from the timing controller 130 may be input to the shift register in the gate driver 120 through the level shifter 150. The gate timing control signal may include a start pulse, a clock, etc. The level shifter 150 may receive the gate timing control signal to generate a start pulse and a shift clock, and provide them to the gate driver 120 through the clock lines CL1 to CLn. The level shifter 150 may supply the MUX control signal to the demultiplexer array 112. The input signal of the level shifter 150 may be a signal of a digital signal voltage level, and the output signal from the level shifter 150 may be an analog voltage signal swinging between a gate high voltage VGH and a gate low voltage VGL.

[0100] The host system 200 may include a mainboard of any one of a television system, a set-top box, a navigation system, a personal computer (PC), an in-vehicle system, a mobile terminal such as a smart phone or an electronic board, or a wearable terminal. The host system may scale an image signal from a video source to match the resolution of the display panel 100, and may transmit the image signal to the timing controller 130 together with a timing signal.

[0101] In a mobile system, the host system 200 may be implemented by an application processor (AP). The host system 200 may transmit pixel data of an input image to a processor via a mobile industry processor interface (MIPI). Figure 3 The host system 200 may be electrically connected to the driver IC (DIC) through a flexible printed circuit (eg, a flexible printed circuit (FPC)). Figure 3The driver IC may be bonded to the display panel 100 in a COG (Chip on Glass) process. The driver IC may be electrically connected to a wire on the display panel 100 as a Chip on Film (COF) structure mounted on a flexible circuit film.

[0102] The timing controller 130 or the host system 200 may enter a low power mode when a still image or always-on display (AOD) data is input to reduce or minimize the power consumption of the display device. In normal mode, the pixel 101 may have a refresh rate of 60 Hz, 144 Hz, 240 Hz, etc. The refresh rate is the frequency at which pixel data is written to the pixel 101. In low power mode, the refresh rate of the pixel 101 is reduced to a frequency lower than 60 [Hz], for example, 1 [Hz] to 30 [Hz]. When the refresh rate is 1 [Hz], the first frame of 60 frames per second may be a refresh frame, and the next 59 frames may be holding frames. After the data voltage Vdata of the pixel data is charged to the pixel 101 during the refresh frame period, the pixel 101 may maintain the data voltage charged in the previous refresh frame during the continuous holding frame period without recharging the data voltage Vdata, so that the luminous state is maintained.

[0103] The display panel driving circuit may include a compensation voltage generator 160 that outputs compensation voltages Vpark, VOBS, and VAR. At least a portion of the compensation voltage generator 160 may use resources from other components such as the power supply 140, the data driver 110, the display panel 100, etc. The compensation voltage generator 160 may change the voltage level of each of the compensation voltages Vpark, VOBS, and VAR under the control of the timing controller 130. The power supply 140 may be implemented as a single power supply IC together with the compensation voltage generator 160.

[0104] Each of the sub-pixels includes a driving element for driving a light emitting element and a pixel circuit including a capacitor connected to the driving element. The pixel circuit of each of the sub-pixels may include an internal compensation circuit to compensate the data voltage by a threshold voltage of the driving element.

[0105] Figure 4 is a diagram schematically illustrating a shift register in a gate driver according to an exemplary embodiment of the present disclosure.

[0106] Reference Figure 4, the gating driver includes one or more shift registers. The shift register includes a plurality of signal transmission parts ST connected in cascade. The shift register can be implemented with any known shift register circuit for driving a display panel. The signal transmission part can be understood as a stage circuit of a shift register. Each of the signal transmission parts includes a CLK node to which clocks CLK1 to CLK4 are input, a VST node to which a start pulse VST or a carry signal from a previous signal transmission part is input, a first control node Q, a second control node QB, an output node 44, and a buffer BUF that charges and discharges the output node 44 in response to the voltage on the control nodes Q and QB to output a pulse of a gating signal.

[0107] The phases of the clocks CLK1 to CLK4 are sequentially shifted. The signal transmission part ST may receive one or more clocks as input. Figure 4 In the embodiment, each of the signal transmission parts ST receives two clocks as input, but is not limited thereto. Figure 4 In the example of , the CLK node of the signal transmission part ST can be connected to the clock line 42 provided in the non-display area BZ of the display panel 100 to receive the clocks CLK1 to CLK4. The first signal transmission part ST can receive the first clock CLK1 and the second clock CLK2 and the start pulse, and can output the pulse of the selection signal GOUT1 and the pulse of the carry signal CAR. The second signal transmission part ST can receive the second clock CLK2 and the third clock CLK3 and the pulse of the first carry signal CAR, and output the pulse of the second selection signal GOUT2 and the pulse of the second carry signal CAR. The nth (where n is a natural number) signal transmission part ST can receive the first clock CLK1 and the fourth clock CLK4 and the pulse of the n-1th carry signal CAR from the n-1th signal transmission part, and output the pulse of the nth selection signal GOUTn and the pulse of the nth carry signal CAR.

[0108] The buffer BUF includes a first buffer transistor Tu controlled by a voltage of a first control node Q and a second buffer transistor Td controlled by a voltage of a second control node QB.

[0109] The first buffer transistor Tu is turned on in response to the voltage of the first control node Q to charge the voltage of the output node 44 to the gate-on voltage Von. The first buffer transistor Tu includes a gate electrode connected to the first control node Q, a first electrode to which the gate-on voltage Von is applied, and a second electrode connected to the output node 44.

[0110] The second buffer transistor Td is turned on in response to the voltage of the second control node QB to supply the gate-off voltage Voff to the output node 44. The second buffer transistor Td includes a gate electrode connected to the second control node QB, a first electrode connected to the output node 44, and a second electrode to which the gate-off voltage Voff is applied.

[0111] In addition, the signal transmission part ST may output pulses of the strobe signals GOUT1 to GOUTn through the first output nodes, respectively, and output a pulse of the carry signal CAR through a separate second output node.

[0112] Figure 5 is a circuit diagram showing a pixel circuit according to an exemplary embodiment of the present disclosure.

[0113] Reference Figure 5 The pixel circuit may include a light emitting element EL, a driving element DT for driving the light emitting element EL, a plurality of switching elements such as switching elements T1 to T4, a capacitor Cst, etc., but is not limited thereto.

[0114] For example, the third switching element T3 and the fourth switching element T4 may each be implemented as an n-channel oxide TFT having a low off-current. Each of the first switching element T1 and the second switching element T2 and the driving element DT may be implemented as a p-channel LTPS TFT having a good on-current characteristic. The n-channel oxide TFT is turned on in response to the gate high voltage VGH, and it is turned off in response to the gate low voltage VGL, as shown in FIG. Figure 6 The p-channel LTPS TFT can be turned on in response to a gate low voltage VGL, while it is turned off in response to a gate high voltage VGH, as shown in FIG. Figure 6 For example, the first switch element T1 is turned on or off in response to the EM signal EMn, and the second switch element T2 is turned on or off in response to the second scan signal SC2n.

[0115] The pixel circuit is connected to the data line DL to which the data voltage Vdata of the pixel data is applied, and to the gate lines G1n, G1n-i, G2n and G3n to which the gate signals SC1n, SC1n-i, SC2n and EMn are applied. The pixel circuit may be connected to the first power line P1 to which the pixel driving voltage ELVDD is applied, the second power line P2 to which the cathode voltage ELVSS is applied, and the third power line P3 to which the initialization voltage Vint is applied. On the display panel, the power lines P1, P2 and P3 may be connected in common to all pixels 101.

[0116] The pixel driving voltage ELVDD and the cathode voltage ELVSS are set to voltages that allow the driving element DT to operate in a saturation region. The cathode voltage ELVSS may be set to a voltage lower than the pixel driving voltage ELVDD. The gate high voltage VGH may be set to a voltage higher than the pixel driving voltage ELVDD, and the gate low voltage VGL may be set to a voltage lower than the cathode voltage ELVSS.

[0117] For example, the data voltage Vdata may have a dynamic range between 2 [V] and 6 [V]. Within the dynamic range, the voltage level of the data voltage Vdata is selected according to the grayscale value of the pixel data. The initialization voltage Vint may be set to, but is not limited to, a voltage lower than the lower limit of the data voltage Vdata and higher than the cathode voltage ELVSS. The voltage difference between the initialization voltage Vint and the cathode voltage ELVSS is a voltage lower than the threshold voltage of the light emitting element EL.

[0118] The selection signals SC1n, SC1n-i, SC2n and EMn include pulses swinging between a gate high voltage VGH and a gate low voltage VGL. The first scanning signals SC1n and SC1n-i include a first-first scanning signal SC1n-i and a first-second scanning signal SC1n outputted in sequence from a shift register. After the first-first scanning signal SC1n-i is outputted from the shift register, the first-second scanning signal SC1n is outputted. The pulses of the first-second scanning signal SC1n are later in phase than the pulses of the first-first scanning signal SC1n-i and have the same pulse width W. Wherein, n and i are natural numbers, wherein n is greater than i. Here, i may be, but is not limited to, a value between 1 and 16. Some periods of the pulses of the first-first scanning signal SC1n-i may overlap with some periods of the pulses of the first-second scanning signal SC1n.

[0119] As an example, the driving element DT may include a gate electrode connected to the first node n1, a first electrode connected to the second node n2, and a second electrode connected to the third node n3. The capacitor Cst may be connected between a node on the first power line P1 to which the pixel driving voltage ELVDD is applied and the first node n1.

[0120] The light emitting element EL may be implemented as an organic OLED or an inorganic LED. The OLED includes an anode, a cathode, and an organic compound layer interposed between the anode and the cathode. In an exemplary embodiment, a first electrode such as an anode of the light emitting element EL may be electrically connected to the third node n3, and a second electrode such as a cathode of the light emitting element EL may be connected to a second power line P2 to which a cathode voltage ELVSS is applied, such as Figure 5 In other exemplary embodiments, the anode of the light emitting element EL may be connected to the fourth node n4, such as Fig. 9A and Fig. 9B As shown. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When a voltage is applied to the anode and cathode of the light emitting element EL, holes from the hole transport layer (HTL) and electrons from the electron transport layer (ETL) move to the light emitting layer (EML) to form excitons. In this case, visible light is emitted from the light emitting layer EML. The OLED can be implemented as an OLED having a tandem structure in which a plurality of light emitting layers are stacked. An OLED having a tandem structure can improve the brightness and life of a pixel. For example, the light emitting layer may include one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL), but the present disclosure is not limited thereto.

[0121] For example, the first switching element T1 is connected between the first power line P1 to which the pixel driving voltage ELVDD is applied and the second node n2. In addition, the first switching element T1 is turned on or off in response to the EM signal EMn, for example, the first switching element T1 is turned on in response to the gate low voltage VGL of the EM signal EMn, and is turned off in response to the gate high voltage VGH of the EM signal EMn, but is not limited thereto. When the first switching element T1 is turned on, the pixel driving voltage ELVDD is applied to the second node n2. The first switching element T1 includes a gate electrode connected to the gate line G3n to which the EM signal EMn is applied, a first electrode connected to the first power line P1, and a second electrode connected to the second node n2.

[0122] For example, the second switch element T2 is connected between the data line DL to which the data voltage Vdata of the pixel data is applied and the second node n2. The second switch element T2 is turned on or off in response to the second scan signal SC2n, for example, the second switch element T2 is turned on in response to the gate low voltage VGL of the second scan signal SC2n, and is turned off in response to the gate high voltage VGH of the second scan signal SC2n, but is not limited thereto. When the second switch element T2 is turned on, the data line DL to which the data voltage Vdata of the pixel data is applied is electrically connected to the second node n2. The second switch element T2 includes a gate electrode connected to the second gate line G2n to which the second scan signal SC2n is applied, a first electrode connected to the data line DL, and a second electrode connected to the second node n2.

[0123] For example, the third switch element T3 is connected between the first node n1 and the third node n3. The third switch element T3 is turned on or off in response to the first-second scan signal SC1n, for example, the third switch element T3 is turned on in response to the gate high voltage VGH of the first-second scan signal SC1n, and is turned off in response to the gate low voltage VGL of the first-second scan signal SC1n, but is not limited thereto. When the third switch element T3 is turned on, the driving element DT operates as a diode whose gate electrode and the second electrode are connected. The third switch element T3 includes a gate electrode connected to the first-second gate line G1n to which the first-second scan signal SC1n is applied, a first electrode connected to the first node n1, and a second electrode connected to the third node n3.

[0124] For example, the fourth switch element T4 is connected between the first node n1 and the third power line P3 to which the initialization voltage Vint is applied. The fourth switch element T4 is turned on or off in response to the first-first scan signal SC1n-i, for example, the fourth switch element T4 is turned on in response to the gate high voltage VGH of the first-first scan signal SC1n-i, and is turned off in response to the gate low voltage VGL of the first-first scan signal SC1n-i. When the fourth switch element T4 is turned on, the initialization voltage Vint is applied to the gate electrode of the capacitor Cst and the driving element DT. The fourth switch element T4 includes a gate electrode connected to the first-first gate line G1n-i to which the first-first scan signal SC1n-i is applied, a first electrode connected to the first node n1, and a second electrode connected to the third power line P3 to which the initialization voltage Vint is applied.

[0125] Figure 6 is shown applied to Figure 5 The waveform diagram of the gate signal and data voltage of the pixel circuit shown. FIG. 7A to FIG. 7C It is shown Figure 5 A circuit diagram of the phased operation of the pixel circuit is shown.

[0126] Reference Figures 5 to 7C , the driving period of the pixel may include an initialization period INI, a sampling period SAM and a light emitting period EMI.

[0127] During the initialization period INI, the first-first scan signal SC1n-i for controlling the turning on and off of the fourth switching element T4 is generated as the gate high voltage VGH, and then the first-second scan signal SC1n for controlling the turning on and off of the third switching element T3 is generated as the gate high voltage VGH. During the initialization period INI, the voltage of the second scan signal SC2n for controlling the turning on and off of the second switching element T2 and the voltage of the EM signal EMn for controlling the turning on and off of the first switching element T1 are the gate high voltage VGH. Therefore, during the initialization period INI, the third switching element T3 and the fourth switching element T4 are turned on, as shown in FIG. Fig. 7A As shown, the initialization voltage Vint is applied to the first node n1 and the third node n3. During the initialization period INI, the first switch element T1 and the second switch element T2 are in the off state. During the initialization period INI, since no current flows through the light emitting element EL, the light emitting element EL is in the off state and does not emit light.

[0128] During the sampling period SAM, the voltage of the second scanning signal SC2n for controlling the turning on and off of the second switching element T2 is generated as a pulse of the gate low voltage VGL synchronized with the data voltage Vdata of the pixel data, and then inverted to the gate high voltage VGH. During the sampling period SAM, the first-first scanning signal SCin-1 for controlling the turning on and off of the fourth switching element T4 is generated as a pulse of the gate low voltage VGL. The pulse width of the second scanning signal SC2n may be one horizontal period. During the sampling period SAM, the first node n1 is connected to the third node n3 through the third switching element T3, so that the driving element DT operates as a diode. During the sampling period SAM, the voltage of the first-second scanning signal SC1n for controlling the turning on and off of the third switching element T3 and the voltage of the EM signal EMn for controlling the turning on and off of the first switching element T1 may be the gate high voltage VGH, and the voltage of the first-first scanning signal SC1n-i may be the gate low voltage VGL. When the second switching element T2 and the third switching element T3 are turned on in the sampling period SAM, the data voltage Vdata is applied to the second node n2, and the data voltage Vdata is also applied to the first node n1 and the third node n3 through the driving element DT in the turned-on state. Figure 7B During the sampling period SAM, the first switch element T1 and the fourth switch element T4 are turned off. Figure 7BAs shown. In this case, the voltage of the first node n1 is the data voltage Vdata, and the voltage of each of the second node n2 and the third node n3 is the voltage Vdata+Vth obtained by adding the threshold voltage Vth of the driving element DT to the data voltage Vdata. During the sampling period SAM, the gate-source voltage Vgs of the driving element DT is the threshold voltage Vth of the driving element DT. At this time, the threshold voltage Vth of the driving element DT is sampled and stored in the capacitor Cst with the compensated data voltage Vdata+Vth. At the end of the sampling period SAM, the voltage of the capacitor Cst is given by the voltage of ELVDD-(Vdata+Vth). During the sampling period SAM, since no current flows through the light-emitting element EL, the EL does not emit light.

[0129] During the light emission period EMI, the voltage of the first scan signal SC1n-i for controlling the turning on and off of the fourth switching element T4, the voltage of SC1n for controlling the turning on and off of the third switching element T3, and the voltage of the EM signal EMn for controlling the turning on and off of the first switching element T1 are the gate low voltage VGL, and the voltage of the second scan signal SC2n for controlling the turning on and off of the second switching element T2 is the gate high voltage VGH. During the light emission period EMI, the first switching element T1 is turned on in response to the gate low voltage VGL of the EM signal EMn to apply the pixel driving voltage ELVDD to the second node n2, as shown in FIG. Figure 7C As shown. During the light-emitting period EMI, a current path is formed between the pixel driving voltage ELVDD and the cathode voltage ELVSS. During the light-emitting period EMI, a current determined by the gate-source voltage Vgs of the driving element DT flows through the light-emitting element EL, so that the light-emitting element EL can emit light with a brightness corresponding to the grayscale value of the pixel data. During the light-emitting period EMI, the second switching element T2, the third switching element T3 and the fourth switching element T4 are in the off state.

[0130] Figure 8 is shown for output applied to Figure 5 FIG. 1 is a diagram of a gate driver 120 that displays a gate signal for a pixel circuit.

[0131] Reference Figure 5 and Figure 8 The gate driver 120 may include a plurality of shift registers for sequentially outputting scan signals, for example, a first shift register SR1 for sequentially outputting pulses of first scan signals SC1n-i, SC1n, a second shift register SR2 for sequentially outputting pulses of second scan signals SC2n, and a third shift register SR3 for outputting pulses of EM signals EMn, but the present disclosure is not limited thereto.

[0132] For example, the first shift register SR1 may include a plurality of signal transmission parts ST1 connected in cascade. The first shift register SR1 receives a start pulse VST1 and a clock CLK, and sequentially outputs pulses of a first scanning signal in the order of SC11, SC12, ..., SC1n-i, and SC1n. For example, a first signal transmission part ST1 among the plurality of signal transmission parts ST1 receives a start pulse VST1, and all of the plurality of signal transmission parts ST1 receive a clock CLK.

[0133] The second shift register SR2 includes a plurality of signal transmission parts ST2 connected in cascade. The second shift register SR2 receives a start pulse VST2 and a clock CLK, and sequentially outputs pulses of a second scanning signal in the order of SC21, SC22, ..., SC2n-i, and SC2n. For example, the first signal transmission part ST2 among the plurality of signal transmission parts ST2 receives the start pulse VST2, and all the plurality of signal transmission parts ST2 receive the clock CLK.

[0134] The third shift register SR3 may include a plurality of signal transmission parts ST3 connected in cascade. The third shift register SR3 receives a start pulse VST3 and a clock CLK, and sequentially outputs pulses of EM signals in the order of EM1, EM2, ..., EMn-i, and EMn. For example, the first signal transmission part ST3 of the plurality of signal transmission parts ST3 receives the start pulse VST3, and all the plurality of signal transmission parts ST3 receive the clock CLK.

[0135] The clock CLK input to the shift registers SR1, SR2 and SR3 may be two or more clocks with different phases, but the present disclosure is not limited thereto. The start pulse and the clock input to the shift registers SR1, SR2 and SR3 may have one or more of different phases, frequencies and duty cycles.

[0136] Figure 5 The pixel circuit shown requires four selection signals SC1n, SC1n-i, SC2n, and EMn. In the present disclosure, three shift registers SR1, SR2, and SR3 are used to output the selection signals SC1n, SC1n-i, SC2n, and EMn, thereby allowing the circuit size of the selection driver 120 to be reduced or minimized. For example, the first shift register SR1 is used to output the selection signals SC11 to SC1n, the second shift register SR2 is used to output the selection signals SC21 to SC2n, and the third shift register SR3 is used to output the selection signals EM1 to EMn. At the same time, Figure 5 The pixel circuit shown may have a lower driving frequency in the low power mode. In this case, the data voltage Vdata is not applied to the pixel circuit in the holding frame.

[0137] Fig. 9A and Fig. 9B is a circuit diagram illustrating a pixel circuit according to another exemplary embodiment of the present disclosure.

[0138] Reference Fig. 9A and Fig. 9B The pixel circuit may include a light emitting element EL, a driving element DT for driving the light emitting element EL, a plurality of switching elements M1 to M7, and a first capacitor Cst, etc., but the present disclosure is not limited thereto. In addition, the pixel circuit may further include a second capacitor C2, such as Fig. 9B shown.

[0139] The third switching element M3 and the fourth switching element M4 may be implemented as n-channel oxide TFTs, but the present disclosure is not limited thereto. The driving element DT and the first switching element M1, the second switching element M2, the fifth switching element M5, the sixth switching element M6, and the seventh switching element M7 may be implemented as p-channel LTPS TFTs, but the present disclosure is not limited thereto. The n-channel oxide TFT is turned on in response to the gate high voltage VGH, and it is turned off in response to the gate low voltage VGL, as shown in FIG. Fig.11 and Fig.13 The p-channel LTPS TFT is turned on in response to the gate low voltage VGL, and it is turned off in response to the gate high voltage VGH, as shown in FIG. Fig.11 and Fig.13 That is, the third switching element M3 and the fourth switching element M4 are turned on in response to the gate high voltage VGH, and are turned off in response to the gate low voltage VGL. The driving element DT and the first switching element M1, the second switching element M2, the fifth switching element M5, the sixth switching element M6, and the seventh switching element M7 are turned on in response to the gate low voltage VGL, and are turned off in response to the gate high voltage VGH.

[0140] The pixel circuit is connected to the data line DL to which the data voltage Vdata of the pixel data and the first compensation voltage Vpark are applied, and is connected to the gate lines GL11, GL1i, GL2, GL3, GL4, GL5 to which the selection signals SC1n, SC1n-i, SC2n, SC3n, EMn are applied. In the low power mode, the data driver 110 supplies the data voltage Vdata to the data line DL during the sampling period of the refresh frame period, and does not output the data voltage Vdata during the holding frame period. During the holding frame period, the first compensation voltage Vpark is supplied to the data line DL. The first compensation voltage Vpark may be applied from the compensation voltage generator 160.

[0141] The pixel circuit may be connected to a first power line PL1 to which a pixel driving voltage ELVDD is applied, a second power line PL2 to which a cathode voltage ELVSS is applied, a third power line PL3 to which an initialization voltage Vint is applied, a fourth power line PL4 to which a second compensation voltage VOBS is applied, and a fifth power line PL5 to which a third compensation voltage VAR is applied. On the display panel 100, the power sources to which the power lines PL1 to PL5 are connected may be commonly connected to all pixels.

[0142] For example, the pixel driving voltage ELVDD and the cathode voltage ELVSS may be set to, but not limited to, a voltage that allows the driving element DT to operate in a saturation region. The pixel driving voltage ELVDD may be set to, but not limited to, a voltage between 2 [V] and 3 [V], and the cathode voltage ELVSS may be set to, but not limited to, a voltage between -8 [V] and -10 [V], but not limited thereto. The gate high voltage VGH may be set to, but not limited to, a voltage higher than the pixel driving voltage ELVDD, and the gate low voltage VGL may be set to, but not limited to, a voltage lower than the cathode voltage ELVSS, but not limited thereto.

[0143] For example, the data voltage Vdata may have a dynamic range between 2 [V] and 6 [V]. Within the dynamic range, the voltage level of the data voltage Vdata is selected according to the grayscale value of the pixel data. The initialization voltage Vint may be set to, but not limited to, a voltage lower than the lower limit of the data voltage Vdata and higher than the cathode voltage ELVSS. For example, when the data voltage Vdata has a lower limit voltage of 2 [V] and the cathode voltage ELVSS has a lower limit voltage of -9 [V], the initialization voltage Vint may be set to a specific voltage between -5 [V] and -7 [V].

[0144] For example, the first compensation voltage Vpark may be set within a voltage range that is smaller than the dynamic range of the data voltage Vdata. For example, when the dynamic range of the data voltage Vdata is between 2 [V] and 6 [V], the first compensation voltage Vpark may be set to a specific voltage between 4 [V] and 6 [V], or may vary within the voltage range.

[0145] For example, the second compensation voltage VOBS may be set within a voltage range lower than the pixel driving voltage ELVDD and partially overlap with the dynamic range of the data voltage Vdata. For example, when the data voltage Vdata has a dynamic range between 2 [V] and 6 [V], the second compensation voltage VOBS may be set to a specific voltage between 4 [V] and 8 [V], or may vary within the voltage range.

[0146] For example, the third compensation voltage VAR may be set to a specific voltage, or it may vary. For example, when the data voltage Vdata has a dynamic range between 2 [V] and 6 [V], the third compensation voltage VAR may be set to a specific voltage between -4 [V] and 8 [V], or it may vary within the voltage range.

[0147] For example, the compensation voltages Vpark, VOBS, and VAR applied to one sub-pixel at a specific position in the display area AA may be set to different voltages, but the present disclosure is not limited thereto.

[0148] For example, the gate signals SC1n, SCn-i, SC2n, SC3n, and EMn include pulses that swing between a gate high voltage VGH and a gate low voltage VGL. Fig. 9A and Fig. 9B In the pixel circuit shown, the gate driver 120 may include a plurality of shift registers outputting scan signals, for example, a first shift register outputting a first scan signal SC1n, SC1n-i, a second shift register outputting a second scan signal SC2n, a third shift register outputting a third scan signal SC3n, and a fourth shift register outputting an EM signal EMn, etc., but the present disclosure is not limited thereto. Each of the first to fourth shift registers outputs a pulse during a refresh frame and shifts the pulse in sequence. The first shift register and the second shift register have very low power consumption because they do not output a pulse during a hold frame HF.

[0149] The first scanning signals SC1n and SC1n-i include a first-first scanning signal SC1n-i and a first-second scanning signal SC1n which are sequentially output from the first shift register. The first-first scanning signal SC1n-i is output from the first shift register, and then the first-second scanning signal SC1n is output. Some periods of the pulse of the first-first scanning signal SC1n-i may overlap with some periods of the pulse of the first-second scanning signal SC1n. The pulse of the first-first scanning signal SC1n-i is later in phase than the pulse of the first-second scanning signal SC1n, and has the same pulse width W.

[0150] like Fig. 9A and Fig. 9B As shown, the driving element DT includes a gate electrode connected to a first node n1, a first electrode connected to a second node n2, and a second electrode connected to a third node n3. The first capacitor Cst is connected between a node on the first power line PL1 to which the pixel driving voltage ELVDD is applied and the first node n1.

[0151] The first capacitor Cst charges the pixel driving voltage ELVDD and the voltage of the first node n1 to suppress fluctuation of the gate-source voltage Vgs of the driving element DT driving the light emitting element EL.

[0152] like Fig. 9B As shown, the second capacitor C2 is connected between the first node n1 and the third gate line GL3 to which the third scan signal SC3n is applied. The second capacitor C2 suppresses the phenomenon that the gate voltage of the driving element DT fluctuates on the falling edge of the first-second scan signal SC1n and compensates for the amount of fluctuation. Fig.11 As shown, the voltage of the first-second scan signal SC1n may drop from the gate high voltage VGH to the gate low voltage VGL. At this time, due to the kickback voltage generated by the parasitic capacitance between the gate line GL11 to which the voltage of the first-second scan signal SC1n is applied and the first node n1, the gate voltage of the driving element DT may be temporarily reduced. When the voltage on the gate line GL11 to which the voltage of the first-second scan signal SC1n is applied drops to the gate low voltage VGL, the second capacitor C2 may suppress the kickback voltage to the gate high voltage VGH applied to the gate line GL3. In addition, when the voltage of the gate line GL3 to which the voltage of the third scan signal SC3n is applied rises to the gate high voltage VGH, the second capacitor C2 may compensate for the fluctuation of the gate voltage of the driving element DT that is reduced due to the kickback voltage.

[0153] The light emitting element EL may include a first electrode such as an anode connected to the fourth node n4 and a second electrode such as a cathode connected to the second power line PL2 to which the cathode voltage ELVSS is applied.

[0154] For example, the first switching element M1 is connected between the first power line PL1 to which the pixel driving voltage ELVDD is applied and the second node n2. The first switching element M1 is turned on or off in response to the EM signal EMn, for example, the first switching element M1 is turned on in response to the gate low voltage VGL of the EM signal EMn, and is turned off in response to the gate high voltage VGH of the EM signal EMn, but the present disclosure is not limited thereto. When the first switching element M1 is turned on, the pixel driving voltage ELVDD is applied to the second node n2. The first switching element M1 includes a gate electrode connected to the fourth gate line GL4 to which the EM signal EMn is applied, a first electrode connected to the first power line PL1 to which the pixel driving voltage ELVDD is applied, and a second electrode connected to the second node n2.

[0155] For example, the second switch element M2 is connected between the data line DL to which the data voltage Vdata of the pixel data is applied and the second node n2. The second switch element M2 is turned on or off in response to the second scan signal SC2n, for example, the second switch element M2 is turned on in response to the gate low voltage VGL of the second scan signal SC2n, and is turned off in response to the gate high voltage VGH of the second scan signal SC2n, but the present disclosure is not limited thereto. When the second switch element M2 is turned on, the data line DL to which the data voltage Vdata of the pixel data is applied is connected to the second node n2. The second switch element M2 includes a gate electrode connected to the second gate line GL2 to which the second scan signal SC2n is applied, a first electrode connected to the data line DL, and a second electrode connected to the second node n2.

[0156] For example, the third switch element M3 is connected between the first node n1 and the third node n3. The third switch element M3 is turned on or off in response to the first-second scan signal SC1n, for example, the third switch element M3 is turned on in response to the gate high voltage VGH of the first-second scan signal SC1n, and is turned off in response to the gate low voltage VGL of the first-second scan signal SC1n, but the present disclosure is not limited thereto. When the third switch element M3 is turned on, the first node n1 is connected to the third node n3. Therefore, when the third switch element M3 is turned on, the driving element DT operates as a diode whose gate electrode and the second electrode are connected. The third switch element M3 includes a gate electrode connected to the first-second gate line GL11 to which the first-second scan signal SC1n is applied, a first electrode connected to the first node n1, and a second electrode connected to the third node n3.

[0157] For example, the fourth switch element M4 is connected between the first node n1 and the third power line PL3 to which the initialization voltage Vint is applied. The fourth switch element M4 is turned on or off in response to the first-first scan signal SC1n-i, for example, the fourth switch element M4 is turned on in response to the gate high voltage VGH of the first-first scan signal SC1n-i, and is turned off in response to the gate low voltage VGL of the first-first scan signal SC1n-i, but the present disclosure is not limited thereto. When the fourth switch element M4 is turned on, the initialization voltage Vint is applied to the gate electrode of the capacitor Cst and the driving element DT. The fourth switch element M4 includes a gate electrode connected to the first-first gate line GL1i to which the first-first scan signal SC1n-i is applied, a first electrode connected to the first node n1, and a second electrode connected to the third power line PL3.

[0158] For example, the fifth switching element M5 is connected between the second node n2 and the fourth power line PL4 to which the second compensation voltage VOBS is applied. The fifth switching element M5 is turned on or off in response to the third scan signal SC3n, for example, the fifth switching element M5 is turned on in response to the gate low voltage VGL of the third scan signal SC3n, and is turned off in response to the gate high voltage VGH of the third scan signal SC3n, but the present disclosure is not limited thereto. When the fifth switching element M5 is turned on, the second compensation voltage VOBS is applied to the second node n2. The fifth switching element M5 includes a gate electrode connected to the third gate line GL3 to which the third scan signal SC3n is applied, a first electrode connected to the second node n2, and a second electrode connected to the fourth power line PL4.

[0159] For example, the sixth switch element M6 is connected between the fourth node n4 and the fifth power line PL5 to which the third compensation voltage VAR is applied. The sixth switch element M6 is turned on or off in response to the third scan signal SC3n, for example, the sixth switch element M6 is turned on in response to the gate low voltage VGL of the third scan signal SC3n, and is turned off in response to the gate high voltage VGH of the third scan signal SC3n, but the present disclosure is not limited thereto. When the sixth switch element M6 is turned on, the third compensation voltage VAR is applied to the anode of the light emitting element EL connected to the fourth node n4. The sixth switch element M6 includes a gate electrode connected to the third gate line GL3, a first electrode connected to the fourth node n4, and a second electrode connected to the fifth power line PL5 to which the third compensation voltage VAR is applied.

[0160] For example, the seventh switch element M7 is connected between the third node n3 and the fourth node n4. The seventh switch element M7 is turned on or off in response to the EM signal EMn, for example, the seventh switch element M7 is turned on in response to the gate low voltage VGL of the EM signal EMn, and is turned off in response to the gate high voltage VGH of the EM signal EMn, but the present disclosure is not limited thereto. The seventh switch element M7 is turned on in response to the gate low voltage VGL of the EM signal EMn to connect the third node n3 to the fourth node n4. The seventh switch element M7 includes a gate electrode connected to the fourth gate line GL4, a first electrode connected to the third node n3, and a second electrode connected to the fourth node n4.

[0161] The data voltage Vdata of the pixel data is applied to the data line DL during a refresh frame period when the pixel data is written to the pixel. The first compensation voltage Vpark is set to a voltage that compensates for the brightness change of the pixel and is applied to the data line DL during a hold frame period when no pixel data is written to the pixel. During the hold frame, the pixel 101 is driven by the data voltage Vdata charged to the first capacitor Cst in the previous refresh frame.

[0162] When the data line DL and the second node n2 are electrically connected through the turned-on second switching element M2, the data voltage Vdata is applied to the second node n2. In the disconnected state of the second switching element M2, that is, in the state where the data line DL and the second node n2 are electrically disconnected, the first compensation voltage Vpark may be applied to the second node n2 as a leakage current of the second switching element M2, and may be applied to the first node n1 by means of parasitic capacitance. Here, the parasitic capacitance may include a parasitic capacitance existing between the first node n1 and the second node n2 and a parasitic capacitance existing between the first node n1 and the data line DL. The gate-source voltage Vgs of the driving element DT may be finely adjusted by the first compensation voltage Vpark.

[0163] The compensation voltages Vpark, VOBS, and VAR may compensate for a difference in brightness characteristics of the pixels 101 between a refresh frame and a hold frame in the low power mode to improve the quality of an image reproduced from the pixels 101.

[0164] FIG. 10A to FIG. 10E is a waveform diagram showing the luminance characteristics according to the driving frequency and compensation voltage of a pixel. Flicker can be measured based on the amount of change in luminance of a pixel on a time axis. FIG. 10A to FIG. 10D 1. Brightness characteristics of a pixel in which flicker is measured in a pixel due to a change in a threshold voltage characteristic of a driving element according to a change in a driving frequency of the pixel when no compensation voltages Vpark, VOBS, and VAR are applied to the pixel are shown. Fig.10E FIG. 4 shows an improvement in the brightness characteristics of a pixel when the first compensation voltage Vpark, the second compensation voltage VOBS, and the third compensation voltage VAR are applied to the pixel. FIG. 10A to FIG. 10E , "F#" indicates frame numbers from the first frame to the 120th frame (1 to 120 frames). "REF" indicates a brightness reference value representing the brightness of a pixel when a data voltage having the same white gray value is applied to the pixel. "RF" indicates a refresh frame period and "HF" indicates a hold frame period.

[0165] Fig. 10A FIG. 1 shows the brightness characteristics of a pixel when the pixel is driven at a refresh frame frequency of 120 Hz. Fig. 10A In the embodiment, the data voltage Vdata of the pixel data is supplied to the pixel at 120Hz per frame. In this case, since the data voltage Vdata is applied per frame, the pixel is measured to have a constant brightness when the data voltage Vdata is the same, so the flicker is not visible. In this case, the flicker value of the pixel can be constantly measured as the same value.

[0166] Fig. 10B FIG. 1 shows the brightness characteristics of a pixel when the pixel is driven at a refresh frame frequency of 10 Hz. Fig. 10BIn the embodiment of the present invention, a data voltage Vdata is applied to a pixel during a refresh frame (1, ..., 109) set to have a time interval of 12 frame periods within one second (1), and no data voltage Vdata is applied to the pixel during a hold frame (2-12, ..., 110-120) between the refresh frames. During the refresh frame (1, ..., 109), the brightness of the pixel may decrease, and during the hold frame period (2-12, ..., 110-120), the threshold voltage Vth characteristic of the driving element DT may change, causing the brightness of the pixel to increase over time due to the change in the gate-source voltage Vgs. In this case, the brightness of the pixel fluctuates at a periodic rate of 10 Hz, so that a flicker of 10 Hz can be measured.

[0167] Fig. 10C 1 shows the brightness characteristics of the pixel when the pixel is driven at a refresh frame frequency of 10 Hz with an off duration per frame period. Here, the off duration is the time interval during which the light emitting element EL is turned off by the gate cutoff voltage branch of the EM signal. Fig. 10C In the embodiment, a data voltage Vdata is applied to a pixel during a refresh frame (1, ..., 109) which is set to have a time interval of 12 frame periods within one second (1), and no data voltage Vdata is applied to the pixel during a hold frame (2 to 12, ..., 110 to 120). During the refresh frame (1, ..., 109), the brightness of the pixel may decrease, and during the hold frame period (2 to 12, ..., 110 to 120), the brightness of the pixel may change due to a change in the gate-source voltage of the driving element DT. In this case, the brightness of the pixel fluctuates at a periodic rate of 10 Hz, so that a flicker of 10 Hz can be measured. Fig. 10C In the figure, the dotted circle represents the time period when the brightness of the pixel changes.

[0168] Fig. 10D 1 shows the brightness characteristics of a pixel when the pixel is driven at a refresh frame frequency of 10 Hz with an off-duration per frame period. Fig. 10D In the embodiment, a data voltage Vdata is applied to a pixel during a refresh frame (1, ..., 109) set to have a time interval of 12 frame periods within one second (1), and no data voltage Vdata is applied to the pixel during a hold frame (2-12, ..., 110-120). During the periods of the refresh frame (1, ..., 109) and the hold frame (2-12, ..., 110-120), a second compensation voltage VOBS is applied to a second node n2 of the pixel circuit, which reduces or minimizes the brightness difference of the pixel during the period of the hold frame period (2-12, ..., 110-120).

[0169] Fig.10E1 shows the brightness characteristics of a pixel when the pixel is driven at a refresh frame frequency of 10 Hz with an off-duration per frame period. Fig.10E In the embodiment, a data voltage Vdata is applied to a pixel during a refresh frame (1, ..., 109) set to have a time interval of 12 frame periods within one second (1), and no data voltage Vdata is applied to the pixel during a hold frame (2-12, ..., 110-120). During the hold frame (2-12, ..., 110-120), when a first compensation voltage Vpark, a second compensation voltage VOBS, and a third compensation voltage VAR are applied to the pixel circuit, the brightness difference of the pixel between the refresh frame (1, ..., 109) and the hold frame (2-12, ..., 110-120) is further reduced or minimized. In this case, the brightness difference of the pixel can be minimized so that flicker is not measured during the refresh frame (1, ..., 109) and the hold frame (2-12, ..., 110-120).

[0170] The first compensation voltage Vpark is applied to the data line DL during the hold frame (2-12, ..., 110-120). The second compensation voltage VOBS and the third compensation voltage VAR may be generated as an AC voltage changed between the refresh frame RF and the hold frame HF and applied to the power lines PL4 and PL5.

[0171] Fig.11 is a waveform diagram showing a strobe signal and a data voltage generated during a refresh frame RF. FIG. 12A to FIG. 12D is a circuit diagram showing the phased operation of the pixel circuit during a refresh frame RF.

[0172] Reference Fig.11 During the refresh frame RF, the driving period of the pixel may be divided into a first on-bias period OBS1, a first initialization period PRE, a second initialization period INI, a sampling period SAM, a second on-bias period OBS2, and a light-emitting period EMI. A first floating period Tf1 may be set between the first on-bias period OBS1 and the first initialization period PRE, but the present disclosure is not limited thereto. A second floating period Tf2 may be set between the sampling period SAM and the second on-bias period OBS2, but the present disclosure is not limited thereto. A third floating period Tf3 may be set between the second on-bias period OBS2 and the light-emitting period EMI, but the present disclosure is not limited thereto.

[0173] During the first on bias period OBS1, the voltage of the first-second scan signal SC1n for controlling the turning on and off of the third switching element M3, the voltage of the first-first scan signal SC1n-i for controlling the turning on and off of the fourth switching element M4, and the voltage of the third scan signal SC3n for controlling the turning on and off of the fifth switching element M5 and the sixth switching element M6 are the gate low voltage VGL, and the voltage of the second scan signal SC2n for controlling the turning on and off of the second switching element M2 is the gate high voltage VGH, but the present disclosure is not limited thereto. The voltage of the EM signal EMn for controlling the turning on and off of the first switching element M1 and the seventh switching element M7 is the gate high voltage VGH during the first on bias period OBS1. Therefore, during the first on bias period OBS1, the fifth switching element M5 and the sixth switching element M6 are turned on, as shown in FIG. Fig. 12A As shown, the second compensation voltage VOBS is applied to the second node n2 and the third compensation voltage VAR is applied to the fourth node n4.

[0174] During the first on-bias period OBS1, the first switch element M1, the second switch element M2, the third switch element M3, the fourth switch element M4 and the seventh switch element M7 are in the off state. Fig. 12A As shown. During the first on-bias period OBS1, since the on-bias voltage is applied to the driving element DT, the driving element DT may be turned on, but since the seventh switching element M7 is in an off state, no current may be supplied to the light emitting element EL. In addition, since the voltage difference between the third compensation voltage VAR and the cathode voltage ELVSS is less than the threshold voltage of the light emitting element EL, the light emitting element EL does not emit light during the first on-bias period OBS1.

[0175] During the first on bias period OBS1, the voltages of the second node n2 and the third node n3 are the second compensation voltage VOBS, and the voltage of the fourth node n4 is the third compensation voltage VAR. In this case, the voltage of the first node n1 may be a voltage of Vdata+Vth obtained by adding the threshold voltage Vth of the driving element DT to the previously stored data voltage Vdata.

[0176] During the first floating period Tf1, the voltage of the first scan signal Sc1n for controlling the turning on and off of the third switching element M3 and the voltage of SC1n-i for controlling the turning on and off of the fourth switching element M4 are the gate low voltage VGL, and the voltage of the second scan signal SC2n for controlling the turning on and off of the second switching element M2 and the voltage of the second scan signal SC3n for controlling the turning on and off of the fifth switching element M5 and the sixth switching element M6 are the gate high voltage VGH. The voltage of the EM signal EMn for controlling the turning on and off of the first switching element M1 and the seventh switching element M7 is the gate high voltage VGH during the first floating period Tf1. Therefore, during the first floating period Tf1, since the first to seventh switching elements M1 to M7 are all in the off state, the first node n1, the second node n2, the third node n3 and the fourth node n4 are floated to maintain their previous states.

[0177] During the first initialization period PRE, the voltages of the first-first scan signal SC1n-i for controlling the turning on and off of the fourth switching element M4, the second scan signal SC2n for controlling the turning on and off of the second switching element M2, and the third scan signal SC3n for controlling the turning on and off of the fifth switching element M5 and the sixth switching element M6 are the gate high voltage VGH, and the voltage of the first-second scan signal SC1n for controlling the turning on and off of the third switching element M3 is the gate low voltage VGL. Therefore, during the first initialization period PRE, the fourth switching element M4 is turned on, as shown in FIG. Fig. 12B As shown, the initialization voltage Vint is applied to the first node n1. During the first initialization period PRE, the gate-source voltage Vgs of the driving element DT may increase, and thus the on bias voltage may be applied to the driving element DT. During the first initialization period PRE, the light emitting element EL is in an off state and does not emit light.

[0178] During the second initialization period INI, the scan signal SC1n for controlling the turning on and off of the third switch element M3, the SC1n-i for controlling the turning on and off of the fourth switch element M4, the SC2n for controlling the turning on and off of the second switch element M2, the SC3n for controlling the turning on and off of the fifth switch element M5 and the sixth switch element M6, and the EM signal EMn for controlling the turning on and off of the first switch element M1 and the seventh switch element M7 are the gate high voltage VGH. Therefore, during the second initialization period INI, the third switch element M3 and the fourth switch element M4 are turned on to apply the initialization voltage Vint to the first node n1 and the third node n3, and the initialization voltage Vint is also applied to the second node n2 through the driving element DT maintained in the on state. During the second initialization period INI, the light emitting element EL is in the off state and does not emit light. During the second initialization period INI, since the sixth switch element M6 and the seventh switch element M7 are in the off state, the fourth node n4 floats to maintain its previous state.

[0179] During the sampling period SAM, the voltage of the second scanning signal SC2n for controlling the turning on and off of the second switching element M2 is generated as a pulse of the gate low voltage VGL synchronized with the data voltage Vdata of the pixel data, and then inverted to the gate high voltage VGH. The pulse width of the second scanning signal SC2n may be one horizontal period. During the sampling period SAM, the voltage of the first-second scanning signal SC1n for controlling the turning on and off of the third switching element M3, the voltage of the third scanning signal SC3n for controlling the turning on and off of the fifth switching element M5 and the sixth switching element M6, and the voltage of the EM signal EMn for controlling the turning on and off of the first switching element M1 and the seventh switching element M7 are the gate high voltage VGH, and the voltage of the first-first scanning signal SC1n-i for controlling the turning on and off of the fourth switching element M4 is the gate low voltage VGL, and the second scanning signal SC2n for controlling the turning on and off of the second switching element M2 is the gate low voltage VGL. During the sampling period SAM, the second switch element M2 and the third switch element M3 are in the on state, while the first switch element M1, the fourth switch element M4, the fifth switch element M5, the sixth switch element M6 and the seventh switch element M7 are in the off state. Fig.12D When the second switching element M2 is turned on in response to the gate low voltage of the scan pulse in the sampling period SAM, the data voltage Vdata is applied to the second node n2, and when the third switching element M3 is turned on in response to the gate high voltage of the first-second scan signal SC1n, the data voltage Vdata is also applied to the first node n1 and the third node n3 through the driving element DT in the turned-on state, as shown in FIG. Fig.12DIn this case, the voltage of the second node n2 is the data voltage Vdata, and the voltage of each of the first node n1 and the third node n3 is a voltage of Vdata+Vth obtained by adding the threshold voltage Vth of the driving element DT to the data voltage Vdata. During the sampling period SAM, the fourth node n4 is in a floating state, the light emitting element EL is in an off state and thus does not emit light.

[0180] During the second floating period Tf2, the voltage of the first-second scan signal SC1n for controlling the turning on and off of the third switch element M3 and the first-first scan signal SC1n-i for controlling the turning on and off of the fourth switch element M4 is the gate low voltage VGL, and the voltage of the second scan signal SC2n for controlling the turning on and off of the second switch element M2 and the third scan signal SC3n for controlling the turning on and off of the fifth switch element M5 and the sixth switch element M6 is the gate high voltage VGH. The voltage of the EM signal EMn for controlling the turning on and off of the first switch element M1 and the seventh switch element M7 is the gate high voltage VGH during the second floating period Tf2. During the second floating period Tf2, the first switch element M1 to the seventh switch element M7 are all in the off state. Therefore, during the second floating period Tf2, since the first switch element M1 to the seventh switch element M7 are all in the off state, the first node n1, the second node n2, the third node n3 and the fourth node n4 are floated to maintain their previous states.

[0181] During the second on-bias period OBS2, the voltage of the first-second scan signal SC1n for controlling the turning on and off of the third switching element M3, the voltage of the first-first scan signal SC1n-i for controlling the turning on and off of the fourth switching element M4, and the voltage of the third scan signal SC3n for controlling the turning on and off of the fifth switching element M5 and the sixth switching element M6 are the gate low voltage VGL, and the voltage of the second scan signal SC2n for controlling the turning on and off of the second switching element M2 is the gate high voltage VGH. The voltage of the EM signal EMn for controlling the turning on and off of the first switching element M1 and the seventh switching element M7 is the gate high voltage VGH during the second on-bias period OBS2. Therefore, during the second on-bias period OBS2, the fifth switching element M5 and the sixth switching element M6 are turned on, so that the second compensation voltage VOBS is applied to the second node n2 and the third compensation voltage VAR is applied to the fourth node n4, as shown in FIG. Fig.12E shown.

[0182] During the second on-bias period OBS2, the first switch element M1, the second switch element M2, the third switch element M3, the fourth switch element M4 and the seventh switch element M7 are in the off state. Fig.12E As shown. During the second on bias period OBS2, the on bias voltage is applied to the driving element DT. During the second on bias period OBS2, since the seventh switch element M7 is in an off state, no current can be supplied to the light emitting element EL, and since the voltage difference between the third compensation voltage VAR and the cathode voltage ELVSS is less than the threshold voltage of the light emitting element EL, the light emitting element EL does not emit light. In this case, the voltage of the first node n1 may be Vdata+Vth.

[0183] During the third floating period Tf3, the voltage of the first-second scan signal SC1n for controlling the turning on and off of the third switch element M3 and the voltage of the first-first scan signal SC1n-i for controlling the turning on and off of the fourth switch element M4 are the gate low voltage VGL, and the voltage of the second scan signal SC2n for controlling the turning on and off of the second switch element M2 and the voltage of the third scan signal SC3n for controlling the turning on and off of the fifth switch element M5 and the sixth switch element M6 are the gate high voltage VGH. The voltage of the EM signal EMn for controlling the first switch element M1 and the seventh switch element M7 is the gate high voltage VGH during the third floating period Tf3. During the third floating period Tf3, the first switch element M1 to the seventh switch element M7 are all in the off state. Therefore, during the third floating period Tf3, since the first switch element M1 to the seventh switch element M7 are all in the off state, the first node n1, the second node n2, the third node n3 and the fourth node n4 are floated to maintain their previous states.

[0184] During the light emission period EMI of the refresh frame RF, the voltage of the first-second scan signal SC1n for controlling the turning on and off of the third switching element M3, the voltage of the first-second scan signal SC1n-i for controlling the turning on and off of the fourth switching element M4, and the voltage of the EM signal EMn for controlling the turning on and off of the first switching element M1 and the seventh switching element M7 are the gate low voltage VGL, and the voltage of the second scan signal SC2n for controlling the turning on and off of the second switching element M2 and the voltage of the third scan signal SC3n for controlling the turning on and off of the fifth switching element M5 and the sixth switching element M6 are the gate high voltage VGH. During the light emission period EMI, the first switching element M1 and the seventh switching element M7 are turned on in response to the gate low voltage VGL of the EM signal EMn, as shown in FIG. Fig.12F Therefore, during the light emitting period EMI, a current path is formed between the pixel driving voltage ELVDD and the light emitting element EL.

[0185] During the light emitting period EMI, a current determined by the gate-source voltage Vgs of the driving element DT flows through the light emitting element EL, so that the light emitting element EL can emit light with a brightness corresponding to the grayscale value of the pixel data. During the light emitting period EMI, the second switching element M2 to the sixth switching element M6 are in the off state, such as Fig.12F shown.

[0186] Fig.13 is a waveform diagram showing a gate signal and a first compensation voltage generated during a hold frame HF. FIG. 14A to FIG. 14C is a circuit diagram illustrating the phased operation of the pixel circuit during a refresh frame HF.

[0187] Reference Fig.13 During the holding frame HF, the driving period of the pixel may be divided into a third on-bias period OBS3, a fourth on-bias period OBS4, and a light-emitting period EMI, but the present disclosure is not limited thereto. In addition, a fourth floating period Tf4 may be set between the third on-bias period OBS3 and the fourth on-bias period OBS4. In addition, a fifth floating period Tf5 may be set between the fourth on-bias period OBS4 and the light-emitting period EMI.

[0188] The data driver 110 does not output the data voltage Vdata during the holding frame HF. In the holding frame HF, the first compensation voltage Vpark is applied to the data line DL.

[0189] In the holding frame HF, the voltage of the first-second scanning signal SC1n for controlling the connection and disconnection of the third switching element M3 and the first-first scanning signal SC1n-i for controlling the connection and disconnection of the fourth switching element M4 is maintained at the gate low voltage VGL, and the voltage of the second scanning signal SC2n for controlling the connection and disconnection of the second switching element M2 is maintained at the gate high voltage VGH. Therefore, the second switching element M2, the third switching element M3 and the fourth switching element M4 in the pixel circuit remain in the disconnected state during the holding frame HF. In the gate driver 120, the first shift register and the second shift register have very low power consumption because they do not output pulses during the holding frame HF. During the holding frame HF, the pixel circuit can be driven by the capacitor voltage stored during the previous refresh frame RF.

[0190] During the third on-bias period OBS3, the voltage of the first-second scan signal SC1n for controlling the turning on and off of the third switching element M3, the voltage of the first-first scan signal SC1n-i for controlling the turning on and off of the fourth switching element M4, and the voltage of the third scan signal SC3n for controlling the turning on and off of the fifth switching element M5 and the sixth switching element M6 are the gate low voltage VGL, and the voltage of the second scan signal SC2n for controlling the turning on and off of the second switching element M2 is the gate high voltage VGH. The voltage of the EM signal EMn for controlling the turning on and off of the first switching element M1 and the seventh switching element M7 is the gate high voltage VGH during the third on-bias period OBS3. Therefore, during the third on-bias period OBS3, the fifth switching element M5 and the sixth switching element M6 are turned on, as shown in FIG. Fig.14A As shown, the second compensation voltage VOBS is applied to the second node n2 and the third compensation voltage VAR is applied to the fourth node n4. During the third on-bias period OBS3, the first switch element M1, the second switch element M2, the third switch element M3, the fourth switch element M4 and the seventh switch element M7 are in the off state, as shown in FIG. Fig.14A During the third on bias period OBS3, the voltage of the first node n1 is maintained at Vdata+Vth, and the light emitting element EL does not emit light.

[0191] During the fourth floating period Tf4, the voltage of the first-second scan signal SC1n for controlling the turning on and off of the third switching element M3 and the first-first scan signal SC1n-i for controlling the turning on and off of the fourth switching element M4 are the gate low voltage VGL, and the voltage of the second scan signal SC2n for controlling the turning on and off of the second switching element M2 and the third scan signal SC3n for controlling the turning on and off of the fifth switching element M5 and the sixth switching element M6 are the gate high voltage VGH. The voltage of the EM signal EMn for controlling the turning on and off of the first switching element M1 and the seventh switching element M7 is the gate high voltage VGH during the fourth floating period Tf4. During the fourth floating period Tf4, the first to seventh switching elements M1 to M7 are all in the off state, as shown in FIG. Fig. 14B Therefore, during the fourth floating period Tf4, since the first to seventh switching elements M1 to M7 are all in the off state, the first node n1, the second node n2, the third node n3 and the fourth node n4 are floated to maintain their previous states, as shown in FIG. Fig. 14B shown.

[0192] During the fourth on-bias period OBS4, the voltage of the first-second scan signal SC1n for controlling the turning on and off of the third switching element M3, the voltage of the first-first scan signal SC1n-i for controlling the turning on and off of the fourth switching element M4, and the voltage of the third scan signal SC3n for controlling the turning on and off of the fifth switching element M5 and the sixth switching element M6 are the gate low voltage VGL, and the voltage of the second scan signal SC2n for controlling the turning on and off of the second switching element M2 is the gate high voltage VGH. The voltage of the EM signal EMn for controlling the turning on and off of the first switching element M1 and the seventh switching element M7 is the gate high voltage VGH during the fourth on-bias period OBS4. Therefore, during the fourth on-bias period OBS4, the fifth switching element M5 and the sixth switching element M6 are turned on, as shown in FIG. Fig.14A As shown, the second compensation voltage VOBS is applied to the second node n2 and the third compensation voltage VAR is applied to the fourth node n4. During the fourth on-bias period OBS4, the first switch element M1, the second switch element M2, the third switch element M3, the fourth switch element M4 and the seventh switch element M7 are in an off state. During the fourth on-bias period OBS4, the voltage of the first node n1 is maintained at the voltage of Vdata+Vth, and the light emitting element EL does not emit light.

[0193] During the fifth floating period Tf5, the voltage of the first-second scan signal SC1n for controlling the turning on and off of the third switching element M3 and the first-first scan signal SC1n-i for controlling the turning on and off of the fourth switching element M4 are the gate low voltage VGL, and the voltage of the second scan signal SC2n for controlling the turning on and off of the second switching element M2 and the third scan signal SC3n for controlling the turning on and off of the fifth switching element M5 and the sixth switching element M6 are the gate high voltage VGH. The voltage of the EM signal EMn for controlling the turning on and off of the first switching element M1 and the seventh switching element M7 is the gate high voltage VGH during the fifth floating period Tf5. During the fifth floating period Tf5, the first to seventh switching elements M1 to M7 are all in the off state, as shown in FIG. Fig. 14B Therefore, during the fifth floating period Tf5, since the first to seventh switching elements M1 to M7 are all in the off state, the first node n1, the second node n2, the third node n3 and the fourth node n4 are floated to maintain their previous states, as shown in FIG. Fig. 14B shown.

[0194] The first compensation voltage Vpark is supplied to the data line DL during the holding frame HF. Since the second compensation voltage VOBS is applied to the second node n2 through the turned-on fifth switching element M5 during the turned-on bias periods OBS3 and OBS4 of the holding frame HF, the first compensation voltage Vpark has little effect on the first node n1 and the second node n2 during the turned-on bias periods OBS1 and OBS2.

[0195] During the floating periods Tf4 and Tf5 of the holding frame HF, since all the switching elements M1 to M7 in the pixel circuit are in the off state, the second compensation voltage VOBS is not applied to the second node n2. Fig. 14B As shown, the first compensation voltage Vpark can affect the voltages of the first node n1 and the second node n2 of the pixel circuit, thereby allowing the brightness of the pixel to be properly adjusted.

[0196] The first compensation voltage Vpark changes the voltage of the second node n2 by means of the leakage current of the second switch element M2. In addition, the first compensation voltage Vpark affects the voltage of the first node n1 by means of the parasitic capacitance (Cp) between the first node n1 and the second node n2 to change the voltage of the first node n1. The first compensation voltage Vpark can reduce or minimize the brightness difference of the pixel between the refresh frame RF and the hold frame HF, such as Fig.10E as shown in .

[0197] During the light emission period EMI of the hold frame HF, the voltage of the first-second scan signal SC1n for controlling the turning on and off of the third switching element M3, the voltage of the first-first scan signal SC1n-i for controlling the turning on and off of the fourth switching element M4, and the voltage of the EM signal EMn for controlling the turning on and off of the first switching element M1 and the seventh switching element M7 are the gate low voltage VGL, and the voltage of the second scan signal SC2n for controlling the turning on and off of the second switching element M2 and the voltage of the third scan signal SC3n for controlling the turning on and off of the fifth switching element M5 and the sixth switching element M6 are the gate high voltage VGH. During the light emission period EMI, the first switching element M1 and the seventh switching element M7 are turned on in response to the gate low voltage VGL of the EM signal EMn, as shown in FIG. Fig. 14C Therefore, Fig. 14C As shown, during the emission period EMI, a current path is formed between the pixel driving voltage ELVDD and the light emitting element EL. During the emission period EMI, the light emitting element EL can emit light by a current generated according to the gate-source voltage Vgs of the driving element DT stored in the capacitor Cst.

[0198] In the refresh frame RF, during the first initialization period PRE, a turn-on bias voltage may be applied to the driving element DT to increase the gate-source voltage Vgs of the driving element DT. In this case, there may be a difference in brightness of the pixel 101 between the refresh frame RF and the hold frame HF. The second compensation voltage VOBS may be as follows: Fig.15 The changes shown ensure that the brightness characteristics of the pixels are the same between the refresh frame RF and the hold frame HF.

[0199] Reference Fig.15 , the voltage of the second compensation voltage VOBS may be applied to the pixel 101 at a low voltage (L) during the refresh frame RF, and may be applied to the pixel 101 at a high voltage (H) during the hold frame HF. Although the gate-source voltage Vgs of the driving element DT is higher in the refresh frame RF than in the hold frame HF, if the second compensation voltage VOBS is lower in the refresh frame RF than in the hold frame HF, the gate-source voltage Vgs of the driving element DT may be lower, and thus the brightness characteristics of the pixel are the same in both the refresh frame RF and the hold frame HF. For example, the second compensation voltage VOBS may be, but is not limited to, 4 [V] in the refresh frame RF and 5 [V] in the hold frame HF.

[0200] Fig.16 is shown for output applied to Fig. 9A and Fig. 9B FIG. 1 is a diagram of a gate driver for a pixel circuit shown in FIG. Fig.17 It shows the input to Fig.16 The waveforms of the clock and start pulses of the shift register are shown.

[0201] Reference Fig. 9A , Fig. 9B , Fig.16 and Fig.17 The gate driver 120 may include a first shift register SR1 that sequentially outputs pulses of the first scan signals SC1n-i and SC1n, a second shift register SR2 that sequentially outputs pulses of the second scan signal SC2n, a third shift register SR3 that sequentially outputs pulses of the third scan signal SC3n, and a fourth shift register SR4 that outputs pulses of the EM signal EMn.

[0202] The first shift register SR1 includes a plurality of signal transmission parts ST1 connected in cascade. The first shift register SR1 receives a start pulse G1VST and clocks G1CLK1 and G1CLK2, and sequentially outputs pulses of first scanning signals SC1n-i and SC1n. The clocks G1CLK1 and G1CLK2 may include two or more shift clocks having different phases. The first scanning signals SC1n-i and SC1n may have a pulse width set to be wider than one horizontal period, such as Fig.11As shown, and may be simultaneously applied to pixels 101 disposed on a plurality of pixel rows. For example, the first-first scan signal SC1(n-10) and the first-second scan signal SC1(n-2) may be simultaneously applied to the first pixel PXL1 and the second pixel PXL2 vertically adjacent to each other. Subsequently, the first-first scan signal SC1(n-8) and the first-second scan signal SC1(n) may be simultaneously applied to the third pixel PXL3 and the fourth pixel PXL4 vertically adjacent to each other. Subsequently, the first-first scan signal SC1(n-6) and the first-second scan signal SC1(n+2) may be simultaneously applied to the fifth pixel PXL5 and the sixth pixel PXL6 vertically adjacent to each other.

[0203] In order to adjust the brightness difference between the pixel rows, the pulses of the second scanning signals SC21, SC23 and SC25 applied to the odd-numbered pixel rows and the pulses of the second scanning signals SC22, SC24 and SC26 applied to the even-numbered second pixel rows can be adjusted differently from each other in terms of their timing (such as phase, pulse width, etc.). To this end, the second shift register SR2 may include: a plurality of odd-numbered shift registers ST2O, which receive the first start pulse G2VST (ODD) and the first clocks G2CLK1 and G2CLK2 and sequentially output the pulses of the odd-numbered scanning signals SC21, SC23 and SC25; and a plurality of even-numbered shift registers ST2E, which receive the second start pulse G2VST (EVEN) and the second clocks G2CLK3 and G2CLK4 and sequentially output the pulses of the even-numbered scanning signals SC22, SC24 and SC26. The pulse width of the second scanning signals SC21 to SC26 may be one horizontal period. The first clocks G2CLK1 and G2CLK2 may include two or more shift clocks having different phases. The second clocks G2CLK3 and G2CLK4 may include two or more shift clocks having different phases. A carry signal may be transmitted between the odd-numbered signal transmission parts ST2O and the even-numbered signal transmission parts ST2E adjacent to each other.

[0204] After the pulse of the 2-1 scan signal SC21 is applied to the first pixel PXL1, the pulse of the 2-2 scan signal SC22 may be applied to the second pixel PXL2. Subsequently, after the pulse of the 2-3 scan signal SC23 is applied to the third pixel PXL3, the pulse of the 2-4 scan signal SC24 may be applied to the fourth pixel PXL4. Subsequently, after the pulse of the 2-5 scan signal SC25 is applied to the fifth pixel PXL5, the pulse of the 2-6 scan signal SC26 may be applied to the sixth pixel PXL6.

[0205] The third shift register SR3 includes a plurality of signal transmission parts ST3 connected in cascade. The third shift register SR3 receives the start pulse G3VST and the clocks G3CLK1 and G3CLK2, and sequentially outputs pulses of the third scan signal SC3n. The clocks G3CLK1 and G3CLK2 may include two or more shift clocks with different phases. The third scan signal SC3n may have a pulse width (e.g., 100 Hz) set to be wider than one horizontal period. Fig.11 and Fig.13 ), and may be simultaneously applied to pixels 101 disposed on a plurality of pixel rows. For example, a pulse of the third scan signal SC1(n-2) may be simultaneously applied to a first pixel PXL1 and a second pixel PXL2 vertically adjacent to each other. Subsequently, a pulse of the third scan signal SC3(n) may be simultaneously applied to a third pixel PXL3 and a fourth pixel PXL4 vertically adjacent to each other. Subsequently, a pulse of the third scan signal Sc1(n+2) may be simultaneously applied to a fifth pixel PXL5 and a sixth pixel PXL6 vertically adjacent to each other.

[0206] The fourth shift register SR4 includes a plurality of signal transmission parts ST4 connected in cascade. The fourth shift register SR4 receives the start pulse E3VST and the clocks ECLK1 and ECLK2, and sequentially outputs pulses of the EM signal EMn. The clocks ECLK1 and ECLK2 may include two or more shift clocks with different phases. The EM signal EMn may have a pulse width set to be wider than one horizontal period (e.g., Fig.11 and Fig.13 ), and may be simultaneously applied to pixels 101 disposed on a plurality of pixel rows. For example, pulses of the EM signal EM(n-2) may be simultaneously applied to a first pixel PXL1 and a second pixel PXL2 vertically adjacent to each other. Subsequently, pulses of the EM signal EM(n) may be simultaneously applied to a third pixel PXL3 and a fourth pixel PXL4 vertically adjacent to each other. Subsequently, pulses of the EM signal EM(n+2) may be simultaneously applied to a fifth pixel PXL5 and a sixth pixel PXL6 vertically adjacent to each other.

[0207] Fig. 9A and Fig. 9B The pixel circuit shown in FIG. 1 requires five selection signals SC1n, SC1n-i, SC2n, SC3n and EMn. In the present disclosure, as shown in FIG. Fig.16 As shown, four shift registers SR1, SR2, SR3, and SR4 are used to output gate signals SC1n, SC1n-i, SC2n, and EMn, thereby allowing the circuit size of the gate driver 120 to be reduced or minimized.

[0208] Fig.18is a diagram illustrating a compensation voltage generator according to an exemplary embodiment of the present disclosure.

[0209] Reference Fig.18 The compensation voltage generator 160 includes a voltage control unit 168 , a first compensation voltage output unit 162 , a second compensation voltage output unit 164 and a third compensation voltage output unit 166 .

[0210] The voltage control section 168 may determine the frame of the input image and the pixel row into which the pixel data is written by counting the timing signal synchronized with the pixel data of the input image. The timing signal may include one or more of a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. The voltage control section 168 outputs voltage data indicating the voltage level of each of the first compensation voltage Vpark, the second compensation voltage VOBS, and the third compensation voltage VAR. The voltage data may be digital data. The voltage of each of the compensation voltages Vpark, VOBS, and VAR may vary with the voltage data output by the voltage control section 168. For example, in a low power mode, the second compensation voltage VOBS may be adjusted to a lower voltage in the refresh frame RF than in the hold frame HF, such as Fig.15 shown.

[0211] The first compensation voltage output unit 162, the second compensation voltage output unit 164, and the third compensation voltage output unit 166 may each include a digital-to-analog converter (DAC) that converts voltage data into a voltage. The first compensation voltage output unit 162 converts the first voltage data into an analog voltage and outputs a first compensation voltage Vpark. The first compensation voltage Vpark may be applied to the data line DL through a switching element SW. The switching element SW may be implemented as a transistor that is maintained in a cut-off state during the period of the refresh frame RF period under the control of the voltage control unit 168 and is turned on during the period of the hold frame HF. The switching element SW may be embedded in an integrated circuit together with the data driver 110 or mounted on a non-display area BZ of the display panel 100.

[0212] When the switching element SW is in an off state, the data voltage Vdata is applied to the data line DL, and when the switching element SW is turned on, the first compensation voltage Vpark is applied to the data line DL. When the switching element SW is turned on, the data driver 110 does not output the data voltage Vdata.

[0213] The second compensation voltage output part 164 converts the second voltage data into an analog voltage and outputs the second compensation voltage VOBS to the power line PL4. The third compensation voltage output part 166 converts the third voltage data into an analog voltage and outputs the third compensation voltage VAR to the power line PL5.

[0214] According to one or more exemplary embodiments of the present disclosure, the display device may be applied to a mobile device, a video phone, a smart watch, a watch phone, a wearable device, a foldable device, a rollable device, a bendable device, a flexible device, a bending device, a sliding device, a variable device, an electronic organizer, an electronic book, a portable multimedia player (PMP), a personal digital assistant (PDA), an MP3 player, a mobile medical device, a desktop PC, a notebook PC, a netbook computer, a workstation, a navigation, a vehicle navigation, a vehicle display device, a vehicle device, a theater device, a theater display device, a television, a wallpaper device, a sign device, a game device, a notebook computer, a monitor, a camera, a video camera, and a home appliance, etc. In addition, the display device according to one or more exemplary embodiments of the present disclosure may be applied to an organic light emitting lighting device, a quantum dot light emitting device, an inorganic light emitting lighting device, but is not limited thereto.

[0215] The objects to be achieved by the present disclosure described above, and means for achieving the objects and effects of the present disclosure do not specify essential features of the claims, and therefore, the scope of the claims is not limited to the disclosed contents of the present disclosure.

[0216] Although the exemplary embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure.

[0217] CROSS-REFERENCE TO RELATED APPLICATIONS

[0218] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0132356, filed on October 5, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A display device, comprising: A display panel, on which a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of sub-pixels are arranged; a data driver configured to supply a data voltage to the data line; as well as a gate driver configured to supply a gate signal to the gate line, Wherein, each sub-pixel of the plurality of sub-pixels comprises: Light emitting element; a driving element, the driving element including a gate electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to a third node, and the driving element is configured to drive the light emitting element; a first switching element configured to supply a pixel driving voltage to the second node; a second switching element configured to supply the data voltage to the second node; a third switching element configured to connect the first node to the third node; and a fourth switching element configured to supply an initialization voltage to the first node; and Wherein, the selection signal includes: a first-first scan signal applied to the gate electrode of the fourth switching element, a first-second scan signal applied to the gate electrode of the third switching element, a second scan signal applied to the gate electrode of the second switching element, and a light emitting control signal applied to the gate electrode of the first switching element, and The pulse of the first-first scanning signal has the same pulse width as the pulse of the first-second scanning signal and is located before the pulse of the first-second scanning signal.

2. The display device according to claim 1, wherein: The gate driver comprises: a first shift register, the first shift register being configured to output a pulse of the first-first scanning signal and then output a pulse of the first-second scanning signal; a second shift register configured to output a pulse of the second scanning signal; and A third shift register is configured to output a pulse of the light emitting control signal.

3. The display device according to claim 2, wherein: The first shift register includes a plurality of first signal transmission parts connected in cascade. The second shift register includes a plurality of second signal transmission sections connected in cascade, and The third shift register includes a plurality of third signal transmission parts connected in cascade, and The start pulse and the clock input to the first to third shift registers have one or more of different phases, frequencies and duty cycles.

4. The display device according to claim 1, wherein: Each of the sub-pixels further includes a capacitor connected between the pixel driving voltage and the first node, The first switching element includes a gate electrode to which the light emission control signal is applied, a first electrode to which the pixel driving voltage is applied, and a second electrode connected to the second node. The second switching element includes a gate electrode to which the second scan signal is applied, a first electrode connected to the data line, and a second electrode connected to the second node. The third switching element includes a gate electrode to which the first-second scanning signal is applied, a first electrode connected to the first node, and a second electrode connected to the third node. The fourth switching element includes a gate electrode to which the first-first scan signal is applied, a first electrode connected to the first node, and a second electrode to which the initialization voltage is applied, and The light emitting element includes an anode connected to the third node and a cathode to which a cathode voltage is applied.

5. The display device according to claim 4, wherein: During an initialization period, the third switching element and the fourth switching element are configured to be turned on to apply the initialization voltage to the first node and the third node, During a sampling period, the second switching element and the third switching element are configured to be turned on so that the data voltage is applied to the second node and the first node is electrically connected to the third node, and During a light emitting period, the first switching element is configured to be turned on.

6. The display device according to claim 5, wherein: During the sampling period, the second switching element and the third switching element are configured to apply the data voltage to the first node and the third node through the driving element in an on state.

7. The display device according to claim 1, wherein: Each of the plurality of sub-pixels further comprises: a fifth switching element configured to supply a second compensation voltage to the second node; a sixth switching element configured to apply a third compensation voltage to the fourth node; and a seventh switching element configured to connect the third node to the fourth node in response to the light emission control signal, and Wherein, the selection signal also includes: A third scan signal is applied to a gate electrode of each of the fifth switching element and the sixth switching element.

8. The display device according to claim 7, wherein: Each of the plurality of sub-pixels further comprises: a first capacitor connected between the pixel driving voltage and the first node, The first switching element includes a gate electrode to which the light emission control signal is applied, a first electrode to which the pixel driving voltage is applied, and a second electrode connected to the second node. The second switching element includes a gate electrode to which the second scan signal is applied, a first electrode connected to the data line, and a second electrode connected to the second node. The third switching element includes a gate electrode to which the first-second scanning signal is applied, a first electrode connected to the first node, and a second electrode connected to the third node. The fourth switching element includes a gate electrode to which the first-first scan signal is applied, a first electrode connected to the first node, and a second electrode to which the initialization voltage is applied, The fifth switching element includes a gate electrode to which the third scan signal is applied, a first electrode connected to the second node, and a second electrode to which the second compensation voltage is applied. The sixth switching element includes a gate electrode to which the third scan signal is applied, a first electrode connected to the fourth node, and a second electrode to which the third compensation voltage is applied. The seventh switching element includes a gate electrode to which the light emission control signal is applied, a first electrode connected to the third node, and a second electrode connected to the fourth node, and The light emitting element includes an anode connected to the fourth node and a cathode to which a cathode voltage is applied.

9. The display device according to claim 7, wherein: Each of the plurality of sub-pixels further includes a second capacitor connected between a gate line to which the third scan signal is applied and the first node.

10. The display device according to claim 8, wherein: The low power mode includes: a refresh frame in which a data voltage is applied to the sub-pixel through the data line; and a hold frame in which a first compensation voltage is applied to the sub-pixel through the data line. The refresh frame includes a first bias-on period, a first initialization period, a second initialization period, a sampling period, a second bias-on period and a light-emitting period, During the first on-bias period of the refresh frame, the fifth switching element and the sixth switching element are configured to be turned on to apply the second compensation voltage to the second node and the third compensation voltage to the fourth node, During the first initialization period of the refresh frame, the fourth switching element is configured to be turned on to apply the initialization voltage to the first node, During the second initialization period of the refresh frame, the third switching element and the fourth switching element are configured to be turned on to apply the initialization voltage to the first node and the third node, During the sampling period of the refresh frame, the second switching element is configured to be turned on to apply the data voltage to the second node, During the second on-bias period of the refresh frame, the fifth switching element and the sixth switching element are configured to be turned on to apply the second compensation voltage to the second node and the third compensation voltage to the fourth node, and During the light emitting period of the refresh frame, the first switching element and the seventh switching element are configured to be turned on.

11. The display device according to claim 10, wherein: During the sampling period of the refresh frame, the third switching element is configured to be turned on to apply the data voltage to the first node and the third node.

12. The display device according to claim 11, wherein: During the sampling period of the refresh frame, the second switching element and the third switching element are configured to apply the data voltage to the first node and the third node through the driving element in an on state.

13. The display device according to claim 10, further comprising: a switching element configured to apply the first compensation voltage to the data line during the holding frame, In the holding frame, no data voltage is output from the data driver.

14. The display device according to claim 10, wherein: The holding frame includes a third bias-on period, a fourth bias-on period, and a light-emitting period, During each of the third on-bias period and the fourth on-bias period of the hold frame, the fifth switching element and the sixth switching element are configured to be turned on to apply the second compensation voltage to the second node and the third compensation voltage to the fourth node, and During the light emitting period of the hold frame, the first switching element and the seventh switching element are configured to be turned on.

15. The display device according to claim 14, wherein: The refresh frame further includes a first floating period between the first on-bias period and the first initialization period, a second floating period between the sampling period and the second on-bias period, and a third floating period between the second on-bias period and the light emitting period of the refresh frame, The holding frame further includes a fourth floating period between the third on-bias period and the fourth on-bias period, and a fifth floating period between the fourth on-bias period and the light emitting period of the holding frame, and The first to seventh switching elements are in an off state in each of the first to fifth floating periods.

16. The display device according to claim 10, wherein: A voltage of the second compensation voltage is smaller in the refresh frame than in the hold frame.

17. The display device according to claim 7, wherein: The gate driver comprises: a first shift register, the first shift register being configured to output a pulse of the first-first scanning signal and then output a pulse of the first-second scanning signal; a second shift register, the second shift register being configured to output a pulse of the second scanning signal; a third shift register configured to output a pulse of the third scanning signal; and A fourth shift register is configured to output a pulse of the light emitting control signal.

18. The display device according to claim 17, wherein: The second shift register comprises: a plurality of odd-numbered signal transmission parts configured to sequentially output pulses of odd-numbered scan signals; and a plurality of even-numbered signal transmission parts, the plurality of even-numbered signal transmission parts being configured to sequentially output pulses of even-numbered scanning signals, and Wherein, a carry signal is transmitted between the odd-numbered signal transmission parts and the even-numbered signal transmission parts adjacent to each other.

19. A method for driving a display device, the method comprising the following steps: supplying a gate signal to a plurality of gate lines connected to the pixel circuits during a refresh frame period and a hold frame period; During the refresh frame period, supplying a data voltage to a plurality of data lines, and supplying the data voltage, a second compensation voltage, and a third compensation voltage to the pixel circuit; as well as During the holding frame period, a first compensation voltage is supplied to the data line, and the first compensation voltage, the second compensation voltage, and the third compensation voltage are supplied to the pixel circuit, Wherein, the selection signal includes: pulses of the first-first scanning signal and the first-second scanning signal sequentially output from the first shift register, pulses of the second scanning signal sequentially output from the second shift register, and pulses of the light emitting control signal sequentially output from the third shift register, wherein a pulse of the first-first scanning signal is generated, and then a pulse of the first-second scanning signal is generated, and The pulse of the first-first scanning signal has the same pulse width as the pulse of the first-second scanning signal and precedes the pulse of the first-second scanning signal.

20. A method for driving a display device, the method comprising the following steps: supplying a gate signal to a plurality of gate lines connected to the pixel circuits during a refresh frame period and a hold frame period; During the refresh frame period, supplying a data voltage to a plurality of data lines, and supplying the data voltage, a second compensation voltage, and a third compensation voltage to the pixel circuit; as well as During the holding frame period, a first compensation voltage is supplied to the data line, and the first compensation voltage, the second compensation voltage, and the third compensation voltage are supplied to the pixel circuit, Wherein, the selection signal includes: pulses of the first-first scanning signal and the first-second scanning signal sequentially output from the first shift register, pulses of the second scanning signal sequentially output from the second shift register, pulses of the third scanning signal sequentially output from the third shift register, and pulses of the light emitting control signal sequentially output from the fourth shift register, and wherein a pulse of the first-first scanning signal is generated, and then a pulse of the first-second scanning signal is generated, and The pulse of the first-first scanning signal has the same pulse width as the pulse of the first-second scanning signal and precedes the pulse of the first-second scanning signal.

21. The method according to claim 19 or 20, wherein: Some periods of pulses of the first-first scanning signal overlap with pulses of the first-second scanning signal.

Images