Pixel circuit and display device including same

Abstract

The invention relates to a pixel circuit and a display device including the same. The pixel circuit includes: a first driving transistor including a first electrode connected to a first node to which a driving voltage is applied, a gate connected to a second node, and a second electrode connected to a third node; a second driving transistor including a first electrode connected to the first node, a gate connected to the fifth node, and a second electrode connected to the sixth node; and a sensing portion configured to sense electrical characteristics of the first driving transistor and the second driving transistor.

Description

Technical Field

[0001] The present disclosure relates to a pixel circuit and a display device including the pixel circuit, and more specifically, for example but not limited to, to a pixel circuit capable of sensing electrical characteristics of a light-emitting element while driving the light-emitting element to display an image and a display device including the pixel circuit. Background Art

[0002] Flat panel display devices include liquid crystal displays (LCDs), electroluminescent displays, field emission displays (FEDs), plasma display panels (PDPs), and micro LED (micro light emitting diode) display devices, etc. Electroluminescent displays can be divided into inorganic light emitting display devices and organic light emitting display devices according to the material of the light emitting layer.

[0003] An active matrix electroluminescent light emitting display includes a self-luminous light emitting diode (hereinafter referred to as "LED") and a driving element for driving the LED. The driving element is implemented as a transistor, which can adjust the current flowing to the LED according to data. The electrical characteristics of the driving element (such as threshold voltage, mobility, etc.) should be the same for all pixels, but the electrical characteristics of the driving element may not be uniform due to process conditions, driving environment, etc. When the driving element runs for a longer period of time, stress may accumulate on it, so its electrical characteristics may deteriorate. Summary of the invention

[0004] The present disclosure has been made in an effort to address the above-mentioned needs and / or disadvantages.

[0005] The present disclosure provides a pixel circuit capable of sensing electrical characteristics of a light emitting element while driving the light emitting element to display an image, and a display device including the pixel circuit.

[0006] The problems to be solved by the present disclosure are not limited to the above problems, and those skilled in the art will clearly understand other problems not mentioned according to the following description, and can be more clearly understood based on the embodiments according to the present disclosure. In addition, it will be easily understood that the purposes and advantages according to the present disclosure can be achieved using the means shown in the claims or their combination.

[0007] A pixel circuit according to an exemplary embodiment of the present disclosure includes: a first driving transistor, which includes a first electrode connected to a first node to which a driving voltage is applied, a gate connected to a second node, and a second electrode connected to a third node; a second driving transistor, which includes a first electrode connected to the first node, a gate connected to a fifth node, and a second electrode connected to a sixth node; and a sensing part, which is configured to sense electrical characteristics of the first driving transistor and the second driving transistor.

[0008] The sensing portion may include a first sensing portion connected to the third node and configured to sense an electrical characteristic of the first driving transistor and a second sensing portion connected to the sixth node and configured to sense an electrical characteristic of the second driving transistor.

[0009] The pixel circuit may further include: a first capacitor connected between the second node and the fourth node; a first switching transistor configured to be turned on in response to the first selection signal to connect the third node to the fourth node; a second switching transistor configured to be turned on in response to the first scan signal to provide a first data voltage to the second node; a second capacitor connected between the fourth node and the fifth node; a third switching transistor configured to be turned on in response to the second selection signal to connect the sixth node to the fourth node; and a fourth switching transistor configured to be turned on in response to the second scan signal to provide a second data voltage to the fifth node.

[0010] The pixel circuit may further include a light emitting element connected to the fourth node.

[0011] The first sensing part may include: a first sensing capacitor connected to a first sensing line; a first sensing switching transistor configured to be turned on in response to a first sensing signal to connect the third node to the first sensing line; a first initialization switching element configured to be turned on in response to a first switching control signal to provide a first reference voltage to the first sensing line; a first analog-to-digital converter configured to convert a first sensing voltage input through the first sensing line into digital data; and a first sampling switching element configured to be turned on in response to a second switching control signal to connect the first sensing line to an input terminal of the first analog-to-digital converter.

[0012] The second sensing part may include: a second sensing capacitor connected to the second sensing line; a second sensing switch transistor configured to be turned on in response to the second sensing signal to connect the sixth node to the second sensing line; a second initialization switch element configured to be turned on in response to the third switch control signal to provide a second reference voltage to the second sensing line; a second analog-to-digital converter configured to convert the second sensing voltage input through the second sensing line into digital data; and a second sampling switch element configured to be turned on in response to the fourth switch control signal to connect the second sensing line to the input terminal of the second analog-to-digital converter.

[0013] During the first driving period, the first driving transistor may be driven and the second driving transistor may be sensed. During the second driving period, the second driving transistor may be driven and the first driving transistor may be sensed.

[0014] During the first driving period, the light emitting element connected to the fourth node can be driven by the first driving transistor, and the second driving transistor can be sensed by the second sensing part. During the second driving period, the light emitting element can be driven by the second driving transistor, and the first driving transistor can be sensed by the first sensing part.

[0015] During the first driving period, the voltage of the first selection signal may be a gate-on voltage, and the voltage of the second selection signal may be a gate-off voltage. During the second driving period, the voltage of the second selection signal may be a gate-on voltage, and the voltage of the first selection signal may be a gate-off voltage.

[0016] During the first driving period, the first switching transistor may be configured to be turned on in response to a gate-on voltage of a first selection signal, and the second switching transistor may be configured to be turned off in response to a gate-off voltage of a second selection signal. During the second driving period, the first switching transistor may be configured to be turned off in response to a gate-off voltage of the first selection signal, and the second switching transistor may be configured to be turned on in response to a gate-on voltage of a second selection signal.

[0017] The first switch transistor may be turned on in response to a gate-on voltage of a first selection signal and turned off in response to a gate-off voltage of the first selection signal. The second switch transistor may be turned on in response to a gate-on voltage of a second selection signal and turned off in response to a gate-off voltage of the second selection signal.

[0018] During the first driving period, the first switching transistor and the second switching transistor may be configured to be turned on, and the third switching transistor may be configured to be turned off.

[0019] During the first period of the first driving period, the first switching transistor, the second switching transistor, the fourth switching transistor, the first sensing switching transistor, the first initialization switching element and the second initialization switching element can be configured to be turned on, while the third switching transistor, the second sensing switching transistor, the first sampling switching element and the second sampling switching element can be configured to be turned off.

[0020] During the second period of the first driving period, the first switching transistor, the second switching transistor, the fourth switching transistor, the first sensing switching transistor, the second sensing switching transistor and the first initialization switching element can be configured to be turned on, while the third switching transistor, the second initialization switching element, the first sampling switching element and the second sampling switching element can be configured to be turned off.

[0021] During a third period of the first driving period, the first switching transistor, the second switching transistor, the first sensing switching transistor, the first initialization switching element and the second sampling switching element may be configured to be turned on, while the third switching transistor, the fourth switching transistor, the second sensing switching transistor, the second initialization switching element and the first sampling switching element may be configured to be turned off.

[0022] During the second driving period, the third switching transistor and the fourth switching transistor may be configured to be turned on, and the first switching transistor may be configured to be turned off.

[0023] During the first period of the second driving period, the second switching transistor, the third switching transistor, the fourth switching transistor, the second sensing switching transistor, the first initialization switching element and the second initialization switching element can be turned on, while the first switching transistor, the first sensing switching transistor, the first sampling switching element and the second sampling switching element can be turned off.

[0024] During the second period of the second driving period, the second switching transistor, the third switching transistor, the fourth switching transistor, the first sensing switching transistor, the second sensing switching transistor and the second initialization switching element can be turned on, while the first switching transistor, the first initialization switching element, the first sampling switching element and the second sampling switching element can be turned off.

[0025] During a third period of the second driving period, the third switching transistor, the fourth switching transistor, the second sensing switching transistor, the second initialization switching element and the first sampling switching element may be turned on, while the first switching transistor, the second switching transistor, the first sensing switching transistor, the first initialization switching element and the second sampling switching element may be turned off.

[0026] The pixel circuit may further include: a light emitting element connected to the fourth node; and a fifth switching transistor connected between the fourth node and the light emitting element and configured to connect the fourth node to an anode of the light emitting element in response to a light emission signal.

[0027] The pixel circuit may further include: a first light-emitting element comprising an anode and an electrode; a second light-emitting element comprising an anode and an electrode; a fifth switching element configured to be turned on in response to the first light-emitting signal to connect the fourth node to the anode of the first light-emitting element; and a sixth switching element configured to be turned on in response to the second light-emitting signal to connect the fourth node to the anode of the second light-emitting element.

[0028] The sensing portion may be connected to the third node and the sixth node. The pixel circuit may further include a light emitting element connected to the fourth node.

[0029] The sensing part may include: a sensing capacitor connected to the sensing line; a first sensing switch transistor, which is configured to be turned on in response to a first sensing signal to connect the third node to the sensing line; a second sensing transistor, which is configured to be turned on in response to a second sensing signal to connect the sixth node to the sensing line; an initialization switch element, which is configured to be turned on in response to a first switch control signal to provide a reference voltage to the sensing line; an analog-to-digital converter, which is configured to convert a sensing voltage input through the sensing line into digital data; and a sampling switch element, which is configured to be turned on in response to a second switch control signal to connect the sensing line to an input terminal of the analog-to-digital converter.

[0030] A display device according to an exemplary embodiment of the present disclosure includes: a display panel, in which a plurality of data lines, a plurality of gate lines and a plurality of display pixels are arranged, and each display pixel may include a pixel circuit.

[0031] According to another exemplary embodiment of the present disclosure, a display device includes: a display panel on which pixel data of an input image is written; and a backlight unit in which a plurality of local dimming pixels for irradiating light to the display panel are provided. Each local dimming pixel may include a pixel circuit.

[0032] According to the present disclosure, multiple driving elements for driving the light-emitting elements of display pixels or local dimming pixels can be connected to the light-emitting elements, the light-emitting elements can emit light through any one driving element, and the electrical characteristics of other driving elements can be sensed in real time at the same time.

[0033] According to the present disclosure, a driving element for driving a light emitting element and a driving element to be sensed can be freely selected by using a selection signal for controlling a switch element connected between the driving element and the light emitting element.

[0034] According to the present disclosure, multiple light-emitting elements can emit light at the same time, thereby increasing the brightness of display pixels or local dimming pixels with a small current. Therefore, the present disclosure can improve the degradation, power consumption and life of driving elements and light-emitting elements, and reproduce HDR (high dynamic range) images with high brightness and high contrast.

[0035] The effects of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned can be apparently understood by those skilled in the art from the following description and the appended claims.

[0036] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0038] Figure 1 is a circuit diagram showing a pixel circuit according to a first exemplary embodiment of the present disclosure;

[0039] Figure 2 It is shown in detail Figure 1 A circuit diagram of an example of a sensing portion shown in ;

[0040] Figure 3 is shown as input to the Figure 2 A waveform diagram of a signal of the pixel circuit shown;

[0041] FIG. 4A to FIG. 4C is shown during the first driving period Figure 2 A circuit diagram of the phased operation of the pixel circuit shown;

[0042] Figure 5 is shown as input to the Figure 2 A waveform diagram of a signal of the pixel circuit shown;

[0043] FIG. 6A to FIG. 6C is shown during the second driving period Figure 2 A circuit diagram of the phased operation of the pixel circuit shown;

[0044] Figure 7 is a circuit diagram showing a pixel circuit according to a second exemplary embodiment of the present disclosure;

[0045] Fig. 8A and Figure 8B is a circuit diagram showing a pixel circuit according to a third exemplary embodiment of the present disclosure;

[0046] Fig. 9 is a circuit diagram showing a pixel circuit according to a third exemplary embodiment of the present disclosure;

[0047] Fig.10 It shows the input to Fig. 9 A waveform diagram of a signal of the pixel circuit shown;

[0048] FIG. 11A to FIG. 11C It is shown Fig. 9 A circuit diagram of the phased operation of the pixel circuit shown;

[0049] Fig.12 is a block diagram showing a display device according to an exemplary embodiment of the present disclosure;

[0050] Fig.13is a block diagram illustrating a display device according to another exemplary embodiment of the present disclosure; and

[0051] Fig.14 It is shown Fig.13 A perspective view of a display panel and a backlight unit is shown.

[0052] Throughout the drawings and detailed description, unless otherwise described, the same drawing reference numerals should be understood to refer to the same elements, features, and structures. The relative sizes and depictions of these elements may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0053] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be illustrated in the accompanying drawings. The described progression of processing steps and / or operations is an example; however, the order of steps and / or operations is not limited to the order set forth herein, and may be varied as is known in the art, except for steps and / or operations that must occur in a particular order. The names of corresponding elements used in the following description may be selected solely for ease of writing the specification, and therefore may differ from the names used in the actual product.

[0054] According to the exemplary embodiments described below with reference to the accompanying drawings, the advantages and features of the present disclosure and the methods for implementing the present disclosure will be more clearly understood. However, the present disclosure is not limited to the following exemplary embodiments, but can be implemented in various different forms. On the contrary, this embodiment will make the disclosure of the present disclosure complete and allow those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is limited only within the scope of the appended claims.

[0055] The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings used to describe the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout this specification, the same reference numerals generally represent the same elements. In addition, when describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0056] As used herein, terms such as "including," "comprising," "having," and "comprising" are generally intended to allow for the addition of additional components unless such terms are used with the term "only." Any reference to the singular includes the plural unless expressly stated otherwise.

[0057] Even if not explicitly stated, the components are interpreted as including the ordinary error range.

[0058] When interpreting an element, the element is interpreted as including a margin of error even if not explicitly described.Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.

[0059] When describing a position or interconnection relationship between two components, such as "on top of," "above," "below," "under," "adjacent," "connected or coupled to," "crossing," "intersecting," etc., one or more other components may be interposed between them, unless "immediately" or "directly" is used. For example, when one element or layer is disposed on another element or layer, a third layer or element may be interposed between them.

[0060] Regarding expressions where an element or layer is “contacting,” “overlapping,” etc., with another element or layer, unless otherwise specified, the element or layer may not only be directly in contact with, overlap with, etc., but may also be indirectly in contact with, overlap with, etc., with another element or layer by having one or more intermediate elements or layers disposed or interposed between the elements or layers.

[0061] When describing a temporal precedence relationship such as "after", "subsequently", "next", "before", etc., it may not be continuous on a temporal basis unless "just", "immediately" or "directly" is used.

[0062] The terms "first", "second", "A", "B", "(a)", and "(b)", etc. may be used to distinguish components from each other, but the function or structure of a component is not limited by the sequence number or component name preceding the component. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.

[0063] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of a first element, a second element, and a third element" may include all combinations of two or more elements selected from the first element, the second element, and the third element, as well as each individual element of the first element, the second element, and the third element.

[0064] The following exemplary embodiments may be partially or completely combined or combined with each other, and may be technically linked and operated in various ways. The exemplary embodiments may be performed independently of each other or in association with each other.

[0065] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments belong. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having, for example, a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein. For example, the term "component" or "unit" may apply, for example, to a separate circuit or structure, an integrated circuit, a computing block of a circuit device, or any structure configured to perform the described function, as will be understood by one of ordinary skill in the art.

[0066] In the following, various aspects of the present disclosure will be described with reference to the accompanying drawings. Since the proportions of each element shown in the accompanying drawings are different from the actual proportions for the convenience of description, the present disclosure is not limited to the proportions shown. In addition, all components of each display device, display apparatus, and display panel according to all aspects of the present disclosure are operably connected and configured.

[0067] The pixel circuit and the gate drive circuit of the display device may include a plurality of transistors. The transistor may be implemented as a thin film transistor (TFT). The transistor may be implemented as an oxide thin film transistor (TFT) including an oxide semiconductor, a low temperature polysilicon TFT (LTPS TFT) including low temperature polysilicon, etc. In the following, the pixel circuit refers to a display pixel circuit for driving a light emitting element of a display panel that visually reproduces an input image by writing pixel data of the input image, and a local dimming pixel circuit for driving a light source that radiates light to the display panel.

[0068] The display device according to the exemplary embodiment may be an electroluminescent display device. The electroluminescent display device may be any one of an organic light emitting diode (OLED) display device, a quantum dot light emitting diode display device, an inorganic light emitting diode display device, a micro LED display device, etc., but is not limited thereto.

[0069] A transistor may be a three-electrode element including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. In a transistor, carriers begin to flow from the source. The drain is an electrode through which carriers leave the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n-channel transistor (n-channel metal oxide semiconductor (NMOS)), since the carriers are electrons, the source voltage is a voltage lower than the drain voltage, so that electrons can flow from the source to the drain. An n-channel transistor has a direction of current flowing from the drain to the source. In the case of a p-channel transistor (p-channel metal oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed according to the applied voltage. Therefore, the present disclosure does not limit the source and drain of the transistor. In the following description, the source and drain of the transistor may be referred to as the first electrode and the second electrode, and the present disclosure is not limited thereto. Alternatively, the source and drain of the transistor may be referred to as the second electrode and the first electrode.

[0070] The gating signal swings between a gate-on voltage and a gate-off voltage. The transistor turns on in response to the gate-on voltage and turns off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate high voltage VGH, and the gate-off voltage may be a gate low voltage VGL. In the case of a p-channel transistor, the gate-on voltage may be a gate low voltage VGL, and the gate-off voltage may be a gate high voltage VGH.

[0071] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0072] Reference Figure 1 , a pixel circuit according to an exemplary embodiment of the present disclosure may include a light emitting element LD, a first driving part DRV1 and a second driving part DRV2 for driving the light emitting element LD, but is not limited thereto. The pixel circuit may further include a first sensing part SU1 and a second sensing part SU2. The first sensing part SU1 is connected to the first driving part DRV1. The second sensing part SU2 is connected to the second driving part DRV2.

[0073] The first driving part DRV1 and the second driving part DRV2 may be alternately driven according to the driving time to slow down the acceleration of degradation. During the first driving period, the first driving part DRV1 may drive the light emitting element LD, and the second driving part DRV2 may be sensed. During the second driving period, the second driving part DRV2 may drive the light emitting element LD, and the first driving part DRV1 may be sensed. However, the present disclosure is not limited thereto. For example, the first driving part DRV1 is sensed by the first sensing part SU1, and the second driving part DRV2 is sensed by the second sensing part SU2.

[0074] The driving cycle of each of the first driving part DRV1 and the second driving part DRV2 may be a predetermined time, for example, a fixed time such as a day or a month. In addition, the driving cycle of each of the first driving part DRV1 and the second driving part DRV2 may be a driving duration of its continuous driving, such as a predetermined threshold time such as 1 hour or 10 hours. For example, the first driving part DRV1 may drive the light emitting element LD for 1 hour, then the second driving part DRV2 may drive the light emitting element LD for 1 hour, and then the first driving part DRV1 may drive the light emitting element LD for 1 hour again.

[0075] The driving part DRV1 or DRV2 stops its driving when its electrical characteristics are sensed by its corresponding sensing part SU1 or SU2, and at this time, the other driving part DRV2 or DRV1 can be driven. For example, the second driving part DRV2 can be sensed and compensated while the light emitting element LD is driven by the first driving part DRV1, and then the first driving part DRV1 can be sensed and compensated while the light emitting element LD is driven by the second driving part DRV2.

[0076] As an example, the first driving part DRV1 may include at least a first driving element DT1, a first switching element M01, a second switching element M02, a first capacitor C1, etc. As an example, the second driving part DRV2 may include at least a second driving element DT2, a third switching element M03, a fourth switching element M04, a second capacitor C2, etc. The driving elements DT1 and DT2 and each of the switching elements M01 to M04 may be implemented as a transistor, and the present disclosure is not limited thereto.

[0077] The light emitting element LD may be implemented as an organic light emitting diode (hereinafter referred to as "OLED") or an inorganic light emitting element (LED), and the present disclosure is not limited thereto. The anode of the light emitting element LD may be connected to the fourth node n4 of the first driving part DRV1, and the cathode of the light emitting element LD may be connected to a node to which a cathode voltage VSS is applied. When the light emitting element LD is implemented as an OLED, the light emitting element LD includes an organic compound layer formed between the anode and the cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The OLED may be implemented as a series structure having a plurality of light emitting layers stacked on each other. An OLED having a series structure may improve the brightness and life of a sub-pixel.

[0078] The first driving element DT1 may be connected between the first node n1 and the third node n3. The first driving element DT1 drives the light emitting element LD by generating a current according to the gate-source voltage Vgs and providing the current to the light emitting element LD. The first driving element DT1 includes a first electrode connected to the first node n1, a gate connected to the second node n2, and a second electrode connected to the third node n3. A driving voltage VDD may be applied to the first node n1. The driving voltage VDD is a voltage higher than the cathode voltage VSS.

[0079] The first capacitor C1 may be connected between the second node n2 and the fourth node n4. The gate-source voltage Vgs of the first driving element DT is charged in the first capacitor C1.

[0080] The first sensing part SU1 may be connected to the third node n3 to sense a voltage or current flowing at the third node n3. The voltage or current at the third node n3 may change according to the electrical characteristics (e.g., at least one of a threshold voltage and a mobility) of the first driving element DT1. Therefore, the first sensing part SU1 may sense the electrical characteristics of the first driving element DT1.

[0081] The first switch element M01 may be connected between the third node n3 and the fourth node n4. The first switch element M01 is turned on or off in response to the first selection signal SEL1. For example, the first switch element M01 is turned on in response to the gate-on voltage VGH of the first selection signal SEL1. When the first switch element M01 is turned on, the third node n3 is connected to the fourth node n4. The first switch element M01 includes a first electrode connected to the third node n3, a gate to which the first selection signal SEL1 is applied, and a second electrode connected to the fourth node n4.

[0082] The second switch element M02 may be connected between the first data line to which the first data voltage DATA1 is applied and the second node n2. The second switch element M02 is turned on or off in response to the first scan signal SCAN1. For example, the second switch element M02 is turned on in response to the gate-on voltage VGH of the first scan signal SCAN1. When the second switch element M02 is turned on, the second switch element M02 provides the first data voltage DATA1 to the second node n2. The second switch element M02 includes a first electrode connected to the first data line to which the first data voltage DATA1 is applied, a gate to which the first scan signal SCAN1 is applied, and a second electrode connected to the second node n2.

[0083] The second driving element DT2 may be connected between the first node n1 and the sixth node n6. The second driving element DT2 drives the light emitting element LD by generating a current according to the gate-source voltage Vgs and providing the current to the light emitting element LD. The second driving element DT2 includes a first electrode connected to the first node n1, a gate connected to the fifth node n5, and a second electrode connected to the sixth node n6.

[0084] The second capacitor C2 may be connected between the fourth node n4 and the fifth node n5. The gate-source voltage Vgs of the second driving element DT2 is charged in the second capacitor C2.

[0085] The second sensing part SU2 is connected to the sixth node n6 to sense the voltage or current flowing at the sixth node n6. The voltage or current at the sixth node n6 may change according to the electrical characteristics (e.g., at least one of the threshold voltage and the mobility) of the second driving element DT2. Therefore, the second sensing part SU2 may sense the electrical characteristics of the second driving element DT2.

[0086] The third switch element M03 may be connected between the sixth node n6 and the fourth node n4. The third switch element M03 is turned on or off in response to the second selection signal SEL2. For example, the third switch element M03 is turned on in response to the gate-on voltage VGH of the second selection signal SEL2, but is not limited thereto. When the third switch element M03 is turned on, the sixth node n6 is connected to the fourth node n4. The third switch element M03 includes a first electrode connected to the sixth node n6, a gate to which the second selection signal SEL2 is applied, and a second electrode connected to the fourth node n4.

[0087] The fourth switch element M04 may be connected between the second data line to which the second data voltage DATA2 is applied and the fifth node n5. The fourth switch element M04 is turned on or off in response to the second scan signal SCAN2. For example, the fourth switch element M04 is turned on in response to the gate-on voltage VGH of the second scan signal SCAN2, but is not limited thereto. When the fourth switch element M04 is turned on, the fourth switch element M04 provides the second data voltage DATA2 to the fifth node n5. The fourth switch element M04 includes a first electrode connected to the second data line to which the second data voltage DATA2 is applied, a gate to which the second scan signal SCAN2 is applied, and a second electrode connected to the fifth node n5.

[0088] The first data voltage DATA1 and the second data voltage DATA2 may be, but are not limited to, the same voltage. For example, when the first driving element DT1 and the second driving element DT2 have different degradation accumulations resulting in differences in their electrical characteristics, the first data voltage DATA1 and the second data voltage DATA2 may be different according to compensation levels of data voltages compensated according to sensing results of electrical characteristics of the first driving element DT1 and the second driving element DT2.

[0089] The light emitting element LD may be a light emitting element for forming a display pixel on the display panel or a local dimming light source that irradiates light onto the display panel. Figure 1 The pixel circuit shown may be at least one of a display pixel circuit of a display panel that visually reproduces an input image by writing pixel data of the input image, and a local dimming pixel circuit that drives a backlight light source to illuminate the transmissive display panel.

[0090] The first data voltage DATA1 and the second data voltage DATA2 applied to the display pixel circuit may be data voltages corresponding to the grayscale or brightness value of the pixel data of the input image. The first data voltage DATA1 and the second data voltage DATA2 applied to the local dimming pixel circuit may be data voltages corresponding to the local dimming brightness calculated based on the grayscale or brightness value of the pixel data of the input image.

[0091] Figure 2 It is shown in detail Figure 1 FIG. 1 is a circuit diagram of an example of sensing parts SU1 and SU2. Figure 2 In the circuit shown, Figure 1 Substantially the same components are denoted by the same reference numerals, and a detailed description thereof will be omitted or provided briefly.

[0092] The pixel circuit is connected to a plurality of data lines and a gate line. For example, the pixel circuit is connected to the data lines to which the data voltages DATA1 and DATA2 are applied and the gate lines to which the gate signals SCAN1, SCAN2, SEL1 and SEL2 are applied, but not limited thereto. The gate signals SCAN1, SCAN2, SEL1 and SEL2 include a first scan signal SCAN1 input to the pixel circuit through a first gate line, a second scan signal SCAN2 input to the pixel circuit through a second gate line, a first selection signal SEL1 input to the pixel circuit through a third gate line, and a second selection signal SEL2 input to the pixel circuit through a fourth gate line. In this case, the gate drive circuit may include, but is not limited to, a first shift register that sequentially provides a pulse of the first scan signal SCAN1 to the first gate line, a second shift register that sequentially provides a pulse of the second scan signal SCAN2 to the second gate line, a third shift register that sequentially provides a pulse of the first selection signal SEL1 to the third gate line, and a fourth shift register that sequentially provides a pulse of the second selection signal SEL2 to the fourth gate line.

[0093] The pulses of the selection signals SCAN1, SCAN2, SEL1 and SEL2 swing between the gate-on voltage VGH and the gate-off voltage VGL. The switching elements in the pixel circuit are turned on or off according to the gate voltage applied to the gate thereof. As an example, the switching elements M01 to M04 in the pixel circuit are turned on according to the gate-on voltage VGH applied to the gate thereof and are turned off according to the gate-off voltage VGL, but are not limited thereto.

[0094] The pixel circuit may be connected to a first power line to which a driving voltage VDD is applied and a second power line to which a cathode voltage VSS is applied. In addition, the pixel circuit may be connected to a first sensing line SL1 and a second sensing line SL2.

[0095] The driving voltage VDD may be set to a voltage higher than the maximum voltage of the data voltages DATA1 and DATA2. The driving voltage VDD is a voltage higher than the cathode voltage VSS. The first reference voltage Vref1 and the second reference voltage Vref2 may be set to a voltage greater than or equal to the cathode voltage VSS. The first reference voltage Vref1 and the second reference voltage Vref2 may be set to, but not limited to, the same voltage. The gate-on voltage VGH may be set to a voltage higher than the driving voltage VDD, and the gate-off voltage VGL may be set to a voltage lower than the cathode voltage VSS. For example, but not limited to, VDD=15 to 20 [V], VSS=0 [V], Vref1=Vref2=1 to 3 [V], VGH=24 [V], and VGL=-12 [V]. The data voltages DATA1 and DATA2 may have a dynamic range between 0V and 18V, but not limited thereto.

[0096] As an example, the first sensing part SU1 may include a first sensing switch element M05, a first initialization switch element SW1, a first sampling switch element SW2, a first sensing capacitor CS1 and / or a first analog-to-digital converter (hereinafter referred to as "ADC") ADC1. Each of the switch elements M05, SW1 and SW2 may be implemented as a transistor, but is not limited thereto. The first sensing capacitor CS1 is connected to the first sensing line SL1.

[0097] The first sensing switch element M05 may be connected between the third node n3 and the first sensing line SL1. The first sensing switch element M05 is turned on or off in response to the first sensing signal SENSE1. For example, the first sensing switch element M05 is turned on in response to the gate-on voltage VGH of the first sensing signal SENSE1 to connect the third node n3 to the first sensing line SL1. When the first sensing switch element M05 is turned on, the first sensing capacitor CS1 is charged by the charge from the third node n3. The first sensing switch element M05 includes a first electrode connected to the third node n3, a gate to which the first sensing signal SENSE1 is applied, and a second electrode connected to the first sensing line SL1.

[0098] The pixel circuit may be connected to a fifth gate line to which the first sensing signal SENSE1 is applied. The gate driving circuit may further include a fifth shift register that sequentially outputs pulses of a gate signal (ie, the first sensing signal SENSE1) for controlling the first sensing switch element M05 to the fifth gate line.

[0099] The first initialization switching element SW1 is turned on or off in response to the first switch control signal SPRE1. When the first initialization switching element SW1 is turned on, the first initialization switching element SW1 applies the first reference voltage Vref1 to the first sensing line SL1. The first initialization switching element SW1 includes a first electrode connected to the first sensing line SL1, a gate to which the first switch control signal SPRE1 is applied, and a second electrode to which the first reference voltage Vref1 is applied.

[0100] The first sampling switch element SW2 is turned on or off in response to the second switch control signal SAM1. When the first sampling switch element SW2 is turned on, the first sampling switch element SW2 connects the first sensing line SL1 to the input terminal of the first ADC ADC1. When the first sampling switch element SW2 is turned on, the first sensing voltage Vsen1 charged in the first sensing capacitor CS1 is input to the first ADC ADC1. The first sampling switch element SW2 includes a first electrode connected to the first sensing line SL1, a gate to which the second switch control signal SAM1 is applied, and a second electrode connected to the input terminal of the first ADC ADC1.

[0101] The first ADC ADC1 converts the first sensing voltage Vsen1 input when the first sampling switch element SW2 is turned on into digital data and outputs the first sensing data. The first sensing data is input to the compensation part, which is omitted in the figure. Based on the first sensing data, the compensation part can perform a compensation algorithm to compensate for the degradation of the electrical characteristics of the first driving element DT1. Any known degradation compensation algorithm can be used as the compensation algorithm. The compensation part can select a compensation value corresponding to the first sensing data, and modulate the first data voltage DATA1 based on the compensation value, thereby compensating for the degradation of the electrical characteristics of the first driving element DT1. For example, the compensation part can increase the first data voltage DATA1 by adding or multiplying the compensation value to the first compensation data (digital data). In this case, since the gate voltage of the first driving element DT1 is increased, the gate-source voltage Vgs of the first driving element DT1 is increased, so that the degradation of the electrical characteristics of the first driving element DT1 can be compensated. The first compensation data output from the compensation part can be converted into the first data voltage DATA1 by a digital-to-analog converter (hereinafter referred to as "DAC").

[0102] As an example, the second sensing part SU2 may include a second sensing switch element M06, a second initialization switch element SW3, a second sampling switch element SW4, a second sensing capacitor CS2 and / or a second ADC ADC2. Each of the switch elements M06, SW3 and SW4 may be implemented as a transistor, but is not limited thereto. The second sensing capacitor CS2 is connected to the second sensing line SL2.

[0103] The second sensing switch element M06 may be connected between the sixth node n6 and the second sensing line SL2. The second sensing switch element M06 is turned on or off in response to the second sensing signal SENSE2. For example, the second sensing switch element M06 is turned on in response to the gate-on voltage VGH of the second sensing signal SENSE2 to connect the sixth node n6 to the second sensing line SL2. When the second sensing switch element M06 is turned on, the second sensing capacitor CS2 is charged by the charge from the sixth node n6. The second sensing switch element M06 includes a first electrode connected to the sixth node n6, a gate to which the second sensing signal SENSE2 is applied, and a second electrode connected to the second sensing line SL2.

[0104] The pixel circuit may be connected to a sixth gate line to which the second sensing signal SENSE2 is applied. The gate driving circuit may further include a sixth shift register that sequentially outputs pulses of a gate signal (ie, the second sensing signal SENSE2) for controlling the second sensing switch element M06 to the sixth gate line.

[0105] The second initialization switch element SW3 is turned on or off in response to the third switch control signal SPRE2. When the second initialization switch element SW3 is turned on, the second initialization switch element SW3 applies the second reference voltage Vref2 to the second sensing line SL2. The second initialization switch element SW3 includes a first electrode connected to the second sensing line SL2, a gate to which the third switch control signal SPRE2 is applied, and a second electrode to which the second reference voltage Vref2 is applied.

[0106] The second sampling switch element SW4 is turned on or off in response to the fourth switch control signal SAM2. When the second sampling switch element SW4 is turned on, the second sampling switch element SW4 connects the second sensing line SL2 to the input terminal of the second ADC ADC2. When the second sampling switch element SW4 is turned on, the second sensing voltage Vsen2 charged in the second sensing capacitor CS2 is provided to the second ADC ADC2. The second sampling switch element SW4 includes a first electrode connected to the second sensing line SL2, a gate to which the fourth switch control signal SAM2 is applied, and a second electrode connected to the input terminal of the second ADC ADC2.

[0107] The second ADC ADC2 converts the second sensing voltage Vsen2 input when the second sampling switch element SW4 is turned on into digital data and outputs the second sensing data. The second sensing data is input to the compensation part, which is omitted in the figure. Based on the second sensing data, the compensation part can perform a compensation algorithm to compensate for the degradation of the electrical characteristics of the second driving element DT2. Any known degradation compensation algorithm can be used as the compensation algorithm. The compensation part can select a compensation value corresponding to the second sensing data, and modulate the second data voltage DATA2 based on the compensation value to compensate for the degradation of the electrical characteristics of the second driving element DT2. For example, the compensation part can increase the second data voltage DATA2 by adding or multiplying the compensation value to the second compensation data (digital data). In this case, since the gate voltage of the second driving element DT2 increases, the gate-source voltage Vgs of the second driving element DT2 increases, so that the degradation of the electrical characteristics of the second driving element DT2 can be compensated. The second compensation data output from the compensation part can be converted into the second data voltage DATA2 by the DAC.

[0108] The switch control signals SPRE1 , SPRE2 , SAM1 , and SAM2 for controlling the initialization switch elements SW1 and SW3 and the sampling switch elements SW2 and SW4 may be generated by a separate controller such as, but not limited to, a controller, but are not limited thereto.

[0109] Figure 3 is a graph showing the input to the first driving period TDRV1. Figure 2 : Waveform diagram of signals of the pixel circuit shown in . FIG. 4A to FIG. 4C It shows that during the first driving period TDRV1 Figure 2 The circuit diagram of the pixel circuit shown in FIG. Figure 3 In , 'H' is the gate-on voltage of the switch control signal, and 'L' is the gate-off voltage of the switch control signal. FIG. 4A to FIG. 4C In FIG. 1 , the bold line represents the current flowing through the switched-on switching element.

[0110] During the first driving period TDRV1, the first driving element DT1 is driven and the second driving element DT2 is sensed. For example, the light emitting element LD may be driven by the first driving element DT1, and the second driving element DT2 may be sensed by the second sensing part SU2. Figure 3 As shown, the first driving period TDRV1 may be divided into a first period t11, a second period t12, and a third period t13, but is not limited thereto.

[0111] like Figure 3 As shown, during the first driving period TDRV1, the first selection signal SEL1 may be a gate-on voltage VGH, and the second selection signal SEL2 may be a gate-off voltage VGL. Therefore, during the first driving period TDRV1, the first switching element M01 is turned on, and the third switching element M03 is in an off state. Specifically, during the first driving period TDRV1, the first switching element M01 is turned on in response to the gate-on voltage VGH of the first selection signal SEL1, and the third switching element M03 is turned off in response to the gate-off voltage VGL of the second selection signal SEL2.

[0112] Reference Figure 3 and Figure 4A During the first period t11, the voltages of the first scan signal SCAN1 and the second scan signal SCAN2, the first switch control signal SPRE1 and the third switch control signal SPRE2, and the first sensing signal SENSE1 are the gate-on voltage (VGH, H). Therefore, during the first period t11, the first switch element M01, the second switch element M02, the fourth switch element M04, the first sensing switch element M05, the first initialization switch element SW1, and the second initialization switch element SW3 are turned on. At this time, the first data voltage DATA1 is charged in the first capacitor C1, and the second data voltage DATA2 is charged in the second capacitor C2.

[0113] During the first period t11, the voltages of the second sensing signal SENSE2, the second switch control signal SAM1 and the fourth switch control signal SAM2 are the gate cut-off voltage (VGL, L). Therefore, during the first period t11, the third switch element M03, the second sensing switch element M06, the first sampling switch element SW2 and the second sampling switch element SW4 are cut off.

[0114] During the first period t11, the first switch element M01 and the second switch element M02 are turned on, and the third switch element M03 is turned off. During the first period t11, a current path can be formed between the driving voltage VDD and the cathode voltage VSS through the first driving element DT1 and the first switch element M01, so that the light emitting element LD can be driven by the first driving element DT1, and the second driving part DRV2 can be sensed. In this case, the light intensity of the light emitting element LD can be adjusted according to the first data voltage DATA1. At the same time, during the first period t11, the second sensing voltage Vsen2 is input to the second ADC ADC2, and the second ADC ADC2 outputs the second sensing data.

[0115] Reference Figure 3 and Figure 4B During the second period t12, the voltages of the first scan signal SCAN1 and the second scan signal SCAN2, the first switch control signal SPRE1, the first sensing signal SENSE1 and the second sensing signal SENSE2 are the gate-on voltage (VGH, H). Therefore, during the second period t12, the first switch element M01, the second switch element M02, the fourth switch element M04, the first sensing switch element M05, the second sensing switch element M06 and the first initialization switch element SW1 are turned on.

[0116] During the second period t12, the voltages of the third switch control signal SPRE2, the second switch control signal SAM1 and the fourth switch control signal SAM2 are the gate-off voltage (VGL, L). Therefore, during the second period t12, the third switch element M03, the second initialization switch element SW3, the first sampling switch element SW2 and the second sampling switch element SW4 are turned off.

[0117] During the second period t12, the voltage of the sixth node n6 may rise, and the level of the rise may be different according to the electrical characteristics of the second driving element DT2. At this time, the second sensing voltage Vsen2 sensed from the sixth node n6 is charged in the second sensing capacitor CS2. According to the electrical characteristics of the second driving element DT2, the second sensing voltage Vsen2 may be higher or lower than the second data voltage DATA2.

[0118] During the second period t12, the first switch element M01 and the second switch element M02 are turned on, and the third switch element M03 is turned off. During the second period t12, a current path is formed between the driving voltage VDD and the cathode voltage VSS through the first driving element DT1 and the first switching element M01, so that the light emitting element LD can be driven by the first driving element DT1, and the second driving part DRV2 can be sensed. In this case, the light intensity of the light emitting element LD can be adjusted according to the first data voltage DATA1. At the same time, during the second period t12, the second sensing voltage Vsen2 is input to the second ADC ADC2, and the second ADC ADC2 outputs the second sensing data.

[0119] Reference Figure 3 and Figure 4C During the third period t13, the voltages of the first scan signal SCAN1, the first switch control signal SPRE1, the first sensing signal SENSE1 and the fourth switch control signal SAM2 are the gate-on voltage (VGH, H). Therefore, during the third period t13, the first switch element M01, the second switch element M02, the first sensing switch element M05, the first initialization switch element SW1 and the second sampling switch element SW4 are turned on.

[0120] During the third period t13, the voltages of the second scan signal SCAN2, the second sensing signal SENSE2, the second switch control signal SAM1, and the third switch control signal SPRE2 are the gate-off voltage (VGL, L). Therefore, during the third period t13, the third switch element M03, the fourth switch element M04, the second sensing switch element M06, the second initialization switch element SW3, and the first sampling switch element SW2 are turned off.

[0121] During the third period t13, the first switch element M01 and the second switch element M02 are turned on, and the third switch element M03 is turned off. During the third period t13, a current path is formed between the driving voltage VDD and the cathode voltage VSS through the first driving element DT1 and the first switching element M01, so that the light emitting element LD can be driven by the first driving element DT1, and the second driving part DRV2 can be sensed. In this case, the light intensity of the light emitting element LD can be adjusted according to the first data voltage DATA1. At the same time, during the third period t13, the second sensing voltage Vsen2 is input to the second ADC ADC2, and the second ADC ADC2 outputs the second sensing data. At the same time, during the third period t13, the second sensing voltage Vsen2 is input to the second ADC ADC2, and the second ADC ADC2 outputs the second sensing data.

[0122] Figure 5is shown in Figure 2. Figure 2 : Waveform diagram of signals of the pixel circuit shown in . FIG. 6A to FIG. 6C is a graph showing the current during the second driving period TDRV2. Figure 2 The circuit diagram of the pixel circuit shown in FIG. Figure 5 In , 'H' is the gate-on voltage of the switch control signal, and 'L' is the gate-off voltage of the switch control signal. FIG. 6A to FIG. 6C In FIG. 1 , the bold line represents the current flowing through the switched-on switching element.

[0123] During the second driving period TDRV2, the second driving element DT2 is driven and the first driving element DT1 is sensed. For example, the light emitting element LD may be driven by the second driving element DT2, and the first driving element DT1 may be sensed by the first sensing part SU1. Figure 5 As shown, the second driving period TDRV2 may be divided into a first period t21 , a second period t22 , and a third period t23 , but is not limited thereto.

[0124] like Figure 5 As shown, during the second driving period TDRV2, the first selection signal SEL1 is the gate-off voltage VGL, and the second selection signal SEL2 is the gate-on voltage VGH. Therefore, during the second driving period TDRV2, the third switching element M03 is turned on, and the first switching element M01 is in the off state. Specifically, during the second driving period TDRV2, the third switching element M03 is turned on in response to the gate-on voltage VGH of the second selection signal SEL2, and the first switching element M01 is turned off in response to the gate-off voltage VGL of the first selection signal SEL1.

[0125] Reference Figure 5 and Fig. 6A During the first period t21, the voltages of the first scan signal SCAN1 and the second scan signal SCAN2, the first switch control signal SPRE1 and the third switch control signal SPRE2, and the second sensing signal SENSE2 are the gate-on voltage (VGH, H). Therefore, during the first period t21, the second switch element M02, the third switch element M03, the fourth switch element M04, the second sensing switch element M06, the first initialization switch element SW1, and the second initialization switch element SW3 are turned on. At this time, the first data voltage DATA1 is charged in the first capacitor C1, and the second data voltage DATA2 is charged in the second capacitor C2.

[0126] During the first period t21, the voltages of the first sensing signal SENSE1, the first switch control signal SAM1 and the fourth switch control signal SAM2 are the gate cut-off voltage (VGL, L). Therefore, during the first period t21, the first switch element M01, the first sensing switch element M05, the first sampling switch element SW2 and the second sampling switch element SW4 are cut off.

[0127] During the first period t21, the first switch element M01 is turned off, and the third switch element M03 and the fourth switch element M04 are turned on. During the first period t21, a current path can be formed between the driving voltage VDD and the cathode voltage VSS through the second driving element DT2 and the third switching element M03, so that the light emitting element LD can be driven by the second driving element DT2, and the first driving part DRV1 can be sensed. In this case, the light intensity of the light emitting element LD can be adjusted according to the second data voltage DATA2. At this time, during the first period t21, the first sensing voltage Vsen1 is input to the first ADC ADC1 that outputs the first sensing data.

[0128] Reference Figure 5 and Figure 6B During the second period t22, the voltages of the first scan signal SCAN1 and the second scan signal SCAN2, the third switch control signal SPRE2, the first sensing signal SENSE1 and the second sensing signal SENSE2 are the gate-on voltage (VGH, H). Therefore, during the second period t22, the second switch element M02, the third switch element M03, the fourth switch element M04, the first sensing switch element M05, the second sensing switch element M06 and the second initialization switch element SW3 are turned on.

[0129] During the second period t22, the voltages of the first switch control signal SPRE1, the second switch control signal SAM1 and the fourth switch control signal SAM2 are the gate-off voltage (VGL, L). Therefore, during the second period t22, the first switch element M01, the first initialization switch element SW1, the first sampling switch element SW2 and the second sampling switch element SW4 are turned off.

[0130] During the second period t22, the voltage of the third node n3 may rise, and the level of the rise may be different according to the electrical characteristics of the first driving element DT1. At this time, the first sensing voltage Vsen1 sensed from the third node n3 is charged in the first sensing capacitor CS1. Depending on the electrical characteristics of the first driving element DT1, the first sensing voltage Vsen1 may be higher or lower than the first data voltage DATA1.

[0131] During the second period t22, the first switch element M01 is turned off, and the third switch element M03 and the fourth switch element M04 are turned on. During the second period t22, a current path can be formed between the driving voltage VDD and the cathode voltage VSS through the second driving element DT2 and the third switching element M03, so that the light emitting element LD can be driven by the second driving element DT2, and the first driving part DRV1 can be sensed. In this case, the light intensity of the light emitting element LD can be adjusted according to the second data voltage DATA2. At this time, during the second period t22, the first sensing voltage Vsen1 is input to the first ADC ADC1 that outputs the first sensing data.

[0132] Reference Figure 5 and Figure 6C During the third period t23, the voltages of the second scan signal SCAN2, the third switch control signal SPRE2, the second sensing signal SENSE2 and the second switch control signal SAM1 are the gate-on voltage (VGH, H). Therefore, during the third period t23, the third switch element M03, the fourth switch element M04, the second sensing switch element M06, the second initialization switch element SW3 and the first sampling switch element SW2 are turned on.

[0133] During the third period t23, the voltages of the first scan signal SCAN1, the first sensing signal SENSE1, the fourth switch control signal SAM2, and the first switch control signal SPRE1 are the gate-off voltage (VGL, L). Therefore, during the third period t23, the first switch element M01, the second switch element M02, the first sensing switch element M05, the first initialization switch element SW1, and the second sampling switch element SW4 are turned off.

[0134] During the third period t23, the first switch element M01 is turned off, and the third switch element M03 and the fourth switch element M04 are turned on. During the third period t23, a current path can be formed between the driving voltage VDD and the cathode voltage VSS through the second driving element DT2 and the third switching element M03, so that the light emitting element LD can be driven by the second driving element DT2, and the first driving part DRV1 can be sensed. In this case, the light intensity of the light emitting element LD can be adjusted according to the second data voltage DATA2. At this time, during the third period t23, the first sensing voltage Vsen1 is input to the first ADC ADC1, and the first ADC ADC1 outputs the first sensing data.

[0135] On the other hand, the time when the light emitting element LD is driven by the first driving part DRV1 can be separated from the sensing timing of the second driving part DRV2. Similarly, the time when the light emitting element LD is driven by the second driving part DRV2 can be separated from the sensing timing of the first driving part DRV1.

[0136] In the pixel circuit according to the exemplary embodiment of the present disclosure, the cathode voltage VSS may be changed to adjust the light emitting time of the light emitting element LD, such as Figure 3 and Figure 5 For example, the light emission of the light emitting element LD can be suppressed by increasing the cathode voltage VSS in the first period t11, t21 and the second period t12, t22 of the first driving period TDRV1 and the second driving period TDRV2. In another exemplary embodiment, a separate switching element can be added between the light emitting element LD and the switching elements M01 and M03 to switch the current path between the light emitting element LD and the switching elements M01 and M03, as shown in FIG. Figure 7 as shown in .

[0137] Figure 7 is a circuit diagram showing a pixel circuit according to a second exemplary embodiment of the present disclosure. Figure 7 In the circuit shown, Figure 2 The substantially same components are denoted by the same reference numerals, and their detailed descriptions will be omitted or briefly given. Figure 7 In the pixel circuit shown in FIG. 1 , the first sensing part SU1 and the second sensing part SU2 can alternately sense the electrical characteristics of the first driving element DT1 and the second driving element DT2. Figures 3 to 6A During the first driving period, the first driving part DRV1 may drive the light emitting element LD, and the second driving part DRV2 may be sensed by the second sensing part SU2. During the second driving period, the second driving part DRV2 may drive the light emitting element LD, and the first sensing part SU1 may sense the first driving part DRV1.

[0138] Reference Figure 7 ,Apart from Figure 2 In addition to the components shown in the exemplary embodiment of the present invention, the pixel circuit may further include a fifth switching element M07 that connects the fourth node n4 to the anode of the light emitting element LD in response to a light emitting signal (hereinafter referred to as an "EM signal"), but is not limited thereto. The fifth switching element M07 may be implemented as a transistor, but is not limited thereto.

[0139] The gate driving circuit may further include, but is not limited to, a seventh shift register for sequentially providing the EM signal EM to the seventh gate line.

[0140] The fifth switch element M07 may be connected between the fourth node n4 and the anode of the light emitting element LD. The fifth switch element M07 is turned on or off in response to the EM signal EM. For example, the fifth switch element M07 is turned on in response to the gate low voltage VGL of the EM signal EM, and is turned off in response to the gate high voltage VGH of the EM signal EM, but is not limited thereto. When the fifth switch element M07 is turned on, the fourth node n4 may be electrically connected to the anode of the light emitting element LD to provide current to the light emitting element LD so that the light emitting element LD emits light. When the fifth switch element M07 is turned off in response to the gate cut-off voltage of the EM signal EM, the current path between the fourth node n4 and the light emitting element LD is electrically disconnected so that the light emitting element LD does not emit light. The fifth switch element M07 includes a first electrode connected to the fourth node n4, a gate to which the EM signal EM is applied, and a second electrode connected to the anode of the light emitting element LD.

[0141] The fifth switching element M07 may be turned off in the first period t11, t21 and the second period t12, t22 of the first driving period TDRV1 and the second driving period TDRV2, but is not limited thereto. The brightness of the light emitting element LD may be adjusted by adjusting the duty ratio of the EM signal EM.

[0142] Fig. 8A and Figure 8B is a circuit diagram showing a pixel circuit according to a third exemplary embodiment of the present disclosure. Fig. 8A and Figure 8B In the circuit shown, Figure 2 The substantially same components are denoted by the same reference numerals, and their detailed descriptions will be omitted or briefly given. Fig. 8A and Figure 8B In the circuit shown in FIG. 1 , the first sensing part SU1 and the second sensing part SU2 can alternately sense the electrical characteristics of the first driving element DT1 and the second driving element DT2. Figures 3 to 6A During the first driving period, the first driving part DRV1 may drive the light emitting element LD, and the second driving part DRV2 may be sensed by the second sensing part SU2. During the second driving period, the second driving part DRV2 may drive the light emitting element LD, and the first sensing part SU1 may sense the first driving part DRV1.

[0143] Reference Fig. 8A and Figure 8B ,Apart from Figure 2 In addition to the components shown in the exemplary embodiment of the present invention, the pixel circuit may further include a fifth switching element M08, a sixth switching element M09, a first light emitting element LD1 and a second light emitting element LD2, but is not limited thereto. The fifth switching element M08 and the sixth switching element M09 may be implemented as transistors, but are not limited thereto.

[0144] The gate driving circuit may further include, but is not limited to, a seventh shift register sequentially providing the first EM signal EM1 to the seventh gate line and an eighth shift register sequentially providing the second EM signal EM2 to the eighth gate line.

[0145] The fifth switch element M08 may be connected between the fourth node n4 and the anode of the first light emitting element LD1. The fifth switch element M08 is turned on or off in response to the first EM signal EM1. For example, the fifth switch element M08 is turned on in response to the gate-on voltage VGH of the first EM signal EM1, and is turned off in response to the gate-off voltage VGL of the first EM signal EM1. When the fifth switch element M08 is turned on, the fourth node n4 may be electrically connected to the anode of the first light emitting element LD1 to provide current to the first light emitting element LD1 so that the first light emitting element LD1 emits light. When the fifth switch element M08 is turned off in response to the gate-off voltage of the first EM signal EM1, the current path between the fourth node n4 and the first light emitting element LD1 is electrically disconnected, so that the first light emitting element LD1 does not emit light. The fifth switch element M08 includes a first electrode connected to the fourth node n4, a gate to which the first EM signal EM1 is applied, and a second electrode connected to the anode of the first light emitting element LD1.

[0146] The sixth switch element M09 may be connected between the fourth node n4 and the anode of the second light emitting element LD2. The sixth switch element M09 is turned on or off in response to the first EM signal EM2. For example, the sixth switch element M09 is turned on in response to the gate-on voltage VGH of the first EM signal EM2, and is turned off in response to the gate-off voltage VGL of the first EM signal EM2. When the sixth switch element M09 is turned on, the fourth node n4 may be electrically connected to the second light emitting element LD2 to provide current to the second light emitting element LD2 so that the second light emitting element LD2 emits light. When the sixth switch element M09 is turned off in response to the gate-off voltage of the second EM signal EM2, the current path between the fourth node n4 and the second light emitting element LD2 is electrically disconnected so that the second light emitting element LD2 does not emit light. The sixth switch element M09 includes a first electrode connected to the fourth node n4, a gate to which the second EM signal EM2 is applied, and a second electrode connected to the anode of the second light emitting element LD2.

[0147] When the first switching element M01, the second switching element M02, and the fifth switching element M08 in the transistor belonging to the first driving part DRV1 are turned on and at least the sixth switching element M09 in the transistor belonging to the second driving part DRV2 is turned off, only the first light emitting element LD1 may emit light. At this time, the electrical characteristics of the second driving element DT2 may be sensed. On the other hand, when the third switching element M03, the fourth switching element M04, and the sixth switching element M09 in the transistor belonging to the second driving part DRV2 are turned on and at least the fifth switching element M08 in the transistor belonging to the first driving part DRV1 is turned off, only the second light emitting element LD2 may emit light. At this time, the electrical characteristics of the first driving element DT1 may be sensed.

[0148] When the first to sixth switching elements M01 to M04 , M08 , and M09 are turned on at the same time, the first light emitting element LD1 and the second light emitting element LD2 may emit light at the same time.

[0149] In the present exemplary embodiment, when at least one of the light emitting elements LD1 and LD2 is driven by the corresponding driving elements DT1 and DT2, the electrical characteristics of the other light emitting element can be sensed in real time, and both the light emitting elements LD1 and LD2 can emit light at the same time, so as to increase the brightness of the display pixel and / or the local dimming pixel with a smaller current. Therefore, not only can the degradation, power consumption and life of the driving elements DT1 and DT2 and the light emitting elements LD1 and LD2 be improved, but also an HDR (high dynamic range) image can be reproduced with the highest possible brightness and high contrast.

[0150] Fig. 9 FIG. 2 is a circuit diagram showing a pixel circuit according to a fourth exemplary embodiment of the present disclosure. In this exemplary embodiment, the circuit configuration of the sensing portion can be simplified. Fig. 9 In the circuit shown, Figure 2 Substantially the same components are denoted by the same reference numerals, and a detailed description thereof will be omitted or given briefly.

[0151] Reference Fig. 9 The sensing part of the pixel circuit may include a sensing capacitor CS, a first sensing switch element M5, a second sensing switch element M6, an initialization switch element SW1, a sampling switch element SW2 and an ADC. The sensing part is connected to the third node n3 and the sixth node n6 to sense the electrical characteristics of the first driving element DT1 and the second driving element DT2.

[0152] The sensing capacitor CS is connected to the sensing line SL. The first sensing switch element M5 is connected between the third node n3 and the sensing line SL. The first sensing switch element M5 is turned on or off in response to the first sensing signal SENSE1. For example, the first sensing switch element M5 is turned on in response to the gate-on voltage VGH of the first sensing signal SENSE1, and is turned off in response to the gate-off voltage VGL of the first sensing signal SENSE1, but is not limited thereto. The first sensing switch element M5 is turned on in response to the gate-on voltage VGH of the first sensing signal SENSE1 to connect the third node n3 to the sensing line SL. When the first sensing switch element M5 is turned on, the sensing capacitor CS is charged by the charge from the third node n3. The first sensing switch element M5 includes a first electrode connected to the third node n3, a gate to which the first sensing signal SENSE1 is applied, and a second electrode connected to the sensing line SL.

[0153] The second sensing switch element M6 is connected between the sixth node n6 and the sensing line SL. The second sensing switch element M6 is turned on or off in response to the second sensing signal SENSE2. For example, the second sensing switch element M6 is turned on in response to the gate-on voltage VGH of the second sensing signal SENSE2, and is turned off in response to the gate-off voltage VGL of the second sensing signal SENSE2, but is not limited thereto. The second sensing switch element M6 is turned on in response to the gate-on voltage VGH of the second sensing signal SENSE2 to connect the sixth node n6 to the sensing line SL. When the second sensing switch element M6 is turned on, the sensing capacitor CS is charged by the charge from the sixth node n6. The second sensing switch element M6 includes a first electrode connected to the sixth node n6, a gate to which the second sensing signal SENSE2 is applied, and a second electrode connected to the sensing line SL.

[0154] The initialization switching element SW1 is turned on in response to the first switch control signal SPRE to apply the reference voltage Vref to the sensing line SL. The initialization switching element SW1 includes a first electrode connected to the sensing line SL, a gate to which the first control signal SPRE is applied, and a second electrode to which the reference voltage Vref is applied.

[0155] The sampling switch element SW2 is turned on in response to the second switch control signal SAM to provide the sensing voltage Vsen charged in the sensing capacitor CS to the ADC. The sampling switch element SW2 includes a first electrode connected to the sensing line SL, a gate to which the second switch control signal SAM is applied, and a second electrode connected to an input terminal of the ADC.

[0156] The ADC converts the sensing voltage Vsen input when the sampling switch element SW2 is turned on into digital data and outputs the sensing data.

[0157] The switch control signals for controlling the initialization switch element SW1 and the sampling switch element SW2 may be generated from separate controllers, but are not limited thereto.

[0158] Fig.10 It shows the input to Fig. 9 : Waveform diagram of signals of the pixel circuit shown in . FIG. 11A to FIG. 11C It is shown Fig. 9 A circuit diagram of the phased operation of the pixel circuit is shown.

[0159] like Fig.10 As shown, the voltage of the first selection signal SEL1 may be a gate-on voltage VGH, and the voltage of the second selection signal SEL2 may be a gate-off voltage VGL, but is not limited thereto. Therefore, the first switch element M01 is turned on, and the third switch element M03 is in a cut-off state. Specifically, the first switch element M01 is turned on in response to the gate-on voltage VGH of the first selection signal SEL1, and the third switch element M03 is cut off in response to the gate-off voltage VGL of the second selection signal SEL2. In this case, the first drive element DT1 may drive the light emitting element LD, and the electrical characteristics of the second drive element DT2 may be sensed. Alternatively, the voltage of the second selection signal SEL2 may be a gate-on voltage VGH, and the voltage of the first selection signal SEL1 may be a gate-off voltage VGL. In this case, the second drive element DT2 may drive the light emitting element LD, and the electrical characteristics of the first drive element DT1 may be sensed. Fig.10 The example in which the voltage of the first selection signal SEL1 is the gate-on voltage VGH and the voltage of the second selection signal SEL2 is the gate-off voltage VGL is not shown.

[0160] Reference Fig.10 and Fig.11A , during the first period t1, the voltages of the first selection signal SEL1, the first scan signal SCAN1 and the second scan signal SCAN2, the first switch control signal SPRE and the first sensing signal SENSE1 are the gate-on voltage (VGH, H). Therefore, during the first period t1, the first switch element M01, the second switch element M02, the fourth switch element M04, the first sensing switch element M5 and the initialization switch element SW1 are turned on. At this time, the first data voltage DATA1 is charged in the first capacitor C1, and the second data voltage DATA2 is charged in the second capacitor C2.

[0161] During the first period t1, the voltages of the second selection signal SEL2, the second sensing signal SENSE2 and the second switch control signal SAM are the gate-off voltage (VGL, L). Therefore, during the first period t1, the third switch element M03, the second sensing switch element M6 and the sampling switch element SW2 are turned off.

[0162] During the first period t1, the first switching element M01 and the second switching element M02 are turned on, and the third switching element M03 is turned off. During the first period t1, a current path can be formed between the driving voltage VDD and the cathode voltage VSS through the first driving element DT1 and the first switching element M01, so that the light emitting element LD can be driven.

[0163] Reference Fig.10 and Fig. 11B During the second period t2, the voltages of the first selection signal SEL1, the second scan signal SCAN2 and the second sensing signal SENSE2 are the gate-on voltage (VGH, H). Therefore, during the second period t2, the first switch element M01, the fourth switch element M04 and the second sensing switch element M6 are turned on.

[0164] During the second period t2, the voltages of the second selection signal SEL2, the first scan signal SCAN1, the first sensing signal SENSE1, the first switch control signal SPRE and the second switch control signal SAM2 are the gate cut-off voltage (VGL, L). Therefore, during the second period t2, the second switch element M02, the third switch element M03, the first sensing switch element M5, the initialization switch element SW1 and the sampling switch element SW2 are cut off.

[0165] Reference Fig.10 and Fig. 11C During the third period t3, the voltages of the first selection signal SEL and the second switch control signal SAM are the gate-on voltage (VGH, H). Therefore, during the third period t3, the first switch element M01 and the sampling switch element SW2 are turned on.

[0166] During the third period t3, the voltages of the second selection signal SEL2, the first scan signal SCAN1, the second scan signal SCAN2, the first sensing signal SENSE1, the second sensing signal SENSE2 and the first switch control signal SPRE are the gate-off voltage (VGL, L). Therefore, during the third period t3, the third switch element M03, the second switch element M02, the fourth switch element M04, the first sensing switch element M5, the second sensing switch element M6 and the initialization switch element SW1 are turned off.

[0167] exist Fig.10In the pixel circuit shown in FIG. 1 , a separate switching element may be added between the light emitting element LD and the switching elements M1 and M3. The switching element may connect the fourth node n4 to the anode of the light emitting element LD in response to the EM signal. Figure 7 shown.

[0168] The pixel circuit may be applied to a display pixel of a display panel that displays an input image. In addition, the pixel circuit may be applied to a local dimming pixel of a backlight unit (BLU) that irradiates light onto a transmissive display panel, but is not limited thereto.

[0169] Fig.12 is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0170] Reference Fig.12 The display device may include a display panel 100 and a display panel driving circuit for writing pixel data into pixels of the display panel 100 . In addition, the display device may further include a power supply 150 .

[0171] The display panel 100 may be, but is not limited to, a panel including a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. For example, the display panel 100 may be a deformed panel that is at least partially curved or elliptical, but is not limited thereto.

[0172] The display area AA of the display panel 100 includes a pixel array for displaying an input image thereon. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 crossing the data lines 102, and display pixels 101 arranged in a matrix form. The display panel 100 may also include power lines commonly connected to the display pixels 101. The power lines may be commonly connected to the pixel circuits, and provide the voltages required to drive the display pixels 101 to the display pixels 101.

[0173] Each display pixel 101 can be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color implementation, but is not limited thereto. Each display pixel 101 can be divided into sub-pixels of other colors (e.g., cyan, magenta, or yellow, etc.). Each display pixel 101 can also include a white sub-pixel. Each sub-pixel includes a display pixel circuit for driving a light-emitting element. The light-emitting element may include an OLED or an inorganic LED. Each display pixel circuit is connected to a data line, a gate line, and a power line. The display pixel circuit can be implemented as Figures 1 to 11C The pixel circuit shown.

[0174] The display pixel 101 can be set as a real color pixel and a pentile pixel. By using a preset pixel rendering algorithm to drive two sub-pixels with different colors into one display pixel 101, the pentile pixel can achieve a higher resolution than the real color pixel. The pixel rendering algorithm can compensate for the insufficient color representation in each display pixel 101 with the color of the light emitted from its adjacent display pixel 101.

[0175] The display array AA includes a plurality of display pixel rows L1 to Ln. Each of the display pixel rows L1 to Ln includes a row of display pixels 101 arranged in the display area AA of the display panel 100 along the row direction (X-axis direction). The display pixels 101 arranged in one pixel row may share a gate line 103. Sub-pixels arranged in the column direction (Y-axis direction) of the data line direction may share the same data line 102. One horizontal cycle is a time obtained by dividing one frame period by the total number of the pixel rows L1 to Ln.

[0176] The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device in which an image is displayed on a screen and an actual object in the background is visible. The display panel 100 may be made into a flexible display panel that can be flexibly bent.

[0177] The power supply 150 receives an input voltage provided from the host system 300, and outputs a voltage required to drive the display pixel 101 of the display panel 100 and the display panel driving circuit. To this end, the power supply 150 may include a DC to DC converter (DC-DC converter). The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply 150 may output a constant voltage (or DC voltage) such as a gate-on voltage, a gate-off voltage, a pixel driving voltage, a cathode voltage, a reference voltage, an IC driving voltage of a display panel driving circuit, etc. through a DC-DC converter. The gate-on voltage and the gate-off voltage may be provided to the level shifter 140 and the gate driver 120. Constant voltages such as the pixel driving voltage, the cathode voltage, the reference voltage, etc. are provided to the display pixel 101 through a power line commonly connected to the display pixel 101.

[0178] The power supply 150 may also include a gamma voltage generator. The gamma voltage generator receives a high potential reference voltage and a low potential reference voltage, and outputs a plurality of gamma reference voltages divided at predetermined voltage intervals on a preset gamma curve (e.g., a 2.2 gamma curve). The gamma reference voltage is provided to the data driver 110. In the data driver 110, the gamma reference voltage is divided by a voltage divider circuit and subdivided into grayscale voltages. The gamma voltage generator may be implemented as a programmable gamma circuit that is capable of adjusting each of the gamma reference voltages according to digital data. The controller 130 or the host system 300 or a separate external device may update the digital data stored in the register of the programmable gamma circuit through a communication interface.

[0179] The display panel driving circuit writes the pixel data of the input image to the display pixel 101 of the display panel 100 under the control of the controller 130. The display panel driving circuit may include a data driver 110 and a gate driver 120, but is not limited thereto. In the display device according to one or more exemplary embodiments of the present disclosure, the gate driver 120 may be implemented as a gate-in-panel (GIP) type and may be directly disposed on the substrate of the display panel. Alternatively, the gate driver 120 may be integrated and arranged on the display panel, or each gate driver 120 may be implemented by a chip-on-film COF method in which components are mounted on a film connected to the display panel.

[0180] In addition, the display panel driving circuit may further include a touch sensor driver for driving the touch sensor. Fig.12 The touch sensor driver is omitted in FIG. The data driver 110 and the touch sensor driver may be integrated into a source driver integrated circuit (IC).

[0181] The data driver 110 receives pixel data of an input image received as a digital signal from the controller 130 and outputs a data voltage. The data driver 110 may receive a gamma reference voltage through a voltage divider circuit and generate a gamma compensation voltage for each grayscale. The gamma compensation voltage for each grayscale is provided to a digital-to-analog converter ("DAC") provided on each channel of the data driver 110.

[0182] The data driver 110 samples and latches the digital data received from the controller 130 and then inputs the digital data to the DAC. The digital data includes pixel data of an input image. The DAC converts the pixel data into a gamma compensation voltage and outputs a data voltage of the pixel data.

[0183] The gate driver 120 may be formed on the display panel 100 together with the circuit elements and wirings of the display area AA. The gate driver 120 may be disposed in the non-display area NA of at least one of the right side or the left side outside the display area AA in the display panel 100, or at least a portion thereof may be disposed in the display area AA, but is not limited thereto.

[0184] The gate driver 120 may be disposed in the non-display area NA on both sides of the display panel 100 with the display area AA of the display panel interposed therebetween, and the gate driver 120 may provide a gate pulse from both sides of the gate line 103 by a double feeding method. The gate driver 120 may be disposed in at least one of the left and right non-display areas NA of the display panel 100 to provide a gate signal to the gate line 103 by a single feeding method. The gate driver 120 may shift the pulses of the gate signal using a shift register to sequentially provide them to the gate line 103. When a plurality of gate signals are applied to each display pixel 101, the gate driver 120 may include a plurality of shift registers. The gate signal may include a scan signal or an EM light emitting signal (alternatively referred to as an "EM signal") input to the pixel circuit via a plurality of gate lines.

[0185] The controller 130 receives an input image signal and a timing signal synchronized with the input image signal from the host system 300. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The horizontal synchronization signal Hsync and the data enable signal DE have a period of one horizontal period (1H).

[0186] The controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110 and a gate timing control signal for controlling the operation timing of the gate driver 120 to control the display panel driving circuit based on the timing signals Vsync, Hsync, and DE received from the host system 300. The controller 130 can synchronize the data driver 110 and the gate driver 120 by controlling the operation timing of the display panel driving circuit.

[0187] The timing control signal output from the controller 130 may be input to the shift register in the gate driver 120 through the level shifter 140. The level shifter 140 may convert the voltage level of the gate timing signal received from the controller 130 into a swing width between a gate-on voltage and a gate-off voltage, and provide it to the gate driver 120.

[0188] The controller 130 may include a compensation part that receives sensing data from a sensing part of the display pixel circuit. The compensation part may compensate for degradation of electrical characteristics of the first and second driving elements DT1 and DT2 of each display pixel 101 by modulating pixel data based on the sensing data.

[0189] Fig.13 is a block diagram illustrating a display device according to another exemplary embodiment of the present disclosure. Fig.14 It is shown Fig.13 A perspective view of a display panel and a backlight unit is shown.

[0190] Reference Fig.13 and Fig.14 The display device may include a display panel 400, a display panel driving circuit for writing pixel data to display pixels 401 of the display panel 400, a backlight unit 200 for irradiating the display panel 400 with light emitted from the light-emitting element LD of the local dimming pixel 201, and a backlight driving circuit for writing local dimming data to the local dimming pixel 201, etc.

[0191] The display panel 400 may be a transmissive display panel including a liquid crystal layer without a light-emitting element. On the lower transparent substrate of the display panel 400, the data line 402 and the gate line 403 are crossed, and the display pixel 401 connected to the data line 402 and the gate line 403 is set. The display panel 400 may also include a power line connected to the display pixel 401 in common. The power line may be connected to the pixel circuit in common, and provide the display pixel 401 with the voltage required to drive the display pixel 401. A black matrix, a color filter, and a common electrode to which a common voltage is applied may be formed on the upper transparent substrate of the display panel 400. The common electrode may be formed on the upper transparent substrate in a vertical field drive mode such as a TN (twisted nematic) mode and a VA (vertical alignment) mode, and may be arranged on the lower transparent substrate in a horizontal field drive mode such as an IPS (in-plane switching) mode and an FFS (edge ​​field switching) mode, together with the pixel electrode of the display pixel 401.

[0192] A polarizer having orthogonal optical axes is attached to each of the upper and lower transparent substrates of the display panel 400. In each of the upper and lower transparent substrates of the display panel 400, an alignment film for setting a pre-tilt angle of liquid crystal is formed on an inner surface contacting the liquid crystal layer.

[0193] Each display pixel 401 can be divided into red sub-pixel, green sub-pixel and blue sub-pixel for color realization.Each display pixel 401 can also include white sub-pixel, but is not limited to this.Each display pixel 401 can be divided into sub-pixels of other colors (for example, cyan, magenta or yellow, etc.).Display pixel 401 can be set to true color pixel and pixel arrangement pixel.Each sub-pixel can include a switching element, such as TFT, that the data voltage applied to data line 402 is delivered to pixel electrode in response to the gating signal from gating line 403.Each sub-pixel uses the liquid crystal molecules driven by the electric field between pixel electrode and common electrode to adjust the transmittance of the light passing through polarizer.

[0194] The display array AA includes a plurality of display pixel rows L1 to Ln. Each of the display pixel rows L1 to Ln includes a row of display pixels 401 arranged along the row direction (X-axis direction) in the display area AA of the display panel 400. The display pixels 401 arranged in one pixel row may share a gate line 403. Sub-pixels arranged in the column direction (Y-axis direction) along the data line direction may share the same data line 402.

[0195] The power supply 450 receives an input voltage provided from the host system 600 and outputs a voltage required to drive the display pixels 401, the display panel driving circuit, the local dimming pixels 201, and the backlight driving circuit of the display panel 400. To this end, the power supply 450 may include a direct current to direct current converter (DC-DC converter).

[0196] The display panel driving circuit writes the pixel data of the input image to the display pixel 401 of the display panel 400 under the control of the first controller 430. The display panel driving circuit may include a data driver 410 and a gate driver 420, but is not limited thereto. In addition, the display panel driving circuit may further include a touch sensor driver for driving a touch sensor. Fig.13 The touch sensor driver is omitted in FIG. The data driver 410 and the touch sensor driver may be integrated into a source driver integrated circuit (IC).

[0197] The data driver 410 receives pixel data of an input image provided as a digital signal from the first controller 430 and outputs a data voltage. The data voltage output from the data driver 410 is provided to the data line 402 of the display panel 400. The circuit of the data driver 410 may be implemented as a driver IC (DIC) and mounted on a flexible film of a chip on film (COF), such as Fig.14 The COF may be bonded to the display panel 400 through an anisotropic conductive film (ACF), but is not limited thereto.

[0198] The gate driver 420 outputs pulses of the gate signal while shifting them using a shift register. The pulses of the gate signal output from the gate driver 420 are sequentially supplied to the gate lines 403 of the display panel 400.

[0199] The first controller 430 receives an input image signal and a timing signal synchronized with the input image signal from the host system 600. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. The first controller 430 generates a data timing control signal for controlling the operation timing of the data driver 410 and a gate timing control signal for controlling the operation timing of the gate driver 420 based on the timing signals Vsync, Hsync, and DE received from the host system 300 to control the display panel driving circuit.

[0200] The gate timing control signal output from the first controller 430 may be input to the shift register in the gate driver 420 through the level shifter 440. The level shifter 440 may convert the voltage level of the gate timing signal received from the first controller 430 into a swing width between a gate-on voltage and a gate-off voltage, and provide it to the gate driver 420.

[0201] The first controller 430 or the second controller 500 generates local dimming data from the pixel data of the input image. The local dimming data can be calculated for each block of the display panel 400. The display area AA of the display panel 400 can be virtually divided into a plurality of blocks, and the backlight brightness of the plurality of blocks is independently controlled by local dimming. Each block of the display panel 400 includes a plurality of pixels. The local dimming data can be calculated as, but is not limited to, an average value of the pixel data of the input image in units of blocks of the display panel 400. The first controller 430 can transmit the pixel data of the input image or the local dimming data to the second controller 500.

[0202] The backlight unit 200 includes a plurality of local dimming pixels 201. Each local dimming pixel 201 includes a local dimming pixel circuit that drives a corresponding light emitting element LD. The light emitting element LD may be implemented as an OLED or an inorganic LED, and the present disclosure is not limited thereto. Each local dimming pixel circuit is connected to a data line 202, a gate line 203, and a power line. The local dimming pixel circuit may be implemented as Figures 1 to 11C The pixel circuit shown.

[0203] The light emitting element LD of the backlight unit 200 is disposed below the display panel 400. Fig.14The backlight unit 200 further includes a light emitting element LD of the local dimming pixel 201 and one or more optical sheets 250 disposed between the display panel 400 . The optical sheet 250 uniformly irradiates light from the light emitting element LD in a direction perpendicular to a surface of the display panel 400 .

[0204] The backlight driving circuit writes the local dimming data to the local dimming pixel 201 under the control of the second controller 500. The backlight driving circuit includes a data driver 210 and a gate driver 220.

[0205] The data driver 210 converts the local dimming data received from the second controller 500 into data voltages and supplies them to the data lines 202 connected to the local dimming pixels 201. The gate driver 220 may shift pulses of gate signals using a shift register to sequentially supply them to the gate lines 203.

[0206] The second controller 500 may receive local dimming data from the first controller 430 or receive pixel data of an input image from the first controller 430 to generate local dimming data. The second controller 500 transmits the local dimming data to the data driver 210 and controls the operation timing of the data driver 210 and the gate driver 220. The second controller 500 may control the operation timing of the data driver 210 and the gate driver 220.

[0207] The second controller 500 may include a compensation part that receives sensing data from the sensing part of the local dimming pixel circuit. The compensation part may compensate for degradation of electrical characteristics of the first driving element DT1 and the second driving element DT2 of each local dimming pixel 201 by modulating the local dimming data based on the sensing data. The second controller 500 may be implemented as a micro control unit (MCU), but is not limited thereto.

[0208] According to one or more exemplary embodiments of the present disclosure, the display device may be applied to a mobile device, a video phone, a smart watch, a watch phone, a wearable device, a foldable device, a rollable device, a bendable device, a flexible device, a bending device, a sliding device, a variable device, an electronic organizer, an electronic book, a portable multimedia player (PMP), a personal digital assistant (PDA), an MP3 player, a mobile medical device, a desktop PC, a laptop PC, a netbook computer, a workstation, a navigation, a vehicle navigation, a vehicle display device, a vehicle device, a theater device, a theater display device, a television, a wallpaper device, a sign device, a game device, a laptop computer, a monitor, a camera, a video camera, and a home appliance, etc. In addition, the display device according to one or more exemplary embodiments of the present disclosure may be applied to an organic light emitting display device or an inorganic light emitting display device, and the present disclosure is not limited thereto.

[0209] The objects to be achieved by the present disclosure, means for achieving the objects, and effects of the present disclosure described above do not specify essential features of the claims, and therefore, the scope of the claims is not limited to the disclosed contents of the present disclosure.

[0210] Although the exemplary embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure.

[0211] CROSS-REFERENCE TO RELATED APPLICATIONS

[0212] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0132371, filed on October 5, 2023, the disclosure of which is incorporated herein by reference in its entirety for all purposes as if fully set forth herein.

Claims

1. A pixel circuit, comprising: a first drive transistor including a first electrode connected to a first node to which a drive voltage is applied, a gate connected to a second node, and a second electrode connected to a third node; a second driving transistor including a first electrode connected to the first node, a gate connected to a fifth node, and a second electrode connected to a sixth node; as well as A sensing portion configured to sense electrical characteristics of the first driving transistor and the second driving transistor.

2. The pixel circuit according to claim 1, wherein: The sensing part comprises: a first sensing part connected to the third node and configured to sense an electrical characteristic of the first driving transistor; and A second sensing part is connected to the sixth node and configured to sense an electrical characteristic of the second driving transistor.

3. The pixel circuit according to claim 2, further comprising: a first capacitor connected between the second node and a fourth node; a first switch transistor configured to be turned on in response to a first selection signal to connect the third node to the fourth node; a second switching transistor configured to be turned on in response to a first scan signal to provide a first data voltage to the second node; a second capacitor connected between the fourth node and the fifth node; a third switch transistor configured to be turned on in response to a second selection signal to connect the sixth node to the fourth node; as well as a fourth switching transistor configured to be turned on in response to a second scan signal to provide a second data voltage to the fifth node.

4. The pixel circuit according to claim 3, further comprising: A light emitting element is connected to the fourth node.

5. The pixel circuit according to claim 3, wherein: The first sensing portion comprises: a first sensing capacitor connected to a first sensing line; a first sensing switch transistor configured to be turned on in response to a first sensing signal to connect the third node to the first sensing line; a first initialization switching element configured to be turned on in response to a first switch control signal to provide a first reference voltage to the first sensing line; a first analog-to-digital converter configured to convert a first sensing voltage input through the first sensing line into digital data; and a first sampling switch element configured to be turned on in response to a second switch control signal to connect the first sensing line to an input terminal of the first analog-to-digital converter, and Wherein, the second sensing part comprises: a second sensing capacitor connected to a second sensing line; a second sensing switch transistor configured to be turned on in response to a second sensing signal to connect the sixth node to the second sensing line; a second initialization switching element configured to be turned on in response to a third switch control signal to provide a second reference voltage to the second sensing line; a second analog-to-digital converter configured to convert a second sensing voltage input through the second sensing line into digital data; and A second sampling switch element is configured to be turned on in response to a fourth switch control signal to connect the second sensing line to an input terminal of the second analog-to-digital converter.

6. The pixel circuit according to claim 5, wherein: During a first driving period, driving the first driving transistor and sensing the second driving transistor, During a second driving period, the second driving transistor is driven and the first driving transistor is sensed.

7. The pixel circuit according to claim 6, wherein: During the first driving period, the light emitting element connected to the fourth node is driven by the first driving transistor, and the second driving transistor is sensed by the second sensing portion, and During the second driving period, the light emitting element is driven by the second driving transistor, and the first driving transistor is sensed by the first sensing part.

8. The pixel circuit according to claim 6, wherein: During the first driving period, the voltage of the first selection signal is a gate-on voltage, and the voltage of the second selection signal is a gate-off voltage, and During the second driving period, a voltage of the second selection signal is the gate-on voltage, and a voltage of the first selection signal is the gate-off voltage.

9. The pixel circuit according to claim 8, wherein: During the first driving period, the first switch transistor is configured to be turned on in response to a gate-on voltage of the first selection signal, and the second switch transistor is configured to be turned off in response to a gate-off voltage of the second selection signal; and During the second driving period, the first switch transistor is configured to be turned off in response to a gate-off voltage of the first selection signal, and the second switch transistor is configured to be turned on in response to a gate-on voltage of the second selection signal.

10. The pixel circuit according to claim 6, wherein: During the first driving period, the first switching transistor and the second switching transistor are configured to be turned on, and the third switching transistor is configured to be turned off.

11. The pixel circuit according to claim 10, wherein: During a first period of the first driving period, the first switching transistor, the second switching transistor, the fourth switching transistor, the first sensing switching transistor, the first initialization switching element, and the second initialization switching element are configured to be turned on, and the third switching transistor, the second sensing switching transistor, the first sampling switching element, and the second sampling switching element are configured to be turned off, During a second period of the first driving period, the first switching transistor, the second switching transistor, the fourth switching transistor, the first sensing switching transistor, the second sensing switching transistor, and the first initialization switching element are configured to be turned on, and the third switching transistor, the second initialization switching element, the first sampling switching element, and the second sampling switching element are configured to be turned off, and During a third period of the first driving period, the first switching transistor, the second switching transistor, the first sensing switching transistor, the first initialization switching element, and the second sampling switching element are configured to be turned on, and the third switching transistor, the fourth switching transistor, the second sensing switching transistor, the second initialization switching element, and the first sampling switching element are configured to be turned off.

12. The pixel circuit according to claim 11, wherein: During the second driving period, the third switching transistor and the fourth switching transistor are configured to be turned on, and the first switching transistor is configured to be turned off.

13. The pixel circuit according to claim 11, wherein: During a first period of the second driving period, the second switch transistor, the third switch transistor, the fourth switch transistor, the second sensing switch transistor, the first initialization switch element, and the second initialization switch element are configured to be turned on, and the first switch transistor, the first sensing switch transistor, the first sampling switch element, and the second sampling switch element are configured to be turned off, During a second period of the second driving period, the second switch transistor, the third switch transistor, the fourth switch transistor, the first sensing switch transistor, the second sensing switch transistor and the second initialization switch element are configured to be turned on, while the first switch transistor, the first initialization switch element, the first sampling switch element and the second sampling switch element are configured to be turned off, and During a third period of the second driving period, the third switching transistor, the fourth switching transistor, the second sensing switching transistor, the second initialization switching element and the first sampling switching element are configured to be turned on, while the first switching transistor, the second switching transistor, the first sensing switching transistor, the first initialization switching element and the second sampling switching element are configured to be turned off.

14. The pixel circuit according to claim 3, further comprising: a light emitting element connected to the fourth node; as well as a fifth switching transistor connected between the fourth node and the light emitting element and configured to connect the fourth node to an anode of the light emitting element in response to a light emitting signal.

15. The pixel circuit according to claim 3, further comprising: a first light emitting element, the first light emitting element comprising an anode and a cathode; a second light emitting element, the second light emitting element comprising an anode and a cathode; a fifth switching element configured to be turned on in response to a first light emitting signal to connect the fourth node to an anode of the first light emitting element; as well as a sixth switching element configured to be turned on in response to a second light emitting signal to connect the fourth node to an anode of the second light emitting element.

16. The pixel circuit according to claim 3, wherein: The sensing portion is connected to the third node and the sixth node.

17. The pixel circuit according to claim 16, further comprising: A light emitting element is connected to the fourth node.

18. The pixel circuit according to claim 16, wherein: The sensing part comprises: a sensing capacitor connected to the sensing line; a first sensing switch transistor configured to be turned on in response to a first sensing signal to connect the third node to the sensing line; a second sensing transistor configured to be turned on in response to a second sensing signal to connect the sixth node to the sensing line; an initialization switch element, the initialization switch element being configured to be turned on in response to a first switch control signal to provide a reference voltage to the sensing line; an analog-to-digital converter configured to convert a sensing voltage input through the sensing line into digital data; and A sampling switch element is configured to be turned on in response to a second switch control signal to connect the sensing line to an input terminal of the analog-to-digital converter.

19. A display device, comprising: A display panel, in which a plurality of data lines, a plurality of gate lines and a plurality of display pixels are arranged; Wherein each of the display pixels comprises a pixel circuit according to any one of claims 1 to 18.

20. A display device, comprising: a display panel on which pixel data of an input image is written; as well as a backlight unit, in which a plurality of local dimming pixels are arranged for irradiating light to the display panel, Each of the local dimming pixels comprises a pixel circuit according to any one of claims 1 to 18.

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