Pixel and display device

Abstract

The invention discloses a pixel and a display device. The pixel includes: a first transistor for outputting a current supplied to a light emitting device; a second transistor electrically connected between a gate of the first transistor and a first terminal of the first transistor; a third transistor electrically connected between the first voltage line and a second terminal of the first transistor; a fourth transistor electrically connected between a first terminal of the first transistor and the light emitting device; and a fifth transistor configured to supply a bias voltage to a second terminal of the first transistor. A gate on voltage may be supplied to a gate of the fifth transistor during at least a portion of a period in which a gate off voltage may be supplied to a gate of the third transistor and a gate of the fourth transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0132076 filed in the Korean Intellectual Property Office on October 4, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to a pixel and a display device including the pixel. Background Art

[0004] Applications of display devices have recently diversified. In addition, as display devices become thinner and lighter, their scope of use has expanded.

[0005] Since the display device can be utilized in various ways, the shape of the display device can be designed using various methods, and functions that can be electrically connected or linked to the display device are increasing. Summary of the invention

[0006] One or more embodiments include a display device with improved display quality. However, aspects of the embodiments may not be limited thereto, and the above characteristics do not limit the scope of the embodiments according to the present disclosure.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0008] According to one or more embodiments, a pixel may include: a light emitting device; a first transistor electrically connected between a first voltage line and the light emitting device and configured to control a current supplied to the light emitting device; a second transistor electrically connected between a first node electrically connected to a gate of the first transistor and a second node electrically connected to a first terminal of the first transistor; a third transistor electrically connected between the first voltage line and a third node electrically connected to a second terminal of the first transistor; a fourth transistor electrically connected between the second node and the light emitting device; and a fifth transistor configured to supply a bias voltage to the third node. During at least a portion of a period in which a gate-off voltage of a second level may be supplied to a gate of the third transistor and a gate of the fourth transistor, a gate-on voltage of a first level may be supplied to a gate of the fifth transistor.

[0009] The gate-on voltage may be supplied to the gate of the second transistor at the same time that the gate-on voltage may be supplied to the gate of the fifth transistor.

[0010] The frame may include: a first scanning period during which a data signal may be supplied and light may be emitted at a brightness corresponding to the data signal; and a second scanning period during which the data signal supplied during the first scanning period may be maintained and light may be emitted at a brightness corresponding to the data signal. The fifth transistor may supply a first bias voltage to a third node when a gate-on voltage may be supplied to a gate of the fifth transistor during the first scanning period, and may supply a second bias voltage to the third node when a gate-on voltage may be supplied to the gate of the fifth transistor during the second scanning period.

[0011] The second bias voltage may be higher than the first bias voltage.

[0012] The first scan period may include a first period during which, within a period in which a gate-off voltage of a second level may be supplied to the gate of the third transistor and the gate of the fourth transistor, a gate-on voltage may be supplied to each of the gate of the second transistor and the gate of the fifth transistor. The second scan period may include a second period during which, within a period in which a gate-off voltage of a second level may be supplied to the gate of the third transistor and the gate of the fourth transistor, a gate-off voltage may be supplied to the gate of the second transistor and a gate-on voltage may be supplied to the gate of the fifth transistor.

[0013] A gate of the third transistor and a gate of the fourth transistor may be electrically connected to the first gate line, and a gate of the fifth transistor may be electrically connected to the second gate line.

[0014] The pixel may further include a sixth transistor electrically connected between the pixel electrode of the light emitting device and the second voltage line, and a gate of the sixth transistor may be electrically connected to the second gate line.

[0015] The pixel may further include: a first capacitor electrically connected between the first voltage line and the fourth node; a second capacitor electrically connected between the fourth node and the first node; a seventh transistor electrically connected between the data line and the fourth node; an eighth transistor electrically connected between the fourth node and the third voltage line; and a ninth transistor electrically connected between the first node and the fourth voltage line.

[0016] The fifth transistor may be electrically connected between the third node and the third voltage line.

[0017] A gate of the seventh transistor may be electrically connected to the third gate line, a gate of the second transistor and a gate of the eighth transistor may be electrically connected to the fourth gate line, and a gate of the ninth transistor may be electrically connected to the fifth gate line.

[0018] According to one or more embodiments, a display device may include a plurality of pixels, each of the plurality of pixels may include: a light emitting device; a first transistor electrically connected between a first voltage line and the light emitting device and configured to control a current supplied to the light emitting device; a second transistor electrically connected between a first node electrically connected to a gate of the first transistor and a second node electrically connected to a first terminal of the first transistor; a third transistor electrically connected between the first voltage line and a third node electrically connected to a second terminal of the first transistor; a fourth transistor electrically connected between the second node and the light emitting device; and a fifth transistor configured to supply a bias voltage to the third node. The gate of the third transistor and the gate of the fourth transistor may be electrically connected to a first gate line supplying a first gate signal, and the gate of the fifth transistor may be electrically connected to a second gate line supplying a second gate signal.

[0019] Each of the plurality of pixels may further include: a first capacitor electrically connected between the first voltage line and the fourth node; a second capacitor electrically connected between the fourth node and the first node; a sixth transistor electrically connected between the data line and the fourth node; a seventh transistor electrically connected between the fourth node and the second voltage line; an eighth transistor electrically connected between the first node and the third voltage line; and a ninth transistor electrically connected between the pixel electrode of the light-emitting device and the fourth voltage line.

[0020] The fifth transistor may be electrically connected between the third node and the second voltage line.

[0021] The gate of the ninth transistor can be electrically connected to the second gate line, the gate of the second transistor and the gate of the seventh transistor can be electrically connected to the third gate line supplying a third gate signal, the gate of the sixth transistor can be electrically connected to the fourth gate line supplying a fourth gate signal, and the gate of the eighth transistor can be electrically connected to the fifth gate line supplying a fifth gate signal.

[0022] The frame may include a first scan period during which a data signal may be received and light may be emitted with brightness corresponding to the data signal, and the first bias voltage may be supplied to the second voltage line during the first scan period.

[0023] The frame may further include at least one second scanning period after the first scanning period, wherein, during the at least one second scanning period, the data signal supplied during the first scanning period may be maintained and light may be emitted with a brightness corresponding to the data signal, and a second bias voltage may be supplied to the second voltage line during the second scanning period.

[0024] The second bias voltage may be higher than the first bias voltage.

[0025] The display device may further include a gate drive circuit configured to supply a plurality of gate signals to a plurality of pixels, and the first scanning period and the second scanning period may include a non-emission period and an emission period, respectively. The gate drive circuit may: supply a first gate signal of a gate-off voltage to a first gate line during a non-emission period in each of the first scanning period and the second scanning period, supply a second gate signal of a gate-on voltage to a second gate line and supply a third gate signal of a gate-on voltage to a third gate line during a first period of the non-emission period of the first scanning period, and supply a second gate signal of a gate-on voltage to a second gate line and supply a third gate signal of a gate-off voltage to a third gate line during a second period of the non-emission period of the second scanning period.

[0026] The gate driving circuit may supply a fourth gate signal of a gate-on voltage to the fourth gate line during a writing period between a first period of the first scanning period and an emission period of the first scanning period.

[0027] The gate driving circuit may supply a fifth gate signal of a gate-on voltage to the fifth gate line before a first period of the non-emission period of the first scanning period. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1A and Figure 1B is a schematic diagram of a display device according to an embodiment;

[0030] Figure 2 is a schematic block diagram of a display device according to an embodiment;

[0031] Figure 3A and Figure 3B is a diagram for explaining a method of driving a display device according to a driving frequency;

[0032] Figure 4 is a schematic diagram of a display device according to an embodiment;

[0033] Figure 5 yes Figure 4 A schematic diagram of an equivalent circuit of a pixel;

[0034] Figure 6 is supplied to the Figure 4 A timing diagram of a pixel signal;

[0035] Figure 7 is supplied to the Figure 4 A timing diagram of a pixel signal;

[0036] Figure 8 is a timing diagram showing bias voltages supplied to pixels during a first scanning period and a second scanning period;

[0037] Fig. 9 is a schematic cross-sectional view of a structure of a display element according to an embodiment;

[0038] Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig.11A and Fig. 11B is a schematic cross-sectional view of a structure of a display element according to an embodiment; and

[0039] Fig.12 is a schematic cross-sectional view of a structure of a pixel of a display device according to an embodiment. DETAILED DESCRIPTION

[0040] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of the equipment or methods disclosed herein. However, it is apparent that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments need not be exclusive, nor limit the present disclosure. For example, the specific shape, configuration, and characteristics of an embodiment may be used or implemented in another embodiment.

[0041] Unless otherwise specified, the illustrated embodiments will be understood to provide features of the present invention. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of various embodiments (hereinafter, individually or collectively referred to as "elements") may be combined, separated, interchanged and / or rearranged in other ways without departing from the present invention.

[0042] The use of cross hatching and / or shadows in the drawings is generally provided to make the boundaries between adjacent elements clear. In this way, unless otherwise specified, the presence or absence of cross hatching or shadows does not convey or indicate any preference or demand for a specific material, material properties, scale, ratio, commonality between the illustrated elements and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, for clarity and / or descriptive purposes, the size and relative size of the elements may be exaggerated. When the embodiment can be implemented differently, a specific process sequence can be performed in a sequence different from that described. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to that described. In addition, the same reference numerals and / or reference characters refer to the same elements.

[0043] When an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, it may be directly on, directly connected to or coupled to the other element or layer, or there may be an intervening element or layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there is no intervening element or layer. For this reason, the term "connection" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without an intervening element. In addition, the x-direction, the y-direction, and the z-direction are not limited to directions corresponding to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the x-direction, the y-direction, and the z-direction may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0044] For the purpose of this disclosure, "at least one of A and B" may be interpreted as only A, only B, or any combination of A and B. In addition, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be understood as only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0045] Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0046] For descriptive purposes, spatially relative terms such as "below," "below," "under," "down," "above," "up," "above," "higher," and "side" (e.g., as in "sidewall") may be used herein and thereby describe the relationship of one element to another element(s) as illustrated in the figures. In addition to the orientations depicted in the figures, spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is flipped, an element described as being "below" or "below" other elements or features will then be oriented to be "above" the other elements or features. Thus, the term "below" can encompass both above and below orientations. In addition, the device can be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and as such, the spatially relative descriptors used herein should be interpreted accordingly.

[0047] The term used herein is for the purpose of describing a particular embodiment, and is not intended to be limiting. Unless the context clearly indicates otherwise, the "one" and "the (described)" in the singular as used herein are intended to also include plural forms. In addition, when used in this specification, the term "includes" and / or "comprising" and its variants indicate the existence of stated features, integral bodies, steps, operations, elements, parts and / or their groups, but do not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, parts and / or their groups. It should also be noted that, as used herein, the term "substantially", "about" and other similar terms are used as approximate terms and are not used as terms of degree, and so, are used to consider the inherent deviations in measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0048] Various embodiments are described herein with reference to cross-sectional illustrations and / or exploded illustrations as schematic illustrations of embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are expected. Therefore, the embodiments disclosed herein should not necessarily be interpreted as being limited to the shapes of the specifically illustrated zones, but will include deviations in shape due to, for example, manufacturing. In this way, the zones illustrated in the drawings may be schematic in nature, and the shapes of these zones may not reflect the actual shapes of the zones of the device, and as such, need not be intended to be limiting.

[0049] As is customary in the art, some embodiments are described and illustrated in the accompanying drawings in terms of functional blocks, units and / or modules. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as, logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements and wiring connections, etc.), which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where these blocks, units and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and they can be optionally driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware for performing some functions and a processor for performing other functions (e.g., one or more programmed microprocessors and associated circuits). In addition, each block, unit and / or module of some embodiments can be physically separated into two or more interacting and discrete blocks, units and / or modules without departing from the scope of the inventive concept. Furthermore, the blocks, units and / or modules of some embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the inventive concept.

[0050] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and unless explicitly defined as such in this article, these terms should not be interpreted in an ideal or overly formal sense.

[0051] The display device according to the embodiment displays a video or a still image, and can therefore be used as a display screen for various products, such as not only portable electronic devices such as mobile phones, smart phones, tablet computers (PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs), but also televisions, notebook computers, monitors, advertising panels, and Internet of Things (IoT) devices. The display device according to the embodiment can also be used in wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs). The display device according to the embodiment can also be used as a dashboard of a car, a central instrument panel of a car, or a central information display (CID) of a dashboard, a car's interior mirror display replacing a car's side mirror, and a display arranged on the rear side of the front seat to be used as an entertainment device for rear seat passengers of the car. The display device can be flexible.

[0052] Figure 1A and Figure 1B is a schematic diagram of a display device 10 according to an embodiment. Figure 2 is a schematic block diagram of a display device 10 according to an embodiment. Figure 3A and Figure 3B is a diagram for explaining a method of driving a display device according to a driving frequency.

[0053] refer to Figure 1A and Figure 1B , the display device 10 may include a display area DA displaying an image and a peripheral area PA around the display area DA. The display area DA may be completely surrounded by the peripheral area PA.

[0054] When the display area DA is viewed in a plan view, the display area DA may have a rectangular shape. According to an embodiment, the display area DA may have other polygonal shapes (e.g., a triangular shape, a pentagonal shape, or a hexagonal shape), a circular shape, an elliptical shape, or an irregular shape, etc. The display area DA may have a shape with rounded edge corners. According to an embodiment, the display device 10 may have a display area DA having a shape in which the length in the x direction may be greater than the length in the y direction, such as Figure 1A According to an embodiment, the display device 10 may have a display area DA having a shape in which the length in the y direction may be greater than the length in the x direction, such as Figure 1B The z direction may be perpendicular to the plane defined by the x direction and the y direction.

[0055] refer to Figure 2 The display device 10 according to the embodiment may include a pixel region 11 , a gate driving circuit 13 , a data driving circuit 15 , a power supply circuit 17 , and a controller 19 .

[0056] The pixel area 11 may be included in the display area DA. Various wires for transmitting electrical signals to be applied to the display area DA, external circuits electrically connected to the pixel circuits, and pads to which a printed circuit board (PCB) or a driver integrated circuit (IC) chip may be attached may be located in the peripheral area PA. For example, a gate driving circuit 13, a data driving circuit 15, a power supply circuit 17, and a controller 19 may be included in the peripheral area PA.

[0057] like Figure 2 As shown in FIG. 1 , a plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels PX electrically connected thereto may be disposed in a display area DA. The pixels PX may be arranged in a stripe configuration, Configuration, Diamond The pixels PX may be arranged in any of various configurations such as a pixel configuration and a mosaic configuration to display an image. Each of the pixels PX may include an organic light emitting diode OLED (see Figure 5 ) as a display element (light emitting device), and the organic light emitting diode OLED can be electrically connected to the pixel circuit. The pixel circuit may include a plurality of transistors and at least one capacitor. Each of the pixels PX can emit, for example, red light, green light, blue light or white light via the organic light emitting diode OLED. Each of the pixels PX can be electrically connected to at least one corresponding gate line among the gate lines GL and a corresponding data line among the data lines DL.

[0058] Each of the gate lines GL may extend in the x direction (row direction) and may be electrically connected to the pixels PX located in the same row. Each of the gate lines GL may transmit a gate signal to the pixels PX in the same row. Each of the data lines DL may extend in the y direction (column direction) and may be electrically connected to the pixels PX in the same column. Each of the data lines DL may transmit a data signal to the pixels PX in the same column in synchronization with the gate signal.

[0059] According to an embodiment, the peripheral area PA may be a non-display area in which the pixel PX may not be disposed. According to an embodiment, a plurality of pixels PX may be arranged in a portion of the peripheral area PA. For example, the pixel PX may be arranged at at least one corner of the peripheral area PA and may overlap with the gate driving circuit 13. Accordingly, the dead zone may be reduced and the display area DA may be expanded.

[0060] The gate drive circuit 13 may be electrically connected to the gate line GL, may generate a gate signal GS according to a control signal GCS from the controller 19, and may sequentially supply the gate signal GS to the gate line GL. The gate line GL may be electrically connected to the gate of the transistor included in the pixel PX. The gate signal GS may be a gate control signal for controlling the on and off operation of the transistor whose gate may be electrically connected to the gate line GL. The gate signal GS may be a signal including a gate-on voltage for turning on the transistor and a gate-off voltage for turning off the transistor.

[0061] Despite Figure 2 The pixel PX may be illustrated as being electrically connected to the gate line GL, but this may be exemplary, and the pixel PX may be electrically connected to two or more gate lines, and the gate driving circuit 13 may supply two or more gate signals to the gate lines corresponding to the two or more gate signals, and the on-voltages of the two or more gate signals may be applied at different timings.

[0062] The data driving circuit 15 may be electrically connected to the data line DL, and may supply a data signal to the data line DL according to a control signal DCS from the controller 19. The data signal supplied to the data line DL may be supplied to the pixel PX to which the gate signal has been supplied. The data driving circuit 15 may convert input image data having a grayscale input from the controller 19 into a data signal DATA in the form of a voltage or a current.

[0063] The power supply circuit 17 may generate a voltage required to drive the pixel PX in response to a control signal PCS from the controller 19. The power supply circuit 17 may generate a first driving voltage ELVDD and a second driving voltage ELVSS and supply them to the pixel PX. The first driving voltage ELVDD may be a high-level voltage that may be supplied to a terminal of a driving transistor electrically connected to a first electrode (i.e., a pixel electrode or an anode) of a display element included in the pixel PX. The second driving voltage ELVSS may be a low-level voltage that may be supplied to a second electrode (i.e., a counter electrode or a cathode) of a display element included in the pixel PX.

[0064] The controller 19 may generate control signals GCS, DCS, and PCS based on signals input from the outside, and may supply them to the gate driving circuit 13, the data driving circuit 15, and the power supply circuit 17, respectively. The control signal GCS output to the gate driving circuit 13 may include a plurality of clock signals and a gate start signal. The control signal DCS output to the data driving circuit 15 may include a data start signal and a clock signal.

[0065] The display device 10 may include a display panel, and the display panel may include a substrate. The pixel PX may be arranged in a display area DA of the substrate. During the process of forming transistors constituting a pixel circuit in the display area DA of the substrate, a portion or all of the gate drive circuit 13 may be formed (e.g., directly formed) in the peripheral area PA of the substrate. The data drive circuit 15, the power supply circuit 17, and the controller 19 may be formed as independent IC chips, respectively, or may be formed as a single IC chip, and may be arranged on a flexible printed circuit board (FPCB) electrically connected to a pad arranged on one side of the substrate. According to an embodiment, the data drive circuit 15, the power supply circuit 17, and the controller 19 may be arranged (e.g., directly arranged) on the substrate by using a chip on glass (COG) method or a chip on plastic (COP) method.

[0066] The display device 10 may support a variable refresh rate (VRR). The refresh rate may be the frequency at which a data signal may be actually written to the driving transistor of the pixel PX, and may also be referred to as a screen refresh rate or a screen reproduction rate, and may represent the number of image frames reproduced within one second. According to an embodiment, the refresh rate may be the output frequency of the gate drive circuit 13 and / or the data drive circuit 15. The frequency corresponding to the refresh rate may be the driving frequency. The display device 10 may adjust the output frequency of the gate drive circuit 13 and the output frequency of the data drive circuit 15 corresponding thereto according to the driving frequency.

[0067] The display device 10 supporting VRR can be operated by changing the driving frequency within the range of the maximum driving frequency to the minimum driving frequency. For example, in the case of a refresh rate of about 60 Hz, the gate signal for writing the data signal from the gate driving circuit 13 can be supplied to each horizontal line (row) 60 times per second. The display device 10 can display an image while changing the driving frequency according to the refresh rate.

[0068] According to the driving frequency, the frame 1F may include a first scanning period AS, or may include a first scanning period AS and one or more second scanning periods SS. Figure 3A As shown in FIG. 1 , in a display device 10 operating at a driving frequency of AHz, a frame 1F may include a first scanning period AS. Figure 3B As shown in , in a display device 10 operated at a driving frequency of BHz lower than a driving frequency of AHz, a frame 1F may include a first scanning period AS and one or more second scanning periods SS. As the driving frequency decreases, the time length of the frame 1F may increase. According to an embodiment, Figure 3A AHz in may be a driving frequency of about 240 Hz, and Figure 3B BHz in the example may be a driving frequency lower than about 240 Hz (eg, about 10 Hz).

[0069] The first scanning period AS may be defined as an address scanning period, during which a data signal may be written to the pixel PX, and the pixel PX may emit light at a brightness corresponding to the written data signal. The operation of writing a data signal from a data line DL to a pixel PX may also be referred to as a data programming operation. The second scanning period SS may be defined as a self-scanning period, during which no data signal may be written to the pixel PX. During the second scanning period SS, the data signal written during the first scanning period AS may be maintained, and the pixel PX may emit light at a brightness corresponding to the data signal written during the first scanning period AS. The length of the second scanning period SS may be equal to the length of the first scanning period AS.

[0070] Figure 4is a schematic diagram of a display device 10A according to the embodiment. Figure 5 yes Figure 4 Schematic diagram of the equivalent circuit of the pixel PX.

[0071] refer to Figure 4 The display device 10A may include a pixel region 11A, a gate driving circuit 13A, a data driving circuit 15A, a power supply circuit 17A, and a controller 19A. The display device 10A may support a variable refresh rate (VRR). The display device 10A may be Figure 2 The embodiment of the display device 10 shown in FIG. Figure 2 The configuration and description of the display device 10 shown in FIG. 1 are the same as the configuration and the same as the description.

[0072] The pixel region 11A may include a plurality of pixels PX. Each of the pixels PX may be electrically connected to a first gate line GWL transmitting a first gate signal GW, a second gate line GIL transmitting a second gate signal GI, a third gate line GCL transmitting a third gate signal GC, a fourth gate line EML transmitting a fourth gate signal EM, a fifth gate line GBL transmitting a fifth gate signal GB, and a data line DL transmitting a data signal DATA. Since the light emission of the pixel PX may be controlled by the fourth gate signal EM, the fourth gate signal EM may be referred to as an emission control signal, and the fourth gate line EML may be referred to as an emission control line.

[0073] The pixel PX may receive a first driving voltage ELVDD (or a first voltage), a second driving voltage ELVSS (or a second voltage), a reference voltage VREF (or a third voltage), a first initialization voltage VINT (or a fourth voltage), and a second initialization voltage AINT (or a fifth voltage). According to an embodiment, the pixel PX may receive a reference voltage VREF as Figure 5 The bias voltage Vbias.

[0074] The gate drive circuit 13A may be electrically connected to the first gate line GWL, the second gate line GIL, the third gate line GCL, the fourth gate line EML, and the fifth gate line GBL, and may sequentially supply the first gate signal GW, the second gate signal GI, the third gate signal GC, the fourth gate signal EM, and the fifth gate signal GB to the first gate line GWL, the second gate line GIL, the third gate line GCL, the fourth gate line EML, and the fifth gate line GBL, respectively. The gate drive circuit 13A may include first to fourth gate drive circuits. Each of the first to fourth gate drive circuits may include a plurality of stages.

[0075] The first gate driving circuit may be electrically connected to a plurality of first gate lines GWL, and may sequentially supply a first gate signal GW to the first gate lines GWL. The second gate driving circuit may be electrically connected to a plurality of second gate lines GIL and a plurality of third gate lines GCL, and sequentially supply a second gate signal GI to the second gate lines GIL, and sequentially supply a third gate signal GC to the third gate lines GCL. The third gate driving circuit may be electrically connected to a plurality of fourth gate lines EML, and may sequentially supply a fourth gate signal EM to the fourth gate line EML. The fourth gate driving circuit may be electrically connected to a plurality of fifth gate lines GBL, and may sequentially supply a fifth gate signal GB to the fifth gate line GBL.

[0076] According to an embodiment, the first gate signal GW, the second gate signal GI, the third gate signal GC, the fourth gate signal EM and the fifth gate signal GB may be supplied to the first gate line GWL, the second gate line GIL, the third gate line GCL, the fourth gate line EML and the fifth gate line GBL in each pixel row at each time (e.g., a predetermined time or an optional time). According to an embodiment, the first gate signal GW may be sequentially supplied to the first gate line GWL of each pixel row at each time (e.g., a predetermined time or an optional time), and the second gate signal GI, the third gate signal GC, the fourth gate signal EM and the fifth gate signal GB may be simultaneously supplied to the second gate line GIL, the third gate line GCL, the fourth gate line EML and the fifth gate line GBL in two pixel rows, respectively, and may be sequentially supplied in units of two pixel rows. For example, the third gate drive circuit may simultaneously supply the fourth gate signal EM to the fourth gate line EML of each pixel row in the two pixel rows, and may sequentially supply the fourth gate signal EM in units of two pixel rows.

[0077] The data driving circuit 15A may supply the data signal DATA to the plurality of data lines DL in response to the control signal DCS from the controller 19A.

[0078] According to an embodiment, an output frequency of the first gate driving circuit outputting the first gate signal GW and / or an output frequency of the data driving circuit 15A may be determined according to a driving frequency corresponding to a refresh rate.

[0079] The power supply circuit 17A may supply the first driving voltage ELVDD and the second driving voltage ELVSS to the pixels PX of the pixel area 11A. The power supply circuit 17A may generate a reference voltage VREF, a first initialization voltage VINT, and a second initialization voltage AINT, and supply them to the pixels PX.

[0080] The power supply circuit 17A may supply different reference voltages VREF to the pixel PX during the first scanning period AS and the second scanning period SS. According to an embodiment, the power supply circuit 17A may supply the first reference voltage VREF1 (see FIG. 14 ) during the first scanning period AS. Figure 8 ) is supplied to the pixel PX, and the second reference voltage VREF2 (see Figure 8 ) is supplied to the pixel PX.

[0081] The controller 19A may generate control signals GCS1 to GCS4, DCS, and PCS based on signals input from an external source, and may supply them to the gate driving circuit 13A, the data driving circuit 15A, and the power supply circuit 17A, respectively. The controller 19A may supply the control signals GCS1 to GCS4 to the first to fourth gate driving circuits of the gate driving circuit 13A, respectively.

[0082] refer to Figure 5 , the pixel PX may include a pixel circuit PC and an organic light emitting diode OLED as a display element electrically connected to the pixel circuit PC.

[0083] The pixel circuit PC of the pixel PX may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9, and signal lines electrically connected to the transistors. The signal lines may include a data line DL, a first gate line GWL, a second gate line GIL, a third gate line GCL, a fourth gate line EML, a fifth gate line GBL, a driving voltage line VDL, a reference voltage line VRL, a first initialization voltage line VIL1, and a second initialization voltage line VIL2.

[0084] The first transistor T1 can be a driving transistor in which the size of the source-drain current can be determined according to the gate-source voltage, and the second transistor T2 to the ninth transistor T9 can be a switching transistor that can be turned on / off according to the gate-source voltage (basically the gate voltage). The first transistor T1 to the ninth transistor T9 can be implemented as a thin film transistor. Depending on the type of transistor (p-type or n-type) and / or its operating conditions, the first terminal of each of the first transistor T1 to the ninth transistor T9 can be a source or a drain, and its second terminal can be a terminal different from the first terminal. For example, in the case where the first terminal can be a source, the second terminal can be a drain.

[0085] The first transistor T1 to the ninth transistor T9 may be P-type silicon thin film transistors. The gate-on voltage of the gate signal that turns on the first transistor T1 to the ninth transistor T9 may be a low-level voltage (second-level voltage), and the gate-off voltage of the gate signal that turns off the first transistor T1 to the ninth transistor T9 may be a high-level voltage (first-level voltage).

[0086] The first transistor T1 may be electrically connected between the driving voltage line VDL and the organic light emitting diode OLED. The first transistor T1 may be electrically connected to the driving voltage line VDL through the sixth transistor T6, and may be electrically connected to the organic light emitting diode OLED through the seventh transistor T7. The first transistor T1 may include a gate electrically connected to the first node N1, a first terminal electrically connected to the second node N2, and a second terminal electrically connected to the third node N3. The first transistor T1 may supply a driving current corresponding to the voltage applied to the first node N1 to the organic light emitting diode OLED according to a switching operation of the second transistor T2.

[0087] The second transistor T2 may be electrically connected between the data line DL and the fourth node N4. The second transistor T2 may include a gate electrically connected to the first gate line GWL, a first terminal electrically connected to the data line DL, and a second terminal electrically connected to the fourth node N4. The second transistor T2 may be turned on in response to the first gate signal GW received through the first gate line GWL, and thus transmit the data signal DATA received through the data line DL to the fourth node N4.

[0088] The third transistor T3 may be electrically connected between the first node N1 and the third node N3. The third transistor T3 may be electrically connected to the organic light emitting diode OLED via the seventh transistor T7. The third transistor T3 may include a gate electrically connected to the third gate line GCL, a first terminal electrically connected to the third node N3, and a second terminal electrically connected to the first node N1. The third transistor T3 may be turned on in response to the third gate signal GC received through the third gate line GCL, and thus the first transistor T1 may be diode-connected. In the case where the first transistor T1 is diode-connected, the threshold voltage of the first transistor T1 may be compensated.

[0089] The fourth transistor T4 may be electrically connected between the first node N1 and the first initialization voltage line VIL1. The fourth transistor T4 may include a gate electrically connected to the second gate line GIL, a first terminal electrically connected to the first node N1, and a second terminal electrically connected to the first initialization voltage line VIL1. The fourth transistor T4 may be turned on in response to a second gate signal GI received through the second gate line GIL, and thus transmit the first initialization voltage VINT to the first node N1 to thereby initialize the first node N1, i.e., the gate of the first transistor T1.

[0090] The fifth transistor T5 may be electrically connected between the fourth node N4 and the reference voltage line VRL. The fifth transistor T5 may include a gate electrically connected to the third gate line GCL, a first terminal electrically connected to the fourth node N4, and a second terminal electrically connected to the reference voltage line VRL. The gate of the fifth transistor T5 may be electrically connected to the gate of the third transistor T3. The fifth transistor T5 may be turned on in response to the third gate signal GC received through the third gate line GCL, and thus transmit the reference voltage VREF to the fourth node N4, so as to initialize the fourth node N4.

[0091] The sixth transistor T6 may be electrically connected between the driving voltage line VDL and the second node N2. The seventh transistor T7 may be electrically connected between the third node N3 and the organic light emitting diode OLED. The sixth transistor T6 may include a gate electrically connected to the fourth gate line EML, a first terminal electrically connected to the driving voltage line VDL, and a second terminal electrically connected to the second node N2. The seventh transistor T7 may include a gate electrically connected to the fourth gate line EML, a first terminal electrically connected to the third node N3, and a second terminal electrically connected to the pixel electrode of the organic light emitting diode OLED. In the case where the sixth transistor T6 and the seventh transistor T7 can be turned on at the same time according to the fourth gate signal EM received via the fourth gate line EML, the driving current may flow through the organic light emitting diode OLED.

[0092] The eighth transistor T8 may be electrically connected between the organic light emitting diode OLED and the second initialization voltage line VIL2. The eighth transistor T8 may include a gate electrically connected to the fifth gate line GBL, a second terminal electrically connected to the seventh transistor T7 and a pixel electrode of the organic light emitting diode OLED at a fifth node N5, and a second terminal electrically connected to the second initialization voltage line VIL2. The eighth transistor T8 may be turned on in response to a fifth gate signal GB received via the fifth gate line GBL, and thus transmit the second initialization voltage AINT to the pixel electrode of the organic light emitting diode OLED to thereby initialize the pixel electrode of the organic light emitting diode OLED.

[0093] The ninth transistor T9 may be electrically connected to the second node N2, and may supply the bias voltage Vbias to the first terminal of the first transistor T1. The ninth transistor T9 may include a gate electrically connected to the fifth gate line GBL, a first terminal receiving the bias voltage Vbias, and a second terminal electrically connected to the first terminal of the first transistor T1. The ninth transistor T9 may be turned on in response to the fifth gate signal GB received through the fifth gate line GBL, and thus transmit the bias voltage Vbias to the first terminal of the first transistor T1, so as to thereby control the gate-source voltage of the first transistor T1, thereby compensating for the change in the current characteristic of the first transistor T1. According to an embodiment, the first terminal of the ninth transistor T9 may be electrically connected to the reference voltage line VRL, and the bias voltage Vbias may be the reference voltage VREF.

[0094] The first capacitor C1 may be electrically connected between the driving voltage line VDL and the fourth node N4. The first capacitor C1 may store a voltage corresponding to a voltage difference between the driving voltage line VDL and the fourth node N4.

[0095] The second capacitor C2 may be electrically connected between the first node N1 and the fourth node N4. The second capacitor C2 may store a voltage corresponding to a voltage difference between the first node N1 and the fourth node N4. The first capacitor C1 and the second capacitor C2 may store and hold a data signal DATA written through the second transistor T2.

[0096] The organic light emitting diode OLED may include a pixel electrode (e.g., an anode) and a counter electrode (e.g., a cathode) facing the pixel electrode, and the counter electrode may receive a second driving voltage ELVSS. The organic light emitting diode OLED may receive a driving current corresponding to a data signal DATA from the first transistor T1 and emit light in a specific color to display an image.

[0097] According to an embodiment, a plurality of transistors included in the pixel circuit may be P-type transistors. According to an embodiment, a plurality of transistors included in the pixel circuit may be N-type transistors, or some transistors may be N-type transistors and other transistors may be P-type transistors.

[0098] The transistor according to the embodiment may be an amorphous silicon thin film transistor (amorphous silicon TFT), a low temperature polycrystalline silicon (LTPS) TFT or an oxide TFT. The oxide TFT may include an oxide such as amorphous indium gallium zinc oxide (IGZO), zinc oxide (ZnO) or titanium oxide (TiO) as a semiconductor layer (active layer).

[0099] Figure 6 and Figure 7 is a timing chart for explaining the operation of a pixel according to an embodiment. Figure 6is supplied to the Figure 4 A timing diagram of signals of the pixel PX. Figure 7 is supplied to the Figure 4 A timing diagram of signals of the pixel PX. Figure 8 is a timing diagram showing a bias voltage supplied to the pixel PX during the first scanning period AS and the second scanning period SS.

[0100] During the first scanning period AS and the second scanning period SS, the gate driving circuit 13A may supply the first gate signal GW, the second gate signal GI, the third gate signal GC, the fourth gate signal EM and the fifth gate signal GB to the first gate line GWL, the second gate line GIL, the third gate line GCL, the fourth gate line EML and the fifth gate line GBL, respectively. The start time and the end time of the gate-on voltage maintenance period (gate-on voltage duration) and the gate-off voltage maintenance period (gate-off voltage duration) of the first gate signal GW, the second gate signal GI, the third gate signal GC, the fourth gate signal EM and the fifth gate signal GB may be the same or different, and some signals may overlap with each other during some periods.

[0101] During the first scan period AS and the second scan period SS, the power circuit 17A may supply the first driving voltage ELVDD to the driving voltage line VDL, the reference voltage VREF to the reference voltage line VRL, the first initialization voltage VINT to the first initialization voltage line VIL1 , and the second initialization voltage AINT to the second initialization voltage line VIL2 .

[0102] The reference voltage VREF supplied by the power supply circuit 17A during the first scan period AS may be different from the reference voltage VREF supplied during the second scan period SS. The power supply circuit 17A may supply the first reference voltage VREF1 to the reference voltage line VRL during the first scan period AS, and may supply the second reference voltage VREF2 to the reference voltage line VRL during the second scan period SS. The second reference voltage VREF2 may have a voltage level higher than that of the first reference voltage VREF1. For example, the first reference voltage VREF1 may be 4.6V, and the second reference voltage VREF2 may be 5V to 7V, but the embodiment may not be limited thereto.

[0103] According to an embodiment, the bias voltage Vbias may be a reference voltage VREF, and the terms “reference voltage VREF” and “bias voltage Vbias” may be used interchangeably. For example, the first terminal of the ninth transistor T9 may be electrically connected to the reference voltage line VRL, and Figure 8As shown in FIG. 1 , the first reference voltage VREF1 may be received from the reference voltage line VRL during the first scan period AS, and the second reference voltage VREF2 may be received from the reference voltage line VRL during the second scan period SS.

[0104] refer to Figure 6 , the first scanning period AS may include a period in which a data signal corresponding to an image is written. The first scanning period AS may include a period in which the fourth gate signal EM may be a gate-off voltage and a period in which the fourth gate signal EM may be a gate-on voltage. The period in which the fourth gate signal EM may be a gate-off voltage may be a non-emission period, and the period in which the fourth gate signal EM may be a gate-on voltage may be an emission period. The non-emission period may include at least one initialization period and at least one compensation period. The first scanning period AS may include a first period P1, a second period P2, a third period P3, a fourth period P4, a fifth period P5, and a sixth period P6.

[0105] The first period P1 and the third period P3 may be initialization periods for initializing the first node N1 , and the gate of the first transistor T1 may be electrically connected to the first node N1 .

[0106] During the first period P1 and the third period P3, the second gate signal GI of the gate-on voltage (second level voltage) may be supplied to the second gate line GIL. The first gate signal GW, the third gate signal GC, the fourth gate signal EM, and the fifth gate signal GB, each having a gate-off voltage (first level voltage), may be supplied to the first gate line GWL, the third gate line GCL, the fourth gate line EML, and the fifth gate line GBL, respectively. The fourth transistor T4 may be turned on by the second gate signal GI, and the gate of the first transistor T1 may be initialized with the first initialization voltage VINT.

[0107] The second period P2 and the fourth period P4 may be compensation periods for compensating for the threshold voltage of the first transistor T1 .

[0108] During the second period P2 and the fourth period P4, the third gate signal GC of the gate-on voltage may be supplied to the third gate line GCL, and the fifth gate signal GB of the gate-on voltage may be supplied to the fifth gate line GBL. The first gate signal GW, the second gate signal GI, and the fourth gate signal EM, each having a gate-off voltage, may be supplied to the first gate line GWL, the second gate line GIL, and the fourth gate line EML, respectively. The third transistor T3 and the fifth transistor T5 may be turned on by the third gate signal GC, and the eighth transistor T8 and the ninth transistor T9 may be turned on by the fifth gate signal GB.

[0109] The first reference voltage VREF1 may be supplied to the second node N2 as a bias voltage Vbias through the turned-on ninth transistor T9, and the first reference voltage VREF1 may also be supplied to the fourth node N4 through the turned-on fifth transistor T5. The difference (VREF1-Vth) between the first reference voltage VREF1 and the threshold voltage (Vth) of the first transistor T1 may be supplied to the gate of the first transistor T1 in a diode connection state through the turned-on third transistor T3. The second capacitor C2 may be charged with a voltage corresponding to the threshold voltage (Vth) of the first transistor T1. In other words, the pixel PX may compensate for the threshold voltage of the first transistor T1 by using the first reference voltage VREF1 of a constant voltage.

[0110] The pixel electrode of the organic light emitting diode OLED may be initialized with the second initialization voltage AINT through the turned-on eighth transistor T8. Therefore, the second period P2 and the fourth period P4 may be periods for initializing the pixel electrode of the organic light emitting diode OLED.

[0111] Since the initialization and the threshold voltage compensation can be repeated alternately during the first period P1 to the fourth period P4, the conduction bias voltage can be applied to the first transistor T1 multiple times (for example, a predetermined number of times or a selectable number of times) to shift the threshold voltage of the first transistor T1 in a specific direction, thereby compensating for hysteresis. The conduction bias voltage can be a voltage difference between the gate and the source (first terminal) of the first transistor T1 that turns on the first transistor T1. Initialization and threshold voltage compensation can be repeated alternately multiple times. Figure 6 The figure shows an example in which initialization and threshold voltage compensation may be repeated twice alternately. According to an embodiment, initialization and threshold voltage compensation may each occur once.

[0112] The fifth period P5 may be a writing period (data programming period) during which a data signal may be applied to the pixel PX. During the fifth period P5, a voltage corresponding to the data signal may be stored in the gate of the driving transistor (ie, the first transistor T1).

[0113] During the fifth period P5, the first gate signal GW of the gate-on voltage may be supplied to the first gate line GWL. The second, third, fourth, and fifth gate signals GI, GC, EM, and GB, each having a gate-off voltage, may be supplied to the second, third, fourth, and fifth gate lines GIL, GCL, EML, and GBL, respectively.

[0114] The second transistor T2 may be turned on by the first gate signal GW. The turned-on second transistor T2 may transmit the data signal DATA received from the data line DL to the fourth node N4. Accordingly, the voltage of the fourth node N4 may change a voltage corresponding to the difference between the first reference voltage VREF1 and the data signal DATA, and the voltage of the first node N1 may change corresponding to the voltage change of the fourth node P4. Therefore, the second capacitor C2 may be charged with a data voltage corresponding to the threshold voltage (Vth) of the first transistor T1 and the data signal DATA.

[0115] The sixth period P6 may be an emission period in which the organic light emitting diode OLED emits light.

[0116] During the sixth period P6, the fourth gate signal EM of the gate-on voltage may be supplied to the fourth gate line EML. The first gate signal GW, the second gate signal GI, the third gate signal GC, and the fifth gate signal GB, each having a gate-off voltage, may be supplied to the first gate line GWL, the second gate line GIL, the third gate line GCL, and the fifth gate line GBL, respectively. The sixth transistor T6 and the seventh transistor T7 may be turned on by the fourth gate signal EM.

[0117] A current path from the driving voltage line VDL to the organic light emitting diode OLED may be formed by the turned-on sixth transistor T6 and the turned-on seventh transistor T7. The first transistor T1 may output a driving current having a magnitude corresponding to the data voltage stored in the second capacitor C2, and the organic light emitting diode OLED may emit light at a brightness corresponding to the magnitude of the driving current, which may be independent of the threshold voltage (Vth) of the first transistor T1.

[0118] refer to Figure 7 , the second scanning period SS may include a period in which the fourth gate signal EM may be a gate-off voltage and a period in which the fourth gate signal EM may be a gate-on voltage. The period in which the fourth gate signal EM may be a gate-off voltage may be a non-emission period, and the period in which the fourth gate signal EM may be a gate-on voltage may be an emission period. In order to maintain the brightness of the image output in the first scanning period AS, the second scanning period SS may include a period in which the bias voltage Vbias may be supplied to the first terminal of the first transistor T1 during the non-emission period. The second scanning period SS may include a seventh period P7 and an eighth period P8.

[0119] The seventh period P7 may be a compensation period in which the voltage-current characteristic of the first transistor T1 may be compensated. During the seventh period P7, the fifth gate signal GB of the gate-on voltage may be supplied to the fifth gate line GBL. The first gate signal GW, the second gate signal GI, the third gate signal GC, and the fourth gate signal EM, each having a gate-off voltage, may be supplied to the first gate line GWL, the second gate line GIL, the third gate line GCL, and the fourth gate line EML, respectively. The eighth transistor T8 and the ninth transistor T9 may be turned on by the fifth gate signal GB.

[0120] The second reference voltage VREF2 can be supplied as a bias voltage Vbias to the first terminal of the first transistor T1 through the turned-on ninth transistor T9, so that the gate-source voltage (Vgs) of the first transistor T1 can be controlled, and thus, the change in the voltage-current characteristic of the first transistor T1 caused by the stress applied to the first transistor T1 during the first scanning period AS can be compensated. Accordingly, the pixel PX can maintain the brightness of the image output in the first scanning period AS in the subsequent eighth period P8.

[0121] The pixel electrode of the organic light emitting diode OLED may be initialized with the second initialization voltage AINT through the turned-on eighth transistor T8. Therefore, the seventh period P7 may be a period for initializing the pixel electrode of the organic light emitting diode OLED.

[0122] The eighth period P8 may be an emission period in which the organic light emitting diode OLED emits light.

[0123] During the eighth period P8, the fourth gate signal EM of the gate-on voltage may be supplied to the fourth gate line EML. The first gate signal GW, the second gate signal GI, the third gate signal GC, and the fifth gate signal GB, each having a gate-off voltage, may be supplied to the first gate line GWL, the second gate line GIL, the third gate line GCL, and the fifth gate line GBL, respectively. The sixth transistor T6 and the seventh transistor T7 may be turned on by the fourth gate signal EM.

[0124] A current path from the driving voltage line VDL to the organic light emitting diode OLED may be formed by the turned-on sixth transistor T6 and the turned-on seventh transistor T7. The first transistor T1 may output a driving current having a magnitude corresponding to the data voltage stored in the second capacitor C2, and the organic light emitting diode OLED may emit light at a brightness corresponding to the magnitude of the driving current.

[0125] like Figure 6 and Figure 8As shown in , during the first scan period AS, the fifth gate signal GB may be supplied to the pixel PX simultaneously with the third gate signal GC, so that the first reference voltage VREF1 as the bias voltage Vbias may be supplied to the first terminal of the first transistor T1.

[0126] like Figure 7 and Figure 8 As shown in , during the second scan period SS, the fifth gate signal GB may be supplied to the pixel PX before the eighth period P8 so that the second reference voltage VREF2 as the bias voltage Vbias may be supplied to the first terminal of the first transistor T1.

[0127] The signal being supplied may refer to the gate-on voltage of the signal being supplied, and the signal not being supplied may refer to the gate-off voltage of the signal being supplied.

[0128] Fig. 9 is a schematic cross-sectional view of a structure of a display element according to an embodiment. FIG. 10A to FIG. 11B is a schematic cross-sectional view of a structure of a display element according to an embodiment.

[0129] refer to Fig. 9 The organic light emitting diode OLED as a display element according to the embodiment may include a pixel electrode 211 , an opposing electrode 215 , and an intermediate layer 213 between the pixel electrode 211 (first electrode or anode) and the opposing electrode 215 (second electrode or cathode).

[0130] The pixel electrode 211 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). The pixel electrode 211 may include a reflective layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound of these materials. For example, the pixel electrode 211 may have a multilayer structure of ITO / Ag / ITO.

[0131] The counter electrode 215 may be disposed on the intermediate layer 213. The counter electrode 215 may include a metal, an alloy, a conductive compound, or any combination thereof, each having a low work function. For example, the counter electrode 215 may include lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al), aluminum lithium (Al-Li), calcium (Ca), magnesium indium (Mg-In), magnesium silver (Mg-Ag), ytterbium (Yb), silver ytterbium (Ag-Yb), ITO, IZO, or any combination thereof. The counter electrode 215 may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode.

[0132] The intermediate layer 213 may include a low molecular organic material or a high molecular organic material that emits light of a specific color. In addition to various organic materials, the intermediate layer 213 may further include a metal-containing compound such as an organic metal compound and an inorganic material such as a quantum dot.

[0133] According to an embodiment, the intermediate layer 213 may include an emission layer and a first functional layer and a second functional layer respectively located below and above the emission layer. The first functional layer may include a hole transport layer, or may include a hole transport layer and a hole injection layer. The second functional layer may include an electron transport layer and / or an electron injection layer. The first functional layer or the second functional layer may be omitted. Each of the first functional layer and the second functional layer may be integrally formed to correspond to a plurality of organic light emitting diodes OLED included in the display area DA.

[0134] According to an embodiment, the intermediate layer 213 may include two or more emission portions sequentially stacked with each other between the pixel electrode 211 and the counter electrode 215 and a charge generation layer CGL disposed between the two emission portions. In the case where the intermediate layer 213 includes the emission portion and the charge generation layer, the organic light emitting diode OLED may be a tandem light emitting diode. The organic light emitting diode OLED may improve color purity and light emission efficiency by having a stacked structure of a plurality of emission portions.

[0135] The emission portion may include an emission layer and a first functional layer and a second functional layer located below and above the emission layer, respectively. The charge generation layer CGL may include a negative charge generation layer and a positive charge generation layer. The luminous efficiency of the organic light emitting diode OLED, which may be a tandem light emitting device including a plurality of emission layers, may be further improved by the negative charge generation layer and the positive charge generation layer.

[0136] The negative charge generation layer may be an n-type charge generation layer. The negative charge generation layer may supply electrons. The negative charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material. The positive charge generation layer may be a p-type charge generation layer. The positive charge generation layer may supply holes. The positive charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material.

[0137] According to an embodiment, Fig. 10AAs shown in , the organic light emitting diode OLED may include a first emission part EU1 including a first emission layer EML1 and a second emission part EU2 including a second emission layer EML2, which are sequentially stacked on each other. The charge generation layer CGL may be disposed between the first emission part EU1 and the second emission part EU2. For example, the organic light emitting diode OLED may include a pixel electrode 211, a first emission layer EML1, a charge generation layer CGL, a second emission layer EML2, and a counter electrode 215, which are sequentially stacked on each other. The first functional layer and the second functional layer may be provided below and above the first emission layer EML1, respectively. The first functional layer and the second functional layer may be provided below and above the second emission layer EML2, respectively. The first emission layer EML1 may be a blue emission layer, and the second emission layer EML2 may be a yellow emission layer.

[0138] According to an embodiment, Fig. 10B As shown in , the organic light emitting diode OLED may include a first emission part EU1 and a third emission part EU3 each including a first emission layer EML1, and a second emission part EU2 including a second emission layer EML2. A first charge generation layer CGL1 may be provided between the first emission part EU1 and the second emission part EU2, and a second charge generation layer CGL2 may be provided between the second emission part EU2 and the third emission part EU3. For example, the organic light emitting diode OLED may include a pixel electrode 211, a first emission layer EML1, a first charge generation layer CGL1, a second emission layer EML2, a second charge generation layer CGL2, a first emission layer EML1, and a counter electrode 215 sequentially stacked on each other. The first functional layer and the second functional layer may be provided below and above the first emission layer EML1, respectively. The first functional layer and the second functional layer may be provided below and above the second emission layer EML2, respectively. The first emission layer EML1 may be a blue emission layer, and the second emission layer EML2 may be a yellow emission layer.

[0139] According to an embodiment, in the organic light emitting diode OLED, in addition to the second emission layer EML2, the second emission portion EU2 may further include a third emission layer EML3 and / or a fourth emission layer EML4 disposed below and / or above the second emission layer EML2 and in direct contact with the second emission layer EML2. Direct contact may mean that no other layer is disposed between the second emission layer EML2 and the third emission layer EML3 and / or between the second emission layer EML2 and the fourth emission layer EML4. The third emission layer EML3 may be a red emission layer, and the fourth emission layer EML4 may be a green emission layer.

[0140] For example, Fig. 10CAs shown in , the organic light emitting diode OLED may include a pixel electrode 211, a first emission layer EML1, a first charge generation layer CGL1, a third emission layer EML3, a second emission layer EML2, a second charge generation layer CGL2, a first emission layer EML1, and a counter electrode 215 sequentially stacked one on another. Fig. 10D As shown in the figure, the organic light emitting diode OLED may include a pixel electrode 211, a first emission layer EML1, a first charge generation layer CGL1, a third emission layer EML3, a second emission layer EML2, a fourth emission layer EML4, a second charge generation layer CGL2, a first emission layer EML1 and a counter electrode 215 stacked sequentially on each other.

[0141] Fig.11A It is shown Fig. 10C A schematic cross-sectional view of an example of an organic light emitting diode OLED, and Fig. 11B It is shown Fig. 10D Schematic cross-sectional view of an example of an organic light emitting diode OLED.

[0142] refer to Fig.11A , the organic light emitting diode OLED may include a first emission part EU1, a second emission part EU2, and a third emission part EU3 sequentially stacked on each other. A first charge generation layer CGL1 may be provided between the first emission part EU1 and the second emission part EU2, and a second charge generation layer CGL2 may be provided between the second emission part EU2 and the third emission part EU3. Each of the first charge generation layer CGL1 and the second charge generation layer CGL2 may include a negative charge generation layer nCGL and a positive charge generation layer pCGL.

[0143] The first emission part EU1 may include a blue emission layer BEML. The first emission part EU1 may further include a hole injection layer HIL and a hole transport layer HTL located between the pixel electrode 211 and the blue emission layer BEML. According to an embodiment, a p-doped layer may be included between the hole injection layer HIL and the hole transport layer HTL. The p-doped layer may be formed by doping the hole injection layer HIL with a p-type doping material. According to an embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may be included between the blue emission layer BEML and the hole transport layer HTL. The blue light auxiliary layer may improve the luminous efficiency of the blue emission layer BEML. The blue light auxiliary layer may improve the luminous efficiency of the blue emission layer BEML by adjusting the hole charge balance. The electron blocking layer may prevent electrons from being injected into the hole transport layer HTL. The buffer layer may compensate for the resonance distance according to the wavelength of light emitted by the emission layer.

[0144] The second emission portion EU2 may include a yellow emission layer YEML and a red emission layer REML contacting (e.g., directly contacting) the yellow emission layer YEML below the yellow emission layer YEML. The second emission portion EU2 may further include a hole transport layer HTL located between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red emission layer REML, and may further include an electron transport layer ETL located between the yellow emission layer YEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0145] The third emission portion EU3 may include a blue emission layer BEML. The third emission portion EU3 may further include a hole transport layer HTL located between the positive charge generation layer pCGL of the second charge generation layer CGL2 and the blue emission layer BEML. The third emission portion EU3 may further include an electron transport layer ETL and an electron injection layer EIL located between the blue emission layer BEML and the counter electrode 215. The electron transport layer ETL may be a single layer or a multilayer. According to an embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may be included between the blue emission layer BEML and the hole transport layer HTL. At least one of a hole blocking layer and a buffer layer may be included between the blue emission layer BEML and the electron transport layer ETL. The hole blocking layer may prevent holes from being injected into the electron transport layer ETL.

[0146] In addition to the stacked structure of the second emission part EU2, Fig. 11B The organic light emitting diode OLED shown in FIG. Fig.11A The organic light emitting diode OLED shown in FIG. Fig. 11B , the second emission portion EU2 may include a yellow emission layer YEML, a red emission layer REML contacting (e.g., directly contacting) the yellow emission layer YEML below the yellow emission layer YEML, and a green emission layer GEML contacting (e.g., directly contacting) the yellow emission layer YEML above the yellow emission layer YEML. The second emission portion EU2 may further include a hole transport layer HTL located between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red emission layer REML, and may further include an electron transport layer ETL located between the green emission layer GEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0147] Fig.12 is a schematic cross-sectional view of a structure of a pixel of a display device according to an embodiment.

[0148] refer to Fig.12, the display device may include a plurality of pixels. The plurality of pixels may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a pixel electrode 211, a counter electrode 215, and an intermediate layer 213. According to an embodiment, the first pixel PX1 may be a red pixel, the second pixel PX2 may be a green pixel, and the third pixel PX3 may be a blue pixel. Each pixel may include an organic light emitting diode OLED as a display element, and the organic light emitting diode LED of each pixel may be electrically connected to the pixel circuit.

[0149] The pixel electrode 211 may be independently included in the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 .

[0150] The intermediate layer 213 of the organic light emitting diode OLED of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a first emission part EU1 and a second emission part EU2 sequentially stacked on each other and a charge generation layer CGL located between the first emission part EU1 and the second emission part EU2. The charge generation layer CGL may include a negative charge generation layer nCGL and a positive charge generation layer pCGL. The charge generation layer CGL may be a common layer continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0151] The first emission part EU1 of the first pixel PX1 may include a hole injection layer HIL, a hole transport layer HTL, a red emission layer REML, and an electron transport layer ETL sequentially stacked on one another on the pixel electrode 211. The first emission part EU1 of the second pixel PX2 may include a hole injection layer HIL, a hole transport layer HTL, a green emission layer GEML, and an electron transport layer ETL sequentially stacked on one another on the pixel electrode 211. The first emission part EU1 of the third pixel PX3 may include a hole injection layer HIL, a hole transport layer HTL, a blue emission layer BEML, and an electron transport layer ETL sequentially stacked on one another on the pixel electrode 211. Each of the hole injection layer HIL, the hole transport layer HTL, and the electron transport layer ETL of the first emission part EU1 may be a common layer continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0152] The second emission part EU2 of the first pixel PX1 may include a hole transport layer HTL, an auxiliary layer AXL, a red emission layer REML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. The second emission part EU2 of the second pixel PX2 may include a hole transport layer HTL, a green emission layer GEML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. The second emission part EU2 of the third pixel PX3 may include a hole transport layer HTL, a blue emission layer BEML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. Each of the hole transport layer HTL and the electron transport layer ETL of the second emission part EU2 may be a common layer continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3. According to an embodiment, at least one of a hole blocking layer and a buffer layer may be included between the emission layer and the electron transport layer ETL in the second emission part EU2 of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0153] The thickness H1 of the red emission layer REML, the thickness H2 of the green emission layer GEML, and the thickness H3 of the blue emission layer BEML may be determined according to the resonance distance. The auxiliary layer AXL may be a layer added to adjust the resonance distance and may include a resonance auxiliary material. For example, the auxiliary layer AXL and the hole transport layer HTL may include the same material.

[0154] exist Fig.12 , only the first pixel PX1 includes the auxiliary layer AXL. However, the embodiment may not be limited thereto. For example, the auxiliary layer AXL may be included in at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3 to adjust the resonance distance of at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0155] The display device may further include a capping layer 217 disposed outside the counter electrode 215. According to the principle of constructive interference, the capping layer 217 may be used to improve the luminous efficiency. Accordingly, the light extraction efficiency of the organic light emitting diode OLED may be improved, and thus, the luminous efficiency of the organic light emitting diode OLED may be improved.

[0156] According to the embodiment, a display device capable of improving display quality may be provided.Of course, the scope of the present disclosure may not be limited thereto.

[0157] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. The description of each feature or aspect within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the claims.

Claims

1. A pixel comprising: Light emitting device; a first transistor electrically connected between a first voltage line and the light emitting device and configured to control a current supplied to the light emitting device; a second transistor electrically connected between a first node electrically connected to the gate of the first transistor and a second node electrically connected to the first terminal of the first transistor; a third transistor electrically connected between the first voltage line and a third node electrically connected to the second terminal of the first transistor; a fourth transistor electrically connected between the second node and the light emitting device; as well as a fifth transistor configured to supply a bias voltage to the third node, During at least a portion of a period in which a second-level gate-off voltage is supplied to the gate of the third transistor and the gate of the fourth transistor, a first-level gate-on voltage is supplied to the gate of the fifth transistor.

2. The pixel according to claim 1, wherein: The gate-on voltage is supplied to the gate of the second transistor at the same time as the gate-on voltage is supplied to the gate of the fifth transistor.

3. The pixel according to claim 1, wherein: The frame consists of: a first scanning period during which a data signal is supplied and light is emitted at a brightness corresponding to the data signal; and a second scanning period during which the data signal supplied during the first scanning period is maintained and light is emitted at the brightness corresponding to the data signal, and The fifth transistor supplies a first bias voltage to the third node when the gate-on voltage is supplied to the gate of the fifth transistor during the first scan period, and supplies a second bias voltage to the third node when the gate-on voltage is supplied to the gate of the fifth transistor during the second scan period.

4. The pixel according to claim 3, wherein: The second bias voltage is higher than the first bias voltage.

5. The pixel according to claim 3, wherein: The first scanning period includes a first period during which the gate-on voltage is supplied to each of the gate of the second transistor and the gate of the fifth transistor during the period in which the gate-off voltage of the second level is supplied to the gate of the third transistor and the gate of the fourth transistor, and The second scanning period includes a second period during which, within the period in which the gate-off voltage of the second level is supplied to the gate of the third transistor and the gate of the fourth transistor, the gate-off voltage is supplied to the gate of the second transistor and the gate-on voltage is supplied to the gate of the fifth transistor.

6. The pixel according to claim 5, wherein: The gate of the third transistor and the gate of the fourth transistor are electrically connected to a first gate line, and The gate of the fifth transistor is electrically connected to a second gate line.

7. The pixel according to claim 6, further comprising: a sixth transistor electrically connected between the pixel electrode of the light emitting device and the second voltage line, and Wherein, the gate of the sixth transistor is electrically connected to the second gate line.

8. The pixel according to claim 7, further comprising: a first capacitor electrically connected between the first voltage line and a fourth node; a second capacitor electrically connected between the fourth node and the first node; a seventh transistor electrically connected between the data line and the fourth node; an eighth transistor electrically connected between the fourth node and the third voltage line; as well as A ninth transistor is electrically connected between the first node and a fourth voltage line.

9. The pixel according to claim 8, wherein: The fifth transistor is electrically connected between the third node and the third voltage line.

10. The pixel according to claim 9, wherein: The gate of the seventh transistor is electrically connected to the third gate line, The gate of the second transistor and the gate of the eighth transistor are electrically connected to a fourth gate line, and A gate of the ninth transistor is electrically connected to a fifth gate line.

11. A display device comprising a plurality of pixels, wherein: Each of the plurality of pixels comprises: Light emitting device; a first transistor electrically connected between a first voltage line and the light emitting device and configured to control a current supplied to the light emitting device; a second transistor electrically connected between a first node electrically connected to the gate of the first transistor and a second node electrically connected to the first terminal of the first transistor; a third transistor electrically connected between the first voltage line and a third node electrically connected to the second terminal of the first transistor; a fourth transistor electrically connected between the second node and the light emitting device; and a fifth transistor configured to supply a bias voltage to the third node, A gate of the third transistor and a gate of the fourth transistor are electrically connected to a first gate line supplying a first gate signal, and A gate of the fifth transistor is electrically connected to a second gate line supplying a second gate signal.

12. The display device according to claim 11, wherein: Each of the plurality of pixels further comprises: a first capacitor electrically connected between the first voltage line and a fourth node; a second capacitor electrically connected between the fourth node and the first node; a sixth transistor electrically connected between the data line and the fourth node; a seventh transistor electrically connected between the fourth node and the second voltage line; an eighth transistor electrically connected between the first node and a third voltage line; and A ninth transistor is electrically connected between the pixel electrode of the light emitting device and the fourth voltage line.

13. The display device according to claim 12, wherein: The fifth transistor is electrically connected between the third node and the second voltage line.

14. The display device according to claim 13, wherein: The gate of the ninth transistor is electrically connected to the second gate line, The gate of the second transistor and the gate of the seventh transistor are electrically connected to a third gate line supplying a third gate signal, The gate of the sixth transistor is electrically connected to a fourth gate line supplying a fourth gate signal, and A gate of the eighth transistor is electrically connected to a fifth gate line supplying a fifth gate signal.

15. The display device according to claim 14, wherein: A frame includes a first scanning period during which a data signal is received and light is emitted at a brightness corresponding to the data signal, and A first bias voltage is supplied to the second voltage line during the first scan period.

16. The display device according to claim 15, wherein: The frame further includes at least one second scanning period after the first scanning period, wherein during the at least one second scanning period, the data signal supplied during the first scanning period is maintained and light is emitted at the brightness corresponding to the data signal, and A second bias voltage is supplied to the second voltage line during the second scan period.

17. The display device according to claim 16, wherein: The second bias voltage is higher than the first bias voltage.

18. The display device according to claim 16, wherein: The display device further includes a gate driving circuit configured to supply a plurality of gate signals to the plurality of pixels, The first scanning period and the second scanning period include a non-transmission period and a transmission period, respectively, and The gate driving circuit: supplying the first gate signal of a gate-off voltage to the first gate line during the non-emission period of each of the first scanning period and the second scanning period, During a first period of the non-emission period of the first scanning period, the second gate signal of the gate-on voltage is supplied to the second gate line and the third gate signal of the gate-on voltage is supplied to the third gate line, and During a second period of the non-emission period of the second scanning period, the second gate signal of the gate-on voltage is supplied to the second gate line and the third gate signal of the gate-off voltage is supplied to the third gate line.

19. The display device according to claim 18, wherein: The gate driving circuit supplies the fourth gate signal of the gate-on voltage to the fourth gate line during a writing period between the first period of the first scanning period and the emission period of the first scanning period.

20. The display device according to claim 18, wherein: The gate driving circuit supplies the fifth gate signal of the gate-on voltage to the fifth gate line before the first period of the non-emission period of the first scanning period.

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