Gate driver and display device including the same

Abstract

The invention discloses a gate driver and a display device including the same. The gate driver includes a plurality of signal transmitters that are connected in correlation via carry lines through which carry signals are applied from a previous signal transmitter, where each of the plurality of signal transmitters includes: a first circuit portion that is configured to receive the carry signals from the previous signal transmitter, and a second circuit portion that is configured to receive the carry signals from the previous signal transmitter; the first signal transmitter is configured to receive a carry signal from the previous signal transmitter and charge or discharge the first control node and the second control node; a second circuit section configured to output a strobe signal based on voltages at the first control node and the second control node; and a selection section configured to reverse a voltage applied to the first node during a frame skip interval of a partial region in the pixel array driven at a predetermined frame frequency, and charge the first control node with the voltage of the first node.

Description

Technical Field

[0001] The present disclosure relates to a gate driver and a display device, and more particularly, for example but not limited to, to a gate driver that drives each region at a different frequency and a display device including the gate driver. Background Art

[0002] Electroluminescent display devices are classified into inorganic light-emitting display devices and organic light-emitting display devices according to the material of the light-emitting layer. Active matrix organic light-emitting display devices include organic light-emitting diodes (hereinafter referred to as "OLED") that emit light by themselves, and have the advantages of fast response speed, high luminous efficiency, high brightness and wide viewing angle.

[0003] In an organic light emitting display device, an organic light emitting diode (called "OLED") is formed in each pixel. These organic light display devices not only respond quickly and have excellent luminous efficiency, brightness and viewing angle, but also have excellent contrast and color reproduction rate because they can express black tones as full black.

[0004] A user can play two or more content images on one screen of a display device, or can run two or more applications to play images of different applications on the screen. In this multitasking environment, the pixels of the display device are driven at a single frame frequency.

[0005] A typical gate driver of a display device sequentially outputs gate signals.

[0006] The description provided in the description of the background technology section should not be assumed to be prior art simply because it is mentioned in the description of the background technology section or is associated with the description of the background technology section. The description of the background technology section may include information describing one or more aspects of the subject technology, and the description in this part does not limit the present invention. Summary of the invention

[0007] The inventors have recognized that in the related art, since the gate driver does not have a separate structure capable of blocking the output in the middle of a frame, it is impossible to drive at different frequencies for each area within the panel. Therefore, the present disclosure is intended to solve all the above problems.

[0008] The present disclosure provides a gate driver capable of driving at different frequencies for each area and a display device including the same.

[0009] It should be noted that the objects of the present disclosure are not limited to the above objects, and other objects of the present disclosure will be apparent to those skilled in the art from the following description.

[0010] A gating driver according to an example embodiment of the present disclosure may include: a plurality of signal transmitters connected in relation to each other via a carry line, through which a carry signal is applied from a previous signal transmitter, wherein an nth (n is a positive integer) signal transmitter includes: a first circuit portion configured to receive a carry signal from the previous signal transmitter and to charge or discharge a first control node and a second control node; a second circuit portion configured to output a gating signal based on voltages at the first control node and the second control node; and a selection portion configured to invert a voltage applied to the first node during a frame skip interval of a partial area in a pixel array driven at a predetermined frame frequency, and to charge the first control node using the voltage of the first node.

[0011] A display device according to an example embodiment of the present disclosure may include: a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits are provided; a data driver configured to output data voltages to the plurality of data lines; and a gate driver configured to output gate signals to the plurality of gate lines, wherein the pixel array includes a first pixel array driven at a first frame frequency and a second pixel array driven at a second frame frequency lower than the first frame frequency, and the gate driver outputs the gate signal as a gate-off voltage during a frame skip interval of the second pixel array.

[0012] According to the present disclosure, frame skipping may be achieved by blocking the output of a strobe signal according to regions, so that each region may be driven at a different frequency.

[0013] According to the present disclosure, the positions for dividing the areas so as to drive them at different frequencies can be easily changed by changing the intervals for blocking the output of the gate signal.

[0014] According to the present disclosure, the position for dividing the frequency can be freely adjusted according to the user's working environment, so that power consumption can be reduced and low-power driving can be achieved.

[0015] The effects of the present specification are not limited to the above-mentioned effects, and other effects not mentioned will be apparently understood by those skilled in the art from the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0017] Figure 1 is a block diagram illustrating a display device according to an example embodiment of the present disclosure;

[0018] Figure 2 and Figure 3is a diagram showing the principle of driving at different frequencies;

[0019] Figure 4 is a diagram showing a pixel circuit according to a first exemplary embodiment of the present disclosure;

[0020] Figure 5 It is shown Figure 4 A diagram showing the driving timing of the pixel circuit shown;

[0021] Figure 6 is a diagram showing a shift register of a gate driver according to an example embodiment of the present disclosure;

[0022] Figure 7 is a diagram showing a gate driver according to a first example embodiment;

[0023] Fig. 8A and Figure 8B It is shown Figure 7 FIG. 1 is a diagram of a driving waveform of a gate driver shown;

[0024] Fig.9A , Fig. 9B , Fig. 9C and Fig.9D It is shown Figure 7 A diagram showing the working principle of the gate driver;

[0025] Fig. 10A , Fig. 10B and Fig. 10C is a diagram showing the principle of frame skipping for each frequency;

[0026] Fig.11A , Fig. 11B , Fig. 11C , Fig.11D and Fig.11E is a diagram showing the principle of generating a first reset signal and a second reset signal;

[0027] Fig.12 is a diagram showing a pixel circuit according to a second exemplary embodiment of the present disclosure;

[0028] Fig.13 It is shown Fig.12 A diagram showing the driving timing of the pixel circuit shown;

[0029] Fig.14 is a diagram showing a gate driver according to a second example embodiment;

[0030] Fig.15A and Fig. 15B It is shown Fig.14 FIG. 1 is a diagram of a driving waveform of a gate driver shown;

[0031] Fig.16A, Fig. 16B , Fig. 16C and Fig.16D It is shown Fig.14 A diagram showing the working principle of the gate driver;

[0032] Fig.17 is a diagram showing a pixel circuit according to a third example embodiment of the present disclosure; and

[0033] Fig.18 It is shown Fig.17 A diagram showing the driving timing of the pixel circuit shown.

[0034] Throughout the drawings and detailed description, unless otherwise described, the same drawing reference numerals should be understood to refer to the same elements, features, and structures. The relative sizes and depictions of these elements may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0035] The advantages and features of the present specification and the methods for achieving them will become apparent with reference to the preferred example embodiments described in detail in conjunction with the accompanying drawings. However, the present specification is not limited to the example embodiments to be described below and may be implemented in different forms, which are only provided to fully disclose the present disclosure and fully convey the scope of the present disclosure to those skilled in the art, and the present specification is defined by the disclosed claims.

[0036] Since the shapes, sizes, areas, proportions, angles, quantities, etc. disclosed in the drawings for describing the example embodiments of the present disclosure are only exemplary, the present disclosure is not limited to the items shown. Throughout the specification, the same reference numerals represent the same components. In addition, when describing the present disclosure, when it is determined that the detailed description of the related known technology may unnecessarily obscure the main points of the present disclosure, its detailed description will be omitted.

[0037] When “comprising,” “having,” “including,” “containing,” “consisting of,” “made of,” “formed of,” “composed of,” etc. mentioned in this specification are used, other parts may be added unless “only” is used. Unless otherwise clearly stated, the case of expressing a component in the singular includes the plural form.

[0038] When explaining the components, it should be understood that an error range is included even when there is no separate explicit description.

[0039] In the case of describing a positional relationship, for example, when the positional relationship of two parts is described as "on," "over," "above," "below," "below," "beside," "under," "near," "close," "adjacent," "on the side of," "near," etc., one or more other parts may be located between the two parts unless "immediately" or "directly" is used.

[0040] Spatially relative terms, such as "below," "below," "under," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that in addition to the orientation shown in the figures, spatially relative terms may also include different orientations of elements in use or operation. For example, if the elements in the figures are inverted, elements described as "below" or "below" other elements or features will be oriented "above" other elements or features. Therefore, the exemplary term "below" may include both below and above orientations. Similarly, the exemplary terms "above" or "above" may include both "above" and "below" orientations.

[0041] When describing a temporal relationship, terms such as "after", "subsequently", "next", "following", "before", etc. may include any situation where two events are not consecutive, unless terms such as "immediately", "directly" or "directly" are explicitly used.

[0042] Although "first", "second", "A", "B", "a", and "b", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical spirit of the present disclosure.

[0043] In addition, when describing the components of the present disclosure, terms such as first, second, A, B, (a), (b), etc. may be used herein. Each of these terms is not used to limit the nature, order or sequence of the corresponding components, but is only used to distinguish the corresponding components from other components. In the case of describing that a certain structural element or layer is "connected", "coupled", "bonded" or "joined" to another structural element or layer, it is generally interpreted that the other structural element or layer can be directly or indirectly "connected", "coupled", "bonded" or "joined" to the structural element or layer.

[0044] The term "at least one" should be understood to include any and all combinations of one or more associated listed items. For example, the meaning of "at least one of the first, second, and third items" means the combination of all items proposed from two or more of the first, second, and third items as well as the first, second, or third item.

[0045] The term "device" as used herein may refer to a display device including a display panel and a driver for driving the display panel. Examples of display devices may include light emitting devices, etc. In addition, examples of devices may include laptop computers, televisions, computer monitors, automotive devices, wearable devices, and automotive equipment devices, as well as complete electronic devices (or devices) or complete sets of devices (or devices) that include light emitting devices, etc. as complete products or final products, for example, mobile electronic devices such as smart phones or electronic tablets, but embodiments of the present disclosure are not limited thereto.

[0046] Like reference numerals may refer to substantially like elements throughout this disclosure.

[0047] The following exemplary embodiments may be partially or completely combined or combined with each other, and may be technically linked and operated in various ways. The exemplary embodiments may be performed independently or in association with each other.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the example embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such in this article.

[0049] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0050] In an example embodiment, frame skipping is implemented by blocking the output of a strobe signal, and each region is driven at a different frequency using the frame skipping, and the position for dividing the region may also be variable using the interval of blocking the strobe signal.

[0051] Figure 1 is a block diagram of a display device according to an example embodiment of the present disclosure.

[0052] Reference Figure 1The display device according to the exemplary embodiment of the present disclosure includes a display panel 100, a display panel driving circuit for writing pixel data to pixels of the display panel 100, and a power supply 140 for generating power required to drive the pixels and the display panel driving circuit, but the components of the display device of the present disclosure are not limited thereto. In addition, all components of each display device according to all embodiments of the present disclosure are operably connected and configured.

[0053] The display panel 100 includes a pixel array AA that displays an input image. The pixel array AA includes a plurality of data lines 102, a plurality of gate lines 103 crossing the data lines 102, and pixels arranged in a matrix in an area defined by the plurality of data lines 102 and the plurality of gate lines 103 crossing each other.

[0054] The pixel array AA includes a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln includes a row of pixels arranged along the row direction X in the pixel array AA of the display panel 100. The pixels arranged in one pixel row share a gate line 103. Sub-pixels arranged in the column direction Y along the data line direction share the same data line 102. One horizontal period 1H is a time obtained by dividing one frame period by the total number of the pixel rows L1 to Ln.

[0055] The touch sensor may be implemented in the form of a touch panel outside the display panel 100, or may be integrated inside the display panel 100. A separate touch sensor may be used to sense the touch input, or the touch input may be sensed by a pixel. The touch sensor may be provided as an on-cell type or an additional type on the screen of the display panel, or implemented as an in-cell type touch sensor embedded in the pixel array AA. In the example where the additional type touch sensor is provided in the display panel 100, the touch panel and the display panel 100 may be manufactured separately and combined during the assembly process, and the additional type touch panel may include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate. In the example where the in-cell type touch sensor is provided in the display panel 100, in the process of manufacturing the display panel 100, the touch sensor may be formed on the substrate SUB together with the signal lines and electrodes related to the display drive.

[0056] The display panel 100 may be implemented as a flexible display panel. The flexible display panel may be made of a plastic OLED panel. An organic film may be disposed on a back panel of the plastic OLED panel, and a pixel array AA may be formed on the organic film.

[0057] The backplane of the plastic OLED may be a polyethylene terephthalate (PET) substrate. An organic film is formed on the backplane. The pixel array AA and the touch sensor array may be formed on the organic film. The backplane blocks moisture penetration so that the pixel array AA is not exposed to moisture. The organic film may be a thin polyimide (PI) film substrate. A multilayer buffer film may be formed of an insulating material (not shown) on the organic film. A wire may be formed on the organic film to supply power or signals applied to the pixel array AA and the touch sensor array.

[0058] A plurality of sub-pixels SP is the minimum unit constituting the display area, and n sub-pixels SP form one pixel PX. Each of the plurality of sub-pixels SP may emit light having a different wavelength from each other. The plurality of sub-pixels may include a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit light of different colors from each other. In order to realize color, each pixel may be divided into a red sub-pixel (hereinafter referred to as "R sub-pixel"), a green sub-pixel (hereinafter referred to as "G sub-pixel"), and a blue sub-pixel (hereinafter referred to as "B sub-pixel"). Each pixel may also include a white sub-pixel.

[0059] For example, the plurality of sub-pixels SP may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel ("R sub-pixel", "G sub-pixel", and "B sub-pixel"), wherein the red sub-pixel, the green sub-pixel, and the blue sub-pixel may be arranged in a repeated manner. Alternatively, the plurality of sub-pixels SP may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, wherein the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel may be arranged in a repeated manner, or the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel may be arranged in a quadrilateral type. For example, the red sub-pixel, the blue sub-pixel, and the green sub-pixel may be arranged sequentially along the row direction, or the red sub-pixel, the blue sub-pixel, the green sub-pixel, and the white sub-pixel may be arranged sequentially along the row direction. However, in the example embodiments of the present disclosure, the color type, arrangement type, and arrangement order of the sub-pixels are not limited, and may be configured in various forms according to the luminous characteristics, device life, and device specifications.

[0060] In addition, the sub-pixels may have different light-emitting areas according to the light-emitting characteristics. For example, a sub-pixel emitting light of a color different from the color of the blue sub-pixel may have a light-emitting area different from the light-emitting area of ​​the blue sub-pixel. For example, a red sub-pixel, a blue sub-pixel, and a green sub-pixel, or a red sub-pixel, a blue sub-pixel, a white sub-pixel, and a green sub-pixel may each have a different light-emitting area.

[0061] Each sub-pixel 101 includes a pixel circuit. A pixel circuit is a circuit including a driving transistor, some other transistors and a capacitor for driving a light-emitting element. For example, a pixel circuit may include a driving transistor, a switching transistor, a sensing transistor and a light-emitting control transistor to supply a driving current to the light-emitting element. Transistors and capacitors other than the driving transistor among the multiple transistors included in the pixel circuit may be configured in various forms according to the design, and the present disclosure is not limited thereto.

[0062] The driving transistor includes a driving active layer ACT, a driving gate electrode GE, a driving source electrode SE, and a driving drain electrode DE.

[0063] The driving active layer ACT may be formed of a semiconductor material, such as an oxide semiconductor, an amorphous semiconductor, or a polycrystalline semiconductor, but is not limited thereto.

[0064] Oxide semiconductor materials can have excellent effects of preventing leakage current and relatively cheap manufacturing costs. Oxide semiconductors can be made of metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) and titanium (Ti) or metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) or titanium (Ti) and combinations of their oxides. Specifically, oxide semiconductors can include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO) and indium gallium oxide (IGO), but are not limited thereto.

[0065] The polycrystalline semiconductor material has a fast moving speed of carriers such as electrons and holes, and thus has high mobility, and has low power consumption and excellent reliability. The polycrystalline semiconductor may be made of polycrystalline silicon (poly-Si), but is not limited thereto.

[0066] The amorphous semiconductor material may be made of amorphous silicon (a-Si), but is not limited thereto.

[0067] The pixel circuit is connected to the data line 102 and the gate line 103 .

[0068] The power supply 140 generates the DC power required for driving the pixel array AA of the display panel 100 and the display panel driving circuit by using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply 140 may adjust the DC input voltage from the host system (not shown), and thereby generate DC voltages such as a gamma reference voltage VGMA, a gate-on voltage VGH and VEH, a gate-off voltage VGL and VEL, a pixel driving voltage EVDD, and a pixel low potential power supply voltage EVSS. The gamma reference voltage VGMA is supplied to the data driver 110. The gate-on voltages VGH and VEH and the gate-off voltages VGL and VEL are supplied to the gate driver 120. The pixel driving voltage EVDD and the pixel low potential power supply voltage EVSS are supplied to the pixel together.

[0069] The display panel driving circuit applies analog voltages corresponding to pixel data (digital data) of an input image to pixels of the display panel 100 under the control of a timing controller (TCON) 130 .

[0070] The display panel driving circuit includes a data driver 110 and a gate driver 120 .

[0071] A demultiplexer (DEMUX) 112 may be provided between the data driver 110 and the data lines 102. The demultiplexer 112 sequentially connects one channel of the data driver 110 to the plurality of data lines 102, and distributes the data voltage output from one channel of the data driver 110 to the data lines 102 in a time-division manner, thereby reducing the number of channels of the data driver 110. The demultiplexer 112 may be omitted. In this case, the output buffer AMP of the data driver 110 is directly connected to the data lines 102.

[0072] The display panel driving circuit may further include a touch sensor driver for driving the touch sensor. Figure 1 The touch sensor driver is omitted in FIG. 1. In a mobile device, the timing controller 130, the power supply 140, the data driver 110, etc. may be integrated into one driving integrated circuit (IC).

[0073] The data driver 110 generates a data voltage Vdata by converting pixel data of an input image received from the timing controller 130 with a gamma compensation voltage in each frame period using a digital-to-analog converter (DAC). The gamma reference voltage VGMA is divided for each gray scale by a voltage divider circuit. The gamma compensation voltage divided from the gamma reference voltage VGMA is provided to the DAC of the data driver 110. The data voltage Vdata is output through an output buffer AMP in each channel of the data driver 110. Although Figure 1In the embodiment, one data driver 110 is illustrated as being disposed on one side of the display panel 100, but the number of the data drivers 110 and their arrangement are not limited thereto. For example, two data drivers 110 may be disposed on both sides of the display panel 100, respectively. For example, a plurality of data drivers 110 may be disposed on one side of the display panel 100. Depending on the mounting method, the data driver 110 may be disposed by chip on glass (COG), chip on film (COF), or tape carrier package (TCP) technology, but is not limited thereto.

[0074] The gate driver 120 may be implemented as a gate-in-panel (GIP) circuit directly formed on the bezel BZ region of the display panel 100 together with the TFT array of the pixel array AA. The gate driver 120 sequentially outputs a gate signal to the gate line 103 under the control of the timing controller 130. The gate driver 120 may sequentially supply the gate signal to the gate line 103 by shifting the gate signal using a shift register. Figure 1 In the embodiment, the gate driver 120 is illustrated as being disposed on one side of the display panel 100 , but the number and arrangement of the gate drivers 120 are not limited thereto. For example, the gate drivers 120 may be disposed on both sides of the display panel 100 , respectively.

[0075] The gate signal may include a scan signal for selecting pixels of a row in which data is to be written in synchronization with the data voltage, and an EM signal defining a light emitting time of the pixel charged with the data voltage.

[0076] The gate driver 120 may include a scan driver 121 and an EM driver 122 .

[0077] The scan driver 121 outputs a scan signal SCAN in response to a start pulse and a shift clock from the timing controller 130, and shifts the scan signal SCAN according to the shift clock timing. The EM driver 122 outputs an EM signal EM in response to a start pulse and a shift clock from the timing controller 130, and sequentially shifts the EM signal EM according to the shift clock. The initialization driver 123 outputs an initialization signal INIT in response to a start pulse and a shift clock from the timing controller 130, and shifts the initialization signal INIT according to the shift clock timing. Therefore, the scan signal SCAN, the EM signal EM, and the initialization signal INIT are sequentially supplied to the gate lines 103 of the pixel rows L1 to Ln. In the case of a borderless model, at least some of the transistors and clock lines constituting the gate driver 120 may be dispersedly disposed in the pixel array AA.

[0078] The timing controller 130 receives the digital video data DATA of the input image and the timing signal synchronized therewith from the host system (not shown). The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal CLK, a data enable signal DE, etc. Here, the horizontal synchronization signal is a signal indicating the time taken to display one horizontal line of the picture, and the vertical synchronization signal is a signal indicating the time taken to display one frame of the picture. The data enable signal may correspond to a signal indicating the cycle of supplying the data voltage to the pixel. Since the vertical cycle and the horizontal cycle can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a cycle of one horizontal cycle (1H).

[0079] The host system may be any one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a vehicle system, and a mobile device system.

[0080] The timing controller 130 multiplies the input frame frequency by i and controls the operation timing of the display panel driving circuit at a frame frequency of input frame frequency×i (i is a positive integer greater than 0) Hz. The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) scheme and 50 Hz in the PAL (Phase Alternation Line) scheme.

[0081] Based on the timing signals Vsync, Hsync and DE received from the host system, the timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, a MUX signal for controlling the operation timing of the demultiplexer 112, and a gate timing control signal for controlling the operation timing of the gate driver 120.

[0082] The voltage level of the gate timing control signal output from the timing controller 130 can be converted into gate-on voltages VGH and VEH and gate-off voltages VGL and VEL by a level shifter (not shown), and then supplied to the gate driver 120. That is, the level shifter converts the low-level voltage of the gate timing control signal into the gate-off voltages VGL and VEL, and converts the high-level voltage of the gate timing control signal into the gate-on voltages VGH and VEH. The gate timing control signal includes a start pulse and a shift clock.

[0083] The timing controller 130 according to an example embodiment may control the operation of the data driver 110 using the data timing signal and may control the operation of the gate driver 120 using the gate timing control signal. For example, during the frame skip interval, the timing controller 130 may control the data driver 110 not to output the data voltage, and may control the gate driver 120 not to output the gate signal, that is, control the gate signal output by the gate driver 120 to become a gate-off voltage.

[0084] In an example embodiment of the present disclosure, the plurality of regions may be driven at different frequencies using frame skipping, and the positions for dividing the plurality of regions may also be changed. Here, the plurality of regions may include a first pixel array and a second pixel array.

[0085] Figure 2 and Figure 3 It is a diagram showing the principle of driving at different frequencies.

[0086] Reference Figure 2 In an example embodiment, the screen may be divided into two areas, namely, a first area AA1 and a second area AA2, and the first area AA1 may be driven at a frequency of 120 Hz, and the second area AA2 may be driven at a frequency of 30 Hz.

[0087] In the normal driving mode, image data is applied to the entire areas AA1 and AA2 in one frame interval. In the multi-driving mode in which the first area AA1 and the second area AA2 are divided, first image data DATA1 is applied to the first area AA1 and second image data DATA2 is applied to the second area AA2 in one frame interval. For example, the first image data DATA1 may be moving image data, and the second image data DATA2 may be still image data.

[0088] In this case, the image data may not be applied to the second area AA2 during the frame skipping interval according to the driving frequency.

[0089] For example, when the first area is driven at 120 Hz and the second area is driven at 30 Hz, the first image data is applied to the first area AA1 in each frame interval, and the second image data is not applied to the second area AA2 in three frame intervals in every four frame intervals.

[0090] In this case, since the first area AA1 and the second area AA2 are divided into equal sizes, durations for applying the first image data and the second image data in each frame interval are formed to be the same.

[0091] Reference Figure 3In an example embodiment, the screen is divided into two areas, namely, a first area AA1 and a second area AA2, and the first area AA1 may be driven at a frequency of 120 Hz and the second area AA2 may be driven at a frequency of 60 Hz.

[0092] For example, when the first area AA1 is driven at a frequency of 120 Hz and the second area AA2 is driven at a frequency of 60 Hz, the first image data DATA1 is applied to the first area AA1 in each frame interval, while the second image data DATA2 is not applied to the second area AA2 in one frame interval of every two frame intervals.

[0093] In this case, since the first area AA1 and the second area AA2 are divided into different sizes, durations for applying the first image data DATA1 and the second image data DATA2 in each frame interval are formed to be different.

[0094] Here, the case where the image data is not applied to the second area is described as an example, but the present disclosure is not limited thereto. For example, the image data may not be applied to the first area, or the image data may not be applied to both the first area and the second area. Figure 2 and Figure 3 As described, in order to operate the divided areas at different driving frequencies using frame skipping, it can be achieved by blocking the gate signal applied to the second area during the frame skipping interval.

[0095] exist Figure 2 and Figure 3 In the embodiment, the screen is divided into two areas, namely, the first area AA1 and the second area AA2, however, the embodiments of the present disclosure are not limited thereto, and the screen may be divided into three or more areas. For example, when the multiple areas are divided into equal sizes, the duration of applying the multiple image data in each frame interval is formed to be the same. Alternatively, when the multiple areas are divided into different sizes, the duration of applying the multiple image data in each frame interval is formed to be different. However, the present disclosure is not limited thereto.

[0096] Figure 4 is a diagram showing a pixel circuit according to a first exemplary embodiment of the present disclosure. Figure 5 It is shown Figure 4 A diagram showing the driving timing of the pixel circuit shown.

[0097] Reference Figures 4 to 5The pixel circuit according to the first exemplary embodiment of the present disclosure includes a light emitting element EL, a driving element DT for supplying current to the light emitting element EL, a plurality of switching elements T1, T2, T3, T4, T5, T6, and T7 for switching a current path connected to the driving element DT, and a first capacitor Cst for storing a gate-source voltage of the driving element DT. The driving element DT and the switching elements T2, T3, T4, T6, and T7 may be implemented as P-channel oxide TFTs, and the switching elements T1 and T5 may be implemented as N-channel oxide TFTs.

[0098] The selection signal applied to the pixel circuit includes a first scan signal SCAN1(n), a second scan signal SCAN2(n), a third scan signal SCAN3(n), a fourth scan signal SCAN4(n) and an EM signal EM(n). Here, N is a natural number.

[0099] The capacitor Cst is connected between the first node n1 and the second node n2. The pixel driving voltage ELVDD is supplied to the pixel circuit through the ELVDD line. The first node n1 is connected to the ELVDD line, the first electrode of the third switching element T3, and the first electrode of the capacitor Cst. The second node n2 is connected to the second electrode of the capacitor Cst, the gate electrode of the driving element DT, the first electrode of the first switching element T1, and the first electrode of the fifth switching element T5.

[0100] The first switch element T1 is turned on in response to the gate-on voltage VGH of the first scan signal SCAN1(n), and connects the gate electrode of the driving element DT to its first electrode. The first switch element T1 includes a gate electrode connected to the first scan line GL1, a first electrode connected to the second node n2, and a second electrode connected to the third node n3. The first scan signal SCAN1(n) is supplied to the pixel through the first scan line GL1. The third node n3 is connected to the second electrode of the driving element DT, the second electrode of the first switch element T1, and the first electrode of the fourth switch element T4.

[0101] The second switching element T2 is turned on in response to the gate-on voltage VGL of the second scan signal SCAN2(n), and applies the data voltage Vdata to the first electrode of the driving element DT. The second switching element T2 includes a gate electrode connected to the second scan line GL2, a first electrode connected to the fifth node n5, and a second electrode connected to the data line 60. The fifth node n5 is connected to the first electrode of the driving element DT, the first electrode of the second switching element T2, and the second electrode of the third switching element T3.

[0102] The third switching element T3 supplies the pixel driving voltage ELVDD to the first electrode of the driving element DT in response to the EM signal EM(n). The third switching element T3 includes a gate electrode connected to the EM line GL5, a first electrode connected to the ELVDD line, and a second electrode connected to the fifth node n5. The EM signal EM(n) is supplied to the pixel through the EM line GL5.

[0103] The fourth switching element T4 is turned on in response to the gate-on voltage VGL of the EM signal EM(n), and connects the second electrode of the driving element DT to the anode electrode of the light emitting element EL. The gate electrode of the fourth switching element T4 is connected to the EM line GL5. The first electrode of the fourth switching element T4 is connected to the third node n3, and the second electrode of the fourth switching element T4 is connected to the fourth node n4. The fourth node n4 is connected to the anode electrode of the light emitting element EL, the second electrode of the fourth switching element T4, and the second electrode of the sixth switching element T6.

[0104] The fifth switch element T5 is turned on in response to the gate-on voltage VGH of the fourth scan signal SCAN4 (n), and connects the second node n2 to the Vini line to initialize the capacitor Cst and the gate electrode of the driving element DT during the initialization phase Ti. The fifth switch element T5 includes a gate electrode connected to the fourth scan line GL4, a first electrode connected to the second node n2, and a second electrode connected to the Vini line. The fourth scan signal SCAN4 (n) is supplied to the pixel through the fourth scan line GL4. The initialization voltage Vini is supplied to the pixel through the Vini line.

[0105] The sixth switch element T6 is turned on in response to the gate-on voltage VGL of the third scan signal SCAN3 (n), and connects the VAR line 64 to the anode electrode of the light emitting element EL during the first OBS stage Tobs1 and the second OBS stage Tobs2. During the first OBS stage Tobs1 and the second OBS stage Tobs2, the anode voltage of the light emitting element EL is discharged to the reset voltage VAR through the sixth switch element T6. In this case, since the voltage between the anode and the cathode is lower than its threshold voltage, the light emitting element EL does not emit light. The sixth switch element T6 includes a gate electrode connected to the third scan line GL3, a first electrode connected to the VAR line 64, and a second electrode connected to the fourth node n4.

[0106] The seventh switching element T7 is turned on in response to the gate-on voltage VGL of the third scan signal SCAN3(n), and connects the fifth node n5 to the Vobs line 65 to apply the bias voltage Vobs during the first OBS stage Tobs1 and the second OBS stage Tobs2. During the first OBS stage Tobs1 and the second OBS stage Tobs2, the voltage of the first electrode of the driving element DT is discharged to the bias voltage Vobs through the seventh switching element T7. The seventh switching element T7 includes a gate electrode connected to the third scan line GL3, a first electrode connected to the fifth node n5, and a second electrode connected to the Vobs line 65.

[0107] The driving element DT drives the light emitting element EL by controlling a current flowing through the light emitting element EL based on the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to the second node n2, a first electrode connected to the fifth node n5, and a second electrode connected to the third node n3.

[0108] The light emitting element EL is connected between the fourth node n4 and the ELVSS line. The light emitting element EL may be implemented as an OLED. The OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, an emission layer EML, an electron transport layer ETL, and an electron injection layer EIL, but is not limited thereto. When a voltage is applied to the anode and cathode of the OLED, holes that have passed through the hole transport layer HTL and electrons that have passed through the electron transport layer ETL move to the emission layer EML to form excitons, and thus visible light is emitted from the emission layer EML.

[0109] In the first OBS stage Tobs1 , the seventh switch element T7 is turned on, so that the voltage of the fifth node n5 is discharged to the bias voltage Vobs.

[0110] In the initialization stage Ti, the first switching element T1 and the fifth switching element T5 are turned on, so that the voltages of the second node n2 and the third node n3 are discharged to the initialization voltage Vini.

[0111] In the data writing phase Tw, the second switching element T2 is turned on so that the data voltage is applied to the fifth node n5 and the voltage of the second node n2 becomes the voltage Vdata+Vth. The threshold voltage Vth of the driving element DT is sensed and charged to the capacitor Cst connected to the second node n2.

[0112] In the second OBS stage Tobs2 , the seventh switch element T7 is turned on, so that the voltage of the fifth node n5 is discharged to the bias voltage Vobs.

[0113] In the light emitting stage Tem, the third switch element T3 and the fourth switch element T4 are turned on, so that the current flows to the light emitting element EL through the driving element DT, and the light emitting element EL emits light.

[0114] Since the method of implementing frame skipping is to prevent the output of the strobe signal, the first scanning signal and the fourth scanning signal among the five signals (ie, the first to fourth scanning signals and the EM signal) can be prevented from being output to the EM signal. Figure 4 For example, the first switching element T1 and the fifth switching element T5 are turned off, so that the voltages of the second node n2 and the third node n3 are not initialized during frame skipping.

[0115] exist Figure 4 In the figure, the pixel circuit is shown as a pixel circuit of 8T1C structure, however, the present disclosure is not limited thereto, and various configurations of the internal compensation circuit are possible in the pixel circuit of the present disclosure. For example, the number of transistors TFT in the pixel circuit of the present disclosure may be three or more, and the number of capacitors may be 1 or more, for example, the pixel circuit of the present disclosure may be a 5T1C pixel circuit including five TFTs and one capacitor, a 5T2C pixel circuit including five TFTs and two capacitors, a 7T2C pixel circuit including seven TFTs and two capacitors, or an 8T2C pixel circuit including eight TFTs and two capacitors, etc.

[0116] Figure 6 is a diagram illustrating a shift register of a gate driver according to an exemplary embodiment of the present disclosure.

[0117] refer to Figure 6 , a gate driver according to an example embodiment includes a plurality of signal transmitters ST(1), ST(2), ST(3), . . . , ST(n-2), ST(n-1), and ST(n) which are relatedly connected via a carry line through which a carry signal is transmitted.

[0118] Each of the signal transmitters ST(1), ST(2), ST(3), ..., ST(n-2), ST(n-1) and ST(n) receives a start pulse (start signal) VST or a clock signal CLK and a carry signal output from a previous signal transmitter. The first signal transmitter ST(1) starts to be driven in response to the start pulse VST, and the other signal transmitters ST(2), ST(3), ..., ST(n-2), ST(n-1), ST(n) start to be driven by receiving a carry signal C(1), C(2), ..., C(n-3), C(n-2), C(n-1) from their previous signal transmitters, respectively.

[0119] The signal transmitters ST(1), ST(2), ST(3), ..., ST(n-2), ST(n-1) and ST(n) sequentially output the selection signals GOUT(1), GOUT(2), GOUT(3), ..., GOUT(n-2), GOUT(n-1) and GOUT(n) by shifting the start pulse VST according to the timing of the clock signal or the carry signal C(1), C(2), ..., C(n-3), C(n-2), C(n-1) output from their previous signal transmitters.

[0120] In this case, if the signal transmitter that starts the frame skipping interval does not output a selection signal, the carry signal is not output either, so the next signal transmitter does not output a selection signal either. For example, if the signal transmitter ST(1) does not output a selection signal, the subsequent signal transmitters ST(2), ST(3), ..., ST(n-2), ST(n-1) and ST(n) do not output a selection signal. For example, if the signal transmitter ST(n-2) does not output a selection signal, the subsequent signal transmitters ST(n-1) and ST(n) do not output a selection signal. Here, not outputting a selection signal means outputting a gate cut-off voltage.

[0121] Figure 7 is a diagram showing a gate driver according to a first example embodiment. Fig. 8A and Figure 8B It is shown Figure 7 FIG. 5 is a diagram of the driving waveform of the gate driver shown. Fig.9A , Fig. 9B , Fig. 9C and Fig.9D It is shown Figure 7 A diagram showing the operating principle of the gate driver.

[0122] Reference Figure 7 According to the first example embodiment of the present disclosure, the gate driver may include a first control node for a pull-up output voltage (hereinafter referred to as a “Q node”), a second control node for a pull-down output voltage (hereinafter referred to as a “Qb node”), a first circuit portion 61, a selection portion 62, and a second circuit portion 63.

[0123] The first circuit section 61 is used to control the charging and discharging of the Q node Q(n) and the Qb node Qb(n). The first circuit section 61 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a first capacitor C1 and a second capacitor C2.

[0124] The first transistor T1 is turned on by the clock signal CLK1 and connects the first node 1a to the second node 2a. The first transistor T1 includes a gate electrode to which the clock signal is applied, a first electrode connected to the first node 1a, and a second electrode connected to the second node 2a.

[0125] The second transistor T2 is turned on by the start signal VST or the previous carry signal C(n-1), and connects the 3a node 3a to the first power line PL1 through which the high potential voltage VGH is applied. The second transistor T2 includes a gate electrode to which the start signal VST or the previous carry signal C(n-1) is applied, a first electrode connected to the 3a node 3a, and a second electrode connected to the first power line PL1.

[0126] The third transistor T3 is turned on by the voltage of the 3a node 3a, and connects the 4a node 4a to which the clock signal CLK(n) is applied to the second control node Qb(n). The third transistor T3 includes a gate electrode connected to the 3a node 3a, a first electrode connected to the 4a node 4a, and a second electrode connected to the second control node Qb(n).

[0127] The fourth transistor T4 is turned on by the voltage of the 2a node 2a and connects the second control node Qb(n) to the first power line PL1. The fourth transistor T4 includes a gate electrode connected to the 2a node 2a, a first electrode connected to the second control node Qb(n), and a second electrode connected to the first power line PL1.

[0128] The fifth transistor T5 is turned on by the low potential voltage VGL and connects the 2a node 2a to the first control node Q(n). The fifth transistor T5 includes a gate electrode connected to the second power line PL2 through which the low potential voltage VGL is applied, a first electrode connected to the 2a node 2a, and a second electrode connected to the first control node Q(n).

[0129] The first capacitor C1 is connected between the 3a node 3a and the fourth 4a node 4a, and the second capacitor C2 is connected between the second control node Qb(n) and the first power line PL1.

[0130] The selection part 62 is used to apply the low potential voltage VGL to the first control node Q(n) instead of the start signal VST or the previous carry signal C(n-1) during the frame skip interval. The selection part 62 may include a 1A-th transistor T1A and a 1B-th transistor T1B.

[0131] The 1A transistor T1A is turned on by the first reset signal RST, so the start signal VST or the previous carry signal C(n-1) is applied to the 1a node 1a. The 1A transistor T1A includes a gate electrode to which the first reset signal RST is applied, a first electrode to which the start signal VST or the previous carry signal C(n-1) is applied, and a second electrode connected to the 1a node 1a.

[0132] The 1B-th transistor T1B is turned on by the second reset signal RSTB having a phase opposite to that of the first reset signal RST, and connects the 1a-th node 1a to the second power line PL2 to supply the low potential voltage VGL. The 1B-th transistor T1B includes a gate electrode to which the second reset signal RSTB is applied, a first electrode connected to the second power line PL2, and a second electrode connected to the 1a-th node 1a.

[0133] The second circuit portion 63 may output a scan signal SCAN(n) to the output node OUT based on the potentials of the Q node Q(n) and the Qb node Qb(n). Here, the scan signal SCAN(n) may include a voltage applied to the Q node Q(n). Figure 4 The second circuit portion 63 may include a sixth transistor T6 and a seventh transistor T7.

[0134] The sixth transistor T6 is turned on by the voltage of the first control node Q(n) and outputs the low potential voltage VGL to the output node OUT. The sixth transistor T6 includes a gate electrode connected to the first control node Q(n), a first electrode connected to the second power line PL2, and a second electrode connected to the output node OUT.

[0135] The seventh transistor T7 is turned on by the voltage of the second control node Qb(n) and outputs the high potential voltage VGH to the output node OUT. The seventh transistor T7 includes a gate electrode connected to the second control node Qb(n), a first electrode connected to the output node OUT, and a second electrode connected to the first power line PL1.

[0136] The third capacitor C3 is connected between the gate electrode of the sixth transistor T6 and the second electrode thereof.

[0137] The gate driver according to example embodiments may perform frame skipping through the first reset signal RST and the second reset signal RSTB.

[0138] In the case where frame skipping is not performed, such as Fig. 8AAs shown, when a low-level first reset signal RST is applied to the 1A transistor T1A to turn on the 1A transistor T1A, the start signal VST and the previous carry signal are applied to the 1a node 1a, and when a high-level second reset signal RSTB is applied to the 1B transistor T1B to turn off the 1B transistor T1B, the low-potential voltage VGL is prevented from being applied to the 1a node 1a, thereby outputting a high-level scan signal.

[0139] In the case of frame skipping, such as Figure 8B As shown, when a high-level first reset signal RST is applied to the 1A transistor T1A to turn off the 1A transistor T1A, the start signal VST and the previous carry signal are blocked from being applied to the 1a node 1a, and when a low-level second reset signal RSTB is applied to the 1B transistor T1B to turn on the 1B transistor T1B, the low-potential voltage VGL is applied to the 1a node 1a, thereby outputting a low-level scan signal.

[0140] Since the gate driver applies the low-level first scan signal and the second scan signal to Figure 4 The pixel circuit is thus turned off, so the first switching element and the fifth switching element are turned off.

[0141] In example embodiments, the first reset signal RST and the second reset signal RSTB may be applied at different periods according to a driving frequency. The data driver also does not apply a data voltage according to the first reset signal RST and the second reset signal RSTB in a frame skip interval.

[0142] refer to Fig.9A , Fig. 9B , Fig. 9C and Fig.9D , the gate driver according to the example embodiment may be operated using a driving waveform divided into a first section ①, a second section ②, a third section ③, and a fourth section ④.

[0143] In the first section ①, since the first reset signal is at a low level voltage and the second reset signal is at a high level voltage, the output signal of the gate driver may be at a gate low voltage.

[0144] In the second section ②, since the first reset signal is inverted to a high level voltage and the second reset signal is inverted to a low level voltage, the output signal of the gate driver may be at a gate low voltage.

[0145] In the third section ③, since the voltage of the first control node Q(n) is in a low level state even if the first reset signal is inverted to a low level voltage and the second reset signal is inverted to a high level voltage, the output signal of the enable driver can be in a enable low voltage.

[0146] In the fourth section ④, since the first reset signal is at a low level voltage and the second reset signal is at a high level voltage, the output signal of the gate driver may be at a gate low voltage.

[0147] Therefore, the gate driver can output the gate low voltage during the first section to the fourth section.

[0148] Fig. 10A , Fig. 10B and Fig. 10C is a diagram showing the principle of frame skipping for each frequency.

[0149] refer to Fig. 10A , when the entire screen area is driven at a frequency of 120 Hz without performing multi-frequency driving, the data driver applies image data DATA to the entire screen area every frame, and the gate driver sequentially applies the gate signal through the low-level first reset signal RST and the high-level second reset signal RSTB.

[0150] refer to Fig. 10B When the first area AA1 and the second area AA2 divided for multi-frequency driving are driven at frequencies of 120 Hz and 60 Hz, respectively, the data driver applies the first image data to the first area per frame, applies the second image data to the second area in one frame interval in every two frames, and does not apply the second image data in the remaining one frame interval.

[0151] In this case, the gate driver also applies the gate signal to the first region every frame, applies the gate signal to the second region in one frame interval in every two frames through the first reset signal RST and the second reset signal RSTB, and does not apply the gate signal in the remaining one frame interval.

[0152] refer to Fig. 10C When the first area AA1 and the second area AA2 divided for multi-frequency driving are driven at frequencies of 120 Hz and 30 Hz, respectively, the data driver applies the first image data to the first area per frame, applies the second image data to the second area in one frame interval in every four frames, and does not apply the second image data in the remaining three frame intervals.

[0153] In this case, the gate driver also applies a gate signal to the first region every frame, applies a gate signal to the second region in one frame interval among every four frames through the first reset signal RST and the second reset signal RSTB, and does not apply a gate signal in the remaining three frame intervals.

[0154] Therefore, it is possible to implement operating the divided areas at different driving frequencies by blocking the gate signal applied to the second area during the frame skip interval.

[0155] Fig.11A , Fig. 11B , Fig. 11C , Fig.11D and Fig.11E 2 is a diagram illustrating the principle of generating the first reset signal and the second reset signal.

[0156] refer to Fig.11A In an example embodiment, the first reset signal and the second reset signal may be generated using one level shifter LS. That is, the timing controller 130 generates the first reset signal and the second reset signal together with the start signal and the clock signal at the first voltage level VCC, and applies them to the level shifter LS. The level shifter LS generates the start signal, the clock signal, and the first reset signal and the second reset signal of the first voltage level VCC into a second voltage level (i.e., gate-on voltages VGH and VEH and gate-off voltages VGL and VEL), and applies them to the gate driver 120 in the display panel.

[0157] refer to Fig. 11B In an example embodiment, an additional second level shifter LS2 may be used to generate the first reset signal and the second reset signal. That is, the timing controller 130 generates a start signal and a clock signal at a first voltage level and applies them to the first level shifter LS1, and simultaneously generates a first reset signal and a second reset signal at a first voltage level and applies them to the second level shifter LS2.

[0158] The first level shifter LS1 converts the start signal and the clock signal from the first voltage level to the second voltage level (i.e., the gate-on voltages VGH1 and VEH1 and the gate-off voltages VGL1 and VEL1), and applies them to the gate driver 120 in the display panel, and at the same time, converts the first reset signal and the second reset signal from the first voltage level to the third voltage level (i.e., the gate-on voltages VGH2 and VEH2 and the gate-off voltages VGL2 and VEL2), and applies them to the gate driver 120 in the display panel.

[0159] like Fig.11A As shown, the first reset signal RST and the second reset signal RSTB are generated to have the same voltage level. Fig. 11B In the present invention, the first reset signal RST and the second reset signal RSTB are generated to have different voltage levels.

[0160] The reason for generating the first reset signal RST and the second reset signal RSTB having different voltage levels is that different gate-on voltages or gate-off voltages of the first reset signal RST and the second reset signal RSTB are applied as needed, because as the signal passes through the transistor in the selection driver, the voltage level of the first reset signal RST and the second reset signal RSTB is reduced due to the threshold voltage Vth.

[0161] In this case, the first reset signal RST and the second reset signal RSTB may be formed as follows: Fig. 11C The pulse voltage is in the form of Fig.11D The form of DC voltage shown, or Fig.11E The clock voltage is in the form shown. However, it is not necessarily limited thereto and can be formed in various forms.

[0162] Furthermore, any signal form capable of blocking the gate-on voltage of the gating signal when the clock signal is at a low level and the start signal is at a high level is possible. In particular, a pulse voltage form or a DC voltage form is advantageous in terms of power consumption because the transition is minimized. In addition, a clock voltage form is advantageous in terms of preventing degradation of the buffer transistor because the buffer transistor is alternately driven.

[0163] For example, when the first reset signal RST is at a high level and the second reset signal RSTB is maintained at a low level for at least a 1H period, frame skipping is possible.

[0164] Fig.12 is a diagram showing a pixel circuit according to a second exemplary embodiment of the present disclosure. Fig.13 It is shown Fig.12 A diagram showing the driving timing of the pixel circuit shown.

[0165] Reference Fig.12 and Fig.13 The pixel circuit according to the second exemplary embodiment of the present disclosure includes a light emitting element EL, a driving element DT for supplying current to the light emitting element EL, a plurality of switching elements T1-1, T2-1, T3-1, T4-1, T5-1, and T6-1 for switching a current path connected to the driving element DT, and a first capacitor Cst for storing a gate-source voltage of the driving element DT. The driving element DT and the switching elements T1-1, T2-1, T3-1, T4-1, T5-1, and T6-1 may be implemented as P-channel oxide TFTs.

[0166] The gate signal applied to the pixel circuit includes an nth scan signal SCAN(n), an (n-1)th scan signal SCAN(n-1), and an EM signal EM(n). Here, N is a natural number.

[0167] The capacitor Cst is connected between the 1-1th node n1-1 and the 2-1th node n2-1. The pixel driving voltage ELVDD is supplied to the pixel circuit through the ELVDD line. The 1-1th node n1-1 is connected to the ELVDD line, the first electrode of the 3-1th switching element T3-1, and the first electrode of the capacitor Cst. The 2-1st node n2-1 is connected to the second electrode of the capacitor Cst, the gate electrode of the driving element DT, the first electrode of the 1-1th switching element T1-1, and the first electrode of the 5-1th switching element T5-1.

[0168] The 1-1st switching element T1-1 is turned on in response to the gate-on voltage VGL of the n-th scan signal SCAN(n), and connects the gate electrode of the driving element DT to its first electrode. The 1-1st switching element T1-1 includes a gate electrode connected to the second scan line GL2, a first electrode connected to the 2-1st node n2-1, and a second electrode connected to the 3-1st node n3-1. The n-th scan signal SCAN(n) is supplied to the pixel through the second scan line GL2. The 3-1st node n3-1 is connected to the second electrode of the driving element DT, the second electrode of the 1-1st switching element T1-1, and the first electrode of the 4-1st switching element T4-1.

[0169] The 2-1st switching element T2-1 is turned on in response to the gate-on voltage VGL of the n-th scan signal SCAN(n), and applies the data voltage Vdata to the first electrode of the driving element DT. The 2-1st switching element T2-1 includes a gate electrode connected to the second scan line GL2, a first electrode connected to the 5-1st node n5-1, and a second electrode connected to the data line 60. The 5-1st node n5-1 is connected to the first electrode of the driving element DT, the first electrode of the 2-1st switching element T2-1, and the second electrode of the 3-1st switching element T3-1.

[0170] The 3-1st switching element T3-1 supplies the pixel driving voltage ELVDD to the first electrode of the driving element DT in response to the EM signal EM(n). The 3-1st switching element T3-1 includes a gate electrode connected to the EM line GL3, a first electrode connected to the ELVDD line, and a second electrode connected to the 5-1st node n5-1. The EM signal EM(n) is supplied to the pixel through the EM line GL3.

[0171] The 4-1st switching element T4-1 is turned on in response to the gate-on voltage VGL of the EM signal EM(n), and connects the second electrode of the driving element DT to the anode electrode of the light emitting element EL. The gate electrode of the 4-1st switching element T4-1 is connected to the EM line GL3. The first electrode of the 4-1st switching element T4-1 is connected to the 3-1st node n3-1, and the second electrode of the 4-1st switching element T4-1 is connected to the 4-1st node n4-1. The 4-1st node n4-1 is connected to the anode electrode of the light emitting element EL, the second electrode of the 4-1st switching element T4-1, and the second electrode of the 6-1st switching element T6-1.

[0172] The 5-1st switching element T5-1 is turned on in response to the gate-on voltage VGL of the (n-1)th scan signal SCAN(n-1), and connects the 2-1st node n2-1 to the Vini line during the initialization phase Ti to initialize the capacitor Cst and the gate electrode of the driving element DT. The 5-1st switching element T5-1 includes a gate electrode connected to the first scan line GL1, a first electrode connected to the 2-1st node n2-1, and a second electrode connected to the Vini line. The (n-1)th scan signal SCAN(n-1) is supplied to the pixel through the first scan line GL1. The initialization voltage Vini is supplied to the pixel through the Vini line.

[0173] The 6-1st switching element T6-1 is turned on in response to the gate-on voltage VGL of the n-th scan signal SCAN(n), and connects the Vini line to the anode electrode of the light emitting element EL. The 6-1st switching element T6-1 includes a gate electrode connected to the second scan line GL2, a first electrode connected to the Vini line, and a second electrode connected to the 4-1st node n4-1.

[0174] The driving element DT drives the light emitting element EL by controlling a current flowing through the light emitting element EL based on the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to the 2-1th node n2-1, a first electrode connected to the 5-1th node n5-1, and a second electrode connected to the 3-1th node n3-1.

[0175] The light emitting element EL is connected between the 4-1 node n4-1 and the ELVSS line. The light emitting element EL can be implemented as an OLED. The OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, an emission layer EML, an electron transport layer ETL, and an electron injection layer EIL, but is not limited thereto. When a voltage is applied to the anode and cathode of the OLED, holes that have passed through the hole transport layer HTL and electrons that have passed through the electron transport layer ETL move to the emission layer EML to form excitons, and thus visible light is emitted from the emission layer EML.

[0176] In the initialization stage Ti, the 5-1th switching element T5-1 is turned on, so that the voltage of the 2-1th node n2-1 is discharged to the initialization voltage Vini.

[0177] In the data writing phase Tw, the 1-1th switching element T1-1, the 2-1th switching element T2-1, and the 6-1th switching element T6-1 are turned on, so that the data voltage is applied to the 5-1th node n5-1 and the voltage of the 2-1th node n2-1 becomes Vdata+Vth. The threshold voltage Vth of the driving element is sensed and charged to the capacitor Cst connected to the 2-1th node n2-1.

[0178] In the light emitting stage Tem, the 3-1st switching element T3-1 and the 4-1st switching element T4-1 are turned on, so that the current flows to the light emitting element EL through the driving element DT, and the light emitting element EL emits light.

[0179] Since the method of implementing the frame skipping is to prevent the output of the strobe signal, the (n-1)th scanning signal and the nth scanning signal among the three signals (i.e., the (n-1)th scanning signal, the nth scanning signal and the EM signal) can be prevented from being output to the Fig.12 This is achieved by pixel circuits of the first pixel. For example, the first-1 switching element T1-1 and the second-1 switching element T2-1, the fifth-1 switching element T5-1 and the sixth-1 switching element T6-1 are turned off, so that the voltages of the second-1 node n2-1 and the third-1 node n3-1 are not initialized when the frame is skipped. Therefore, it is possible to operate the divided areas at different driving frequencies by blocking the gating signal applied to the second area during the frame skip interval.

[0180] Fig.14 is a diagram showing a gate driver according to a second example embodiment. Fig.15A and Fig. 15B It is shown Fig.14 FIG. 5 is a diagram of the driving waveform of the gate driver shown. Fig.16A , Fig. 16B , Fig. 16C and Fig.16D It is shown Fig.14 A diagram showing the operating principle of the gate driver.

[0181] Reference Fig.14 The gate driver according to the second example embodiment of the present disclosure may include a first control node for pulling up the output voltage (hereinafter referred to as a "Q node"), a second control node for pulling down the output voltage (hereinafter referred to as a "Qb node"), a 1-1 circuit portion 61-1, a selection portion 62-1 and a 2-1 circuit portion 63-1.

[0182] The 1-1st circuit portion 61-1 is used to control the charging and discharging of the Q node Q(n) and the Qb node Qb(n). The 1-1st circuit portion 61-1 may include a 1-1st transistor T1-1, a 2-1st transistor T2-1, a 3-1st transistor T3-1, a 4-1st transistor T4-1, a 5-1st transistor T5-1, a 6-1st transistor T6-1 and a 1-1st capacitor c1-1.

[0183] The 1-1th transistor T1-1 is turned on by the second clock signal CLK2 and applies the start signal VST to the 2bth node 2b. The 1-1th transistor T1-1 includes a gate electrode to which the second clock signal CLK2 is applied, a first electrode connected to the 1bth node 1b, and a second electrode connected to the 2bth node 2b.

[0184] The 2-1st transistor T2-1 is turned on by the first clock signal CLK1 and connects the 2bth node 2b to the 4bth node 4b. The 2-1st transistor T2-1 includes a gate electrode connected to the first clock signal CLK1, a first electrode connected to the 2bth node 2b, and a second electrode connected to the 4bth node 4b.

[0185] The 3-1st transistor T3-1 is turned on by the voltage of the second control node Qb(n), and connects the 4b-th node 4b to the first power line PL1 through which the high potential voltage VGH is applied. The 3-1st transistor T3-1 includes a gate electrode connected to the second control node Qb(n), a first electrode connected to the 4b-th node 4b, and a second electrode connected to the first power line PL1.

[0186] The fourth transistor T4-1 is turned on by the second clock signal CLK2 and applies the low potential voltage VGL to the second control node Qb(n). The 4-1 transistor T4-1 includes a gate electrode to which the second clock signal CLK2 is applied, a first electrode connected to the second power line PL2 through which the low potential voltage is applied, and a second electrode connected to the second control node Qb(n).

[0187] The 5-1st transistor T5-1 is turned on by the voltage of the 2b-th node 2b and connects the 3b-th node 3b to the second control node Qb(n). The 5-1st transistor T5-1 includes a gate electrode connected to the 2b-th node 2b, a first electrode connected to the 3b-th node 3b, and a second electrode connected to the second control node Qb(n).

[0188] The 6-1st transistor T6-1 is turned on by the low potential voltage VGL and connects the 2b-th node 2b to the first control node Q(n). The 6-1st transistor T6-1 includes a gate electrode to which the low potential voltage VGL is applied, a first electrode connected to the 2b-th node 2b, and a second electrode connected to the first control node Q(n).

[0189] The 1-1th capacitor c1-1 is connected between the second control node Qb(n) and the first power line PL1.

[0190] The selection part 62-1 is used to apply the high potential voltage VGH to the first control node Q(n) instead of the start signal VST or the previous carry signal C(n-1) in the frame skip interval. The selection part 62-1 may include a 1A-1th transistor T1A-1 and a 1B-1th first transistor T1B-1.

[0191] The 1A-1 first transistor T1A-1 is turned on by the first reset signal RST, so the start signal VST or the previous carry signal C(n-1) is applied to the 1b-th node 1b. The 1A-1 first transistor T1A-1 includes a gate electrode to which the first reset signal RST is applied, a first electrode to which the start signal VST or the previous carry signal C(n-1) is applied, and a second electrode connected to the 1b-th node 1b.

[0192] The 1B-1th transistor T1B-1 is turned on by the second reset signal RSTB having a phase opposite to that of the first reset signal RST, and connects the 1bth node 1b to the first power line PL1 to supply the high potential voltage VGH. The 1B-1th transistor T1B-1 includes a gate electrode to which the second reset signal RSTB is applied, a first electrode connected to the first power line PL1, and a second electrode connected to the 1bth node 1b.

[0193] The 2-1st circuit portion 63-1 may output a scan signal SCAN(n) to the output node OUT based on the potentials of the Q node Q(n) and the Qb node Qb(n). Here, the scan signal SCAN(n) may include a voltage applied to the Q node Q(n). Fig.12 The (n-1)th scan signal SCAN(n-1) and the nth scan signal SCAN(n) of the pixel circuit of the 2-1st circuit portion 63-1 may include a 7-1st transistor T7-1, an 8-1st transistor T8-1, and a 2-1st capacitor C2-1.

[0194] The 7-1st transistor T7-1 is turned on by the voltage of the first control node Q(n) and outputs the first clock signal CLK1 to the output node OUT. The 7-1st transistor T7-1 includes a gate electrode connected to the first control node Q(n), a first electrode to which the first clock signal CLK1 is applied, and a second electrode connected to the output node OUT.

[0195] The 8-1st transistor T8-1 is turned on by the voltage of the second control node Qb(n) and outputs the high potential voltage VGH to the output node OUT. The 8-1st transistor T8-1 includes a gate electrode connected to the second control node Qb(n), a first electrode connected to the output node OUT, and a second electrode connected to the first power line PL1.

[0196] The 2-1st capacitor C2-1 is connected between the gate electrode of the 7-1st transistor T7-1 and the second electrode thereof.

[0197] The gate driver according to example embodiments may perform frame skipping through the reset signals RST and RSTB.

[0198] In the case where frame skipping is not performed, such as Fig.15A As shown, when a low-level first reset signal RST is applied to the 1A-1 transistor T1A-1 to turn on the 1A-1 transistor T1A-1, the start signal VST and the previous carry signal are applied to the 1b node 1b, and when a high-level second reset signal RSTB is applied to the 1B-1 transistor T1B-1 to turn off the 1B-1 transistor T1B-1, a low potential voltage is applied to the 1b node 1b, thereby outputting a high-level scan signal.

[0199] In the case of frame skipping, such as Fig. 15B As shown, when a high-level first reset signal RST is applied to the 1A-1 transistor T1A-1 to turn off the 1A-1 transistor T1A-1, the start signal VST and the previous carry signal are prevented from being applied to the 1b node 1b, and when a low-level second reset signal RSTB is applied to the 1B-1 transistor T1B-1 to turn on the 1B-1 transistor T1B-1, a low-potential voltage is prevented from being applied to the 1b node 1b, thereby outputting a high-level scan signal.

[0200] Since the (n-1)th scanning signal and the (n)th scanning signal are applied from the gate driver to the Fig.12 The pixel circuit is configured so that the 1-1 switching element and the 2-1 switching element are turned off.

[0201] In example embodiments, the first reset signal RST and the second reset signal RSTB may be applied at different periods according to a driving frequency. The data driver also does not apply a data voltage according to the first reset signal RST and the second reset signal RSTB in a frame skip interval.

[0202] For example, when the first area AA1 and the second area AA2 divided for multi-frequency driving are driven at frequencies of 120 Hz and 60 Hz, respectively, the selection driver applies a selection signal to the first area per frame, applies a selection signal to the second area within one frame interval in every two frames through the first reset signal RST and the second reset signal RSTB, and does not apply the selection signal in the remaining frame interval.

[0203] For example, when the first area AA1 and the second area AA2 divided for multi-frequency driving are driven at frequencies of 120 Hz and 30 Hz, respectively, the selection driver applies a selection signal to the first area per frame, applies a selection signal to the second area in one frame interval in every four frames through the first reset signal RST and the second reset signal RSTB, and does not apply the selection signal in the remaining three frame intervals.

[0204] Therefore, it is possible to implement operating the divided areas at different driving frequencies by blocking the gate signal applied to the second area during the frame skip interval.

[0205] refer to FIG. 16A to FIG. 16D , the gate driver according to the example embodiment operates using a driving waveform divided into a first section ①, a second section ②, a third section ③, and a fourth section ④.

[0206] In the first section ①, since the first reset signal is at a low level voltage and the second reset signal is at a high level voltage, the output signal of the gate driver may be at a gate high voltage.

[0207] In the second section ②, since the first reset signal is inverted to a high level voltage and the second reset signal is inverted to a low level voltage, the output signal of the gate driver may be at a gate high voltage.

[0208] In the third section ③, since the voltage of the second control node Qb(n) is in a low level state even if the first reset signal is inverted to a low level voltage and the second reset signal is inverted to a high level voltage, the output signal of the enable driver can be in a enable high voltage.

[0209] In the fourth section ④, since the first reset signal is at a low level voltage and the second reset signal is at a high level voltage, the output signal of the gate driver may be at a gate high voltage.

[0210] Therefore, the gate driver can output the gate high voltage during the first section to the fourth section.

[0211] Fig.17 is a diagram showing a pixel circuit according to a third exemplary embodiment of the present disclosure. Fig.18 It is shown Fig.17 A diagram showing the driving timing of the pixel circuit shown.

[0212] Reference Fig.17 and Fig.18 The pixel circuit according to the third exemplary embodiment of the present disclosure includes a light emitting element EL, a driving element DT for supplying current to the light emitting element EL, a plurality of switching elements T1-2, T3-2, T4-2, T5-2, and T6-2 for switching a current path connected to the driving element DT, and a first capacitor Cst for storing a gate-source voltage of the driving element DT. The driving element DT and the switching elements T1-2, T3-2, T4-2, T5-2, and T6-2 may be implemented as P-channel oxide TFTs.

[0213] The selection signal applied to the pixel circuit includes a first scan signal SCAN1(n), a second scan signal SCAN2(n) and an EM signal EM(n). Here, N is a natural number.

[0214] The capacitor Cst is connected between the 1-2nd node n1-2 and the 2-2nd node n2-2. The 1-2nd node n1-2 is connected to the second electrode of the 3-2nd switching element T3-2, the first electrode of the 5-2nd switching element T5-2, and the first electrode of the capacitor Cst. The 2-2nd node n2-2 is connected to the second electrode of the capacitor Cst, the gate electrode of the driving element DT, and the first electrode of the 1-2nd switching element T1-2.

[0215] The 1-2nd switching element T1-2 is turned on in response to the gate-on voltage VGL of the first scan signal SCAN1(n), and connects the gate electrode of the driving element DT to its second electrode. The 1-2nd switching element T1-2 includes a gate electrode connected to the first scan line GL1, a first electrode connected to the 2-2nd node n2-2, and a second electrode connected to the 3-2nd node n3-2. The first scan signal SCAN1(n) is supplied to the pixel through the first scan line GL1. The 3-2nd node n3-2 connects the second electrode of the driving element DT, the second electrode of the 1-2nd switching element T1-2, and the first electrode of the 4-2nd switching element T4-2.

[0216] The 3-2nd switching element T3-2 is turned on in response to the gate-on voltage VGL of the second scan signal SCAN2(n), and applies the data voltage Vdata to the 1-2nd node n1-2. The 3-2nd switching element T3-2 includes a gate electrode connected to the second scan line GL2, a first electrode connected to the data line 60, and a second electrode connected to the 1-2nd node n1-2.

[0217] The 4-2nd switching element T4-2 is turned on in response to the gate-on voltage VGL of the EM signal EM(n), and connects the second electrode of the driving element DT to the anode electrode of the light emitting element EL. The gate electrode of the 4-2nd switching element T4-2 is connected to the EM line GL3. The first electrode of the 4-2nd switching element T4-2 is connected to the 3-2nd node n3-2, and the second electrode of the 4-2nd switching element T4-2 is connected to the 4-2nd node n4-2. The 4-2nd node n4-2 is connected to the anode electrode of the light emitting element EL, the second electrode of the 4-2nd switching element T4-2, and the second electrode of the 6-2nd switching element T6-2.

[0218] The 5-2nd switching element T5-2 is turned on in response to the gate-on voltage VGL of the EM signal EM(n), and connects the 1-2nd node n1-2 to the Vref line 66. The 5-2nd switching element T5-2 includes a gate electrode connected to the EM line GL3, a first electrode connected to the 1-2nd node n1-2, and a second electrode connected to the Vref line 66. The reference voltage Vref is supplied to the pixel through the Vref line 66.

[0219] The 6-2nd switching element T6-2 is turned on in response to the gate-on voltage VGL of the first scan signal SCAN1(n), and connects the Vref line 66 to the anode electrode of the light emitting element EL. The 6-2nd switching element T6-2 includes a gate electrode connected to the first scan line GL1, a first electrode connected to the Vref line 66, and a second electrode connected to the 4-2nd node n4-2.

[0220] In the initialization phase Ti, the 1-2nd switching element T1-2, the 4-2nd switching element T4-2, the 5-2nd switching element T5-2 and the 6-2nd switching element T6-2 are turned on so that the voltages at the 1-2nd node n1-2 and the 4-2nd node n4-2 are discharged to the reference voltage Vref.

[0221] In the data writing phase Tw, the 1-2nd switching element T1-2, the 3-2nd switching element T3-2 and the 6-2nd switching element T6-2 are turned on, so that the data voltage is applied to the 1-2nd node n1-2, and the voltage at the 2-2nd node n2-2 becomes Vref-Vdata+ELVDD+Vth. The threshold voltage Vth of the driving element is sensed and charged to the capacitor Cst connected to the 2-2nd node n2-2.

[0222] In the light emitting stage Tem, the 4-2nd switching element T4-2 and the 5-2nd switching element T5-2 are turned on, so that the current flows to the light emitting element EL through the driving element DT, and the light emitting element EL emits light.

[0223] Since the method for implementing frame skipping is to prevent the output of the strobe signal, it is possible to prevent all three signals (i.e., the first scanning signal, the second scanning signal and the EM signal) from being output to the Fig.17 For example, the 1-2nd switching element T1-2, the 3-2nd switching element T3-2 and the 6-2nd switching element T6-2 are turned off, so that the voltages at the 2-2nd node n2-2 and the 3-2nd node n3-2 are not initialized during frame skipping.

[0224] In this case, the gate driver outputting the first scanning signal to the second scanning signal can be implemented as Figure 7 The circuit and the gate driver that outputs the EM signal can be realized as Fig.14 circuit.

[0225] Depending on the structure of the pixel circuit and whether PMOS / NMOS transistors are used, it may be necessary to apply Figure 7 The circuit Fig.14 Circuit or Figure 7 and Fig.14 Since all current display devices have gate drivers composed of Figure 7 and Fig.14 Therefore, when the gate driver proposed in the present disclosure is applied, frame skipping is possible regardless of the structure of the pixel circuit and whether PMOS / NMOS transistors are used.

[0226] According to example embodiments of the present disclosure, the present disclosure may also be described as follows:

[0227] According to an example embodiment of the present disclosure, a gating driver includes: a plurality of signal transmitters, the plurality of signal transmitters being relatedly connected via carry lines, through which a carry signal is applied from a previous signal transmitter, wherein each of the plurality of signal transmitters includes: a first circuit portion, the first circuit portion being configured to receive the carry signal from the previous signal transmitter, and to charge or discharge a first control node and a second control node; a second circuit portion, the second circuit portion being configured to output a gating signal based on voltages at the first control node and the second control node; and a selection portion, the selection portion being configured to invert a voltage applied to a first node during a frame skip interval of a partial area in a pixel array driven at a predetermined frame frequency, and to charge the first control node using the voltage of the first node.

[0228] The selection unit is used to apply a low potential voltage to the first control node during the frame skipping interval.

[0229] The selection unit includes a 1A transistor and a 1B transistor, the 1A transistor including a gate electrode to which a first reset signal is applied, a first electrode to which a start signal or the carry signal is applied, and a second electrode connected to the first node, and the 1B transistor including a gate electrode to which a second reset signal having a phase opposite to that of the first reset signal is applied, a first electrode connected to a second power line to which a low potential voltage is applied, and a second electrode connected to the first node.

[0230] The 1A transistor is turned on by the first reset signal so that the start signal or the carry signal is applied to the first node, and the 1B transistor is turned on by the second reset signal and connects the first node to a second power line to supply the low potential voltage.

[0231] The first reset signal and the second reset signal are applied in the form of a pulse voltage, a direct current voltage or a clock voltage.

[0232] The first circuit portion includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor, and a second capacitor, the first transistor including a gate electrode connected to a fourth node to which a clock signal is applied, a first electrode connected to the first node, and a second electrode connected to the second node, the second transistor including a gate electrode connected to the first node, a first electrode connected to a third node, and a second electrode connected to a first power line, wherein a high potential voltage is applied through the first power line, the third transistor including a gate electrode connected to the third node, a first electrode connected to the fourth node, and a second electrode connected to the second control node, the fourth transistor including a gate electrode connected to the second node, a first electrode connected to the second control node, and a second electrode connected to the first power line, the fifth transistor including a gate electrode connected to the second power line, a first electrode connected to the second node, and a second electrode connected to the first control node, the first capacitor is connected between the third node and the fourth node, and the second capacitor is connected between the second control node and the first power line.

[0233] The second circuit portion includes a sixth transistor, a seventh transistor and a third capacitor, the sixth transistor including a gate electrode connected to the first control node, a first electrode connected to the second power line and a second electrode connected to an output node, the seventh transistor including a gate electrode connected to the second control node, a first electrode connected to the output node and a second electrode connected to the first power line, and the third capacitor is connected between the gate electrode of the sixth transistor and the second electrode of the sixth transistor.

[0234] The selection section is used to apply a high potential voltage to the first control node during the frame skipping interval.

[0235] The selection unit includes a 1A transistor and a 1B transistor, the 1A transistor including a gate electrode to which a first reset signal is applied, a first electrode to which a start signal or the carry signal is applied, and a second electrode connected to the first node, and the 1B transistor including a gate electrode to which a second reset signal having a phase opposite to that of the first reset signal is applied, a first electrode connected to a first power line, and a second electrode connected to the first node, wherein a high potential voltage is applied through the first power line.

[0236] The 1A transistor is turned on by the first reset signal so that the start signal or the carry signal is applied to the first node, and the 1B transistor is turned on by the second reset signal and connects the first node to the first power line to supply the high potential voltage.

[0237] The first circuit portion includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a first capacitor, the first transistor including a gate electrode connected to a third node to which a second clock signal is applied, a first electrode connected to the first node and a second electrode connected to the second node, the second transistor including a gate electrode to which a first clock signal is applied, a first electrode connected to the second node and a second electrode connected to a fourth node, the third transistor including a gate electrode connected to the second control node, a first electrode connected to the fourth node and a second electrode connected to the first power line, the fourth transistor including a gate electrode connected to the third node, a first electrode connected to the second power line and a second electrode connected to the second control node, the fifth transistor including a gate electrode connected to the second node, a first electrode connected to the third node and a second electrode connected to the second control node, the sixth transistor including a gate electrode connected to the second power line, a first electrode connected to the second node and a second electrode connected to the first control node, and the first capacitor is connected between the second control node and the first power line.

[0238] The second circuit portion includes a seventh transistor, an eighth transistor and a second capacitor, the seventh transistor including a gate electrode connected to the first control node, a first electrode to which the first clock signal is applied, and a second electrode connected to an output node, the eighth transistor including a gate electrode connected to the second control node, a first electrode connected to the output node, and a second electrode connected to the first power line, and the second capacitor is connected between the gate electrode of the seventh transistor and the second electrode of the seventh transistor.

[0239] According to an example embodiment of the present disclosure, a display device includes: a pixel array, in which a plurality of data lines, a plurality of gate lines and a plurality of pixel circuits are arranged; and a gate driver, the gate driver being configured to output a gate signal to the plurality of gate lines, wherein the pixel array includes a first pixel array driven at a first frame frequency and a second pixel array driven at a second frame frequency lower than the first frame frequency, and wherein the gate driver outputs the gate signal as a gate-off voltage during a frame skip interval of the second pixel array.

[0240] The display device further includes a data driver configured to output data voltages to the plurality of data lines, wherein the data driver does not output the data voltages during the frame skip interval.

[0241] The first pixel array and the second pixel array share the plurality of data lines with each other, but do not share the plurality of gate lines with each other.

[0242] The display device further includes a timing controller configured to output a timing control signal for controlling the data driver and the gate driver according to the first frame frequency and the second frame frequency.

[0243] Although the example embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the example embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-mentioned example embodiments are illustrative in all aspects and do not limit the present disclosure.

[0244] CROSS-REFERENCE TO RELATED APPLICATIONS

[0245] This application claims the benefit of priority to Korean Patent Application No. 10-2023-0132315 filed on October 5, 2023, which is hereby expressly incorporated herein in its entirety for all purposes.

Claims

1. A gate driver, comprising: a plurality of signal transmitters, the plurality of signal transmitters being relatedly connected via a carry line through which a carry signal is applied from a previous signal transmitter, Wherein, each of the plurality of signal transmitters comprises: a first circuit portion configured to receive the carry signal from the previous signal transmitter and charge or discharge a first control node and a second control node; a second circuit portion configured to output a gating signal based on voltages at the first control node and the second control node; and A selection section configured to invert a voltage applied to a first node during a frame skip interval of a partial area in a pixel array driven at a predetermined frame frequency and charge the first control node with the voltage of the first node.

2. The gate driver according to claim 1, wherein: The selection unit includes a 1A transistor and a 1B transistor, The 1Ath transistor includes a gate electrode to which a first reset signal is applied, a first electrode to which a start signal or the carry signal is applied, and a second electrode connected to the first node, and The 1B-th transistor includes a gate electrode to which a second reset signal having a phase opposite to that of the first reset signal is applied, a first electrode connected to a second power line to which a low potential voltage is applied, and a second electrode connected to the first node.

3. The gate driver according to claim 2, wherein: The first reset signal and the second reset signal are applied in the form of a pulse voltage, a direct current voltage or a clock voltage.

4. The gate driver according to claim 2, wherein: The first circuit portion includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor and a second capacitor, wherein the first transistor includes a gate electrode connected to a fourth node to which a clock signal is applied, a first electrode connected to the first node, and a second electrode connected to a second node, The second transistor includes a gate electrode connected to the first node, a first electrode connected to a third node, and a second electrode connected to a first power line, wherein a high potential voltage is applied through the first power line, The third transistor includes a gate electrode connected to the third node, a first electrode connected to the fourth node, and a second electrode connected to the second control node, The fourth transistor includes a gate electrode connected to the second node, a first electrode connected to the second control node, and a second electrode connected to the first power line, The fifth transistor includes a gate electrode connected to the second power line, a first electrode connected to the second node, and a second electrode connected to the first control node. The first capacitor is connected between the third node and the fourth node, and The second capacitor is connected between the second control node and the first power line.

5. The gate driver according to claim 4, wherein: the second circuit portion includes a sixth transistor, a seventh transistor and a third capacitor, wherein the sixth transistor includes a gate electrode connected to the first control node, a first electrode connected to the second power line, and a second electrode connected to the output node, The seventh transistor includes a gate electrode connected to the second control node, a first electrode connected to the output node, and a second electrode connected to the first power line, and The third capacitor is connected between the gate electrode of the sixth transistor and the second electrode of the sixth transistor.

6. The gate driver according to claim 1, wherein: The selection unit includes a 1A transistor and a 1B transistor, The 1Ath transistor includes a gate electrode to which a first reset signal is applied, a first electrode to which a start signal or the carry signal is applied, and a second electrode connected to the first node. The 1B-th transistor includes a gate electrode to which a second reset signal having a phase opposite to that of the first reset signal is applied, a first electrode connected to a first power line through which a high potential voltage is applied, and a second electrode connected to the first node.

7. The gate driver according to claim 6, wherein: The first circuit portion includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a first capacitor, wherein the first transistor includes a gate electrode connected to a third node to which a second clock signal is applied, a first electrode connected to the first node, and a second electrode connected to a second node, The second transistor includes a gate electrode to which the first clock signal is applied, a first electrode connected to the second node, and a second electrode connected to a fourth node. The third transistor includes a gate electrode connected to the second control node, a first electrode connected to the fourth node, and a second electrode connected to the first power line, The fourth transistor includes a gate electrode connected to the third node, a first electrode connected to the second power line, and a second electrode connected to the second control node, The fifth transistor includes a gate electrode connected to the second node, a first electrode connected to the third node, and a second electrode connected to the second control node, The sixth transistor includes a gate electrode connected to the second power line, a first electrode connected to the second node, and a second electrode connected to the first control node, and The first capacitor is connected between the second control node and the first power line.

8. The gate driver according to claim 7, wherein: the second circuit portion includes a seventh transistor, an eighth transistor and a second capacitor, wherein the seventh transistor includes a gate electrode connected to the first control node, a first electrode to which the first clock signal is applied, and a second electrode connected to an output node, The eighth transistor includes a gate electrode connected to the second control node, a first electrode connected to the output node, and a second electrode connected to the first power line, and The second capacitor is connected between the gate electrode of the seventh transistor and the second electrode of the seventh transistor.

9. A display device, comprising: A pixel array, wherein a plurality of data lines, a plurality of gate lines and a plurality of pixel circuits are arranged in the pixel array; as well as a gate driver configured to output a gate signal to the plurality of gate lines, The pixel array includes a first pixel array driven at a first frame frequency and a second pixel array driven at a second frame frequency lower than the first frame frequency, and The gate driver outputs the gate signal as a gate-off voltage during a frame skipping interval of the second pixel array.

10. The display device according to claim 9, further comprising a data driver configured to output data voltages to the plurality of data lines, in, The data driver does not output the data voltage during the frame skip interval.

11. The display device according to claim 10, wherein: The first pixel array and the second pixel array share the plurality of data lines with each other, but do not share the plurality of gate lines with each other.

12. The display device according to claim 10, further comprising: A timing controller configured to output a timing control signal for controlling the data driver and the gate driver according to the first frame frequency and the second frame frequency.

13. The display device according to claim 9, wherein: The gate driver includes a plurality of signal transmitters connected in relation to each other via a carry line through which a carry signal is applied from a previous signal transmitter, Wherein, each of the plurality of signal transmitters comprises: a first circuit portion configured to receive the carry signal from the previous signal transmitter and charge or discharge a first control node and a second control node; a second circuit portion configured to output a gating signal based on voltages at the first control node and the second control node; and A selection section configured to invert a voltage applied to a first node during the frame skip interval and charge the first control node with the voltage of the first node.

14. The display device according to claim 13, wherein: The selection unit includes a 1A transistor and a 1B transistor, The 1Ath transistor includes a gate electrode to which a first reset signal is applied, a first electrode to which a start signal or the carry signal is applied, and a second electrode connected to the first node, and The 1B-th transistor includes a gate electrode to which a second reset signal having a phase opposite to that of the first reset signal is applied, a first electrode connected to a second power line to which a low potential voltage is applied, and a second electrode connected to the first node.

15. The display device according to claim 14, wherein: The first reset signal and the second reset signal are applied in the form of a pulse voltage, a direct current voltage or a clock voltage.

16. The display device according to claim 14, wherein: The first circuit portion includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor and a second capacitor, wherein the first transistor includes a gate electrode connected to a fourth node to which a clock signal is applied, a first electrode connected to the first node, and a second electrode connected to a second node, The second transistor includes a gate electrode connected to the first node, a first electrode connected to a third node, and a second electrode connected to a first power line, wherein a high potential voltage is applied through the first power line, The third transistor includes a gate electrode connected to the third node, a first electrode connected to the fourth node, and a second electrode connected to the second control node, The fourth transistor includes a gate electrode connected to the second node, a first electrode connected to the second control node, and a second electrode connected to the first power line, The fifth transistor includes a gate electrode connected to the second power line, a first electrode connected to the second node, and a second electrode connected to the first control node. The first capacitor is connected between the third node and the fourth node, and The second capacitor is connected between the second control node and the first power line.

17. The display device according to claim 16, wherein: the second circuit portion includes a sixth transistor, a seventh transistor and a third capacitor, wherein the sixth transistor includes a gate electrode connected to the first control node, a first electrode connected to the second power line, and a second electrode connected to the output node, The seventh transistor includes a gate electrode connected to the second control node, a first electrode connected to the output node, and a second electrode connected to the first power line, and The third capacitor is connected between the gate electrode of the sixth transistor and the second electrode of the sixth transistor.

18. The display device according to claim 13, wherein: The selection unit includes a 1A transistor and a 1B transistor, The 1Ath transistor includes a gate electrode to which a first reset signal is applied, a first electrode to which a start signal or the carry signal is applied, and a second electrode connected to the first node. The 1B-th transistor includes a gate electrode to which a second reset signal having a phase opposite to that of the first reset signal is applied, a first electrode connected to a first power line through which a high potential voltage is applied, and a second electrode connected to the first node.

19. The display device according to claim 18, wherein: The first circuit portion includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a first capacitor, wherein the first transistor includes a gate electrode connected to a third node to which a second clock signal is applied, a first electrode connected to the first node, and a second electrode connected to a second node, The second transistor includes a gate electrode to which the first clock signal is applied, a first electrode connected to the second node, and a second electrode connected to a fourth node. The third transistor includes a gate electrode connected to the second control node, a first electrode connected to the fourth node, and a second electrode connected to the first power line, The fourth transistor includes a gate electrode connected to the third node, a first electrode connected to the second power line, and a second electrode connected to the second control node, The fifth transistor includes a gate electrode connected to the second node, a first electrode connected to the third node, and a second electrode connected to the second control node, The sixth transistor includes a gate electrode connected to the second power line, a first electrode connected to the second node, and a second electrode connected to the first control node, and The first capacitor is connected between the second control node and the first power line.

20. The display device according to claim 19, wherein: the second circuit portion includes a seventh transistor, an eighth transistor and a second capacitor, wherein the seventh transistor includes a gate electrode connected to the first control node, a first electrode to which the first clock signal is applied, and a second electrode connected to an output node, The eighth transistor includes a gate electrode connected to the second control node, a first electrode connected to the output node, and a second electrode connected to the first power line, and The second capacitor is connected between the gate electrode of the seventh transistor and the second electrode of the seventh transistor.

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