Display device

Abstract

A display device includes a display panel including a plurality of sub-pixels, a source film connected to one side of the display panel and on which a source driving integrated circuit supplying a data voltage to the display panel is implemented, and a source printed circuit board on which the source driving integrated circuit supplies the data voltage to the display panel, a low-potential voltage line for transmitting a reference voltage to the display panel through the source film is disposed on the source printed circuit board in a closed-loop structure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0131391, filed on October 4, 2023, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Embodiments of the present disclosure relate to a display device, and more particularly, to a display device capable of reducing heat generated in a display panel by forming a low-potential voltage line disposed on a source printed circuit board in a closed loop structure. Background Art

[0004] As the information society develops, various demands for display devices that display images are increasing, and various types of display devices such as liquid crystal displays (LCDs), organic light emitting displays (OLEDs), etc. are being utilized.

[0005] Among these display devices, an organic light emitting display device uses a self-luminous organic light emitting diode, providing advantages such as quick response and better contrast, light emitting efficiency, brightness, and viewing angle.

[0006] An organic light emitting display device may include organic light emitting diodes respectively arranged in a plurality of sub-pixels provided on a display panel, and emit light by controlling current flowing to the organic light emitting diodes, thereby displaying an image while controlling the brightness of each sub-pixel.

[0007] As these display devices display higher brightness, higher current is supplied to the display panel through the low potential voltage line, which may lead to the problem of increased heating of the display panel. Summary of the invention

[0008] Therefore, the inventors of the present disclosure have invented a display device capable of reducing heat generated in a display panel.

[0009] Embodiments of the present disclosure may provide a display device capable of reducing heat generated in a display panel and operating at low power by forming a low potential voltage line disposed on a source printed circuit board in a closed loop structure.

[0010] An embodiment of the present disclosure provides a display device, which includes a display panel, a source film and a source printed circuit board. The display panel includes a plurality of sub-pixels. The source film is connected to one side of the display panel, and a source driver integrated circuit for providing a data voltage to the display panel is implemented on the source film. A low-potential voltage line for transmitting a reference voltage (base voltage) to the display panel through the source film is arranged on the source printed circuit board in a closed-loop structure.

[0011] According to the embodiments of the present disclosure, the heat generated in the display panel can be reduced.

[0012] According to an embodiment of the present disclosure, it is possible to reduce heat generated in a display panel and operate at low power by forming a low potential voltage line disposed on a source printed circuit board in a closed loop structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other objects, features and advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0014] Figure 1 is a diagram schematically showing a display device according to an embodiment of the present disclosure;

[0015] Figure 2 is a system example diagram showing a display device according to an embodiment of the present disclosure;

[0016] Figure 3 is a diagram showing an example of a circuit constituting a sub-pixel in a display device according to an embodiment of the present disclosure;

[0017] Figure 4 is a diagram specifically showing a source film connecting a source printed circuit board to a display panel in a display device according to an embodiment of the present disclosure;

[0018] Figure 5 is a diagram showing a structure of a low potential voltage line formed on a source printed circuit board in a display device according to an embodiment of the present disclosure;

[0019] Figure 6 is a diagram showing a structure in which the width of a low potential voltage line varies according to a position in a display device according to an embodiment of the present disclosure;

[0020] Figures 7A to 7D is an experimental diagram showing a signal characteristic according to a width of a low potential voltage line in a display device according to an embodiment of the present disclosure;

[0021] Figure 8 is a conceptual diagram showing a multi-layer source printed circuit board in a display device according to an embodiment of the present disclosure;

[0022] Fig.9A and 9B A temperature graph measured in a display panel for a case where a low potential voltage line having an open structure is formed on a source printed circuit board and a case where a low potential voltage line having a closed loop structure is formed on a source printed circuit board in a display device according to an embodiment of the present disclosure is shown; and

[0023] Fig.10 is a diagram showing a case where a low potential connection line extending from a low potential voltage line of a source printed circuit board is formed in a double structure in a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to exemplary drawings. In the following description of examples or embodiments of the present disclosure, reference will be made to the drawings, in which specific examples or embodiments that can be implemented are shown by way of illustration, and in which even when the same or similar parts are shown in different drawings from each other, the same reference numerals and symbols can be used to represent the same or similar parts. In addition, in the following description of examples or embodiments of the present disclosure, when it is determined that the detailed description of the well-known functions and parts incorporated herein may make the subject matter in some embodiments of the present disclosure unclear, its description will be omitted. Terms such as "including", "having", "containing", "constituting", "consisting of" and "formed by" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only". As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0025] Terms such as "first", "second", "A", "B", "(A)" or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to define the nature, order, sequence or quantity of an element, etc., but is only used to distinguish the corresponding element from other elements.

[0026] When it is mentioned that a first element is “connected or coupled”, “contacted or overlapped”, etc. with a second element, it should be interpreted that not only the first element can be “directly connected or coupled” or “directly contacted or overlapped” with the second element, but also a third element can be “inserted” between the first element and the second element, or the first element and the second element can be “connected or coupled”, “contacted or overlapped”, etc. with each other via a fourth element. Here, the second element can be included in at least one of the two or more elements that are “connected or coupled”, “contacted or overlapped”, etc. with each other.

[0027] When time relative terms such as “after,” “subsequently,” “next,” “before,” etc. are used to describe a process or operation of an element or configuration, or a flow or step in an operation, process, or method of manufacture, these terms may be used to describe non-sequential or non-sequential processes or operations unless the terms “directly” or “immediately” are used together.

[0028] In addition, when any dimension, relative size, etc. is mentioned, even when no relevant description is specified, the numerical value or corresponding information (e.g., level, range, etc.) of the element or feature should be considered to include tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term "may" fully encompasses all meanings of the term "can".

[0029] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0030] Figure 1 is a diagram schematically showing a display device according to an embodiment of the present disclosure.

[0031] refer to Figure 1 , the display device 100 according to an embodiment of the present disclosure may include a display panel 110 and a driving circuit for driving the display panel 110 .

[0032] The display panel 110 may include a display area DA where an image is displayed and a bezel area BA where no image is displayed. The bezel area BA may also be referred to as a non-display area.

[0033] The display panel 110 may include a plurality of sub-pixels SP for displaying an image. For example, a plurality of sub-pixels SP may be disposed in the display area DA. In some cases, at least one sub-pixel SP may be disposed in the border area BA. At least one sub-pixel SP disposed in the border area BA is also referred to as a dummy sub-pixel.

[0034] The display panel 110 may also include a plurality of signal lines for driving the plurality of sub-pixels SP. For example, the plurality of signal lines may include a plurality of data lines DL and a plurality of gate lines GL. Depending on the structure of the sub-pixels SP, the signal lines may also include other signal lines in addition to the plurality of data lines DL and the plurality of gate lines GL. For example, the other signal lines may include a driving voltage line and a reference voltage line.

[0035] A plurality of data lines DL and a plurality of gate lines GL may cross each other. Each of the plurality of data lines DL may be arranged while extending in a first direction. Each of the plurality of gate lines GL may be arranged while extending in a second direction. Here, the first direction may be a column direction, and the second direction may be a row direction. In the present disclosure, the column direction and the row direction are relative. For example, the column direction may be a vertical direction, and the row direction may be a horizontal direction. As another example, the column direction may be a horizontal direction, and the row direction may be a vertical direction.

[0036] The driving circuit may include a data driving circuit 130 for driving a plurality of data lines DL and a gate driving circuit 120 for driving a plurality of gate lines GL. The driving circuit may further include a timing controller 140 for controlling the data driving circuit 130 and the gate driving circuit 120.

[0037] The data driving circuit 130 is a circuit for driving a plurality of data lines DL, and can output data signals (also referred to as data voltages) corresponding to image signals to the plurality of data lines DL. The gate driving circuit 120 is a circuit for driving a plurality of gate lines GL, and can generate gate signals and output the gate signals to the plurality of gate lines GL. The gate signals may include one or more scanning signals and light emitting signals.

[0038] The timing controller 140 may start scanning according to the timing implemented in each frame, and may control data driving at an appropriate time according to scanning. The timing controller 140 may convert input image data input from the outside to a data signal format suitable for use by the data driving circuit 130, and provide the converted image data DATA to the data driving circuit 130.

[0039] The timing controller 140 may receive a display driving control signal and input image data from the external host system 200. For example, the display driving control signal may include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, and a clock signal.

[0040] The timing controller 140 may generate a data driving control signal DCS and a gate driving control signal GCS based on a display driving control signal input from the host system 200. The timing controller 140 may control a driving operation and a driving timing of the data driving circuit 130 by providing the data driving control signal DCS to the data driving circuit 130. The timing controller 140 may control a driving operation and a driving timing of the gate driving circuit 120 by providing the gate driving control signal GCS to the gate driving circuit 120.

[0041] The data driving circuit 130 may include one or more source driving integrated circuits SDIC (see Figure 2). Each source driver integrated circuit may include a shift register, a latch circuit, a digital-to-analog converter (DAC), an output buffer, etc. In some cases, each source driver integrated circuit may also include an analog-to-digital converter (ADC).

[0042] For example, each source driver integrated circuit can be connected to the display panel 110 via a tape automated bonding (TAB) method, or connected to a bonding pad of the display panel 110 via a chip on glass (COG) or chip on panel (COP) method, or can be implemented and connected to the display panel 110 via a chip on film (COF) method.

[0043] The gate driving circuit 120 may output a gate signal of an on-level voltage or a gate signal of an off-level voltage according to the control of the timing controller 140. The gate driving circuit 120 may sequentially drive the plurality of gate lines GL by sequentially providing the gate signal of an on-level voltage to the plurality of gate lines GL.

[0044] The gate drive circuit 120 may include one or more gate drive integrated circuits GDIC (see Figure 2 ).

[0045] The gate drive circuit 120 may be connected to the display panel 110 by a TAB method, or connected to a bonding pad of the display panel 110 by a COG or COP method, or may be connected to the display panel 110 according to a COF method. Alternatively, the gate drive circuit 120 may be formed in a frame area BA of the display panel 110 in a gate in panel (GIP) type. The gate drive circuit 120 may be disposed on a substrate or may be connected to a substrate. That is, a gate drive circuit 120 of a GIP type may be disposed in a frame area BA of a substrate. A gate drive circuit 120 of a chip on glass (COG) type or a chip on film (COF) type may be connected to a substrate.

[0046] Meanwhile, at least one of the data driving circuit 130 and the gate driving circuit 120 may be disposed in the display area DA. For example, at least one of the data driving circuit 130 and the gate driving circuit 120 may be disposed not to overlap with the subpixels SP, or to overlap with all or some of the subpixels SP.

[0047] The data driving circuit 130 may be connected to one side (e.g., the upper side or the lower side) of the display panel 110. The data driving circuit 130 may be connected to both sides (e.g., the upper side and the lower side) of the self-luminous display panel 110, or to two or more of the four sides of the self-luminous display panel 110, depending on a driving scheme or a panel design scheme.

[0048] The gate driving circuit 120 may be connected to one side (e.g., the left side or the right side) of the display panel 110. Depending on a driving scheme or a panel design scheme, the gate driving circuit 120 may be connected to both sides (e.g., the left side and the right side) of the display panel 110, or to two or more of the four sides of the display panel 110.

[0049] The timing controller 140 may be implemented as a component separated from the data driving circuit 130, or the timing controller 140 and the data driving circuit 130 may be integrated into an integrated circuit (IC). The timing controller 140 may be a controller used in a typical display technology, or a control device that may perform other control functions as well as the function of the timing controller, or a circuit in a control device. The timing controller 140 may be implemented as various circuits or electronic components, such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor.

[0050] The timing controller 140 may be mounted on a printed circuit board or a flexible printed circuit, and may be electrically connected to the data driving circuit 130 and the gate driving circuit 120 through the printed circuit board or the flexible printed circuit. The timing controller 140 may transmit / receive signals to / from the data driving circuit 130 according to one or more predetermined interfaces. The interface may include, for example, a low voltage differential signaling (LVDS) interface, an EPI interface, and a serial peripheral interface (SP).

[0051] The display device 100 according to an embodiment of the present disclosure may be a self-luminous display device in which the display panel 110 emits light by itself. When the display device 100 according to an embodiment of the present disclosure is a self-luminous display device, each of the plurality of sub-pixels SP may include a light-emitting element. For example, the display device 100 according to an embodiment of the present disclosure may be an organic light-emitting diode display, in which the light-emitting element is implemented as an organic light-emitting diode (OLED). As another example, the display device 100 according to an embodiment of the present disclosure may be an inorganic light-emitting display device, in which the light-emitting element is implemented as a light-emitting diode based on an inorganic material. As another example, the display device 100 according to an embodiment of the present disclosure may be a quantum dot display device, in which the light-emitting element is implemented as a quantum dot, which is a self-luminous semiconductor crystal.

[0052] Figure 2 is a system example diagram showing a display device according to an embodiment of the present disclosure.

[0053] Figure 2An example is shown in which, in a display device 100 according to an embodiment of the present disclosure, the data driving circuit 130 is implemented by a chip-on-film (COF) type among various types (e.g., TAB, COG, and COF), and the gate driving circuit 120 is implemented by a gate-in-panel (GIP) type among various types (e.g., TAB, COG, COF, and GIP).

[0054] When the gate driving circuit 120 is implemented in a GIP type, a plurality of gate driving integrated circuits GDIC included in the gate driving circuit 120 may be directly formed in the bezel region of the display panel 110. In this case, the gate driving integrated circuit GDIC may receive various signals (e.g., clock, gate high signal, gate low signal, etc.) required to generate a scan signal through a gate driving-related signal line provided in the bezel region.

[0055] Similarly, one or more source driver integrated circuits SDIC included in the data driver circuit 130 may each be mounted on the source film SF, and one side of the source film SF may be electrically connected to one side of the display panel 110. Lines for electrically connecting the source driver integrated circuit SDIC and the display panel 110 may be provided on the source film SF. In one embodiment, the display device 100 includes the following: Figure 2 A plurality of source films SF are shown, and a corresponding one of the source driver integrated circuits SDIC is mounted on each source film SF.

[0056] The display device 100 may include at least one source printed circuit board SPCB for circuit connection between a plurality of source driving integrated circuits SDIC and other devices, and a control printed circuit board CPCB for mounting control parts and various electrical devices.

[0057] The other side of the source film SF on which the source driver integrated circuit SDIC is provided may be connected to at least one source printed circuit board SPCB. That is, one side of the source film SF on which the source driver integrated circuit SDIC is mounted may be electrically connected to the display panel 110, and the other side of the source film may be electrically connected to the source printed circuit board SPCB.

[0058] The timing controller 140 and the power management circuit 150 may be mounted on the control printed circuit board CPCB. The timing controller 140 may control the operations of the data driving circuit 130 and the gate driving circuit 120. The power management circuit 150 may provide a driving voltage or current to the display panel 110, the data driving circuit 130, and the gate driving circuit 120, and control the provided voltage or current.

[0059] At least one source printed circuit board SPCB and a control printed circuit board CPCB may be circuit-connected by at least one connecting member. The connecting member may include, for example, a flexible printed circuit FPC or a flexible flat cable FFC. At least one source printed circuit board SPCB and a control printed circuit board CPCB may be integrated into a single printed circuit board.

[0060] The display device 100 may further include a setting board 170 electrically connected to the control printed circuit board CPCB. In this case, the setting board 170 may be referred to as a power distribution board. A main power management circuit 160 for managing the total power supply of the display device 100 may exist on the setting board 170. The main power management circuit 160 may interact with the power management circuit 150.

[0061] In the display device 100 thus configured, a driving voltage is generated in the setting board 170 and transmitted to the power management circuit 150 in the control printed circuit board CPCB. The power management circuit 150 transmits the driving voltage required for display driving or characteristic value sensing to the source printed circuit board SPCB through the flexible printed circuit FPC or the flexible flat cable FFC. The driving voltage transmitted to the source printed circuit board SPCB is provided to emit light or sense a specific sub-pixel SP in the display panel 110 through the source drive integrated circuit SDIC.

[0062] Each sub-pixel SP arranged in the display panel 110 in the display device 100 may include a light emitting element and a circuit element for driving an organic light emitting diode, such as a driving transistor.

[0063] The type and number of circuit elements constituting each sub-pixel SP may vary depending on the functions to be provided and the design scheme.

[0064] Figure 3 is a diagram showing an example of a circuit constituting a sub-pixel in a display device according to an embodiment of the present disclosure.

[0065] refer to Figure 3 In the display device 100 according to an embodiment of the present disclosure, the sub-pixel SP may include one or more transistors and capacitors and an organic light emitting diode (OLED) as a light emitting element ED.

[0066] For example, the sub-pixel SP may include a driving transistor DRT, a switching transistor SWT, a sensing transistor SENT, a storage capacitor Cst, and a light emitting element ED.

[0067] The driving transistor DRT includes a first node N1, a second node N2, and a third node N3. The first node N1 of the driving transistor DRT may be a gate node to which a data voltage Vdata is provided from the data driving circuit 130 through the data line DL when the switching transistor SWT is turned on. The second node N2 of the driving transistor DRT may be electrically connected to the anode electrode of the light emitting element ED, and may be a source node or a drain node. The third node N3 of the driving transistor DRT may be electrically connected to a high potential voltage line DVL that provides a high potential sub-pixel driving voltage EVDD greater than a low potential reference voltage EVSS, and may be a drain node or a source node.

[0068] In this case, during the display driving period, the sub-pixel driving voltage EVDD required for displaying an image may be supplied to the driving voltage line DVL. For example, the sub-pixel driving voltage EVDD required for displaying an image may be 27V.

[0069] The switching transistor SWT is electrically connected between the first node N1 of the driving transistor DRT and the data line DL, and the gate line GL is connected to the gate node. Therefore, the switching transistor SWT is operated according to the scan signal SCAN provided through the gate line GL. When turned on, the switching transistor SWT transmits the data voltage Vdata provided through the data line DL to the gate node of the driving transistor DRT, thereby controlling the operation of the driving transistor DRT.

[0070] The sensing transistor SENT is electrically connected between the second node N2 of the driving transistor DRT and the reference voltage line RVL, and the gate line GL is connected to the gate node. The sensing transistor SENT is operated according to the sensing signal SENSE provided through the gate line GL. When the sensing transistor SENT is turned on, the sensing reference voltage Vref provided through the reference voltage line RVL is transmitted to the second node N2 of the driving transistor DRT.

[0071] That is, when the switching transistor SWT and the sensing transistor SENT are controlled, the voltage of the first node N1 and the voltage of the second node N2 of the driving transistor DRT are controlled so that a current for driving the light emitting element ED can be provided.

[0072] The gate nodes of the switching transistor SWT and the sensing transistor SENT may be connected to one gate line GL in common, or may be connected to different gate lines GL. An example is shown in which the switching transistor SWT and the sensing transistor SENT are connected to different gate lines GL, in which case the switching transistor SWT and the sensing transistor SENT may be independently controlled by a scan signal SCAN and a sensing signal SENSE transmitted through different gate lines GL.

[0073] In contrast, if the switching transistor SWT and the sensing transistor SENT are connected to one gate line GL, the switching transistor SWT and the sensing transistor SENT may be simultaneously controlled by the scan signal SCAN or the sensing signal SENSE transmitted through one gate line GL, and the aperture ratio of the subpixel SP may be increased.

[0074] The transistor provided in the sub-pixel SP may be an n-type transistor or a p-type transistor, and in the illustrated example, the transistor is an n-type transistor.

[0075] The storage capacitor Cst is electrically connected between the first node N1 and the second node N2 of the driving transistor DRT, and maintains the data voltage Vdata during one frame.

[0076] According to the type of the driving transistor DRT, the storage capacitor Cst may also be connected between the first node N1 and the third node N3 of the driving transistor DRT. The anode electrode of the light emitting element ED may be electrically connected to the second node N2 of the driving transistor DRT, and the low potential reference voltage EVSS may be provided to the cathode electrode of the light emitting element ED.

[0077] The reference voltage EVSS may be a ground voltage or a voltage higher or lower than the ground voltage. The reference voltage EVSS may vary according to the driving state. For example, the reference voltage EVSS during display driving and the reference voltage EVSS during sensing driving may be set to be different from each other.

[0078] The structure of the sub-pixel SP described as an example above is a 3T (transistor) 1C (capacitor) structure, which is only an example for description, and may also include one or more transistors, or in some cases one or more capacitors. A plurality of sub-pixels SP may have the same structure, or some of the plurality of sub-pixels SP may have different structures.

[0079] Figure 4 FIG. 1 is a diagram specifically illustrating a source film connecting a source printed circuit board to a display panel in a display device according to an embodiment of the present disclosure.

[0080] refer to Figure 4 In the display device 100 according to an embodiment of the present disclosure, the source driving integrated circuit SDIC may be implemented on the source film SF connecting the source printed circuit board SPCB to the display panel 110 .

[0081] The source driver integrated circuit SDIC may be disposed on the source film SF in a chip-on-film (COF) type.

[0082] The source film SF may include one or more first pins 131 connected to the display panel 110 .

[0083] The one or more first pins 131 may include first data pins 131 b and 131 c for supplying a data voltage Vdata generated in a source driving integrated circuit SDIC to the display panel 110 and first driving pins 131 a and 131 d for supplying a driving voltage.

[0084] The driving voltage provided to the display panel 110 through the first driving pins 131 a and 131 d may be a low potential reference voltage EVSS or a high potential sub-pixel driving voltage EVDD.

[0085] In addition, the source film SF may include one or more second pins 132 connected to the source printed circuit board SPCB.

[0086] The one or more second pins 132 may include second data pins 132 b and 132 c receiving the image data DATA provided from the timing controller 140 and second driving pins 132 a and 132 d receiving the driving voltage provided from the power management circuit 150 .

[0087] The image data DATA provided through the second data pins 132 b and 132 c may be converted into an analog data voltage Vdata in the source driver integrated circuit SDIC and transmitted through the first data pins 131 b and 131 c.

[0088] The driving voltages EVDD and EVSS provided by the second driving pins 132 a and 132 d may be transmitted to the first driving pins 131 a and 131 d through the connection line 133 .

[0089] At this time, since a high current flows in a voltage line transmitting a low potential reference voltage EVSS in the source printed circuit board SPCB of the display panel 110 emitting light at high brightness, heat in the source printed circuit board SPCB increases.

[0090] In particular, since the source printed circuit board SPCB is in direct contact with the display panel 110 through the source film SF, the temperature of the display panel 110 increases.

[0091] The display device 100 of the present disclosure may ensure a transmission path for a reference voltage and reduce heat generated in the display panel 110 by disposing a low potential voltage line in a closed loop structure on the source printed circuit board SPCB.

[0092] Figure 5 is a diagram illustrating a structure of a low potential voltage line formed on a source printed circuit board in a display device according to an embodiment of the present disclosure.

[0093] refer to Figure 5According to an embodiment of the present disclosure, one or more source driver integrated circuits SDIC included in the data driver circuit 130 may be implemented in the form of a chip-on-film (COF) on a source film SF in the display device 100 .

[0094] One side of the source film SF may be electrically connected to the display panel 110 , and the other side of the source film SF may be electrically connected to the source printed circuit board SPCB.

[0095] The timing controller 140 and the power management circuit 150 may be implemented on a control printed circuit board CPCB.

[0096] The timing controller 140 may provide the image data DATA to the source driving integrated circuit SDIC disposed on the source film SF.

[0097] The power management circuit 150 may provide a high potential sub-pixel driving voltage EVDD and a low potential reference voltage EVSS for driving the display panel 110. Here, only a low potential voltage line SVL for providing the low potential reference voltage EVSS is shown.

[0098] At this time, the low potential voltage line SVL transmitting the reference voltage EVSS may be formed in a closed loop structure on the source printed circuit board SPCB. That is, in a plan view, the low potential voltage line SVL is not formed in an open structure extending in a curved straight line from the power management circuit 150 to the source film SF, but is formed in a closed loop shape similar to a square structure between the power management circuit 150 and the source film SF.

[0099] In this way, when the low potential voltage line SVL is formed on the source printed circuit board SPCB in a closed loop structure, the path of the reference voltage EVSS transmitted through the low potential voltage line SVL can be increased. As a result, since the heat generated by the reference voltage EVSS is diffused over a wide area, the temperature of the low potential voltage line SVL can be reduced.

[0100] At this time, the low potential connection line SSVL extending from a specific point of the low potential voltage line SVL having a closed loop structure may be provided along one side of the source film SF. In one embodiment, a plurality of low potential connection lines SSVL extend from the low potential voltage line SVL to the display panel 110, so that each low potential connection line SSVL overlaps with a corresponding source film SF among the plurality of source films SF, but does not overlap with a source driver integrated circuit SDIC on the corresponding source film SF. One end of each low potential connection line SSVL is electrically connected to the display panel 110.

[0101] Each low potential connection line SSVL may be disposed on the corresponding source film SF, and may extend along one side of the source driving integrated circuit SDIC on the source film SF.

[0102] At this time, by changing the width of the low potential voltage line SVL having a closed loop structure formed on the source printed circuit board SPCB according to the distance from the display panel 110 , the heat can be reduced more effectively.

[0103] Figure 6 is a diagram illustrating a structure in which the width of a low potential voltage line varies according to a position in a display device according to an embodiment of the present disclosure.

[0104] refer to Figure 6 According to an embodiment of the present disclosure, the low potential voltage line SVL formed in a closed loop structure on the source printed circuit board SPCB in the display device 100 may be composed of a first low potential voltage line SVL1, a second low potential voltage line SVL2 spaced apart from the first low potential voltage line SVL1, and a pair of third low potential voltage lines SVL3.

[0105] The first low potential voltage line SVL1 may be located in a first region CR1 adjacent to the display panel 110. The first region CR1 may extend along a long axis of the display panel 110, and may be a region adjacent to the display panel 110.

[0106] The second low potential voltage line SVL2 may be located in the second region CR2 farther from the display panel 110 than the first region CR1. The second region CR2 may extend along the long axis of the display panel 110 and may be a region farther from the display panel 110 than the first region CR1.

[0107] The third low potential voltage line SVL3 may be a portion connecting the first low potential voltage line SVL1 and the second low potential voltage line SVL2 in the third region CR3. The third region CR3 may be a region extending in a direction perpendicular to the long axis of the display panel 110 on the left and right sides of the source printed circuit board SPCB.

[0108] In one embodiment, a first end (e.g., left end) of the first low potential voltage line SVL1 is connected to a first end of a first one of the third low potential voltage lines SVL3, and a second end of the first low potential voltage line SVL1 is connected to a first end of a second one of the third low potential voltage lines SVL3. A first end of the second low potential voltage line SVL2 is connected to a second end of a first one of the third low potential voltage lines SVL3, and a second end of the second low potential voltage line SVL2 is connected to a second end of a second one of the third low potential voltage lines SVL3, thereby forming a closed loop shape.

[0109] At this time, the width of the low potential voltage line SVL formed in a closed loop structure on the source printed circuit board SPCB for transmitting the low potential reference voltage EVSS may vary according to a position.

[0110] Heat generated by the reference voltage EVSS flowing through the low potential voltage line SVL may increase the temperature of the display panel 110. Therefore, in order to reduce the temperature increase of the display panel 110, the first width D1 of the first low potential voltage line SVL1 located in the first region CR1 adjacent to the display panel 110 may be greater than the second width D2 of the second low potential voltage line SVL2 located in the second region CR2 away from the display panel 110. The third width D3 of the third low potential voltage line SVL3 is greater than the first width D1 of the first low potential voltage line SVL1.

[0111] At this time, the sum of the first width D1 of the first low potential voltage line SVL1 located in the first area CR1 adjacent to the display panel 110 and the second width D2 of the second low potential voltage line SVL2 located in the second area CR2 away from the display panel 110 can be maintained as a constant reference value D, that is, D1+D2=D.

[0112] The reference value D of the low potential voltage line SVL may correspond to a width when the low potential voltage line SVL is formed in an open structure.

[0113] For example, when the low potential voltage line SVL between the power management circuit 150 and the source film SF is formed in an open structure with a stepped straight line, the reference value D of the low potential voltage line SVL may be 10 mm. At this time, the low potential voltage line SVL having a closed loop structure may be formed to have a reference value of 10 mm corresponding to the sum of the first width D1 of the first low potential voltage line SVL1 located in the first region CR1 and the second width D2 of the second low potential voltage line SVL2 located in the second region CR2.

[0114] At this time, a first width D1 of the first low potential voltage line SVL1 located in the first region CR1 adjacent to the display panel 110 may be greater than a second width D2 of the second low potential voltage line SVL2 located in the second region CR2 distant from the display panel 110 .

[0115] At this time, the first width D1 of the first low potential voltage line SVL1 and the second width D2 of the second low potential voltage line SVL2 may be determined through experiments in the display device 100 having the same specifications.

[0116] Figures 7A to 7D is an experimental diagram showing signal characteristics according to the width of a low potential voltage line in a display device according to an embodiment of the present disclosure.

[0117] refer to Figures 7A to 7D , the display device 100 according to the embodiment of the present disclosure may be judged based on the signal characteristics of IPC-2221, which represents an international standard for assembly and production standards of electronic devices and device components.

[0118] Specifically, temperature, current density, current, and power density may be detected as signal characteristics of the low potential voltage line SVL.

[0119] Fig. 7A The temperature characteristics according to the changed width of the low potential voltage line SVL are shown. Figure 7B The current density characteristics according to the changed width of the low potential voltage line SVL are shown. Figure 7C The current characteristics according to the changed width of the low potential voltage line SVL are shown. Fig.7D The power density characteristics according to the changed width of the low potential voltage line SVL are shown.

[0120] In each graph, the sum D1+D2 of the first width D1 of the first low potential voltage line SVL1 located in the first region CR1 adjacent to the display panel 110 and the second width D2 of the second low potential voltage line SVL2 located in the second region CR2 away from the display panel 110 is maintained at a constant reference value D. In this state, the signal characteristics are shown as a decrease in the first width D1 of the first low potential voltage line SVL1 and an increase in the second width D2 of the second low potential voltage line SVL2.

[0121] Here, OR represents a case where the low potential voltage line SVL having the same width as the reference value D is formed in a step-line open structure between the power management circuit 150 and the source film SF.

[0122] Therefore, a first width D1 of the first low potential voltage line SVL1 located in the first region CR1 adjacent to the display panel 110 and a second width D2 of the second low potential voltage line SVL2 located in the second region CR2 distant from the display panel 110 may be determined by reflecting these signal characteristics.

[0123] For example, the first width D1 of the first low potential voltage line SVL1 located in the first region CR1 adjacent to the display panel 110 may be selected within a range of 60% to 70% of the reference value D of the low potential voltage line SVL. In addition, the second width D2 of the second low potential voltage line SVL2 located in the second region CR2 away from the display panel 110 may be selected within a range of 30% to 40% of the reference value D of the low potential voltage line SVL.

[0124] For example, when the reference value D of the low potential voltage line SVL is 10 mm, the first width D1 of the first low potential voltage line SVL1 located in the first region CR1 adjacent to the display panel 110 may be 6.5 mm, and the second width D2 of the second low potential voltage line SVL2 located in the second region CR2 away from the display panel 110 may be 3.5 mm.

[0125] At this time, the first low potential voltage line SVL1 may be connected to the second low potential voltage line SVL2 through the third low potential voltage line SVL3 located in the third region CR3 corresponding to the left and right sides of the source printed circuit board SPCB.

[0126] The third width D3 of the third low potential voltage line SVL3 may be equal to a reference value D of the low potential voltage line SVL, which is the sum of the first width D1 of the first low potential voltage line SVL1 and the second width D2 of the second low potential voltage line SVL2. Therefore, the third width D3 is greater than the first width D1 and greater than the second width D2. For example, when the first width D1 of the first low potential voltage line SVL1 located in the first region CR1 adjacent to the display panel 110 is 6.5 mm, and the second width D2 of the second low potential voltage line SVL2 located in the second region CR2 away from the display panel 110 is 3.5 mm, the third width D3 of the third low potential voltage line SVL3 may be 10 mm.

[0127] In this way, when the low potential voltage line SVL transmitting the reference voltage EVSS is formed in a closed loop structure, it can be electrically contacted with another driving voltage line, for example, such as the high potential voltage line DVL transmitting the high potential sub-pixel driving voltage EVDD. Therefore, the source printed circuit board SPCB can have a multi-layer structure in which driving voltage lines transmitting different driving voltages are formed in different layers.

[0128] Figure 8 is a conceptual diagram illustrating a multi-layer source printed circuit board in a display device according to an embodiment of the present disclosure.

[0129] refer to Figure 8 , the source printed circuit board SPCB in the display device 100 according to an embodiment of the present disclosure may include a first source printed circuit board layer SPCB-L1 and a second source printed circuit board layer SPCB-L2 separated by an insulating material.

[0130] The low potential voltage line SVL having a closed loop structure may be disposed on the first source printed circuit board layer SPCB-L1.

[0131] The high potential voltage line DVL may be disposed on the second source printed circuit board layer SPCB-L2. At this time, the high potential voltage line DVL may have an open structure with stepped straight lines or a closed loop structure.

[0132] When the first source printed circuit board layer SPCB-L1 and the second source printed circuit board layer SPCB-L2 are formed in a multi-layer structure separated by an insulating material, the low potential voltage line SVL of the closed loop structure formed in the first source printed circuit board layer SPCB-L1 can be electrically separated from the high potential voltage line DVL and other voltage lines.

[0133] Fig.9A and 9B A temperature diagram measured in a display panel for a case where a low potential voltage line having an open structure is formed on a source printed circuit board and a case where a low potential voltage line having a closed loop structure is formed on a source printed circuit board in a display device according to an embodiment of the present disclosure is shown.

[0134] refer to Fig.9A When the low potential voltage line SVL between the power management circuit 150 and the display panel 110 is formed in a straight line (or stepped straight line) structure on the source printed circuit board SPCB, the maximum operating temperature (Max) of the display panel 110 increases to about 49.8 degrees.

[0135] refer to Fig. 9B , when the low potential voltage line SVL located between the power management circuit 150 and the display panel 110 is formed in a closed loop structure on the source printed circuit board SPCB, it is confirmed that the maximum temperature (Max) of the operation of the display panel 110 increases to about 45.5 degrees, resulting in a temperature decrease of about 4.3 degrees.

[0136] Meanwhile, the display device 100 of the present disclosure may form a dual structure low potential connection line SSVL extending from the low potential voltage line SVL having a closed loop structure through the source film SF to the display panel 110. In this case, the transmission characteristics and thermal characteristics of the reference voltage EVSS may be further improved.

[0137] Fig.10 is a diagram showing a case where a low potential connection line extending from a low potential voltage line of a source printed circuit board is formed in a double structure in a display device according to an embodiment of the present disclosure.

[0138] refer to Fig.10 One or more source driver integrated circuits SDIC included in the data driver circuit 130 in the display device 100 according to an embodiment of the present disclosure may be implemented on the source film SF in the form of a chip-on-film (COF).

[0139] One side of the source film SF may be electrically connected to the display panel 110 , and the other side of the source film SF may be electrically connected to the source printed circuit board SPCB.

[0140] The power management circuit 150 may provide a high potential sub-pixel driving voltage EVDD and a low potential reference voltage EVSS for driving the display panel 110. Here, only a low potential voltage line SVL for providing the low potential reference voltage EVSS is shown.

[0141] At this time, a low potential voltage line SVL transmitting the reference voltage EVSS may be formed in a closed loop structure on the source printed circuit board SPCB.

[0142] In this way, when the low potential voltage line SVL is formed in a closed loop structure on the source printed circuit board SPCB, the path of the reference voltage EVSS transmitted through the low potential voltage line SVL can be increased. As a result, since the heat generated by the reference voltage EVSS is diffused over a wide area, the temperature of the low potential voltage line SVL can be reduced.

[0143] At this time, the low potential connection line SSVL may extend from a specific point of the low potential voltage line SVL formed in a closed loop structure. The low potential connection line SSVL may be disposed along the source film SF, specifically, formed in a dual structure along both sides of the source driver integrated circuit SDIC disposed on the source film SF, and electrically connected to the display panel 110.

[0144] That is, the first low potential connection line SSVL1 can be arranged along the left side of the source driver integrated circuit SDIC on the source film SF, and the second low potential connection line SSVL2 can be arranged along the right side of the source driver integrated circuit SDIC on the source film SF. In other words, a plurality of first low potential connection lines SSVL1 extend from the voltage line SVL to the display panel 110, so that each first low potential connection line SSVL1 overlaps with the corresponding source film SF and is located on the first side of the source driver integrated circuit SDIC on the corresponding source film SF. In addition, a plurality of second low potential connection lines SSVL2 extend from the voltage line SVL to the display panel 110, so that each second low potential connection line SSVL2 overlaps with the corresponding source film SF and is located on the second side of the source driver integrated circuit SDIC on the corresponding source film SF.

[0145] In this way, when the low potential connection line SSVL is arranged in a dual structure for each source film SF, the low potential current transmitted from the low potential voltage line SVL formed on the source printed circuit board SPCB in a closed loop structure to the display panel 110 can be dispersed. Thus, the heat generated by the display panel 110 is further reduced, and the signal characteristics are improved.

[0146] The foregoing embodiments are briefly described below.

[0147] An embodiment of the present disclosure may provide a display device, which includes a display panel, a source film and a source printed circuit board, wherein the display panel includes a plurality of sub-pixels, the source film is connected to one side of the display panel, and a source driver integrated circuit for providing a data voltage to the display panel is implemented on the source film, and a low-potential voltage line for transmitting a reference voltage to the display panel through the source film is provided on the source printed circuit board in a closed-loop structure.

[0148] The source printed circuit board includes a timing controller configured to provide image data to the source drive integrated circuit.

[0149] The source printed circuit board includes a power management circuit configured to generate a reference voltage.

[0150] The low potential voltage line includes a first low potential voltage line located in a first area of ​​the source printed circuit board, a second low potential voltage line located in a second area of ​​the source printed circuit board, and a third low potential voltage line connecting the first low potential voltage line to the second low potential voltage line in a third area of ​​the source printed circuit board.

[0151] The first region is a region adjacent to the display panel and extending along a long axis of the display panel.

[0152] The second region is a region extending along the long axis of the display panel and away from the display panel.

[0153] The third region is a region extending in a direction perpendicular to the long axis of the display panel on the left and right sides of the source printed circuit board.

[0154] A first width of the first low potential voltage line is greater than a second width of the second low potential voltage line.

[0155] A sum of a first width of the first low potential voltage line and a second width of the second low potential voltage line is a constant reference value.

[0156] A first width of the first low potential voltage line is in a range of 60% to 70% of the reference value.

[0157] A second width of the second low potential voltage line is in a range of 30% to 40% of the reference value.

[0158] A sum of a first width of the first low potential voltage line and a second width of the second low potential voltage line is equal to a third width of the third low potential voltage line.

[0159] The display device further includes a low potential connection line extending from a specific point of the low potential voltage line, disposed along the source film, and electrically connected to the display panel.

[0160] The low potential connection line includes a first low potential connection line arranged along one side of the source driver integrated circuit and a second low potential connection line arranged along the other side of the source driver integrated circuit.

[0161] The source printed circuit board includes a first source printed circuit board layer on which the low potential voltage line is disposed, and a second source printed circuit board layer separated from the first source printed circuit board layer by an insulating material and on which a high potential voltage line is disposed.

[0162] The high potential voltage line is arranged in a closed loop structure.

[0163] A display device may include a display panel, the display panel including a plurality of sub-pixels; a plurality of source films, each of the source films having a first side and a second side, the first side of each of the plurality of source films being connected to the display panel; a plurality of source driver integrated circuits, the plurality of source driver integrated circuits being configured to provide data voltages to the display panel, each source driver integrated circuit being on a corresponding source film among the plurality of source films; a source printed circuit board, the source printed circuit board being connected to the second side of each of the plurality of source films; and a voltage line on the source printed circuit board, the voltage line providing a voltage to the display panel, the voltage line including a first voltage line having a first end and a second end, a second voltage line that is farther from the display panel than the first voltage line and has a first end and a second end, a third voltage line connected to the first end of the first voltage line and the first end of the second voltage line, and a fourth voltage line connected to the second end of the first voltage line and the second end of the second voltage line.

[0164] The display device may further include a plurality of connecting lines extending from the voltage line to the display panel, such that each connecting line overlaps with a corresponding source film among the plurality of source films but does not overlap with a source driver integrated circuit among the plurality of source driver integrated circuits located on the corresponding source film, wherein each of the plurality of connecting lines is electrically connected to the display panel.

[0165] The display device may further include a plurality of first connection lines extending from the voltage line to the display panel so that each first connection line overlaps with a corresponding source film and is on a first side of a source driver integrated circuit located on the corresponding source film among the plurality of source driver integrated circuits; and a plurality of second connection lines extending from the voltage line to the display panel so that each second connection line overlaps with a corresponding source film and is on a second side of the source driver integrated circuit located on the corresponding source film, wherein each of the plurality of first connection lines and each of the plurality of second connection lines are electrically connected to the display panel.

[0166] The width of the first voltage line may be greater than the thickness of the second voltage line, and the lengths of the third voltage line and the fourth voltage line are both greater than the width of the first voltage line.

[0167] The third voltage line and the fourth voltage line may have the same width.

[0168] A sum of a width of the first voltage line and a width of the second voltage line may be equal to a width of the third voltage line and equal to a width of the fourth voltage line.

[0169] The voltage may be one of a ground voltage or a high potential voltage greater than the ground voltage.

[0170] The above description has been presented to enable any person skilled in the art to make and use the technical concept of the present disclosure, and the above description has been provided in the context of a specific application and its requirements. Various modifications, additions and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. The above description and accompanying drawings provide examples of the technical concept of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concept of the present disclosure.

Claims

1. A display device, comprising: A display panel, the display panel comprising a plurality of sub-pixels; a source film connected to one side of the display panel; a source driver integrated circuit on the source film, the source driver integrated circuit being configured to provide a data voltage to the display panel; a source printed circuit board connected to the source film; as well as A low potential voltage line is on the source printed circuit board and has a closed loop structure in a plan view of the display device, and transmits a reference voltage to the display panel through the source film.

2. The display device according to claim 1, wherein: The source printed circuit board includes a timing controller configured to provide image data to the source driver integrated circuit, and the source driver integrated circuit generates a data voltage based on the image data.

3. The display device according to claim 1, wherein: The source printed circuit board includes a power management circuit configured to provide the reference voltage.

4. The display device according to claim 1, wherein: The low potential voltage line comprises: a first low potential voltage line, the first low potential voltage line being located in a first area of ​​the source printed circuit board; a second low potential voltage line located in a second region of the source printed circuit board spaced apart from the first region; and a third low potential voltage line connecting the first low potential voltage line to the second low potential voltage line in a third region of the source printed circuit board.

5. The display device according to claim 4, wherein: The first region is a region adjacent to the display panel and extending along a long axis of the display panel.

6. The display device according to claim 4, wherein: The second region is a region that is farther from the display panel than the first region and extends along the long axis of the display panel.

7. The display device according to claim 4, wherein: The third region is a region extending in a direction perpendicular to a long axis of the display panel on the left and right sides of the source printed circuit board.

8. The display device according to claim 4, wherein: A first width of the first low potential voltage line is greater than a second width of the second low potential voltage line.

9. The display device according to claim 4, wherein: A sum of a first width of the first low potential voltage line and a second width of the second low potential voltage line is a constant reference value.

10. The display device according to claim 9, wherein: A first width of the first low potential voltage line is in a range of 60% to 70% of the reference value.

11. The display device according to claim 9, wherein: A second width of the second low potential voltage line is in a range of 30% to 40% of the reference value.

12. The display device according to claim 4, wherein: A sum of a first width of the first low potential voltage line and a second width of the second low potential voltage line is equal to a third width of the third low potential voltage line. 13 . The display device according to claim 1 , further comprising a low potential connection line extending from a specific point of the low potential voltage line, disposed along the source film, and electrically connected to the display panel.

14. The display device according to claim 13, wherein: The low potential connecting line comprises: a first low potential connection line, wherein the first low potential connection line is arranged along one side of the source driver integrated circuit; and A second low potential connection line is provided along the other side of the source driver integrated circuit.

15. The display device according to claim 1, wherein: The source printed circuit board comprises: a first source printed circuit board layer, the low potential voltage line being arranged on the first source printed circuit board layer; and A second source printed circuit board layer is separated from the first source printed circuit board layer by an insulating material, and a high potential voltage line is disposed on the second source printed circuit board layer.

16. The display device according to claim 15, wherein: The high potential voltage line is arranged in a closed loop structure.

17. A display device comprising: A display panel, the display panel comprising a plurality of sub-pixels; a plurality of source films, each source film having a first side and a second side, the first side of each of the plurality of source films being connected to the display panel; a plurality of source driver integrated circuits, the plurality of source driver integrated circuits being configured to provide data voltages to the display panel, each source driver integrated circuit being on a corresponding source film among the plurality of source films; a source printed circuit board connected to a second side of each of the plurality of source films; as well as voltage lines on the source printed circuit board, the voltage lines providing voltage to the display panel, the voltage lines comprising a first voltage line having a first end and a second end, a second voltage line which is farther away from the display panel than the first voltage line and has a first end and a second end, a third voltage line connected to the first end of the first voltage line and the first end of the second voltage line, and a fourth voltage line connected to the second end of the first voltage line and the second end of the second voltage line.

18. The display device according to claim 17, further comprising: a plurality of connection lines extending from the voltage line to the display panel so that each connection line overlaps with a corresponding source film among the plurality of source films but does not overlap with a source driver integrated circuit located on the corresponding source film among the plurality of source driver integrated circuits, Wherein, each of the plurality of connection lines is electrically connected to the display panel.

19. The display device according to claim 17, further comprising: a plurality of first connection lines extending from the voltage line to the display panel so that each first connection line overlaps with a corresponding source film and is located on a first side of a source driver integrated circuit among the plurality of source driver integrated circuits on the corresponding source film; as well as a plurality of second connection lines extending from the voltage line to the display panel so that each second connection line overlaps with a corresponding source film and is located on a second side of the source driver integrated circuit on the corresponding source film, Wherein, each of the plurality of first connection lines and each of the plurality of second connection lines are electrically connected to the display panel.

Images