Manufacturing method of large-through-flow small-area TVS (Transient Voltage Suppressor) device

Abstract

The invention belongs to the field of design and manufacturing of semiconductors / integrated circuits, and particularly relates to a manufacturing method of a large-through-flow and small-area TVS (Transient Voltage Suppressor) device. Firstly, a P-type substrate with proper resistivity is selected, and an N-type epitaxial layer is grown on the P-type substrate by using a chemical vapor deposition process; and forming an oxide layer, etching a deep isolation groove, and filling polycrystalline silicon for isolation. And performing ion implantation between the isolation grooves to form P-type traps, etching the grooves, filling N-type doped polycrystalline silicon, and sealing the grooves. And removing the surface layer, performing high-temperature diffusion, depositing a through hole dielectric layer, forming a through hole, and filling conductive metal into the through hole. And finally, depositing metal and photoetching to reserve metal in a specific area, and passivating to form the TVS device. By optimizing the structure and the process, large through-flow and small area are realized, the cost is reduced, the requirements of miniaturized electronic products are met, and the performance and the reliability of electronic equipment are improved.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor / integrated circuit design and manufacturing, and specifically relates to a method for manufacturing a TVS device with large through-current and small area. Background Art

[0002] In the field of modern electronic technology, the performance and reliability of electronic equipment are constantly improving, and semiconductor devices play a vital role. As an important semiconductor protection device, TVS devices have the main function of quickly clamping excessive voltage within a safe range when transient overvoltage occurs in the circuit, thereby protecting the back-end electronic components from damage.

[0003] As electronic devices such as smartphones, tablets, and wearable devices develop rapidly towards miniaturization, multi-functions, and high performance, their internal circuits are becoming increasingly complex and integrated. Within the limited circuit board space, the size of components must be reduced as much as possible to meet the requirements of miniaturization. However, traditional TVS devices face a severe challenge in the design and manufacturing process, namely the contradiction between current carrying capacity and chip area.

[0004] Generally, in order to achieve a larger current capacity, TVS devices require a larger chip area to accommodate sufficient PN junctions and other structures. This is because the current capacity is closely related to the area of ​​the PN junction. A larger PN junction area can provide more carrier channels in transient overvoltage events, thereby allowing a larger current to pass. However, increasing the chip area will not only increase production costs, but also run counter to the trend of miniaturization of electronic devices, limiting its application in small electronic products.

[0005] In addition, traditional TVS devices have gradually exposed their limitations in some high-performance application scenarios. For example, in high-speed data transmission circuits, the response speed and clamping accuracy of TVS devices are extremely high, and traditional devices may not be able to meet these stringent requirements. At the same time, with the continuous expansion of the operating voltage range of electronic equipment, new challenges have been raised to the voltage resistance of TVS devices. Traditional manufacturing methods make it difficult to achieve higher voltage resistance performance without significantly increasing the chip area. Summary of the invention

[0006] In view of the shortcomings of the prior art, the present invention proposes a method for manufacturing a TVS device with large through-current and small area. By optimizing the device structure and manufacturing process, the chip area is significantly reduced, the production cost is reduced, the applicability of TVS devices in miniaturized electronic products is improved, and the overall performance and reliability of electronic equipment are enhanced while ensuring large through-current capability.

[0007] The technical solution of the present invention is as follows:

[0008] A method for manufacturing a TVS device with large through-current and small area, comprising:

[0009] A P-type substrate is selected according to the resistivity, and an N-type epitaxial layer is formed on the P-type substrate by a chemical vapor deposition process;

[0010] An oxide layer is formed on the surface of the N-type epitaxial layer by thermal oxidation or chemical vapor deposition process, and then a plurality of deep isolation grooves are etched in the epitaxial layer and extended to the P-type substrate by photolithography and dry etching process;

[0011] Using in-situ polysilicon to fill deep isolation trenches;

[0012] An ion implantation process is used between the deep isolation trenches to form a P-type well;

[0013] Through photolithography and dry etching processes, grooves a, b, c, and d are etched in the N-type epitaxial layer;

[0014] Through a deposition process, N-type doped polysilicon is filled into trenches a, b, c, and d and sealed;

[0015] The surface N-type doped polysilicon and oxide layer are removed by etching process, and then the junction is pushed to the required junction voltage performance by high-temperature diffusion;

[0016] By means of a deposition process, an oxide layer is deposited on the surface of the N-type epitaxial layer as a through-hole dielectric layer, through holes are opened on the through-hole dielectric layer corresponding to the positions of the grooves a, b, c, and d by means of a photolithography and etching process, and conductive metal is filled in the through holes;

[0017] Metal is deposited on the through-hole dielectric layer through a deposition process, and the metal above trench a and trench d, and between trench b and trench c are retained through photolithography and etching processes, and then the required TVS device is formed after a final passivation treatment.

[0018] Furthermore, the P-type substrate is selected to have a resistivity between 0.001 and 0.008 Ω.cm.

[0019] Furthermore, the thickness of the oxide layer formed on the surface of the N-type epitaxial layer is 100-10000A;

[0020] In the dry etching process, the etching gas is a mixture of fluorine-based gas and inert gas;

[0021] The deep isolation trench has a width of 0.5-1.2 um and a depth of 3-25 um.

[0022] Furthermore, the in-situ polysilicon is filled into the deep isolation trenches using low-pressure chemical vapor deposition technology.

[0023] Furthermore, in the ion implantation process, boron ions are selected as implanted ions, and the ion implantation energy is between 10-100 keV. During the ion implantation process, rotation and scanning motions are performed.

[0024] Furthermore, when the grooves a, b, c, and d are etched in the N-type epitaxial layer, the depths of the grooves a, b, c, and d do not pass through the N-type epitaxial layer.

[0025] Furthermore, the doping concentration of the N-type doped polysilicon is 1E11-1E20cm -3 .

[0026] Furthermore, the through-hole dielectric layer has a thickness of 2-3 um.

[0027] Furthermore, the metal deposited on the through-hole dielectric layer is metal AlCu or AlSiCu.

[0028] Furthermore, the connection method between the basic structural units of the TVS device includes: using a plurality of doped silicon in parallel and a plurality of basic structural units in series.

[0029] The beneficial effects of the present invention are:

[0030] 1. The present invention adopts deep trench isolation and trench filling doped polysilicon technology, which can greatly reduce the chip size.

[0031] 2. In the present invention, the PN junction formed by the doped polysilicon trench has a uniform doping concentration distribution, which improves the uniformity of the current flowing inside the device and effectively avoids the possibility of device failure caused by current concentration.

[0032] 3. In the present invention, the depth / width of the PN junction formed by the doped polysilicon trench can be precisely controlled according to demand, which is conducive to precise control of the clamping voltage.

[0033] 4. In the present invention, the PN junction formed by the doped polysilicon trench has a larger area than the planar PN junction, which effectively increases the surge current absorption capacity, and the process is simple and has low requirements on the machine.

[0034] 5. In the present invention, multiple doped polysilicon trenches are connected in parallel, which can reduce the body resistance of the PN junction, thereby obtaining a low clamping voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 The overall flow chart of the manufacturing method of a TVS device with large through-current and small area;

[0036] Figure 2 The schematic diagram of the structure of forming an N-type epitaxial layer on a P-type substrate is shown;

[0037] Figure 3It shows the structure after an oxide layer is formed on the surface of the N-type epitaxial layer and a deep isolation trench is etched;

[0038] Figure 4 The structure after the deep isolation trench is filled with in-situ polysilicon;

[0039] Figure 5 The structure after forming a P-type well between deep isolation trenches is presented;

[0040] Figure 6 It is the structure after the grooves a, b, c, and d are etched in the N-type epitaxial layer;

[0041] Figure 7 The structure is formed after the trench is filled with N-type doped polysilicon and sealed;

[0042] Figure 8 To remove the surface N-type doped polysilicon and oxide layer and diffuse the structure after high temperature junction;

[0043] Fig. 9 The structure is formed after depositing a through-hole dielectric layer, opening a through-hole and filling it with a conductive metal;

[0044] Fig.10 The final TVS device structure is presented;

[0045] Fig.11 This is a connection diagram of the basic structural unit of the TVS device. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0047] Example 1

[0048] In electronic devices, TVS devices are used to protect circuits from transient overvoltages. However, traditional TVS devices have difficulty in achieving both high current capability and small area design. High current capability usually requires a larger chip area, which increases costs and is not conducive to the application of miniaturized electronic products.

[0049] See also Figure 1 , which shows a method for manufacturing a TVS device with large through-current and small area provided by an embodiment of the present invention, comprising:

[0050] S100: selecting a P-type substrate according to resistivity, and forming an N-type epitaxial layer on the P-type substrate by a chemical vapor deposition process.

[0051] S200: forming an oxide layer on the surface of the N-type epitaxial layer by thermal oxidation or chemical vapor deposition, and then etching a plurality of deep isolation grooves in the epitaxial layer and extending them to the P-type substrate by photolithography and dry etching.

[0052] S300: Using in-situ polysilicon to fill deep isolation trenches.

[0053] S400: An ion implantation process is used between the deep isolation trenches to form a P-type well.

[0054] S500: Etching grooves a, b, c, and d in the N-type epitaxial layer through photolithography and dry etching processes.

[0055] S600: Filling the trenches a, b, c, and d with N-type doped polysilicon through a deposition process and sealing the trenches.

[0056] S700: The surface N-type doped polysilicon and oxide layer are removed through an etching process, and then the junction is pushed to the required junction voltage performance through high-temperature diffusion.

[0057] S800: depositing an oxide layer as a through-hole dielectric layer on the surface of the N-type epitaxial layer through a deposition process, opening through holes on the through-hole dielectric layer corresponding to the positions of the grooves a, b, c, and d through photolithography and etching processes, and filling the through holes with conductive metal.

[0058] S900: Deposit metal on the through-hole dielectric layer through a deposition process, and retain the metal above the groove a and the groove d, and between the groove b and the groove c through a photolithography and etching process, and then passivate the metal to form the required TVS device.

[0059] By optimizing the device structure and manufacturing process, the TVS device of the present invention can effectively reduce the chip area and reduce the cost while achieving a large current capacity, which is conducive to the miniaturization of electronic products.

[0060] S100 carefully selects P-type substrates with resistivity in the range of 0.001-0.008Ω.cm, and uses chemical vapor deposition technology to grow an N-type epitaxial layer with a thickness of 2-20μm on the P-type substrate under strict control of parameters such as temperature, gas flow and pressure.

[0061] S100 specifically includes the following steps:

[0062] S110: P-type substrate selection.

[0063] Screen P-type substrate materials with different resistivities. Resistivity is an important parameter that affects the performance of TVS devices. Select P-type substrates with resistivity between 0.001 and 0.008 Ω.cm. Too low a resistivity may lead to excessive leakage current, while too high a resistivity may affect the conduction performance of the device.

[0064] In a possible implementation, electrical performance tests are performed on P-type substrate materials, including resistivity measurement, carrier mobility analysis, etc., to select substrate materials that meet the requirements.

[0065] S120: forming an N-type epitaxial layer on a P-type substrate, such as Figure 2 shown.

[0066] The chemical vapor deposition (CVD) process is used to grow the N-type epitaxial layer. The growth temperature is one of the key factors and is generally controlled between 900-1200°C.

[0067] At the same time, the reaction gas flow and pressure are adjusted. The reaction gas usually includes silicon source gas (such as silane) and doping gas (such as phosphine). The silicon source gas flow is generally controlled at 10-100 sccm, and the doping gas flow is adjusted according to the required doping concentration of the epitaxial layer, generally between 0.1-10 sccm. The pressure is maintained at 10-100 Torr.

[0068] During the growth process, the thickness and doping concentration of the epitaxial layer are monitored in real time, the thickness is measured using an optical interferometer, and the resistivity is measured using the four-probe method to adjust the process parameters to ensure that the thickness of the epitaxial layer is within the range of 2-20μm and the doping concentration meets the design requirements, so as to form a good PN junction structure and lay the foundation for subsequent device manufacturing.

[0069] like Figure 3 As shown, S200 first generates an oxide layer of 100-10000A on the surface of the N-type epitaxial layer through thermal oxidation or chemical vapor deposition process, and then sequentially performs photolithography process and dry etching process, so as to accurately etch deep isolation grooves on the epitaxial layer.

[0070] S200 specifically includes the following steps:

[0071] S210: forming an oxide layer on the surface of the N-type epitaxial layer.

[0072] The oxide layer can be formed by thermal oxidation or chemical vapor deposition. The thermal oxidation process reacts silicon with oxygen at 800-1200°C to generate silicon dioxide. Its advantages are that the generated oxide layer is of high quality, good density, and low interface state density with the silicon substrate.

[0073] For example, the breakdown electric field strength of the oxide layer generated by thermal oxidation at 1000° C. can reach above 10 MV / cm.

[0074] The chemical vapor deposition process uses silicon source gas (such as tetraethoxysilane) and oxygen to react to form an oxide layer at 300-600°C. The advantage of the chemical vapor deposition process is that the oxide layer can be deposited after process steps that are not suitable for high-temperature processing, and the thickness uniformity of the oxide layer can be better controlled.

[0075] In the present invention, a suitable process is selected according to actual process requirements to form an oxide layer with a thickness of 100-10000A. Thickness control is achieved by adjusting parameters such as process time and gas flow rate. For example, in a thermal oxidation process, the longer the oxidation time, the thicker the oxide layer. The oxide layer grows approximately 1000-5000A per hour.

[0076] S220: etching a plurality of deep isolation trenches in the epitaxial layer and extending them all the way to the P-type substrate.

[0077] Perform photoresist coating, soft baking, exposure, post-baking and development photolithography process operations to form photoresist patterns. Ensure the accuracy and clarity of the photoresist patterns, thereby providing a guarantee for the subsequent accurate etching of the grooves.

[0078] Through the etching process, several deep isolation grooves are etched in the epitaxial layer and extended to the P-type substrate. For the etching of the deep isolation grooves, a suitable etching gas is selected. For example, the etching gas is a mixture of fluorine-based gas and inert gas. The etching time is calculated and adjusted according to the required depth of the deep isolation groove to ensure that the deep isolation groove is 0.5-1.2μm wide, 3-25μm deep, and extends to the P-type substrate. During the etching process, the etching depth is monitored by endpoint detection technology. When the characteristic spectral signal of the silicon substrate is detected, the etching is stopped to prevent excessive etching from damaging the substrate.

[0079] like Figure 4 As shown, S300 uses in-situ polysilicon to fill deep isolation trenches to achieve isolation effect.

[0080] The in-situ polysilicon deposition process uses low-pressure chemical vapor deposition (LPCVD) technology.

[0081] In a possible implementation, silane is selected as the silicon source gas, and deposition is performed under the conditions of a reaction chamber pressure of 10-100 mTorr and a temperature of 500-700° C. The silane flow rate is controlled between 10-100 sccm, and hydrogen is used as a carrier gas with a flow rate of 100-1000 sccm.

[0082] For example, when the silane flow rate is 50 sccm, the hydrogen flow rate is 500 sccm, the reaction chamber pressure is 50 mTorr, and the temperature is 600°C, a polysilicon layer with good quality and good filling performance can be obtained. During the deposition process, the growth rate of polysilicon is closely related to the process parameters, generally between 0.05-0.5 μm / min. By real-time monitoring of the deposition rate and thickness, the process parameters are adjusted to ensure that the deep isolation trench is fully filled.

[0083] like Figure 5 As shown, S400 uses an ion implantation process between deep isolation trenches to form a P-type well.

[0084] First, a suitable impurity ion source is selected. Boron ions are usually selected as implanted ions because boron atoms can provide hole carriers, thereby forming a P-type semiconductor region in the silicon material. The ion implantation energy is a key factor in determining the depth of the P-type well, and its range is generally between 10-100keV. By accurately adjusting the energy size, the implantation depth and implantation dose of boron ions in the silicon lattice can be controlled.

[0085] During the ion implantation process, the wafer needs to be rotated and scanned precisely to ensure that the entire wafer surface can receive the ion implantation evenly. The rotation and scanning motion can evenly distribute the ions in the area between the deep isolation grooves, forming a P-type well with good uniformity and stable electrical performance.

[0086] like Figure 6 As shown, S500 etches grooves a, b, c, and d in the N-type epitaxial layer through photolithography and dry etching processes.

[0087] S500 is similar to S220, and the photolithography process operations of photoresist coating, soft baking, exposure, post-baking and development are performed again to form a photoresist pattern corresponding to the grooves a, b, c, and d. The accuracy and clarity of the photoresist pattern are ensured, thereby providing a guarantee for the subsequent accurate etching of the grooves.

[0088] The etching gas is also a mixed gas of fluorine-based gas and inert gas.

[0089] The etching time is calculated according to the required depth of the trench to ensure that the trench depth does not penetrate the N-type epitaxial layer. During the etching process, the etching rate and depth are monitored in real time and measured using an optical interferometer or scanning electron microscope (SEM) to ensure the dimensional accuracy and shape quality of the trench.

[0090] like Figure 7 As shown, S600 uses a deposition process to increase the doping concentration to 1E11-1E20cm -3 N-type doped polysilicon is filled into the previously etched trench and sealed.

[0091] S600 specifically includes the following steps:

[0092] S610: depositing N-type doped polysilicon trenches a, b, c, and d by a low pressure chemical vapor deposition process.

[0093] N-type doped polysilicon is deposited using low pressure chemical vapor deposition. The doping concentration of doped polysilicon is 1E11-1E20cm -3 , different doping concentrations can be achieved by adjusting the flow rate of the doping gas.

[0094] For example, phosphine is selected as the doping gas. When the phosphine flow rate is 0.5-5 sccm, a doping concentration of 1E15-1E18 cm -3 During the deposition process, the trench is ensured to be completely filled while maintaining the uniformity of doping concentration.

[0095] S620: sealing the grooves a, b, c, and d.

[0096] After the trench is filled with polysilicon, the trench needs to be sealed to prevent impurities from entering the trench during subsequent processes.

[0097] like Figure 8 As shown, S700 removes the surface N-type doped polysilicon and oxide layer through an etching process, and then pushes the junction to the required junction voltage performance through high-temperature diffusion. The diffusion temperature is 900-1200°C, and the diffusion time is 10-90 minutes. Among them, the trench spacing needs to ensure that the diffusion areas formed after high-temperature diffusion do not hold hands, and there is still a gap in the middle, so that the NPN structure can still be formed.

[0098] S710: removing the N-type doped polysilicon and oxide layer on the surface through a dry etching process.

[0099] The etching gas is a fluorine-based gas, such as CF4 or SF6.

[0100] At the same time, the etching parameters are adjusted, the RF power is between 300-1000W, the reaction chamber pressure is between 5-50mTorr, and the etching time is between 1-10min.

[0101] During the etching process, endpoint detection technology is used to ensure that the surface layer is completely removed while avoiding excessive etching that may damage the underlying structure.

[0102] S720: Perform a high temperature diffusion process within a specific temperature and time range.

[0103] The high temperature diffusion process is carried out in a high temperature furnace at 900-1200°C, and the diffusion time is 10-90 minutes.

[0104] During the diffusion process, precise control of temperature and time is crucial to forming the required junction voltage performance. Higher temperature and longer time will increase the diffusion depth and reduce the junction voltage; conversely, the junction voltage will increase. Through simulation calculations and actual tests, the appropriate temperature and time combination is determined to ensure that the trench spacing does not hold hands in the diffusion zone formed after high-temperature diffusion, and there is still a gap in the middle, and the NPN structure can still be formed. At the same time, during the diffusion process, the stability and uniformity of the furnace atmosphere must be guaranteed to avoid uneven distribution of impurities and affect device performance.

[0105] like Fig. 9 As shown, S800 deposits an oxide layer as a through-hole dielectric layer with a thickness of 2-3um through a deposition process, and through holes are opened at the positions of grooves a, b, c, and d through photolithography and etching processes, and conductive metals such as W are filled in the through holes.

[0106] The specific steps of S800 include:

[0107] S810: depositing an oxide layer as a through-hole dielectric layer on the surface of the N-type epitaxial layer through a deposition process.

[0108] A 2-3μm thick oxide layer is deposited as the through-hole dielectric layer by chemical vapor deposition. During the deposition process, the growth rate and thickness of the oxide layer are monitored in real time and measured using optical interferometers and other equipment to ensure that the oxide layer thickness meets the 2-3μm requirement.

[0109] S820: Opening through holes on the through-hole dielectric layer corresponding to the positions of the grooves a, b, c, and d by photolithography and etching processes.

[0110] The photolithography process of photoresist coating, soft baking, exposure, post-baking and development is carried out to form photoresist patterns corresponding to the through-hole dielectric layer at the positions of grooves a, b, c, and d. The accuracy and clarity of the photoresist patterns are ensured, thus providing guarantee for the subsequent accurate etching of the grooves.

[0111] The photoresist pattern is etched through an etching process to open a through hole.

[0112] S830: After the through hole etching is completed, metal filling is performed.

[0113] Select a conductive metal and fill the vias using a chemical vapor deposition (CVD) process. First, evacuate the reaction chamber to less than 10 -4 Torr, then introduce tungsten hexafluoride (WF6) as tungsten source gas and hydrogen (H2) as reducing agent. The flow rate of WF6 is 1-10sccm, the flow rate of H2 is 10-100sccm, the pressure of the reaction chamber is 10-100mTorr, and the temperature is between 300-600℃.

[0114] During the deposition process, temperature sensors and pressure sensors are used to monitor the temperature and pressure of the reaction chamber in real time, and the gas flow is accurately adjusted through the flow controller to ensure the stability of the process parameters. The deposition rate is generally between 0.05-0.5μm / min. The deposition time is calculated according to the required through-hole filling height to ensure that the through-hole is completely filled. At the same time, the uniformity and continuity of the filling metal are guaranteed to provide reliable protection for the electrical connection of subsequent devices. After the filling is completed, the wafer is annealed at a temperature between 400-800℃ for 30-120min to eliminate the stress generated during the metal filling process and improve the adhesion between the metal and the through-hole wall and the underlying structure.

[0115] like Fig.10 As shown, S900 deposits metal AlCu or AlSiCu with a thickness of 3-5um on the through-hole dielectric layer through a deposition process, and retains the metal above the groove a and groove d, and between the groove b and groove c through a photolithography and etching process, and then undergoes a final passivation treatment to form the required TVS device.

[0116] The specific steps of S900 include:

[0117] S910: depositing metal AlCu or AlSiCu on the through-hole dielectric layer by physical vapor deposition or chemical vapor deposition process.

[0118] Taking physical vapor deposition as an example, the sputtering process is used to sputter and deposit AlCu or AlSiCu targets onto the wafer surface in an argon (Ar) plasma environment. During the deposition process, the sputtering power is controlled between 100-1000W and the gas pressure is between 0.1-10mTorr. For example, when the sputtering power is 500W and the gas pressure is 1mTorr, a metal layer with uniform thickness and good adhesion can be obtained. The thickness of the metal layer is controlled between 3-5μm, which is achieved by adjusting the deposition time and rate. The deposition rate is generally between 0.05-0.5μm / min. The deposition time is calculated according to the required thickness to ensure that the metal layer meets the design requirements.

[0119] S920: Through photolithography and etching processes, the metal above the groove a and the groove d and between the groove b and the groove c is retained.

[0120] In the process of retaining the metal above the groove a and groove d, and between the groove b and groove c through the photolithography and etching process, the photolithography operation is first performed using a high-precision photolithography machine and a custom-designed mask. After the photolithography steps of photoresist coating, soft baking, exposure, post-baking and development, a photoresist pattern that completely corresponds to the desired metal retention pattern is formed. This photoresist pattern serves as a mask layer for subsequent etching to protect the metal area that needs to be retained. Then metal etching is performed to accurately etch away the unnecessary metal parts, leaving only the metal above the groove a and groove d, and between the groove b and groove c.

[0121] S910: After the metal patterning is completed, a passivation process is performed.

[0122] After metal patterning is completed, passivation treatment is performed to protect the device from external environmental influences. The passivation layer can be made of silicon nitride or silicon oxide.

[0123] For example, taking chemical vapor deposition of silicon nitride as an example, silane and ammonia are used as reaction gases, and deposition is performed under the conditions of a reaction chamber pressure of 10-100mTorr and a temperature of 300-600°C. The silane flow rate is 1-10sccm, and the ammonia flow rate is 10-100sccm. The deposition thickness and quality of the passivation layer are crucial to the long-term stability and reliability of the device. By optimizing the process parameters, it is ensured that the passivation layer is free of defects such as pinholes and cracks, and effectively blocks the intrusion of impurities such as water vapor and ions, thereby improving the service life and performance stability of the TVS device, and ultimately forming the required large through-current small area TVS device.

[0124] Example 2

[0125] In the basic structural unit formed by S100-S900 in Example 1, multiple doped silicons can be connected in parallel according to the needs to greatly increase the PN junction area, obtain a larger current capacity, and reduce the body resistance to obtain a lower clamping voltage. Multiple basic units can also be connected in series to obtain the required withstand voltage. Fig.11 shown.

[0126] In the design of TVS devices, the construction and combination of basic structural units have a key impact on their performance.

[0127] In terms of increasing the current carrying capacity, multiple doped silicons are connected in parallel. During the manufacturing process, each doped silicon part forms a PN junction. Multiple such PN junctions are connected in parallel, which is equivalent to connecting multiple conductive channels in parallel. At the same time, due to the existence of multiple conductive channels, the overall body resistance is reduced. According to Ohm's law, under the same current, lower body resistance will result in lower voltage drop, that is, a lower clamping voltage. This is crucial to protecting the back-end circuit from excessive voltage shocks, because the lower clamping voltage can more effectively limit transient overvoltages to a safe range and reduce the risk of damage to circuit components.

[0128] In order to meet the voltage withstand requirements, the method of expanding multiple basic units in series is adopted. Each basic unit can withstand a certain voltage in structure. When multiple basic units are connected in series, the total voltage they can withstand is equal to the sum of the voltage withstand values ​​of each basic unit. In this way, according to the specific requirements for the voltage withstand of TVS devices in actual applications, the number of basic units in series can be flexibly selected to accurately obtain the required voltage withstand value, ensuring that TVS devices can work reliably in circuit environments of various voltage levels and effectively protect circuits from damage caused by excessive voltage.

[0129] This design, which can flexibly adjust the current carrying capacity and withstand voltage value, enables TVS devices to better adapt to the needs of diverse electronic equipment and circuit systems, improving their versatility and practicality.

[0130] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0131] The block diagrams of the devices, apparatuses, equipment, and systems involved in this application are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagram. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including", "comprising", "having", etc. are open words, referring to "including but not limited to", and can be used interchangeably with them. The words "or" and "and" used here refer to the words "and / or" and can be used interchangeably with them, unless the context clearly indicates otherwise. The words "such as" used here refer to the phrase "such as but not limited to", and can be used interchangeably with them.

[0132] It should also be noted that in the apparatus, device and method of the present application, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present application.

[0133] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present application. Therefore, the present application is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features of the present invention.

[0134] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for manufacturing a TVS device with large through-current and small area, characterized in that: include: A P-type substrate is selected according to the resistivity, and an N-type epitaxial layer is formed on the P-type substrate by a chemical vapor deposition process; An oxide layer is formed on the surface of the N-type epitaxial layer by thermal oxidation or chemical vapor deposition process, and then a plurality of deep isolation grooves are etched in the epitaxial layer and extended to the P-type substrate by photolithography and dry etching process; Using in-situ polysilicon to fill deep isolation trenches; An ion implantation process is used between the deep isolation trenches to form a P-type well; Through photolithography and dry etching processes, grooves a, b, c, and d are etched in the N-type epitaxial layer; Through a deposition process, N-type doped polysilicon is filled into trenches a, b, c, and d and sealed; The surface N-type doped polysilicon and oxide layer are removed by etching process, and then the junction is pushed to the required junction voltage performance by high-temperature diffusion; By means of a deposition process, an oxide layer is deposited on the surface of the N-type epitaxial layer as a through-hole dielectric layer, through holes are opened on the through-hole dielectric layer corresponding to the positions of the grooves a, b, c, and d by means of a photolithography and etching process, and conductive metal is filled in the through holes; Metal is deposited on the through-hole dielectric layer through a deposition process, and the metal above trench a and trench d, and between trench b and trench c are retained through photolithography and etching processes, and then the required TVS device is formed after a final passivation treatment.

2. The method for manufacturing a TVS device with large through-current and small area according to claim 1, characterized in that: The P-type substrate is selected from a substrate with a resistivity between 0.001 and 0.008 Ω.cm.

3. The method for manufacturing a TVS device with large through-current and small area according to claim 1, characterized in that: The thickness of the oxide layer formed on the surface of the N-type epitaxial layer is 100-10000A; In the dry etching process, the etching gas is a mixture of fluorine-based gas and inert gas; The deep isolation trench has a width of 0.5-1.2 um and a depth of 3-25 um.

4. The method for manufacturing a TVS device with large through-current and small area according to claim 1, characterized in that: The in-situ polysilicon is filled into the deep isolation trench by using low pressure chemical vapor deposition technology.

5. The method for manufacturing a TVS device with large through-current and small area according to claim 1, characterized in that: In the ion implantation process, boron ions are selected as implanted ions, and the ion implantation energy is between 10-100 keV. Meanwhile, during the ion implantation process, rotation and scanning motion are performed.

6. The method for manufacturing a TVS device with large through-current and small area according to claim 1, characterized in that: When the grooves a, b, c, and d are etched in the N-type epitaxial layer, the depths of the grooves a, b, c, and d do not pass through the N-type epitaxial layer.

7. The method for manufacturing a TVS device with large through-current and small area according to claim 1, characterized in that: The doping concentration of the N-type doped polysilicon is 1E11-1E20cm -3 .

8. The method for manufacturing a TVS device with large through-current and small area according to claim 1, characterized in that: The through-hole dielectric layer has a thickness of 2-3 um.

9. The method for manufacturing a TVS device with large through-current and small area according to claim 1, characterized in that: The metal deposited on the through-hole dielectric layer is metal AlCu or AlSiCu.

10. A method for manufacturing a TVS device with large through-current and small area according to any one of claims 1 to 9, characterized in that: The connection method between the basic structural units of the TVS device includes: using a plurality of doped silicon in parallel and a plurality of basic structural units in series.

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