Mask pattern, semiconductor device, and method of forming fine pattern of semiconductor device

Abstract

The invention relates to a mask pattern, a semiconductor device and a method of forming a fine pattern of the semiconductor device. The mask pattern may include a first spacer and a second spacer. A first spacer may be formed over the layer. A second spacer may be formed over the first spacer. The first spacer and the second spacer may define a mesh structure having a plurality of open regions. The open region may be etched to form a hole array region and a plurality of dummy holes in the layer. The aperture array region may include a plurality of apertures. The dummy holes may be configured to surround the array of holes.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Application No. 10-2023-0132708, filed on October 5, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure generally relate to a mask pattern and a method of forming a fine pattern of a semiconductor device using the mask pattern. Background Art

[0004] As a design rule for semiconductor devices, size reduction requires higher integration, finer patterns, and improved manufacturing techniques for forming finer patterns. The prior art of semiconductor devices requires forming fine patterns with a pitch lower than the resolution of existing exposure equipment. Therefore, in order to further reduce the size of semiconductor devices, various methods for manufacturing finer patterns are currently being studied.

[0005] Recently, a method of manufacturing fine patterns may employ a spacer patterning technology (SPT) and a double patterning technology (DPT). In addition, a storage node contact hole having a fine size is formed using at least one of the SPT and the DPT. Summary of the invention

[0006] Various embodiments of the present disclosure provide a mask pattern capable of forming a storage contact hole without a bridge error.

[0007] Various embodiments of the present disclosure also provide a method of forming a fine pattern of a semiconductor device using a mask pattern having improved electrical characteristics.

[0008] According to an embodiment of the present disclosure, a mask pattern may be provided. The mask pattern may include a first spacer and a second spacer. The first spacer may be formed on a layer. The second spacer may be formed on the first spacer. The first spacer and the second spacer may define a mesh structure having a plurality of opening areas. The opening area may be etched to form a hole array area and a plurality of dummy holes in the layer. The hole array may include a plurality of holes. The dummy holes may be configured to surround the hole array. At least one of the first spacer and the second spacer may include a diagonal pattern portion and a bending pattern portion. The diagonal pattern portion may extend along a diagonal line inclined at an angle to an imaginary line, which may be connected between the center points of the holes in the hole array arranged in a horizontal direction. The bending pattern portion may be formed at both ends of the diagonal pattern portion. The bending pattern portion may extend in a horizontal direction or a longitudinal direction. At least one of the first spacer and the second spacer may include a plurality of annular patterns having an upper surface with an opening and a lower surface with an opening.

[0009] According to an embodiment of the present disclosure, a method for forming a fine pattern of a semiconductor device may be provided. In the method for forming a fine pattern of a semiconductor device, a layer may be prepared. A lower hard mask pattern may be formed on the layer. The lower hard mask pattern may include a first spacer having a plurality of ring patterns. An upper hard mask pattern may be formed on the lower hard mask pattern to form a mesh structure including a plurality of opening areas. The upper hard mask pattern may include a second spacer having a plurality of ring patterns. A mask may be formed on a portion of an edge area of ​​the mesh structure to define a dummy hole area. The plurality of opening areas may be etched to form a hole array and a plurality of dummy holes in the layer. At least one of the first spacer and the second spacer may include a diagonal pattern portion and a bending pattern portion. The diagonal pattern portion may extend along a diagonal line inclined at an angle to an imaginary line, which may be connected between the center points of the holes in the hole array arranged in a horizontal direction. The bending pattern portion may be formed at both ends of the diagonal pattern portion. The bending pattern portion may extend in a horizontal direction or a longitudinal direction. At least one of the first spacer and the second spacer may include a plurality of ring-shaped patterns having an opened upper surface and an opened lower surface.

[0010] According to an embodiment of the present disclosure, a semiconductor device may be provided. The semiconductor device may include a hole array region and a dummy hole region. The hole array region may include a plurality of holes repeatedly arranged at a first pitch along a first diagonal line and a second diagonal line intersecting the first diagonal line. The dummy hole region may include a plurality of first dummy holes and a plurality of second dummy holes. The first dummy hole may be arranged above and below an edge region of the hole array region. The first dummy hole may be repeatedly arranged at a second pitch. The second dummy hole may be arranged on the left and right sides of an edge region of the hole array region. The second dummy hole may be repeatedly arranged at a third pitch.

[0011] In an embodiment of the present disclosure, a crossing angle between the first diagonal line and the second diagonal line may be from about 50° to about 70°.

[0012] In an embodiment of the present disclosure, the holes may be repeatedly arranged at a fourth pitch in the horizontal direction. The first pitch may be substantially the same as or different from the fourth pitch.

[0013] In an embodiment of the present disclosure, a size of each first dummy hole may be different from a size of each second dummy hole.

[0014] According to an embodiment of the present disclosure, the mask pattern may use a spacer. The spacer may include two diagonal patterns, a bending pattern extending from both ends of the diagonal pattern in a horizontal direction or a longitudinal direction, and a ring pattern with an opening. The mask pattern may use a spacer to ensure the SPC process margin. The mask pattern may work by preventing parasitic holes and normal holes at the edge area of ​​the hole array area from being opened when forming a fine pattern.

[0015] In addition, the mask pattern can control the size of the opening area to control the size of the dummy hole differently using a mask configured to determine the opening of the meander pattern in the annular pattern. Therefore, the mask pattern can prevent edge errors of the hole array and bridges between holes.

[0016] Furthermore, the method of forming a fine pattern of a semiconductor device using a mask pattern can form a semiconductor device having a fine pattern with improved electrical characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other aspects, features and advantages of the subject matter of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1 is a plan view showing a hole array formed according to a mesh spacer patterning method for forming a storage node according to an embodiment of the present disclosure;

[0019] Figure 2 It is shown in Figure 1 A plan view of a structure of forming a mask for removing unnecessary holes on the hole array;

[0020] Figure 3A is a SEM (scanning electron microscope) image showing parasitic holes in a hole array formed according to a mesh spacer patterning method according to an embodiment of the present disclosure;

[0021] Figure 3B is a SEM image showing unopened holes in a hole array formed according to a mesh spacer method according to an embodiment of the present disclosure;

[0022] Figure 4 is a SEM image showing bridging at an edge region of a hole array formed according to a mesh spacer method according to an embodiment of the present disclosure;

[0023] Figure 5 is a plan view showing a mask pattern having a first mesh structure according to an embodiment of the present disclosure;

[0024] Figure 6 is a plan view showing a mask pattern having a second mesh structure according to an embodiment of the present disclosure;

[0025] Figure 7 is a plan view showing a first spacer formed on an etch target layer according to an embodiment of the present disclosure;

[0026] Fig. 8A It is shown Figure 7 an enlarged plan view of a first ring-shaped pattern of a first spacer;

[0027] Figure 8B It is shown Figure 7 an enlarged plan view of a second ring-shaped pattern of a first spacer;

[0028] Fig. 9 is a plan view showing a 2-1 spacer formed on an etch target layer according to an embodiment of the present disclosure;

[0029] Fig.10 is a plan view showing a mask pattern having a mask on a first mesh structure according to an embodiment of the present disclosure;

[0030] Fig.11 is a plan view showing a partial area of ​​an etch target layer having a hole array and dummy holes formed using a mask on a first mesh structure according to an embodiment of the present disclosure;

[0031] Fig.12 is a plan view showing a portion of an etch target layer having a hole array and dummy holes formed by a first mesh structure according to an embodiment of the present disclosure;

[0032] Fig.13 is a plan view showing a 2-2 spacer formed on an etch target layer according to an embodiment of the present disclosure;

[0033] Fig.14 is a plan view showing a mask pattern having a mask on a second mesh structure according to an embodiment of the present disclosure;

[0034] Fig.15 is a plan view showing a partial area of ​​an etch target layer having a hole array and dummy holes formed using a mask on a second mesh structure according to an embodiment of the present disclosure;

[0035] Fig.16 is a flow chart of a method for forming a fine pattern of a semiconductor device according to an embodiment of the present disclosure;

[0036] Figures 17 to 26 is a perspective view showing a method of forming a first mesh structure according to an embodiment of the present disclosure;

[0037] Figures 27 to 31 is a perspective view illustrating a method of forming a second mesh structure according to an embodiment of the present disclosure; and

[0038] Fig.32 and Fig.33 is a plan view showing a semiconductor device having layers according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] Various embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The accompanying drawings are schematic illustrations of various embodiments and intermediate structures. Therefore, variations in the illustrated configurations and shapes are to be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, the described embodiments should not be interpreted as limited to the specific configurations and shapes shown herein, but may include deviations in configurations and shapes that do not depart from the scope of the present disclosure as defined by the appended claims.

[0040] The present invention is described herein with reference to the cross-sectional views and / or plan views of the embodiments of the present disclosure. However, the embodiments of the present disclosure should not be construed as limiting the inventive concept. Although some embodiments of the present disclosure will be shown and described, it will be understood by those of ordinary skill in the art that these embodiments may be changed without departing from the principles of the present disclosure.

[0041] As used herein, the term "configuration" refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device to facilitate operation of the one or more of the structure and device in a predetermined manner.

[0042] As used herein, the terms "vertical", "longitudinal", "horizontal", and "transverse" are relative to a principal plane of a structure and are not necessarily defined by the Earth's gravitational field. A "horizontal" or "transverse" direction is a direction substantially parallel to a principal plane of a structure, while a "vertical" or "longitudinal" direction is a direction substantially perpendicular to a principal plane of a structure. A principal plane of a structure is defined by a surface of the structure having a relatively large area compared to other surfaces of the structure. With reference to the accompanying drawings, a "horizontal" or "transverse" direction may be perpendicular to an indicated "Z" axis, and may be parallel to an indicated "X" axis and / or parallel to an indicated "Y" axis; a "vertical" or "longitudinal" direction may be parallel to an indicated "Z" axis, may be perpendicular to an indicated "X" axis, and may be perpendicular to an indicated "Y" axis.

[0043] As used herein, for ease of description, spatially relative terms (e.g., "below," "below," "bottom," "above," "upper," "top," "front," "back," "left," "right," etc.) may be used to describe the relationship between an element or feature as shown in the figure and another element or feature. Unless otherwise stated, spatially relative terms are intended to cover different orientations of materials in addition to the orientations depicted in the figure. For example, if the material in the figure is inverted, the element described as "below" or "below" or "under" or "bottom" of other elements or features will be oriented to be "above" or "top" of other elements or features. Therefore, depending on the context in which the term is used, the term "below" can cover both the orientation of the above and below, which is obvious to those of ordinary skill in the art. The material can be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped) and the spatially relative descriptors used herein are interpreted accordingly.

[0044] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0045] As used herein, the phrases "coupled" and "connected" refer to structures that are operatively connected to one another, such as by a direct ohmic connection or by an indirect connection (eg, electrical connection through another structure).

[0046] As used herein, the term "substantially" in reference to a given parameter, property, or condition means and includes the extent to which one of ordinary skill in the art would understand the given parameter, property, or condition to be met with some degree of variation, such as within an acceptable tolerance range. For example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be at least 90.0% met, at least 95.0% met, at least 99.0% met, at least 99.9% met, or even 100.0% met.

[0047] The spacer patterning technology (SPT) can form spacers for patterning an etching target layer. The spacer structure includes a line width lower than the resolution of an exposure device.

[0048] In order to form a mask pattern having a plurality of holes such as storage node contact holes using SPT, immersion lithography such as ArF (argon / fluoride) immersion can be used. However, since it is impossible to form a mask pattern including holes arranged below a 30nm pitch by ArF immersion-based SPT, a mesh spacer patterning technology (Mesh SPT) is proposed.

[0049] According to an embodiment of the present disclosure, Figure 1is a plan view showing a hole array formed according to a mesh spacer patterning method for forming a storage node, Figure 2 It is shown in Figure 1 A plan view of a structure of a mask for removing unnecessary holes formed on a hole array, Figure 3A is a SEM (scanning electron microscope) image showing parasitic holes in a hole array formed according to a mesh spacer patterning method, Figure 3B is a SEM image showing unopened holes in a hole array formed according to the mesh spacer method, and Figure 4 is a SEM image showing bridging at the edge region of a hole array formed according to the mesh spacer method.

[0050] Reference Figure 1 , at least one first spacer 910 extends in a first direction. At least one second spacer 930 extends in a second direction different from the first direction. For example, the second spacer 930 extends to pass through the first spacer 910. The first spacer 910 and the second spacer 930 may form a mesh structure. In addition, the area where the hole is formed is defined at the intersection between the first spacer 910 and the second spacer 930. For example, the arrangement of the holes may be defined as a hole array, and the above-mentioned method for forming the hole array may refer to the mesh spacer patterning method.

[0051] Reference Figure 2 , the hole array may include an undesired hole UH in an edge portion of the hole array. The SPC (SN periclose) mask 950 may cover the edge portion of the hole array to prevent undesired holes UH from being formed in the edge region of the hole array. Here, the edge region may be a boundary region of a cell array region including the hole array and a peripheral region P in which a peripheral circuit is integrated.

[0052] In a 6F2 layout having diagonal cells of a DRAM (Dynamic Random Access Memory) device, holes H for storage nodes may be arranged in a zigzag shape. Therefore, in the 6F2 layout, normal holes NH and unnecessary holes UH are continuously arranged at a fine pitch.

[0053] Depending on the position of the SPC mask 950, this may result in a parasitic hole PH (see Figure 3A ), where undesirable pores are not removed, or unopened pores (NO) may occur (see Figure 3B ). The unopened pores are a phenomenon in which abnormal pores are formed at positions where normal pores NH should be formed.

[0054] In addition, if Figure 4As shown, as described above, a parasitic hole (PH), a non-opened hole (NO) or a bridge error (BE) is generated. The bridge error BE refers to a phenomenon in which a defect occurs during hole formation and a plurality of adjacent holes (H) are connected at the lower end.

[0055] In order to control the error, it may be necessary to prevent the generation of parasitic holes PH and unopened holes NO by ensuring the SPC process margin.

[0056] Figure 5 is a plan view illustrating a mask pattern having a first mesh structure according to an embodiment of the present disclosure.

[0057] Reference Figure 5 , the mask pattern of the embodiment may include a first mesh structure MS1. The first mesh structure MS1 may include a first spacer S1 and a 2-1 spacer S2a. The 2-1 spacer S2a may be formed on the first spacer S1. The first mesh structure MS1 may define a plurality of first openings O1 and a plurality of second openings O2 formed by the first spacer S1 and the 2-1 spacer S2a.

[0058] The first spacer S1 may face the 2-1 spacer S2a. The first spacer S1 and the 2-1 spacer S2a may be linearly symmetrical with respect to the horizontal direction X or the longitudinal direction Y.

[0059] For example, the first spacer S1 may be formed by a first SPT process. The 2-1 spacer S2a may be formed by a second SPT process. The first SPT process and the second SPT process may be described in detail later.

[0060] Figure 6 is a plan view illustrating a mask pattern having a second mesh structure according to an embodiment of the present disclosure.

[0061] Reference Figure 6 , the mask pattern of the embodiment may include a second mesh structure MS2 formed by the first spacer S1 and the 2-2 spacer S2b. The 2-2 spacer S2b may be formed on the first spacer S1. The first mesh structure MS1 may define a plurality of first openings O1 and a plurality of second openings O2 formed by the first spacer S1 and the 2-2 spacer S2b.

[0062] The first spacer S1 may be formed by a first SPT process. The 2-2 spacer S2b may be formed by a second SPT process. The first SPT process and the second SPT process may be described in detail later.

[0063] Hereinafter, a mask pattern including a first mesh structure MS1 formed using a first spacer S1 and a 2-1 spacer S2a may be illustrated.

[0064] Figure 7is a plan view showing a first spacer formed on an etch target layer according to an embodiment of the present disclosure, Fig. 8A It is shown Figure 7 FIG. 4 is an enlarged plan view of a first ring-shaped pattern of a first spacer. Figure 8B It is shown Figure 7 FIG. 4 is an enlarged plan view of the second ring-shaped pattern of the first spacer.

[0065] Reference Figure 7 , the first spacer S1 may be formed on the etching target layer 120. The first spacer S1 may include a plurality of first annular patterns 10a and a plurality of second annular patterns 10b. Each of the first annular pattern 10a and the second annular pattern 10b may have a central region and end regions located at both ends of the central region. The central regions of the first annular pattern 10a and the second annular pattern 10b may extend in the first diagonal direction D1 and may be referred to as a first diagonal pattern portion 11. The second annular pattern 10b may be arranged on both sides of the first annular pattern 10a in a point-symmetrical structure based on the center point CP.

[0066] Reference Fig. 8A , the first annular pattern 10a may include a first diagonal pattern portion 11 and a first longitudinal bend pattern portion 12. For example, the first diagonal pattern portion 11 may extend along the first diagonal line D1. The first longitudinal bend pattern portion 12 may be formed at both ends of the first diagonal pattern portion 11. The first longitudinal bend pattern portion 12 may extend along the longitudinal direction Y. The first annular pattern 10a may include an opening 15 formed at a central portion of the first diagonal pattern portion 11 and the first longitudinal bend pattern portion 12.

[0067] Reference Figure 8B The second annular pattern 10 b may include a first diagonal pattern portion 11 , a first longitudinal bending pattern portion 12 , and a first horizontal bending pattern portion 13 .

[0068] The first diagonal pattern portion 11 may extend along the first diagonal line D1. The first longitudinal bend pattern portion 12 may be formed at one end of the first diagonal pattern portion 11. The first longitudinal bend pattern portion 12 may extend along the longitudinal direction Y. The first horizontal bend pattern portion 13 may be formed at the other end of the first diagonal pattern portion 11. The first horizontal bend pattern portion 13 may extend along the horizontal direction X. The second annular pattern 10b may include an opening 15 formed at a central portion of the first diagonal pattern portion 11, the first longitudinal bend pattern portion 12, and the first horizontal bend pattern portion 13.

[0069] Specifically, the first diagonal pattern portion 11 may extend along the first diagonal direction D1. The first diagonal pattern portion 11 may include two rod structures BS1 and BS2 spaced apart from each other. The first longitudinal bending pattern portion 12 and the first horizontal bending pattern portion 13 may include a semi-ring structure HR connected to both ends of the first diagonal pattern portion 11, respectively. For example, the semi-ring structure HR may be an open curved structure. The first annular pattern 10a may include a semi-ring structure HR connected to the rod structures BS1 and BS2 in the longitudinal direction. The second annular pattern 10b may include a semi-ring structure HR connected to both ends of the rod structures BS1 and BS2 in the longitudinal direction Y and the horizontal direction X.

[0070] The first longitudinal bending pattern portion 12 and the first horizontal bending pattern portion 13 may extend at an obtuse angle from both ends of the first diagonal pattern portion 11. For example, the angle θ between the bar structures BS1 and BS2 and the half ring structure HR may be an obtuse angle.

[0071] Furthermore, the sizes of the plurality of holes H may be adjusted by the sizes of the first diagonal pattern portion 11 , the first longitudinal bending pattern portion 12 , and the first horizontal bending pattern portion 13 .

[0072] Fig. 9 is a plan view showing a 2-1 spacer formed on an etch target layer according to an embodiment of the present disclosure.

[0073] Reference Fig. 9 , a 2-1 spacer S2a may be formed on the etch target layer 120. The 2-1 spacer S2a may include a first ring pattern 10a and a second ring pattern 10b.

[0074] The plurality of first ring patterns 10 a and the plurality of second ring patterns 10 b may extend in a second diagonal direction D2 opposite to the first diagonal direction D1 .

[0075] Fig.10 is a plan view illustrating a mask pattern having a mask on a first mesh structure according to an embodiment of the present disclosure.

[0076] Reference Fig.10, the first mesh structure MS1 may include a first spacer S1 and a 2-1 spacer S2a formed on the first spacer S1. The first mesh structure MS1 may include a plurality of openings O1 and O2. The plurality of openings O1 and O2 may be defined by the central portions of the first and second ring patterns 10a and 10b in the first spacer S1 and the central portions of the first and second ring patterns 10a and 10b in the 2-1 spacer S2a. Both ends of the first spacer S1 may overlap with both ends of the 2-1 spacer S2a. The first opening O1 may form a space in which a plurality of holes may be formed after etching the etching target layer 120. The second opening O2 may form a space in which a plurality of dummy holes may be formed after etching the etching target layer 120.

[0077] A mask M may be formed on the first mesh structure MS1. The mask M may determine the size of the second opening O2 (ie, dummy hole) on the first mesh structure MS1.

[0078] Specifically, the mask M may cover portions of both ends of the annular patterns 10a and 10b to define the size of the second opening O2. When the area of ​​the mask M covering both ends of the annular patterns 10a and 10b may be increased, the size of the second opening O2 may be reduced, so that the size of the dummy hole may also be reduced. Conversely, when the area of ​​the mask M covering both ends of the annular patterns 10a and 10b may be reduced, the size of the second opening O2 may be increased.

[0079] More specifically, the mask M may be disposed on both ends of the annular patterns 10a and 10b to cover both ends of the annular patterns 10a and 10b. The mask M may increase the margin between the normal holes located at the outermost edge of the hole array region 121 and the dummy holes of the dummy hole region 123. For example, the size of the dummy holes may be adjusted by the size of the opening area of ​​the mask M. In addition, the mask M may increase the size of the dummy holes O2 to prevent the normal holes located at the outermost edge of the hole array region 121 (hereinafter, edge normal holes) from not being opened.

[0080] A plurality of holes for forming a hole array may be formed in the hole array region 121 by the first mesh structure SM1 and the mask M for forming the openings O1 and O2. The hole array region 121 may be located at the central portion of the ring patterns 10a and 10b. The size of the second opening O2 at both ends of the ring patterns 10a and 10b may be controlled by the mask M to form a dummy hole.

[0081] In an embodiment of the present disclosure, a size of the second opening O2 may be larger than a size of the first opening O1 .

[0082] Specifically, the size of the second opening O2 may be about 105% to about 200% of the size of the first opening O1. When the ratio of the area of ​​the second opening O2 to the area of ​​the first opening O1 may be lower than about 105%, the edge normal hole may not be opened. On the contrary, when the ratio of the area of ​​the second opening O2 to the area of ​​the first opening O1 may be higher than about 200%, a bridging error may occur. That is, the size of the dummy hole formed by the second opening O2 may be larger than the size of the hole formed by the first opening O1.

[0083] In an embodiment of the present disclosure, in the first mesh structure MS1, the first diagonal direction D1 and the second diagonal direction D2 may cross each other at an angle A (hereinafter, a cross angle). The cross angle A1 between the first diagonal direction D1 and the second diagonal direction D2 may be about 40° to about 90°. When the cross angle A1 may exceed the range (about 40° to about 90°), the hole may not be formed at the desired position. Examples of holes formed by the first mesh structure MS1 may be as follows: Fig.11 shown.

[0084] Specifically, the intersection angle A1 between the first diagonal direction D1 and the second diagonal direction D2 may be about 50° to about 70°, preferably about 60°.

[0085] Therefore, in the first mesh structure MS1, the central portions of the ring patterns 10a and 10b of the first spacer S1 and the 2-1 spacer S2a may extend in different directions to have a mesh structure. In the first mesh structure MS1, both ends and the central region of the ring patterns 10a and 10b may overlap with each other to form a cross region and a non-cross region. The non-cross region may form openings O1 and O2. Then, the first mesh structure MS1 having the openings O1 and O2 may be used to selectively etch the etching target layer 120 to form a hole in the etching target layer 120.

[0086] Fig.11 is a plan view showing a partial area of ​​an etch target layer having a hole array and dummy holes formed using a mask on a first mesh structure according to an embodiment of the present disclosure.

[0087] Reference Fig.11 A plurality of holes H for forming a hole array may be formed in the central portion of the ring patterns 10a and 10b (i.e., the hole array region 121) by the first mesh structure MS1 and the mask M. In the first mesh structure MS1, a plurality of dummy holes DH may be formed at both ends of the ring patterns 10a and 10b, i.e., in the dummy hole region 123.

[0088] In an embodiment of the present disclosure, the first diagonal direction D1 and the second diagonal direction D2 may be inclined at a predetermined angle to an imaginary line IL, which may connect between the center points of the holes H in the horizontal direction X in the hole array region 121 of the etch target layer 120. The horizontal direction X may be substantially parallel to the imaginary line IL. The longitudinal direction Y may be substantially perpendicular to the imaginary line IL.

[0089] In addition, an angle A2 between the first diagonal direction D1 and the imaginary line IL may be from about 40° to about 70°, and an angle A3 between the second diagonal direction D2 and the imaginary line IL may be from about 110° to about 135°.

[0090] In the drawings, the first spacer S1 may include annular patterns 10a and 10b extending along the first diagonal direction D1. The 2-1 spacer S2a may include annular patterns 10a and 10b extending along the second diagonal direction D2. Alternatively, the first diagonal line D1 and the second diagonal line D2 may be replaced with each other. That is, the first spacer S1 may include annular patterns 10a and 10b extending along the second diagonal direction D2. The 2-1 spacer S2a may include annular patterns 10a and 10b extending along the first diagonal direction D1.

[0091] Fig.12 is a plan view showing a portion of an etch target layer having a hole array and dummy holes formed by a first mesh structure according to an embodiment of the present disclosure.

[0092] Reference Fig.12 , the hole H and the dummy hole DH may be formed in the etch target layer 120 by the mask pattern.

[0093] In addition, the etch target layer 120 may include a hole array region 121 , a dummy hole region 123 , and a non-hole array region 125 .

[0094] Specifically, a hole array including a plurality of holes H may be formed in the hole array region 121 at the central portion of the etch target layer 120 by a mask pattern. A dummy hole DH configured to surround the hole array region 121 may be formed in the dummy hole region 123 by a mask pattern. The holes H and the dummy holes DH may not be formed in the non-hole array region 125. The non-hole array region 125 may surround the dummy hole region 123. The dummy hole region 123 may be located between the hole array region 121 and the non-hole array region 125. For example, the non-hole array region 125 may be a peripheral region.

[0095] In an embodiment of the present disclosure, the hole H may form a structure such as a storage node.

[0096] Refer again Figure 6, the mask pattern of the embodiment may include a second mesh structure MS2 formed by a first spacer S1 and a 2-2 spacer S2b. The first spacer S1 may include a plurality of first ring patterns 10a and a plurality of second ring patterns 10b. The 2-2 spacer S2b may include a plurality of third ring patterns 10c. The third ring pattern 10c may extend linearly along the horizontal direction X.

[0097] The first ring pattern 10a, the second ring pattern 10b, and the third ring pattern 10c may have upper and lower surfaces with openings. The third ring pattern 10c may be formed on the first ring pattern 10a and the second ring pattern 10b. The mask pattern may include a second mesh structure MS2 formed by a first spacer S1 and a 2-2 spacer S2b to form openings O1 and O2.

[0098] Fig.13 is a plan view showing a 2-2 spacer formed on an etch target layer according to an embodiment of the present disclosure.

[0099] Reference Fig.13 , a 2-2 spacer S2b may be formed on the etch target layer 120. The 2-2 spacer S2b may include a third ring pattern 10c having a rectangular ring shape.

[0100] The third annular pattern 10c may include a line pattern portion 17 and a dummy pattern portion 18. The line pattern portion 17 may be formed in a central region of the third annular pattern 10c. The dummy pattern portion 18 may be formed at both ends of the line pattern portion 17 and may be aligned with the line pattern portion 17. The line pattern portion 17 and the dummy pattern portion 18 may have substantially the same width. An opening 19 having an upper surface and a lower surface of the opening may be formed to pass through the central region of the third annular pattern 10c.

[0101] Fig.14 is a plan view illustrating a mask pattern having a mask on a second mesh structure according to an embodiment of the present disclosure.

[0102] Reference Fig.14 , the second mesh structure MS2 may include a first spacer S1 and a 2-2 spacer S2b formed on the first spacer S1. Therefore, the central portion of the first ring pattern 10a and the second ring pattern 10b of the first spacer S1 may intersect with the central portion of the third ring pattern 10c of the 2-2 spacer S2b. In addition, both ends of the first ring pattern 10a and the second ring pattern 10b may overlap with both ends of the third ring pattern 10c. Therefore, openings O1 and O2 may be formed on the etching target layer 120. The openings O1 and O2 may form a space in which a hole or a dummy hole may be formed by etching the etching target layer 120.

[0103] A mask M may be formed on the second mesh structure MS2. The mask M may determine the size of the second opening O2 on the second mesh structure MS2.

[0104] In an embodiment of the present disclosure, the mask pattern may adjust the sizes of the holes H and the dummy holes DH in the hole array by adjusting the widths of the line pattern portion 17 and the dummy pattern portion 18 in the third ring pattern 10 c .

[0105] Fig.15 is a plan view showing a partial area of ​​an etch target layer having a hole array and dummy holes formed using a mask on a second mesh structure according to an embodiment of the present disclosure.

[0106] Reference Fig.15 , the hole H may be formed in the hole array region 121. For example, the hole H may be defined by the central portion of the ring patterns 10a and 10c in the second mesh structure MS2 and the mask M. The dummy hole DH may be formed in the dummy hole region 123. For example, the dummy hole DH may be defined by both ends of the ring patterns 10a and 10b of the second mesh structure MS2 and the mask M.

[0107] In the embodiment of the present disclosure, in the second mesh structure MS, central portions of the first ring pattern 10 a , the second ring pattern 10 b , and the third ring pattern 10 c may cross each other.

[0108] That is, the intersection angle A4 between the first diagonal direction D1 and the horizontal direction X of the third annular pattern 10c may be about 45° to about 90°. When the intersection angle may exceed this range (about 45° to about 90°), the hole may not be formed at the desired position. Examples of the holes formed by the second mesh structure MS2 may be as follows: Fig.15 shown.

[0109] Specifically, a crossing angle A4 between the first diagonal direction D1 of the third annular pattern 10 c and the horizontal direction X may be about 50° to about 70°, preferably about 60°.

[0110] In an embodiment of the present disclosure, the area of ​​the dummy hole DH may be larger than the area of ​​the hole H in the hole array.

[0111] For example, the ratio of the area of ​​the dummy hole DH to the area of ​​the hole H may be about 105% to about 200%. When the area ratio may be lower than about 105%, the edge normal hole may not be opened. On the contrary, when the area ratio may be higher than about 200%, a bridging error may occur.

[0112] In an embodiment of the present disclosure, the positions of the ring patterns 10a, 10b, and 10c may be replaced with each other. That is, a 2-2 spacer S2b may be formed to replace the first spacer S1. The first spacer S1 may be formed on the 2-2 spacer S2b.

[0113] According to an embodiment of the present disclosure, the mask pattern may utilize spacers S1 and S2a. The spacers S1 and S2a may include a diagonal pattern, a bending pattern, and annular patterns 10a and 10b. The bending pattern may extend from both ends of the diagonal pattern in a horizontal direction or a longitudinal direction. The annular patterns 10a and 10b may include openings. Alternatively, the mask pattern may utilize spacers S1 and S2b including annular patterns extending linearly in the horizontal direction. The mask pattern may utilize spacers S1, S2a, and S2b to ensure the SPC process margin. The mask pattern may prevent parasitic holes and unopened edge normal holes from appearing when forming fine patterns of semiconductor devices. That is, sufficient space may be formed between the outermost holes and the dummy holes in the hole array region to ensure the SPC process margin and prevent the formation of parasitic holes and unopened normal holes.

[0114] In addition, the mask pattern can control the size of the opening area using the mask M configured to determine the opening of the ring patterns 10a, 10b and 10c, thereby controlling the size of the dummy hole. Therefore, the mask pattern can prevent edge errors of the hole array and bridges between holes.

[0115] Therefore, the method of forming a fine pattern of a semiconductor device using a mask pattern can manufacture a semiconductor device having an improved fine pattern.

[0116] According to an embodiment of the present disclosure, Fig.16 is a flow chart of a method for forming a fine pattern of a semiconductor device, Figures 17 to 26 is a perspective view showing a method of forming a first mesh structure.

[0117] Reference Fig.16 , the method for forming a fine pattern may include an operation S100 for forming an etching target layer, an operation S200 for forming a lower hard mask pattern having a first spacer, an operation S300 for forming an upper hard mask pattern having a second spacer, an operation S400 for forming a mesh structure including the first spacer and the second spacer and forming a mask on the mesh structure, and an operation S500 for forming a hole and a dummy hole in the etching target layer.

[0118] Reference Fig.16 and Fig.17 , in operation S100 , an etch target layer 120 may be formed on a substrate 110 .

[0119] In an embodiment of the present disclosure, the etch target layer 120 may include a material etched by a subsequent etching process. For example, the etch target layer 120 may include a silicon layer, a metal layer, a silicon oxide layer, a silicon nitride layer, a combination thereof, etc. Specifically, the etch target layer 120 may include a silicon oxide layer.

[0120] Specifically, the etching target layer 120 may include phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), tetraethyl orthosilicate (TEOS), plasma-enhanced TEOS (PE-TEOS), high-density plasma chemical vapor deposition (HDP-CVD) oxide, combinations thereof, and the like.

[0121] In an embodiment of the present disclosure, the etch target layer 120 may include a plurality of regions.

[0122] For example, the etch target layer 120 may include a hole array region 121 , a dummy hole region 123 , and a non-hole array region 125 .

[0123] A plurality of holes may be formed in the hole array region 121. The holes in the hole array region 121 may form an array in which the holes are spaced apart from each other in a regular pattern. The hole array region 121 may be formed in a central portion of the etching target layer 120. The dummy hole region 123 may surround the hole array region 121. Dummy holes may be formed in the dummy hole region 123. Holes and dummy holes may not be formed in the non-hole array region 125. The non-hole array region 125 may surround the dummy hole region 123. The dummy hole region 123 may be located between the hole array region 121 and the non-hole array region 125.

[0124] When the etching target layer is viewed on a plane, the position of the dummy hole region 123 may be an upper side T, a lower side B, a left side L, and a right side R according to the position of the surrounding hole array region 121 .

[0125] The etch target layer 120 may be formed on a substrate 110. The substrate 110 may include a silicon substrate, a silicon germanium substrate, a silicon on insulator (SOI) substrate, etc. The substrate 110 may include a conductive layer, a conductive structure having a conductive layer, etc. The substrate 110 may include an impurity region, an upper insulating layer, etc.

[0126] In operation S200 , a lower hard mask pattern including first spacers may be formed on the etch target layer 120 .

[0127] Reference Fig.18, a first hard mask layer 130 may be formed on the etch target layer 120. The first hard mask layer 130 may include a material having an etch selectivity relative to the etch target layer 120. For example, the first hard mask layer 130 may include silicon nitride or carbon. The first hard mask layer 130 may be formed by CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition), but is not limited thereto.

[0128] The first photoresist pattern 140 may be formed on the first hard mask layer 130. The first photoresist pattern 140 may include a plurality of first preliminary opening patterns 141 and a plurality of second preliminary opening patterns 143. For example, the first photoresist pattern 140 may be provided to form a first spacer S1. The first photoresist pattern 140 may be formed by a photolithography process. For example, each of the first preliminary opening pattern 141 and the second preliminary opening pattern 143 may be repeatedly arranged at a first spacing P1 from each other. The first spacing P1 may be changed to adjust the diameter (or width) of each hole H. Each of the first preliminary opening pattern 141 and the second preliminary opening pattern 142 may include a diagonal pattern extending along a first diagonal direction D1 and a bending pattern extending from both ends of the diagonal pattern in a horizontal direction or a longitudinal direction. The bending pattern may be inclined at an obtuse angle to both ends of the diagonal pattern.

[0129] The second preliminary opening pattern 143 may include a diagonal pattern, a longitudinal bending pattern, and a horizontal bending pattern. The diagonal pattern may extend along the first diagonal direction D1. The longitudinal bending pattern may extend from one end of the diagonal pattern along the longitudinal direction inclined at an obtuse angle to the first diagonal direction D1. The horizontal bending pattern may extend from the other end of the diagonal pattern along the horizontal direction inclined at an obtuse angle to the first diagonal direction D1. The width or area of ​​the horizontal bending pattern may be greater than the width or area of ​​the longitudinal bending pattern.

[0130] The first photoresist pattern 140 may include a first preliminary body 145 and at least one first preliminary path 147. The first preliminary opening pattern 141 and the second preliminary opening pattern 143 may be separated by the first preliminary path 147. The at least one first preliminary path 147 may be connected to the first preliminary body 145 to form a single body.

[0131] The first hard mask layer 130 may be etched using the first photoresist pattern 140 as an etch mask. Thus, the first preliminary opening pattern 141 , the second preliminary opening pattern 143 , the first preliminary body 145 , and the first preliminary via 147 may be transcribed into the first hard mask layer 130 .

[0132] Reference Fig.19The first photoresist pattern 140 may then be removed by a stripping process to form a lower hard mask pattern 130 a including a plurality of first opening patterns 131 , a plurality of second opening patterns 133 , a first body 135 , and a first path 137 .

[0133] Reference Fig. 20 , a first spacer layer 150 may be formed on the lower hard mask pattern 130a. The first spacer layer 150 may include a material having an etching selectivity with respect to the lower hard mask pattern 130a. For example, the first spacer layer 150 may include silicon oxide. The first spacer layer 150 may be formed to have a uniform thickness along the lower hard mask pattern 130a, so that the opening patterns 131 and 133 of the lower hard mask pattern 130a may not be filled by the first spacer layer 150.

[0134] The second hard mask layer 160 may be formed on the first spacer layer 150. The second hard mask layer 160 may include a material having an etch selectivity relative to the first spacer layer 150. For example, the second hard mask layer 160 may include polysilicon. Alternatively, the material of the second hard mask layer 160 may be substantially the same as that of the lower hard mask pattern 130a.

[0135] The first spacer layer 150 and the second hard mask layer 160 may be sequentially formed on the lower hard mask pattern 130a. A planarization process may be performed on the first spacer layer 150 and the second hard mask layer 160 to expose an upper surface of the lower hard mask pattern 130a.

[0136] Reference Fig.21 , the lower hard mask pattern 130a may include a first spacer S1 and a buried structure 161. The first spacer S1 may include a plurality of ring patterns 10a and 10b. The buried structure 161 is filled in the ring patterns 10a and 10b.

[0137] The process for forming the lower hard mask pattern 130 a including the first spacer S1 having the ring patterns 10 a and 10 b may be a first SPT process.

[0138] Refer again Figures 16 to 23 , in operation S300 , an upper hard mask pattern 170 a including the 2-1 spacers S2 a may be formed on the lower hard mask pattern 130 a including the first spacers S1 .

[0139] A third hard mask layer 170 may be formed on the lower hard mask pattern 130a. The third hard mask layer 170 may include a material having an etch selectivity with respect to the first spacer S1.

[0140] In an embodiment of the present disclosure, the third hard mask layer 170 may include silicon nitride or carbon. The third hard mask layer 170 may be formed by CVD or ALD, but is not limited thereto. Specifically, the third hard mask layer 170 may include amorphous carbon.

[0141] A second photoresist pattern 180 may be formed on the third hard mask layer 170. The second photoresist pattern 180 may include a plurality of third preliminary opening patterns 181 and a plurality of fourth preliminary opening patterns 183 corresponding to the 2-1 spacers S2a. The second photoresist pattern 180 may be formed by a photolithography process. The third preliminary opening patterns 181 and the fourth preliminary opening patterns 183 may be repeatedly arranged at a second pitch P2 from each other.

[0142] Specifically, the gap between the third preliminary opening patterns 181 and the gap between the fourth preliminary opening patterns 183 may be a second pitch P2. The second pitch P2 may be changed to adjust the diameter (or width) of the hole H and the dummy hole DH.

[0143] The second photoresist pattern 180 may include a second preliminary body 185 and a second preliminary path 187. The second preliminary body 185 and the second preliminary path 187 may have substantially the same functions as those of the first preliminary body 145 and the first preliminary path 147. Therefore, for the sake of brevity, the functions of the second preliminary body 185 and the second preliminary path 187 may be omitted herein.

[0144] In the first photoresist pattern 140 and the second photoresist pattern 180, each of the first preliminary opening pattern 141 and the third preliminary opening pattern 181 and each of the second preliminary opening pattern 143 and the fourth preliminary opening pattern 183 may have substantially the same width. The first preliminary opening pattern 141 and the third preliminary opening pattern 181 may have substantially the same pitch. The second preliminary opening pattern 143 and the fourth preliminary opening pattern 183 may have substantially the same pitch. The first preliminary path 147 and the second preliminary path 187 may have substantially the same width.

[0145] The third hard mask layer 170 may be etched using the second photoresist pattern 180 as an etch mask. Thus, the third preliminary opening pattern 181 and the fourth preliminary opening pattern 183 may be transcribed into the third hard mask layer 170.

[0146] Reference Fig.23 The second photoresist pattern 180 may then be removed by a stripping process to form an upper hard mask pattern 170 a. The upper hard mask pattern 170 a may include a plurality of third opening patterns 171 , a plurality of fourth opening patterns 173 , a second body 175 , and a second path 177 .

[0147] Reference Fig.24 , a second spacer layer 190 may be formed on the upper hard mask pattern 170a. The second spacer layer 190 may include a material having an etching selectivity relative to the upper hard mask pattern 170a. For example, the second spacer layer 190 may include silicon oxide. The second spacer layer 190 may have a conformal thickness. That is, the second spacer layer 190 may have a uniform thickness so that the opening patterns 171 and 173 of the upper hard mask pattern 170a may not be filled by the second spacer layer 190.

[0148] The second spacer layer 190 may be planarized to expose an upper surface of the upper hard mask pattern 170 a .

[0149] Reference Fig.25 , the upper hard mask pattern 170 a may include a 2-1 spacer S2 a having ring patterns 10 a and 10 b .

[0150] Reference Fig.26 , the lower hard mask pattern 130 a and the upper hard mask pattern 170 a may then be removed to leave the first spacer S1 and the 2-1 spacer S2 a stacked on the first spacer S1 to form a first mesh structure MS1 .

[0151] In an embodiment of the present disclosure, the process for forming the 2-1 spacer S2 a may be a second SPT process.

[0152] Reference Fig.16 , in operation S400 , a mask M may be formed on the first mesh structure MS1 having the first spacer S1 and the 2-1 spacer S2 a as the second spacer.

[0153] In operation S500, the etch target layer 120 may be etched using the first mesh structure MS1 as an etch mask to form a hole array having holes and dummy holes.

[0154] The method of forming a fine pattern of a semiconductor device may form a second mesh structure. In the method, a first spacer S1 may be formed by a first SPT process.

[0155] Figures 27 to 31 is a perspective view illustrating a method of forming a second network structure according to an embodiment of the present disclosure.

[0156] Reference Fig. 27 , a third hard mask layer 170 may be formed on the lower hard mask pattern 130a having the first spacers S1. The third hard mask layer 170 may include a material having an etch selectivity with respect to the first spacers S1.

[0157] The second photoresist pattern 180b may be formed on the third hard mask layer 170. The second photoresist pattern 180b may include a plurality of fifth preliminary opening patterns 184 having a shape similar to that of the ring-shaped belt structure (see FIG. 1 ). Fig.13 ). The fifth preliminary opening pattern 184 may be repeatedly arranged at a second pitch P2 interval from each other. The second photoresist pattern 180b may include a second preliminary body 185 and a second preliminary path 187. The second preliminary body 185 and the second preliminary path 187 may have functions substantially the same as those of the first preliminary body 145 and the first preliminary path 147, respectively. Therefore, for the sake of brevity, any further description of the functions of the second preliminary body 185 and the second preliminary path 187 may be omitted herein.

[0158] The third hard mask layer 170 may be etched using the second photoresist pattern 180 b to transcribe the fifth preliminary opening pattern 184 , the second preliminary body 185 , and the second preliminary via 187 into the third hard mask layer 170 .

[0159] Reference Fig.28 , a second upper hard mask pattern 170 b having a plurality of fifth opening patterns 174 may be formed. The second upper hard mask pattern 170 b may include a second body 175 and a second path 177 .

[0160] Reference Fig.29 , a second spacer layer 190 may be formed on the second upper hard mask pattern 170b. The second spacer layer 190 may include a material having an etch selectivity relative to the second upper hard mask pattern 170b. For example, the second spacer layer 190 may include silicon oxide. The second spacer layer 190 may be formed to have a uniform thickness so that the fifth opening pattern 174 may not be filled by the second spacer layer 190.

[0161] The second spacer layer 190 may be planarized to expose an upper surface of the second upper hard mask pattern 170 b .

[0162] Reference Fig.30 , the second upper hard mask pattern 170b may be formed on the lower hard mask pattern 130a. The second upper hard mask pattern 170b may include a 2-2 spacer S2b having a third ring pattern 10c.

[0163] Reference Fig.31, the lower hard mask pattern 130a and the second upper hard mask pattern 170b may then be removed to retain the first spacer S1 and the 2-2 spacer S2b stacked on the first spacer S1 to form a second mesh structure MS2. The 2-2 spacer S2b includes a third ring pattern 10c extending in the horizontal direction X. For reference, for ease of description, Fig.31 The third annular pattern 10c is partially shown in FIG.

[0164] A mask M for covering the non-hole array region may be formed on the second mesh structure MS2 (see Fig.14 ). The second mesh structure MS2 and the mask M may be used as an etching mask to etch the target layer 120 to form a hole array having holes and dummy holes. An example of the mask M may be Fig.15 Found in etc.

[0165] According to an embodiment of the present disclosure, the mask pattern may use a spacer having a ring pattern, which may include two diagonal patterns and a bending pattern extending in at least one of a horizontal direction and a longitudinal direction, and an opening to ensure the SPC process margin, thereby preventing the generation of parasitic holes and unopened edge normal holes.

[0166] In addition, the size of the dummy hole can be controlled by adjusting the area of ​​the mask used to cover the non-hole array area. In addition, bridging errors can be prevented by adjusting the area of ​​the mask used to cover the non-hole array area.

[0167] Fig.32 and Fig.33 is a plan view showing a semiconductor device having an etch target layer according to an embodiment of the present disclosure.

[0168] Reference Fig.32 and Fig.33 The semiconductor device of the embodiment may include an etch target layer 120 a. The etch target layer 120 a may include a hole array region 121 and a dummy hole region 123. The etch target layer 120 a may further include a non-hole array region 125 configured to surround the dummy hole region 123.

[0169] The hole array region 121 may include a plurality of holes H. The holes H may be repeatedly arranged along the second diagonal direction D2 and spaced apart from each other by a third pitch P3. The holes H may be used to form a structure such as a storage node.

[0170] In addition, the holes H may be spaced apart from each other along the horizontal direction X by a fourth interval P4.

[0171] The third pitch P3 may be substantially the same as the fourth pitch P4. Alternatively, the third pitch P3 may be different from the fourth pitch P4.

[0172] In an embodiment of the present disclosure, a crossing angle between the first diagonal direction D1 and the second diagonal direction D2 may be from about 50° to about 70°.

[0173] The dummy hole region 123 may include a plurality of dummy holes DH. The dummy holes DH may be repeatedly arranged in the edge region of the hole array region 121 at fifth pitches P5-1 and P5-2 spaced apart from each other in the horizontal and longitudinal directions, respectively.

[0174] Specifically, the dummy holes DH may be spaced apart from each other at a 5-1 pitch P5-1 in the horizontal direction X and repeatedly arranged at the upper side T and the lower side B in the edge region of the hole array region 121. The dummy holes DH may be spaced apart from each other at a 5-2 pitch P5-2 in the longitudinal direction Y and repeatedly arranged at the left side L and the right side R in the edge region of the hole array region 121. The 5-1 pitch P5-1 may be substantially equal to or different from the 5-2 pitch P5-2.

[0175] The size and shape of the dummy hole DH at the upper side T and the lower side B may be different from Fig.28 and Fig.29 The size and shape of the dummy hole DH at the left side L and the right side R in FIG.

[0176] The hole array region 121 having the holes H and the dummy hole region 123 having the dummy holes DH may be formed using the mask pattern.

[0177] The above embodiments of the present disclosure are intended to illustrate rather than limit the present invention. A variety of alternatives and equivalents are possible. The present invention is not limited to the embodiments described herein. The present invention is also not limited to any particular type of semiconductor device. Additions, reductions, or modifications to the embodiments that are apparent in light of the present disclosure are intended to fall within the scope of the appended claims. In addition, these embodiments may be combined to form additional embodiments.

Claims

1. A mask pattern, comprising: a first spacer formed on the etching target layer; as well as a second spacer formed on the first spacer, wherein a plurality of openings of the mesh structure formed by the first spacer and the second spacer are etched to form a hole array region and a plurality of dummy holes, the hole array region including a plurality of holes, and the plurality of dummy holes surrounding the hole array region, wherein at least one of the first spacer and the second spacer comprises a plurality of annular patterns, the annular patterns having an open upper surface and a lower surface, and Wherein, each of the annular patterns includes a diagonal pattern portion and a bending pattern portion, the diagonal pattern portion extends in a diagonal direction, the diagonal direction is inclined relative to an imaginary line extending in a horizontal direction and connecting the center points of the holes in the hole array area, and the bending pattern portion extends from both ends of the diagonal pattern portion along the horizontal direction or the longitudinal direction.

2. The mask pattern according to claim 1, in, The first spacer is formed on the etching target layer; wherein the second spacer is formed on the first spacer, and Wherein, the area of ​​each of the dummy holes is larger than the area of ​​each of the holes in the hole array region.

3. The mask pattern according to claim 1, wherein: The area of ​​each of the dummy holes is about 105% to about 200% of the area of ​​each of the holes in the hole array region.

4. The mask pattern according to claim 1, wherein: The width of the bending pattern portion is wider than the width of the diagonal pattern portion.

5. The mask pattern according to claim 1, in, The first spacer includes a plurality of annular patterns having an upper surface and a lower surface with openings, each of the annular patterns includes a diagonal pattern portion and a bending pattern portion, the diagonal pattern portion extending along a first diagonal direction, and the bending pattern portion extending from both ends of the diagonal pattern portion along the horizontal direction or the longitudinal direction, wherein the second spacer comprises a plurality of annular patterns having an upper surface and a lower surface with openings, each of the annular patterns comprises a diagonal pattern portion and a bending pattern portion, the diagonal pattern portion extends along a second diagonal direction, and the bending pattern portion extends from both ends of the diagonal pattern portion along the horizontal direction or the longitudinal direction, and The diagonal pattern portion along the first diagonal direction intersects the diagonal pattern portion along the second diagonal direction, and the bending pattern portion of the first spacer overlaps the bending pattern portion of the second spacer to form the plurality of openings of the mesh structure. 6 . The mask pattern of claim 5 , further comprising a mask disposed over the mesh structure to determine a size of an open area formed by overlapping the bending pattern portion of the first spacer with the bending pattern portion of the second spacer.

7. The mask pattern according to claim 6, in, The holes in the hole array region are formed in the opening region formed by crossing the diagonal pattern portion in the first diagonal direction with the diagonal pattern portion in the second diagonal direction, and The dummy holes are formed in the opening formed by overlapping the bending pattern portion of the first spacer with the bending pattern portion of the second spacer, and a size of each of the dummy holes is determined by the mask.

8. The mask pattern according to claim 1, in, The first spacer includes a plurality of annular patterns having an upper surface and a lower surface with openings, each of the annular patterns includes a diagonal pattern portion and a bending pattern portion, the diagonal pattern portion extending along a first diagonal direction, and the bending pattern portion extending from both ends of the diagonal pattern portion along the horizontal direction or the longitudinal direction, wherein the second spacer includes a plurality of annular patterns having an upper surface and a lower surface with openings, each of the annular patterns includes a line pattern portion and a dummy pattern portion, the line pattern portion horizontally extending along the horizontal direction, and the dummy pattern portion horizontally extending from both ends of the line pattern portion, and The diagonal pattern portion of the first spacer crosses the diagonal pattern portion of the second spacer, and the bending pattern portion of the first spacer overlaps the bending pattern portion of the second spacer to form the plurality of openings of the mesh structure. 9 . The mask pattern of claim 8 , further comprising a mask disposed over the mesh structure to determine a size of an open area formed by overlapping the bending pattern portion of the first spacer with the bending pattern portion of the second spacer.

10. A method for forming a fine pattern of a semiconductor device, the method comprising: providing an etching target layer on the substrate; forming a lower hard mask pattern on the etch target layer, the lower hard mask pattern comprising a first spacer having a plurality of ring-shaped patterns; forming an upper hard mask pattern on the lower hard mask pattern to form a mesh structure having a plurality of openings, the upper hard mask pattern including a second spacer having a plurality of ring-shaped patterns; forming a mask on an edge region of the mesh structure to expose a dummy hole region and a hole array region; as well as etching the etch target layer using the lower hard mask pattern, the upper hard mask pattern, and a mask to form a plurality of holes and a plurality of dummy holes in the etch target layer, wherein at least one of the first spacer and the second spacer comprises a plurality of ring-shaped patterns having an upper surface and a lower surface with openings, and Wherein, each of the annular patterns includes a diagonal pattern portion and a bending pattern portion, the diagonal pattern portion extends in a diagonal direction, the diagonal direction is inclined relative to an imaginary line extending in a horizontal direction and connecting the center points of the holes in the hole array area, and the bending pattern portion extends from both ends of the diagonal pattern portion along the horizontal direction or the longitudinal direction.

11. The method according to claim 10, in, The first spacer includes a plurality of annular patterns having an upper surface and a lower surface with openings, each of the annular patterns includes a diagonal pattern portion and a bending pattern portion, the diagonal pattern portion extending along a first diagonal direction, and the bending pattern portion extending from both ends of the diagonal pattern portion along the horizontal direction or the longitudinal direction, wherein the second spacer comprises a plurality of annular patterns having an upper surface and a lower surface with openings, each of the annular patterns comprises a diagonal pattern portion and a bending pattern portion, the diagonal pattern portion extends along a second diagonal direction, and the bending pattern portion extends from both ends of the diagonal pattern portion along the horizontal direction or the longitudinal direction, and The diagonal pattern portion along the first diagonal direction intersects the diagonal pattern portion along the second diagonal direction, and the bending pattern portion of the first spacer overlaps the bending pattern portion of the second spacer to form the plurality of openings of the mesh structure.

12. The method according to claim 11, wherein: Forming the lower hard mask pattern includes: forming a first hard mask layer on the etch target layer; forming a first photoresist pattern on the first hard mask layer, the first photoresist pattern comprising a plurality of first preliminary opening patterns and a plurality of second preliminary opening patterns; etching the first hard mask layer using the first photoresist pattern as an etch mask to form a first hard mask pattern including a first opening pattern and a second opening pattern; forming a first spacer layer and a second hard mask layer on the first hard mask pattern; and partially removing the second hard mask layer and the first spacer layer to form a lower hard mask pattern having first spacers on the etch target layer, wherein the first spacer comprises a plurality of ring-shaped patterns having an upper surface and a lower surface with openings, and Each of the annular patterns includes a diagonal pattern portion and a bending pattern portion, the diagonal pattern portion extends along a first diagonal direction, and the bending pattern portion extends from both ends of the diagonal pattern portion along the first diagonal direction.

13. The method according to claim 11, wherein: Forming the network structure includes: forming a third hard mask layer on the lower hard mask pattern; forming a second photoresist pattern including a plurality of first preliminary opening patterns and a plurality of second preliminary opening patterns on the third hard mask layer; etching the third hard mask layer using the second photoresist pattern as an etch mask to form a third hard mask pattern including a first opening pattern and a second opening pattern; forming a second spacer layer on the third hard mask pattern, the second spacer layer comprising a plurality of ring-shaped patterns having an upper surface and a lower surface with an opening, each of the ring-shaped patterns comprising a diagonal pattern portion located on the bending pattern portion, and the diagonal pattern portion extending along a second diagonal direction; and The third hard mask layer and the second spacer layer are partially removed to form an upper hard mask pattern having second spacers on the etch target layer, thereby forming a mesh structure having a plurality of open areas through the first spacers and the second spacers.

14. The method according to claim 13, wherein: The bending pattern portion has a width wider than a width of the diagonal pattern portion in the first diagonal direction and the second diagonal direction.

15. The method according to claim 10, in, The first spacer includes a plurality of annular patterns having an upper surface and a lower surface with openings, each of the annular patterns includes a diagonal pattern portion and a bending pattern portion, the diagonal pattern portion extending along a first diagonal direction, and the bending pattern portion extending from both ends of the diagonal pattern portion along the horizontal direction or the longitudinal direction, wherein the second spacer includes a plurality of annular patterns having an upper surface and a lower surface with openings, each of the annular patterns includes a line pattern portion and a dummy pattern portion, the line pattern portion horizontally extending along the horizontal direction, and the dummy pattern portion horizontally extending from both ends of the line pattern portion, and The diagonal pattern portion of the first spacer crosses the diagonal pattern portion of the second spacer, and the bending pattern portion of the first spacer overlaps the bending pattern portion of the second spacer to form the plurality of openings of the mesh structure.

16. The method according to claim 10, wherein: Forming the network structure includes: forming a third hard mask layer on the lower hard mask pattern; forming a second photoresist pattern including a plurality of third preliminary opening patterns on the third hard mask layer; etching the first hard mask layer using the second photoresist pattern as an etch mask to form a third hard mask pattern including a third opening pattern; forming a second spacer layer on the third hard mask pattern; and partially removing the third hard mask layer and the second spacer layer to form an upper hard mask pattern having second spacers on the etch target layer, thereby forming a mesh structure having a plurality of opening areas, The second spacer includes a plurality of annular patterns, and each of the annular patterns includes the line pattern portion and a dummy pattern portion.

17. A semiconductor device comprising: a hole array region, comprising a plurality of holes repeatedly arranged at a first pitch along a first diagonal direction and a second diagonal direction intersecting the first diagonal direction; as well as A dummy hole area includes a plurality of first dummy holes and a plurality of second dummy holes, wherein the first dummy holes are repeatedly arranged at a second pitch in a horizontal direction on the upper side and the lower side of the hole array area, and the second dummy holes are repeatedly arranged at a third pitch different from the second pitch in a longitudinal direction on the left side and the right side of the hole array area.

18. The semiconductor device according to claim 17, wherein: An intersection angle between the first diagonal direction and the second diagonal direction is about 50° to about 70°.

19. The semiconductor device according to claim 17, wherein: The holes are repeatedly arranged at a fourth pitch along the horizontal direction, and the first pitch is substantially equal to or different from the fourth pitch.

20. The semiconductor device according to claim 17, wherein A size of each of the first dummy holes is different from a size of each of the second dummy holes.

Images