Semiconductor device and operating method thereof

Abstract

The embodiment of the invention provides semiconductor equipment and an operation method thereof. The semiconductor equipment comprises a thimble part; the ejector pin component comprises a first base and a plurality of ejector pins located on the top of the first base. The distribution range of the plurality of ejector pins covers a plurality of chips of different sizes which need to be jacked up, and the jacking height of each ejector pin in the plurality of ejector pins can be independently controlled so as to jack up the chips of different sizes.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, a semiconductor device and an operating method thereof. Background Art

[0002] In the current chip-to-wafer bonding equipment, it is necessary to separately configure the ejector component (Ejector), the nozzle component (Pick up Head), and the bonding head component (Bonding Head). Each component is combined to match the size of a product chip. In other words, when the size of the product chip changes, it is necessary to replace the ejector component, the nozzle component, and the bonding head component of different sizes to lift or take chips of different sizes. Although the automatic change (AutoChange) function is currently implemented, calibration is required after replacement, which takes a lot of time and affects the normal operation of the machine. In addition, the number of components that can be installed on the machine is limited; in addition, when the specifications of the product chip change, it is not possible to quickly take different product chips. Summary of the invention

[0003] According to a first aspect of an embodiment of the present disclosure, there is provided a semiconductor device, including:

[0004] The ejector pin component comprises a first base and a plurality of ejector pins located on the top of the first base; the distribution range of the plurality of ejector pins covers a plurality of chips of different sizes that need to be ejected, and the ejection height of each of the plurality of ejector pins can be individually controlled to eject chips of different sizes.

[0005] In some embodiments, the ejector component further includes a plurality of first adjustment structures; the first adjustment structures are located in the first base, each of the first adjustment structures is connected to one of the ejectors, and the first adjustment structures are used to adjust the ejection height of the ejectors.

[0006] In some embodiments, the first adjustment structure includes a first cylinder unit and a first motor unit.

[0007] In some embodiments, the plurality of ejector pins are arranged in an array along a first direction and a second direction, and the first direction intersects with the second direction and is perpendicular to a thickness direction of the first base.

[0008] In some embodiments, the distance between adjacent ejector pins among a plurality of ejector pins located in a middle area of ​​the top of the first base is a first distance, and the distance between adjacent ejector pins among a plurality of ejector pins located in an edge area of ​​the top of the first base is a second distance, and the first distance is smaller than the second distance.

[0009] In some embodiments, the distance between adjacent ejector pins ranges from 1 mm to 3 mm.

[0010] In some embodiments, the semiconductor device also includes: a nozzle component; the nozzle component includes a second base and a plurality of first annular structures with a common geometric center located at the bottom of the second base; a plurality of first holes with vacuum adsorption function are arranged in the first annular structure, and each of the first annular structures can be individually controlled to rise and fall.

[0011] In some embodiments, the nozzle component further includes a plurality of second motor units; the second motor units are located in the second base, and each of the first annular structures is connected to one of the second motor units.

[0012] In some embodiments, the nozzle component further includes a first vacuum adsorption structure; the first vacuum adsorption structure is located in the second base, and the first hole is connected to the first vacuum adsorption structure.

[0013] In some embodiments, the semiconductor device also includes: a bonding head component; the bonding head component includes a third base and a plurality of second annular structures with a common geometric center located at the bottom of the third base; a plurality of second holes with vacuum adsorption function are arranged in the second annular structure, and each of the second annular structures can be individually controlled to rise and fall.

[0014] In some embodiments, the bonding head component further includes a third motor unit; the third motor unit is located in the third base, and each of the second annular structures is connected to one of the third motor units.

[0015] In some embodiments, the bonding head component further includes a second vacuum adsorption structure; the second vacuum adsorption structure is located in the third base, and the second hole is connected to the second vacuum adsorption structure.

[0016] In some embodiments, the semiconductor device includes a handler.

[0017] In some embodiments, the semiconductor device includes a bonding device.

[0018] According to a second aspect of an embodiment of the present disclosure, there is provided an operating method of a semiconductor device, wherein the semiconductor device comprises a ejector pin component; the ejector pin component comprises a first base and a plurality of ejector pins located on the top of the first base; the distribution range of the plurality of ejector pins covers a plurality of chips of different sizes that need to be ejected, and each of the plurality of ejector pins can be individually controlled to have an ejection height to eject chips of different sizes; the operating method comprises:

[0019] According to the size of the chip that currently needs to be lifted, select the ejector pins in the corresponding area to lift up, so as to lift up the chip that currently needs to be lifted up.

[0020] In some embodiments, the step of selecting to lift the pins in the corresponding area according to the size of the chip currently to be lifted includes:

[0021] According to the size of the chip currently to be lifted, lift the ejector pins in the first area among the plurality of ejector pins to a first height;

[0022] The ejector pins in the first sub-region are lifted to a second height; the second height is greater than the first height; the first sub-region is located in the middle region of the first region;

[0023] A first portion of the ejector pins in the first sub-region are lifted to a third height; the third height is greater than the second height; and the first portion of the ejector pins are located in a middle region of the first sub-region.

[0024] In some embodiments, the semiconductor device further comprises: a nozzle component; the nozzle component comprises a second base and a plurality of first annular structures with a common geometric center located at the bottom of the second base; a plurality of first holes with a vacuum adsorption function are arranged in the first annular structure, and each of the first annular structures can be individually controlled to rise and fall; the operation method further comprises:

[0025] According to the size of the chip currently required to be adsorbed, a corresponding first annular structure among the plurality of first annular structures is selected to be raised so that the chip currently required to be adsorbed can be adsorbed.

[0026] In some embodiments, the semiconductor device further comprises: a bonding head component; the bonding head component comprises a third base and a plurality of second annular structures with a common geometric center located at the bottom of the third base; a plurality of second holes with a vacuum adsorption function are arranged in the second annular structure, and each second annular structure can be individually controlled to rise and fall; the operation method further comprises:

[0027] According to the size of the chip currently to be bonded, a corresponding second ring structure among the plurality of second ring structures is selected to be lifted up, so that the chip currently to be bonded can be adsorbed.

[0028] In the disclosed embodiment, the distribution range of the plurality of ejector pins covers a plurality of chips of different sizes that need to be ejected, and the ejection height of each of the plurality of ejector pins can be individually controlled, so that the ejector pin structure can be used to eject chips of different sizes, thereby achieving compatibility with chips of different sizes, improving the efficiency of semiconductor equipment or bonding, and effectively improving the hourly chip output rate and normal operating rhythm of semiconductor equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1A schematic diagram of the structure of the ejector pin component provided in one embodiment of the present disclosure Figure 1 .

[0030] Figure 2 A schematic diagram of the structure of the ejector pin component provided in one embodiment of the present disclosure Figure 2 .

[0031] Figure 3 A schematic diagram of the structure of a nozzle component provided in an embodiment of the present disclosure Figure 1 .

[0032] Figure 4 A schematic diagram of the structure of a nozzle component provided in an embodiment of the present disclosure Figure 2 .

[0033] Figure 5 Schematic diagram of a nozzle component adsorbing a chip according to an embodiment of the present disclosure Figure 1 .

[0034] Figure 6 Schematic diagram of a nozzle component adsorbing a chip according to an embodiment of the present disclosure Figure 2 .

[0035] Figure 7 Schematic diagram of a nozzle component adsorbing a chip according to an embodiment of the present disclosure Figure 3 .

[0036] Figure 8 Schematic diagram of a nozzle component adsorbing a chip according to an embodiment of the present disclosure Figure 4 .

[0037] Fig. 9 Schematic diagram of a nozzle component adsorbing a chip according to an embodiment of the present disclosure Figure 5 .

[0038] Fig.10 Schematic diagram of a nozzle component adsorbing a chip according to an embodiment of the present disclosure Figure 6 .

[0039] Fig.11 A schematic diagram of the structure of a bonding head component provided in an embodiment of the present disclosure Figure 1 .

[0040] Fig.12 A schematic diagram of the structure of a bonding head component provided in an embodiment of the present disclosure Figure 2 .

[0041] Figures 13 to 16 A schematic diagram of a process of lifting a chip using a pin component provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0043] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0044] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0045] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0046] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0047] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0048] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure.

[0049] As the feature size of memory decreases and the interconnection density increases, memory is developing towards three-dimensional direction. Among them, hybrid bonding technology can realize the three-dimensional integration of two different functional chips (also known as tube cores). For example, hybrid bonding of memory array chips and peripheral circuit chips can realize three-dimensional memory with smaller size, higher interconnection density and lower power consumption.

[0050] The hybrid bonding process can be divided into wafer to wafer (W2W) bonding, chip to wafer (C2W) bonding and chip to chip (C2C) bonding according to the bonding object. In the current chip to wafer bonding equipment, it is necessary to separately configure the ejector pin component, the suction nozzle component and the bonding head component. Each component is combined to match the size of a product chip. In other words, when the size of the product chip changes, it is necessary to replace the ejector pin component, the suction nozzle component and the bonding head component of different sizes to lift or take chips of different sizes. Although the automatic change function is currently realized, calibration is required after the replacement, which takes a lot of time and affects the normal operation of the machine. In addition, the number of components that can be installed on the machine is limited. In addition, when the specifications of the product chip change, it is not possible to quickly take different product chips.

[0051] The present disclosure provides a semiconductor device, such as Figure 1 as well as Figure 2 As shown, it includes: a ejector pin component 101; the ejector pin component 101 includes a first base 102 and a plurality of ejector pins 103 located on the top of the first base 102; the distribution range of the plurality of ejector pins 103 covers a plurality of chips of different sizes that need to be ejected, and the ejection height of each of the plurality of ejector pins 103 can be individually controlled to eject chips of different sizes.

[0052] In the disclosed embodiment, the distribution range of the plurality of ejector pins 103 covers a plurality of chips of different sizes that need to be ejected, and the ejection height of each of the plurality of ejector pins 103 can be individually controlled, so that the ejector pin structure can be used to eject chips of different sizes, thereby achieving compatibility with chips of different sizes, achieving efficiency of semiconductor equipment or bonding, and effectively improving the hourly chip output rate and normal operating rhythm of semiconductor equipment.

[0053] In some specific examples, the area that the ejector pins 103 need to cover can be calculated according to the sizes of multiple product chips, so that the distribution range of the multiple ejector pins 103 can cover multiple chips of different sizes that need to be lifted. Each chip of the multiple chips of different sizes that need to be lifted has a corresponding length and width. The length of the chip with the largest length among the multiple chips of different sizes that need to be lifted is recorded as the first length, and the width of the chip with the largest width among the multiple chips of different sizes that need to be lifted is recorded as the first width. Exemplarily, the shape of the distribution range of the multiple ejector pins 103 can be a rectangle, the length of the rectangle can be the aforementioned first length, and the width of the rectangle can be the aforementioned first width; or, the length of the rectangle can be a length slightly smaller than the first length, and the width of the rectangle can be a width slightly smaller than the first width; or, the length of the rectangle can be a length slightly larger than the aforementioned first length, and the width of the rectangle can be a width slightly larger than the aforementioned first width. In other specific examples, the shape of the distribution range of the multiple ejector pins 103 can also be a circle, a square, etc., but the size of the circle or the square can cover all chips of different sizes that need to be lifted.

[0054] In some embodiments, the ejector component 101 further includes a plurality of first adjustment structures; the first adjustment structures are located in the first base 102 , each of the first adjustment structures is connected to one of the ejectors 103 , and the first adjustment structures are used to adjust the ejection height of the ejector 103 .

[0055] It is understandable that each ejector pin 103 may be connected to a corresponding first adjustment structure, and the ejection height of the corresponding ejector pin 103 may be adjusted through the first adjustment structure. All of the ejector pins 103 may be ejected, or only a portion of the ejector pins 103 may be ejected, and the ejection height may be adjusted. The ejector pins 103 in the corresponding area may be selected to be ejected according to the size of the chip that currently needs to be ejected.

[0056] The ejector pin 103 in the embodiment of the present disclosure has a function of controllable elasticity, that is, the ejector pin 103 in the embodiment of the present disclosure can adjust the ejection height of the ejector pin 103 through the above-mentioned first adjustment structure. When the ejection height of the ejector pin 103 is 0, it can be considered that the ejector pin 103 is not ejected.

[0057] In some embodiments, the first adjustment structure includes a first cylinder unit and a first motor unit.

[0058] In the embodiment of the present disclosure, the first cylinder unit can be located below the ejector pin 103, the first motor unit can be located below the first cylinder unit, and the first cylinder unit and the first motor unit are used together to adjust the height of the ejector pin 103; wherein, the first cylinder unit can control the movement of the ejector pin 103, and the first motor unit can control the first cylinder unit.

[0059] In some embodiments, Figure 2 As shown, the plurality of ejector pins 103 are arranged in an array along a first direction and a second direction, wherein the first direction intersects with the second direction and are both perpendicular to the thickness direction of the first base 102 .

[0060] Here, the first direction intersects with the second direction. In the embodiment of the present disclosure, the first direction and the second direction are perpendicular to each other as an example for illustrative description, but the present disclosure is not limited thereto. The first direction can be Figure 1 and Figure 2 The X-axis direction in the second direction can be Figure 1 and Figure 2 In the Y-axis direction, the thickness direction of the first base 102 can be Figure 1 and Figure 2 The Z-axis direction.

[0061] It should be noted that the plurality of ejector pins in the embodiment of the present disclosure are not limited to being arranged in an array along the first direction and the second direction as described in the above embodiment.

[0062] In some embodiments, the distance between adjacent ejector pins 103 among a plurality of ejector pins 103 located in a middle area at the top of the first base 102 is a first distance, and the distance between adjacent ejector pins 103 among a plurality of ejector pins 103 located in an edge area at the top of the first base 102 is a second distance, and the first distance is smaller than the second distance.

[0063] In the embodiment of the present disclosure, the distance between adjacent ejector pins 103 among the multiple ejector pins 103 located in the middle area of ​​the top of the first base 102 is smaller than the distance between adjacent ejector pins 103 among the multiple ejector pins 103 located in the edge area of ​​the top of the first base 102. That is to say, the ejector pins 103 located in the middle area of ​​the top of the first base 102 are more densely distributed than the ejector pins 103 located in the edge area of ​​the top of the first base 102. This can ensure that the chip is subjected to more uniform force when it is lifted, thereby improving the problem of chip breakage caused by uneven force when it is lifted, and can prevent the ejector pins 103 from hitting the edge of the chip, thereby avoiding damage to the edge of the chip.

[0064] In some embodiments, the distance between adjacent ejector pins 103 ranges from 1 mm to 3 mm.

[0065] In the disclosed embodiment, the distance between adjacent ejector pins 103 is set to be relatively small, which is beneficial to the adaptability to chips of different sizes.

[0066] It should be noted that the range of the distance between adjacent ejector pins 103 given in the above embodiment is only an example and is not intended to limit the range of the distance between adjacent ejector pins 103 in the embodiment of the present disclosure.

[0067] In some embodiments, Figure 3 as well as Figure 4 The semiconductor device further includes: a nozzle component 104; the nozzle component 104 includes a second base 106 and a plurality of first annular structures 105 with a common geometric center located at the bottom of the second base 106; a plurality of first holes 112 with a vacuum adsorption function are arranged in the first annular structure 105, and each of the first annular structures 105 can be individually controlled to rise and fall.

[0068] In the disclosed embodiment, the nozzle component 104 includes a second base 106 and a plurality of first annular structures 105 having a common geometric center. The first annular structure 105 is provided with a plurality of first holes 112 having a vacuum adsorption function, and each first annular structure 105 can be individually controlled to extend and contract, so that the nozzle structure can be used to adsorb chips of different sizes, achieving compatibility with chips of different sizes, thereby further improving the efficiency of semiconductor equipment or bonding, and further improving the hourly chip output rate and normal operating rhythm of semiconductor equipment.

[0069] In the embodiment of the present disclosure, the distance between each first ring structure 105 and the geometric center is different. The distance between adjacent first ring structures 105 in the plurality of first ring structures 105 can be set accordingly according to the size of the chip to be adsorbed.

[0070] Figure 4 The shape of the first annular structure 105 given in the specification is circular, but the present disclosure is not limited thereto. The shape of the first annular structure 105 in the present disclosure may also be rectangular, square or other shapes.

[0071] The disclosed embodiment will be exemplified by taking the first annular structure 105 as a circle. When the first annular structure 105 is a circle, the geometric center of the first annular structure 105 is the center of the circle, multiple first annular structures 105 share the same center of the circle, and the diameter of each first annular structure 105 in the multiple first annular structures 105 is different. Each first annular structure 105 can be individually controlled to rise and fall. According to the size of the chip that currently needs to be adsorbed, the corresponding first annular structure 105 can be selected to be raised to adsorb the chip that currently needs to be adsorbed, while other first annular structures 105 may not be raised, and the raised first annular structure 105 removes the chip by vacuum adsorption.

[0072] like Figures 5 to 10 As shown, when selecting which part of the first annular structures 105 to lift out, the long side of the chip 110 currently required to be adsorbed can be used as a basis for judgment, ensuring that the chip 110 currently required to be adsorbed can be successfully adsorbed and will not slip.

[0073] Here Figure 6 as well as Figure 7 for Figure 5 A top view of the structure. Fig. 9 and Fig.10 for Figure 8 A top view of the structure. Figure 5 It can be seen that part of the first annular structure 105 is not raised; Figure 8 It can be seen that all the first annular structures 105 are lifted up.

[0074] In the embodiment of the present disclosure, a plurality of first holes 112 are provided in the first annular structure 105, and the first holes 112 can be used to adsorb the chip. The plurality of first holes 112 can be evenly arranged in the first annular structure 105, so that the force on the chip is more uniform.

[0075] During the bonding process or in the chip sorting process, after the chip is lifted up by the ejector pin component 101, the chip can be taken away by the nozzle component 104. The nozzle component 104 realizes an automatic control function. After the chip is taken away, vacuum release can be used to place the chip in a specified position.

[0076] In some embodiments, the nozzle component 104 further includes a plurality of second motor units; the second motor units are located in the second base 106, and each of the first annular structures 105 is connected to one of the second motor units.

[0077] In the disclosed embodiment, the second motor unit is used to control the extension and contraction of the first annular structure 105 connected thereto.

[0078] In some embodiments, the nozzle component 104 further includes a first vacuum adsorption structure; the first vacuum adsorption structure is located in the second base 106, and the first hole 112 is connected to the first vacuum adsorption structure.

[0079] In some specific examples, the first vacuum adsorption structure includes a vacuum pipeline and a vacuum pump connected to the vacuum pipeline, the vacuum pipeline is connected to the first hole 112, and the first vacuum adsorption structure enables the first hole 112 to have a vacuum adsorption function.

[0080] In some embodiments, Fig.11 as well as Fig.12 As shown, the semiconductor device also includes: a bonding head component 107; the bonding head component 107 includes a third base 109 and a plurality of second annular structures 108 with a common geometric center located at the bottom of the third base 109; a plurality of second holes 113 with a vacuum adsorption function are arranged in the second annular structure 108, and each of the second annular structures 108 can be individually controlled to rise and fall.

[0081] In the disclosed embodiment, the bonding head component 107 includes a third base 109 and a plurality of second annular structures 108 having a common geometric center. The second annular structure 108 is provided with a plurality of second holes 113 having a vacuum adsorption function. Each second annular structure 108 can be individually controlled to rise and fall, so that the bonding head component 107 can be used to adsorb chips of different sizes to achieve compatibility with chips of different sizes, thereby further improving the efficiency of semiconductor equipment or bonding, and further improving the hourly chip output rate and normal operating rhythm of semiconductor equipment.

[0082] In the embodiment of the present disclosure, the distance between each second ring structure 108 and the geometric center is different. The distance between adjacent second ring structures 108 in the plurality of second ring structures 108 can be set accordingly according to the size of the chip to be bonded.

[0083] The shape of the second annular structure 108 in the present disclosure includes but is not limited to circle, rectangle, and square.

[0084] The disclosed embodiment will be exemplified by taking the second annular structure 108 as a circle. When the second annular structure 108 is a circle, the geometric center of the second annular structure 108 is the center of the circle, multiple second annular structures 108 share the same center of the circle, and the diameter of each second annular structure 108 in the multiple second annular structures 108 is different. Each second annular structure 108 can be individually controlled to rise and fall. According to the size of the chip that currently needs to be bonded, the corresponding second annular structure 108 can be selected to rise to adsorb the chip that currently needs to be bonded, while other second annular structures 108 may not be raised, and the raised second annular structure 108 removes the chip by vacuum adsorption.

[0085] When selecting which part of the second annular structures 108 to lift out, the long side of the chip currently to be bonded can be used as a basis for judgment, ensuring that the chip currently to be bonded can be successfully adsorbed and will not slip.

[0086] In the embodiment of the present disclosure, a plurality of second holes 113 are provided in the second annular structure 108, and the second holes 113 can be used to adsorb the chip. The plurality of second holes 113 can be evenly arranged in the second annular structure 108, so that the force on the chip is more uniform.

[0087] In some embodiments, the bonding head component 107 further includes a third motor unit; the third motor unit is located in the third base 109, and each of the second annular structures 108 is connected to one of the third motor units.

[0088] In the disclosed embodiment, the third motor unit is used to control the extension and contraction of the second annular structure 108 connected thereto.

[0089] In some embodiments, the bonding head component 107 further includes a second vacuum adsorption structure; the second vacuum adsorption structure is located in the third base 109, and the second hole 113 is connected to the second vacuum adsorption structure.

[0090] In some specific examples, the second vacuum adsorption structure includes a vacuum pipeline and a vacuum pump connected to the vacuum pipeline, the vacuum pipeline is connected to the second hole 113, and the second vacuum adsorption structure enables the second hole 113 to have a vacuum adsorption function.

[0091] In some embodiments, the semiconductor device includes a sorter.

[0092] In the disclosed embodiment, the sorting machine includes a nozzle component 104 and an ejector component 101 .

[0093] In some embodiments, the semiconductor device includes a bonding device.

[0094] In the embodiment of the present disclosure, the bonding device includes a nozzle component 104, a pin component 101 and a bonding head component 107. The bonding device here includes but is not limited to a chip-to-wafer bonding device and a chip-to-chip bonding device.

[0095] It should be noted that the semiconductor device in the embodiment of the present disclosure is not limited to the sorting machine and bonding equipment given in the above embodiments. The semiconductor device in the embodiment of the present disclosure may also be other semiconductor devices having a nozzle component 104, a ejector component 101 and a bonding head component 107.

[0096] Based on the above semiconductor device, an embodiment of the present disclosure further provides an operating method of the semiconductor device, wherein the semiconductor device comprises a ejector pin component; the ejector pin component comprises a first base and a plurality of ejector pins located on the top of the first base; the distribution range of the plurality of ejector pins covers a plurality of chips of different sizes that need to be ejected, and each of the plurality of ejector pins can be individually controlled to have an ejection height to eject chips of different sizes; the operating method comprises:

[0097] According to the size of the chip that currently needs to be lifted, select the ejector pins in the corresponding area to lift up, so as to lift up the chip that currently needs to be lifted up.

[0098] In an embodiment of the present disclosure, the semiconductor device includes a control unit, which can be used to control the above-mentioned operation method. The control unit is configured to select the pins in the corresponding area to lift up the chip that currently needs to be lifted up according to the size of the chip that currently needs to be lifted up.

[0099] In some embodiments, the step of selecting to lift the pins in the corresponding area according to the size of the chip currently to be lifted includes:

[0100] According to the size of the chip currently to be lifted, lift the ejector pins in the first area among the plurality of ejector pins to a first height;

[0101] The ejector pins in the first sub-region are lifted to a second height; the second height is greater than the first height; the first sub-region is located in the middle region of the first region;

[0102] A first portion of the ejector pins in the first sub-region are lifted to a third height; the third height is greater than the second height; and the first portion of the ejector pins are located in a middle region of the first sub-region.

[0103] like Fig.13 As shown, the ejector component moves to the bottom of the chip 110 that needs to be lifted, as shown in the zero point position, and the bottom of the chip 110 has a UV film 111 as a support; Fig.14 As shown in FIG. 1 , according to the size of the chip 110 currently to be lifted, the ejector pins 103 of the ejector pin component are lifted up in the first section, that is, the ejector pins 103 in the first area among the plurality of ejector pins 103 are lifted up to the first height. The first area here may be a part of the distribution area of ​​the plurality of ejector pins 103, or may be the entire area, and may be determined according to the size of the chip to be lifted up; as shown in FIG. Fig.15 As shown, after the first section lifts up the chip, the second section of the ejector pins 103 continues to lift up, and the ejector pins 103 continue to move upward to form a stepped structure. This structure is beneficial for better separation of the edge UV film 111 from the chip 110 on the one hand, and is beneficial for releasing the adhesive stress of the UV film on the other hand, protecting the contact part between the UV film and the ejector pins from cracking. At the same time, the number of ejector pins 103 extending is determined according to the size of the chip 110. At this time, two-thirds of the effective area of ​​the chip 110 will be lifted to achieve the lifting effect, that is, the ejector pins 103 in the first sub-area will be lifted to the second height; as shown in FIG. Fig.16 As shown, when the chip 110 reaches the third section result, according to the size of the chip 110, the ejector pins 103 lift up the last one-third of the effective area, and then the nozzle component 104 takes the chip away, and the lifting process ends, that is, the first part of the ejector pins 103 in the first sub-area are lifted to the third height.

[0104] In some specific examples, the control unit is configured to: according to the size of the chip that currently needs to be lifted, lift the pins in the first area among the multiple pins to a first height; lift the pins in the first sub-area to a second height; the second height is greater than the first height; the first sub-area is located in the middle area of ​​the first area; lift a first part of the pins in the first sub-area to a third height; the third height is greater than the second height; the first part of the pins are located in the middle area of ​​the first sub-area.

[0105] In some embodiments, the semiconductor device further comprises: a nozzle component; the nozzle component comprises a second base and a plurality of first annular structures with a common geometric center located at the bottom of the second base; a plurality of first holes with a vacuum adsorption function are arranged in the first annular structure, and each of the first annular structures can be individually controlled to rise and fall; the operation method further comprises:

[0106] According to the size of the chip currently required to be adsorbed, a corresponding first annular structure among the plurality of first annular structures is selected to be raised so that the chip currently required to be adsorbed can be adsorbed.

[0107] In some specific examples, the control unit is configured to: select a corresponding first ring structure from the plurality of first ring structures to lift out according to the size of the chip currently required to be adsorbed, so that the chip currently required to be adsorbed is adsorbed.

[0108] In some embodiments, the semiconductor device further comprises: a bonding head component; the bonding head component comprises a third base and a plurality of second annular structures with a common geometric center located at the bottom of the third base; a plurality of second holes with a vacuum adsorption function are arranged in the second annular structure, and each second annular structure can be individually controlled to rise and fall; the operation method further comprises:

[0109] According to the size of the chip currently to be bonded, a corresponding second ring structure among the plurality of second ring structures is selected to be lifted up, so that the chip currently to be bonded can be adsorbed.

[0110] In some specific examples, the control unit is configured to: select to raise a corresponding second ring structure among the plurality of second ring structures according to the size of the chip currently to be bonded, so that the chip currently to be bonded is adsorbed.

[0111] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0112] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0113] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: The ejector pin component comprises a first base and a plurality of ejector pins located on the top of the first base; the distribution range of the plurality of ejector pins covers a plurality of chips of different sizes that need to be ejected, and the ejection height of each of the plurality of ejector pins can be individually controlled to eject chips of different sizes.

2. The semiconductor device according to claim 1, wherein: The ejector component further includes a plurality of first adjustment structures; the first adjustment structures are located in the first base, each of the first adjustment structures is connected to one of the ejectors, and the first adjustment structures are used to adjust the ejection height of the ejectors.

3. The semiconductor device according to claim 2, wherein: The first adjustment structure includes a first cylinder unit and a first motor unit.

4. The semiconductor device according to claim 1, wherein: The plurality of ejector pins are arranged in an array along a first direction and a second direction, wherein the first direction intersects with the second direction and is perpendicular to a thickness direction of the first base.

5. The semiconductor device according to claim 1, wherein: The distance between adjacent ejector pins in the middle area of ​​the top of the first base is a first distance, and the distance between adjacent ejector pins in the edge area of ​​the top of the first base is a second distance, and the first distance is smaller than the second distance.

6. The semiconductor device according to claim 1, wherein: The distance between adjacent ejector pins ranges from 1 mm to 3 mm.

7. The semiconductor device according to claim 1, wherein: The semiconductor device also includes: a suction nozzle component; the suction nozzle component includes a second base and a plurality of first annular structures with a common geometric center located at the bottom of the second base; a plurality of first holes with vacuum adsorption function are arranged in the first annular structure, and each of the first annular structures can be individually controlled to rise and fall.

8. The semiconductor device according to claim 7, wherein: The suction nozzle component also includes a plurality of second motor units; the second motor units are located in the second base, and each of the first annular structures is connected to one of the second motor units.

9. The semiconductor device according to claim 8, characterized in that The suction nozzle component further includes a first vacuum suction structure; the first vacuum suction structure is located in the second base, and the first hole is connected to the first vacuum suction structure.

10. The semiconductor device according to claim 1, wherein: The semiconductor device also includes: a bonding head component; the bonding head component includes a third base and a plurality of second annular structures with a common geometric center located at the bottom of the third base; a plurality of second holes with vacuum adsorption function are arranged in the second annular structure, and each of the second annular structures can be individually controlled to rise and fall.

11. The semiconductor device according to claim 10, wherein: The bonding head component further includes a third motor unit; the third motor unit is located in the third base, and each of the second annular structures is connected to one of the third motor units.

12. The semiconductor device according to claim 11, characterized in that The bonding head component further includes a second vacuum adsorption structure; the second vacuum adsorption structure is located in the third base, and the second hole is connected to the second vacuum adsorption structure.

13. The semiconductor device according to any one of claims 1 to 9, characterized in that: The semiconductor equipment includes a sorter.

14. The semiconductor device according to any one of claims 1 to 12, characterized in that: The semiconductor device includes a bonding device.

15. A method for operating a semiconductor device, characterized in that: The semiconductor device comprises a pin component; the pin component comprises a first base and a plurality of pins located on the top of the first base; the distribution range of the plurality of pins covers a plurality of chips of different sizes that need to be lifted, and each of the plurality of pins can be individually controlled to have a lifting height to lift chips of different sizes; the operation method comprises: According to the size of the chip that currently needs to be lifted, select the ejector pins in the corresponding area to lift up, so as to lift up the chip that currently needs to be lifted up.

16. The operating method according to claim 15, characterized in that: The step of selecting to lift the pins in the corresponding area according to the size of the chip currently to be lifted includes: According to the size of the chip currently to be lifted, lift the ejector pins in the first area among the plurality of ejector pins to a first height; The ejector pins in the first sub-region are lifted to a second height; the second height is greater than the first height; the first sub-region is located in the middle region of the first region; A first portion of the ejector pins in the first sub-region are lifted to a third height; the third height is greater than the second height; and the first portion of the ejector pins are located in a middle region of the first sub-region.

17. The operating method according to claim 15, characterized in that: The semiconductor device further includes: a nozzle component; the nozzle component includes a second base and a plurality of first annular structures with a common geometric center located at the bottom of the second base; a plurality of first holes with a vacuum adsorption function are arranged in the first annular structure, and each of the first annular structures can be individually controlled to rise and fall; the operation method further includes: According to the size of the chip currently required to be adsorbed, a corresponding first annular structure among the plurality of first annular structures is selected to be raised so that the chip currently required to be adsorbed can be adsorbed.

18. The operating method according to claim 15, characterized in that: The semiconductor device further comprises: a bonding head component; the bonding head component comprises a third base and a plurality of second annular structures with a common geometric center located at the bottom of the third base; a plurality of second holes with a vacuum adsorption function are arranged in the second annular structure, and each of the second annular structures can be individually controlled to rise and fall; the operation method further comprises: According to the size of the chip currently to be bonded, a corresponding second ring structure among the plurality of second ring structures is selected to be lifted up, so that the chip currently to be bonded can be adsorbed.

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