Semiconductor device and method of manufacturing the same

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A semiconductor device includes: a first chip having a first chip body and a first bonding layer disposed on the first chip body and including a first bonding pad; and a second chip bonded on the first bonding layer and having a second chip body and a second bonding layer disposed below the second chip body and including a second bonding pad bonded to the first bonding pad, a side surface of the first bonding layer and a side surface of the second chip are retracted into a side surface of the first chip body.

Description

Technical Field

[0001] Various embodiments generally relate to a semiconductor device and a method of manufacturing the same. Background Art

[0002] A technology for forming a semiconductor device by bonding wafers using a hybrid bonding process and then dicing the bonded wafers has been proposed. The reliability of the semiconductor device to which the hybrid bonding process is applied may be degraded due to delamination of the bonding surface. Summary of the invention

[0003] Various embodiments of the disclosed technology relate to a semiconductor device having improved reliability and a method of manufacturing the same.

[0004] In an embodiment, a semiconductor device may include: a first chip including a first chip body and a first bonding layer arranged on the first chip body, the first bonding layer including a first bonding pad; and a second chip bonded on the first bonding layer, the second chip including a second chip body and a second bonding layer arranged under the second chip body, wherein the second bonding layer includes a second bonding pad bonded to the first bonding pad, wherein a side surface of the first bonding layer and a side surface of the second chip are retracted into the side surface of the first chip body.

[0005] In an embodiment, a semiconductor device may include: a first chip, which includes a first chip body and a first bonding layer, the first chip body includes a device area defining a peripheral circuit and a scribe area surrounding the device area, the first bonding layer is arranged on the first chip body and includes a first bonding pad; and a second chip, which is bonded on the first bonding layer and includes a second bonding layer and a second chip body, the second bonding layer includes a second bonding pad bonded to the first bonding pad, the second chip body is arranged on the second bonding layer and includes a memory cell array, wherein the first bonding layer and the second chip overlap with the device area of ​​the first chip body and do not overlap with the scribe area of ​​the first chip body.

[0006] In an embodiment, a method for manufacturing a semiconductor device may include the following steps: providing a first wafer and a second wafer including a device area and a scribe area surrounding the device area; forming a bonding layer and a chip body arranged on the bonding layer in each of the first wafer and the second wafer, the bonding layer including a bonding pad arranged in the device area and a dummy bonding pad arranged in the scribe area; bonding the first bonding layer of the first wafer and the second bonding layer of the second wafer; forming a groove by removing the first bonding layer in the scribe area and the second chip of the second wafer; forming an insulating member filling the groove; and cutting the scribe area.

[0007] According to embodiments of the disclosed technology, delamination of a bonded semiconductor chip may be suppressed or / and prevented, thereby improving the reliability of a semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the disclosed technology.

[0009] Figure 2 yes Figure 1 Detailed view of section A.

[0010] Figures 3 to 12 The diagrams are for explaining a method for manufacturing a semiconductor device according to an embodiment of the disclosed technology.

[0011] Fig.13 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the disclosed technology.

[0012] Fig.14 yes Fig.13 Detailed view of section B.

[0013] Fig.15 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the disclosed technology. DETAILED DESCRIPTION

[0014] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, although shown in different drawings, the same elements will be referred to by the same reference numerals. In addition, in the following description of the present disclosure, when the subject matter of the present disclosure may be unclear, the detailed description of the known functions and configurations contained herein will be omitted. It should be noted that, unless otherwise specifically stated, the terms "including", "having", "comprising", etc. used in the specification and claims should not be interpreted as being limited to the means listed thereafter. In the case of using an indefinite article or a definite article (e.g., "one", "a kind of" and "the") when referring to a singular noun, this may include the plural number of the noun unless otherwise specifically stated.

[0015] In addition, when describing the components of the present disclosure, terms such as first, second, A, B, (a), and (b) may be used. These are only for distinguishing one component from another component, and do not limit the substance, sequence, order, or quantity of the components.

[0016] In the description of the positional relationship of components, in the case of describing that at least two components are “connected,” “coupled,” or “linked,” it will be understood that the at least two components may be directly “connected,” “coupled,” or “linked,” but may be indirectly “connected,” “coupled,” or “linked” with another component interposed between the two components. Here, the other component may be included in at least one of the at least two components that are “connected,” “coupled,” or “linked” to each other.

[0017] In the description of the time flow relationship for components, operating methods or manufacturing methods, when the "before" and "after" relationships in time or the "before" and "after" relationships in process are described, for example, by "after", "subsequently", "next" or "before", non-continuous situations may be included unless "immediately" or "directly" is used.

[0018] In the case of referring to a numerical value of a component or its corresponding information (e.g., height, etc.), even without separate explicit description, the numerical value or its corresponding information may be interpreted as including an error range that may be caused by various factors (e.g., process variables, internal or external impacts, noise, etc.).

[0019] Hereinafter, various embodiments of the disclosed technology will be described in detail with reference to the accompanying drawings.

[0020] Figure 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the disclosed technology.

[0021] Reference Figure 1 , a semiconductor device according to an embodiment of the disclosed technology may include a device region DR and a scribe lane region SLR around the device region DR. The scribe lane region SLR may surround the device region DR.

[0022] A semiconductor device according to an embodiment of the disclosed technology may include a first chip 10 , a second chip 20 , and an insulating member 30 .

[0023] The first chip 10 and the second chip 20 may be fabricated on different wafers and then may be bonded to each other by a bonding process (e.g., a hybrid bonding process). Hybrid bonding, also known in the art as direct bonding (or direct bonding interconnect "DBI") or fusion bonding, generally involves creating a metal-to-metal connection between semiconductor chips bonded together without the need for an additional intermediate layer (e.g., solder or adhesive).

[0024] The first chip 10 may include a first chip body 11 and a first bonding layer 12 disposed on the first chip body 11 .

[0025] As will be referred to later Figure 2As described, the first chip body 11 may include a substrate, a peripheral circuit, and an interconnection structure electrically connected to the peripheral circuit.

[0026] The first bonding layer 12 may include a plurality of first bonding pads P1 and a first bonding insulating layer D1 electrically isolating the first bonding pads P1. The first bonding pads P1 may be connected to an interconnect structure, and may be connected to a peripheral circuit through the interconnect structure.

[0027] For example, the first bonding pad P1 may include copper (Cu) having high conductivity and excellent electromigration characteristics, but is not limited thereto. The first bonding pad P1 may include a metal material, such as at least one of copper (Cu), tungsten (W), cobalt (Co), aluminum (Al), silicide, and any combination thereof. For example, the first bonding insulating layer D1 may include silicon oxide (SiO2). The first bonding layer 12 may have a top surface planarized by a chemical mechanical polishing (CMP) process.

[0028] The second chip 20 may include a second bonding layer 21 and a second chip body 22 disposed on the second bonding layer 21 .

[0029] The second bonding layer 21 may include a plurality of second bonding pads P2 and a second bonding insulating layer D2 electrically isolating the second bonding pads P2 .

[0030] The second bonding pad P2 may include a metal material, such as at least one of copper (Cu), tungsten (W), cobalt (Co), aluminum (Al), silicide, and any combination thereof. For example, the second bonding insulating layer D2 may include silicon oxide (SiO2). The second bonding layer 21 may have a bottom surface planarized by a chemical mechanical polishing (CMP) process.

[0031] As will be referred to later Figure 2 As described, the second chip body 22 may include a memory cell array and an interconnection structure. The memory cell array may be connected to the interconnection structure, and may be connected to the second bonding pad P2 through the interconnection structure.

[0032] The top surface of the first bonding layer 12 and the bottom surface of the second bonding layer 21 may be bonded by a hybrid bonding process. As the first bonding pad P1 and the second bonding pad P2 are bonded to each other, a metal-metal junction may be formed. As the first bonding insulating layer D1 and the second bonding insulating layer D2 are bonded to each other, a dielectric-dielectric junction may be formed.

[0033] As a result of the hybrid bonding process, a bonding interface BS may be formed between the first bonding layer 12 and the second bonding layer 21. The bonding interface BS may be where the first bonding layer 12 and the second bonding layer 21 are bonded to each other. In an embodiment, the bonding interface BS may be a layer of a certain thickness including a top surface of the first bonding layer 12 and a bottom surface of the second bonding layer 21.

[0034] Side surfaces SS2 and SS3 of the first bonding layer 12 and the second chip 20 may be retracted into side surfaces SS1a of the first chip body 11. Edge portions of the first chip body 11 may protrude beyond side surfaces SS2 and SS3 of the first bonding layer 12 and the second chip 20.

[0035] The first bonding layer 12 and the second chip 20 may be disposed on the device region DR of the first chip body 11. The first bonding layer 12 and the second chip 20 may overlap with the device region DR of the first chip body 11, and may not overlap with the scribe region SLR of the first chip body 11. The scribe region SLR of the first chip body 11 may protrude beyond the side surface SS2 of the first bonding layer 12 and the side surface SS3 of the second chip 20.

[0036] The side surface SS2 of the first bonding layer 12 and the side surface SS3 of the second chip 20 may be provided on a single surface. Fig.10 As described, the second wafer ( Fig.10 The scribe line region SLR of the first bonding layer 12 and the scribe line region SLR of the first bonding layer 12 created by the etching process may be disposed on the same surface.

[0037] The top surface of the scribe line region SLR of the first chip body 11 may be located at the same height as the top surface of the device region DR of the first chip body 11. However, the disclosed technology is not limited thereto. Fig.13 and Fig.14 As described, the top surface of the scribe line region SLR of the first chip body 11 may be disposed to be lower than the top surface of the device region DR of the first chip body 11 .

[0038] The insulating member 30 may be defined on the scribe line region SLR of the first chip body 11 and the second chip 20 to cover the side surface SS2 of the first bonding layer 12 and the side surface SS3 and top surface of the second chip 20. The insulating member 30 may have a top surface planarized by a CMP process.

[0039] The insulating member 30 may be formed of an insulating material having a rupture modulus smaller than that of the first and second bonding pads P1 and P2. The insulating member 30 may include at least one of oxide, nitride, SiCOH, N-doped SiC (NDC), and any combination thereof.

[0040] The side surface SS4 of the insulating member 30 and the side surface SS1a of the first chip body 11 may be disposed on the same surface. As will be described later, after the insulating member 30 is formed, the insulating member 30 and the first chip body 11 of the scribe line region SLR may be cut by a dicing process. The side surface SS4 of the insulating member 30 and the side surface SS1a of the first chip body 11 created by the dicing process may be disposed on the same surface.

[0041] Figure 2 yes Figure 1 Detailed view of section A.

[0042] Reference Figure 2 , the semiconductor device may be a memory device. The first chip 10 may include a peripheral circuit PERI controlling an operation of a memory cell array, and the second chip 20 may include a memory cell array.

[0043] Hereinafter, a case where the semiconductor device is a NAND flash memory will be described, but the disclosed technology is not limited thereto. The semiconductor device may include a nonvolatile memory such as a resistive RAM (RRAM), a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), and a ferroelectric RAM (FRAM), or a volatile memory such as a dynamic random access memory (DRAM) and a static RAM (SRAM).

[0044] The first chip body 11 may include a substrate 111 , a peripheral circuit PERI, a first insulating layer 112 , a first interconnection structure CB1 , and a first dummy interconnection structure DCB1 .

[0045] The substrate 111 may include silicon (eg, single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable material.

[0046] The peripheral circuit PERI may be disposed on the device region DR of the substrate 111. The peripheral circuit PERI may include a transistor TR. The transistor TR may include impurity regions Jn1 and Jn2, a gate insulating layer GI, and a gate electrode GE. The impurity regions Jn1 and Jn2 may be formed by doping impurities into the substrate 111. A channel region of the transistor TR may be formed between the impurity regions Jn1 and Jn2, and the gate insulating layer GI may be disposed on the channel region. The gate electrode GE may be disposed on the gate insulating layer GI. In addition to the transistor TR, the peripheral circuit PERI may also include any active or passive components, such as at least one of a diode, a resistor, and a capacitor.

[0047] The first insulating layer 112 may be disposed on the device region DR and the scribe region SLR of the substrate 111 and cover the peripheral circuit PERI. The first insulating layer 112 may include at least one of oxide, nitride, and any combination thereof.

[0048] The first interconnect structure CB1 may be disposed in the device region DR of the first insulating layer 112. The first interconnect structure CB1 may include a plurality of first interconnects ML1 and a plurality of first contacts CT1. The first contacts CT1 may connect the peripheral circuit PERI and the first interconnects ML1, and may connect the first interconnects ML1 disposed at different heights.

[0049] The first dummy interconnection structure DCB1 may be disposed in the scribe line region SLR of the first insulating layer 112. The first dummy interconnection structure DCB1 may include a plurality of first dummy interconnections DML1 and a plurality of first dummy contacts DCT1.

[0050] The first interconnect ML1 and the first dummy interconnect DML1 may be formed of a metal different from the first contact CT1 and the first dummy contact DCT1. The first interconnect ML1 and the first dummy interconnect DML1 may be formed of a metal having a slower oxidation rate than the first contact CT1 and the first dummy contact DCT1. For example, the first interconnect ML1 and the first dummy interconnect DML1 may be formed of copper (Cu), and the first contact CT1 and the first dummy contact DCT1 may be formed of tungsten (W). In order to reduce interconnection resistance, copper (Cu) having a low resistivity may be used as a material of the first interconnect ML1 and the first dummy interconnect DML. The first contact CT1 and the first dummy contact DCT1 may be created by forming a contact hole, filling the contact hole with a metal material, and then removing the metal material formed outside the contact hole. In order to reduce filling defects in a process of filling the contact hole with a conductive material, tungsten (W) having a fast oxidation rate but excellent step coverage may be used as a material of the first contact CT1 and the first dummy contact DCT1.

[0051] The first bonding layer 12 may be disposed on the device region DR of the first chip body 11. Figure 1 As described, the first bonding layer 12 may include a first bonding pad P1 and a first bonding insulating layer D1. The first bonding pad P1 may be connected to the first interconnect structure CB1, and may be connected to the peripheral circuit PERI through the first interconnect structure CB1.

[0052] The second chip body 22 may include a second insulating layer 221 , a stack 222 , a plurality of cell plugs CP, a third insulating layer 223 , a source plate 224 , and a fourth insulating layer 225 .

[0053] The second insulating layer 221 may be disposed on the second bonding layer 21. The second insulating layer 221 may include at least one of oxide, nitride, and any combination thereof.

[0054] The second interconnect structure CB2 may be defined in the second insulating layer 221 to be connected to the second bonding pad P2. The second interconnect structure CB2 may include a second interconnect ML2 and a second contact CT2. The second interconnect ML2 may include a bit line.

[0055] The stack 222 may be disposed on the second insulating layer 221. The stack 222 may include a plurality of electrode layers 222A and a plurality of interlayer insulating layers 222B alternately stacked along the vertically extending cell plugs CP. The electrode layer 222A may include a conductive material (e.g., tungsten). The interlayer insulating layer 222B may include an insulating material (e.g., oxide).

[0056] The electrode layer 222A may include a plurality of word lines and a plurality of selection lines. Among the electrode layers 222A, at least one electrode layer 222A from the bottom electrode layer 222A may form a first selection line, and at least one electrode layer 222A from the top electrode layer 222A may form a second selection line. The first selection line may be a drain selection line, and the second selection line may be a source selection line. The electrode layer 222A between the first selection line and the second selection line may be configured as a word line. The memory cell may be formed in a portion of the word line surrounding the cell plug CP. The selection transistor may be formed in a portion of the selection line surrounding the cell plug CP.

[0057] For example, the cell plug CP may include a filling layer, a channel layer surrounding the filling layer, and a memory layer surrounding the channel layer. The filling layer, the channel layer, and the memory layer may vertically pass through the plurality of electrode layers 222A and the plurality of interlayer insulating layers 222B. The filling layer may include an insulating material. For example, the filling layer may include an oxide. The channel layer may include a semiconductor material. For example, the channel layer may include polysilicon. The memory layer may include a tunnel insulating layer surrounding the channel layer, a data storage layer surrounding the tunnel insulating layer, and a blocking layer surrounding the data storage layer. The tunnel insulating layer may include a material capable of charge tunneling. For example, the tunnel insulating layer may include an oxide. In an embodiment, the data storage layer may include a material capable of charge capture. For example, the data storage layer may include a nitride. In another embodiment, according to a data storage scheme, the data storage layer may include various materials. For example, the data storage layer may include silicon, a phase change material, or nanodots. The blocking layer may include a material capable of blocking the movement of charges. For example, the blocking layer may include an oxide.

[0058] The channel layer of the cell plug CP may be connected to the second interconnection ML2 serving as a bit line through the second contact CT2 and may be connected to the second bonding pad P2 through the second contact CT2 connected to the second interconnection ML2. Each electrode layer 222A may be connected to the second bonding pad P2 through the second interconnect structure.

[0059] The third insulating layer 223 may be disposed on the second insulating layer 221 to surround a side surface of the stack 222. The third insulating layer 223 may include at least one of oxide, nitride, and any combination thereof.

[0060] The source plate 224 may be disposed on the stack 222. The source plate 224 may include, for example, polysilicon, but is not limited thereto.

[0061] The fourth insulating layer 225 may be disposed on the third insulating layer 223, and may surround a side surface of the source plate 224. The fourth insulating layer 225 may include at least one of oxide, nitride, and any combination thereof.

[0062] The semiconductor device may include a guard ring GD. The guard ring GD may be disposed at or near an edge of the device region DR to surround a central portion of the device region DR.

[0063] The guard ring GD can be used to prevent cracks that are likely to occur during the dicing process from propagating into the device region DR or preventing moisture from migrating through the cracks. In addition, the guard ring GD can be used to block electromagnetic interference (EMI) and electrostatic discharge (ESD) generated outside the device region DR and discharge them outward again.

[0064] Although the disclosed technology shows a case where one guard ring GD is included, the disclosed technology is not limited thereto. Two, three or more guard rings may be defined at the edge of the device region DR to double, triple or more surround the device region DR.

[0065] The first bonding layer 12 and the second chip 20 may be disposed on the device region DR of the first chip body 11. The first bonding layer 12 and the second chip 20 may overlap with the device region DR of the first chip body 11, and may not overlap with the scribe line region SLR of the first chip body 11. The side surface of the first bonding layer 12 and the side surface of the second chip 20 may be retracted into the side surface of the first chip body 11.

[0066] The first dummy contact DCT1 may be disposed on the top surface of the scribe region SLR of the first chip body 11. The first dummy contact DCT1 disposed on the top surface of the scribe region SLR of the first chip body 11 may be located at the same height as an uppermost first contact CT1 located uppermost among the first contacts CT1 of the first interconnect structure CB1. The uppermost first contact CT1 may be directly connected to the first bonding pad P1. The top surface of the first chip body 11 may be disposed at the same height in the device region DR and the scribe region SLR.

[0067] The insulating member 30 may be defined on the scribe line region SLR of the first chip body 11 and the second chip 20 to cover the side surface of the first bonding layer 12 and the side surface and top surface of the second chip 20 .

[0068] The third contact CT3 may be formed in the device region DR of the insulating member 30. The third contact CT3 may be connected to the source plate 224 by passing through the insulating member 30.

[0069] The third dummy contact DCT3 may be formed in the scribe region SLR of the insulating member 30. The third dummy contact DCT3 may be disposed at the same height as the third contact CT3. The lower end of the third dummy contact DCT3 may be located inside the insulating member 30. The guard ring contact GCT3 may be formed in the device region DR of the insulating member 30. The guard ring contact GCT3 may be connected to the guard ring GD by passing through the insulating member 30.

[0070] The third interconnection ML3 connected to the third contact CT3 may be formed on the device region DR of the insulating member 30. The third dummy interconnection DML3 connected to the third dummy contact DCT3 may be formed on the scribe region SLR of the insulating member 30. The guard ring interconnection GML3 connected to the guard ring contact GCT3 may be formed on the device region DR of the insulating member 30.

[0071] Figures 3 to 12 It is a view for explaining a method of manufacturing a semiconductor device according to an embodiment of the disclosed technology.

[0072] Reference Figure 3 , a step of forming openings H1 , H2 , and H3 in the first bonding insulation layer D1 of the first wafer W1 is performed.

[0073] The first wafer W1 may include a device region DR and a scribe lane region SLR. Figure 3 Only one device region DR is shown, but a plurality of device regions may be two-dimensionally arranged in the first wafer W1 , and the scribe lane regions SLR may surround the respective device regions.

[0074] The first wafer W1 may include a substrate 111 , a peripheral circuit PERI defined on a device region DR of the substrate 111 , a first insulating layer 112 disposed on the substrate 111 and covering the peripheral circuit PERI, and a first interconnection structure CB1 and a first dummy interconnection structure DCB1 disposed in the first insulating layer 112 .

[0075] The first interconnect structure CB1 may include a first interconnect ML1 and a first contact CT1. The first dummy interconnect structure DCB1 may include a first dummy interconnect DML1 and a first dummy contact DCT1. Additionally or alternatively, a first guard ring portion GD1 may be formed in the first insulating layer 112 at an edge of the device region DR. The first guard ring portion GD1 may be formed together with the peripheral transistor TR and the first interconnect structure CB1 during a process of forming the peripheral transistor TR and the first interconnect structure CB1.

[0076] By forming a first bonding insulating layer D1 on the first insulating layer 112 and patterning the first bonding insulating layer D1 , openings H1 , H2 , and H3 may be formed.

[0077] The openings H1 , H2 , and H3 may include a first opening H1 exposing the first interconnect structure CB1 and a second opening H2 exposing the first dummy interconnect structure DCB1 . Additionally or alternatively, a third opening H3 exposing the first guard ring portion GD1 may be further included.

[0078] Reference Figure 4 , a step of forming a first bonding pad P1 , a first dummy bonding pad DP1 , and a first guard ring pad GP1 is performed.

[0079] A metal material may be formed on the first insulating layer 112 and the first bonding insulating layer D1 to fill the first to third openings H1 to H3 and the metal material formed outside the first to third openings H1 to H3 may be removed by a CMP process, a first bonding pad P1 may be formed in the first opening H1, a first dummy bonding pad DP1 may be formed in the second opening H2, and a first guard ring pad GP1 may be formed in the third opening H3. Therefore, a first bonding layer 12 including the first bonding pad P1, the first dummy bonding pad DP1, the first guard ring pad GP1, and the first bonding insulating layer D1 may be formed on the top surface of the first wafer W1.

[0080] For example, the metal material may include at least one of copper (Cu), tungsten (W), cobalt (Co), aluminum (Al), silicide, and any combination thereof. The metal material may be formed by a plating process, but is not limited thereto.

[0081] By forming the first dummy bonding pad DP1 in the scribe region SLR and forming the first bonding pad P1 in the device region DR, the difference in pattern density between the device region DR and the scribe region SLR can be reduced. Therefore, recess and erosion due to the difference in pattern density during the CMP process can be suppressed or / and prevented.

[0082] Although the disclosed technology shows that the first dummy bonding pad DP1 is formed only in the scribe lane region SLR, the first dummy bonding pad may also be formed in the device region DR.

[0083] Reference Figure 5 , a step of forming openings H4 , H5 , and H6 in the second bonding insulation layer D2 of the second wafer W2 is performed.

[0084] The second wafer W2 may include a device region DR and a scribe lane region SLR. Figure 5Only one device region is shown, but a plurality of device regions may be two-dimensionally arranged in the second wafer W2 , and the scribe lane regions SLR may surround the respective device regions.

[0085] The second wafer W2 may include a stack 222 disposed on the support structure 40 , a plurality of cell plugs CP, second and third insulating layers 221 and 223 , a second interconnection structure CB2 , and a second dummy interconnection structure DCB2 .

[0086] The stack 222 and the cell plugs CP may be disposed on the device region DR of the support structure 40. The third insulating layer 223 may be disposed on the device region DR and the scribe region SLR of the support structure 40 to cover the side surface of the stack 222. The second insulating layer 221 may be disposed on the stack 222 and the third insulating layer 223 to cover the top surface of the stack 222 and the top surface of the third insulating layer 223.

[0087] The second interconnection structure CB2 may be disposed in the device region DR of the second insulating layer 221 and may include a second interconnection ML2 and a second contact CT2. The second dummy interconnection structure DCB2 may be disposed in the scribe region SLR of the third insulating layer 223 and the second insulating layer 221 and may include a second dummy interconnection DML2 and a second dummy contact DCT2.

[0088] Additionally or alternatively, a second guard ring portion GD2 may be formed at an edge of the device region DR through the second insulating layer 221 and the third insulating layer 223. The second guard ring portion GD2 may be created together with the second dummy interconnect DML2 and the second dummy contact DCT2 in a process of forming the second dummy interconnect DML2 and the second dummy contact DCT2.

[0089] By forming a second bonding insulating layer D2 on the second insulating layer 221 and patterning the second bonding insulating layer D2 , the openings H4 , H5 , and H6 may be formed.

[0090] The openings H4 , H5 , and H6 may include a fourth opening H4 exposing the second interconnection structure CB2 , a fifth opening H5 exposing the second dummy interconnection structure DCB2 , and a sixth opening H6 exposing the second guard ring portion GD2 .

[0091] Reference Figure 6 , a step of forming a second bonding pad P2 and a second dummy bonding pad DP2 is performed.

[0092] A metal material may be formed on the second insulating layer 221 and the second bonding insulating layer D2 to fill the fourth opening H4 to the sixth opening H6, and the metal material formed outside the fourth opening H4 to the sixth opening H6 may be removed by a CMP process. Therefore, a second bonding pad P2 may be formed in the fourth opening H4, a second dummy bonding pad DP2 may be formed in the fifth opening H5, and a second guard ring pad GP2 may be formed in the sixth opening H6. Thus, a second bonding layer 21 including a second bonding pad P2, a second dummy bonding pad DP2, a second guard ring pad GP2, and a second bonding insulating layer D2 may be formed on the top surface of the second wafer W2.

[0093] For example, the metal material may include at least one of copper (Cu), tungsten (W), cobalt (Co), aluminum (Al), silicide, and any combination thereof. The metal material may be formed by a plating process, but is not limited thereto.

[0094] By forming the second dummy bonding pad DP2 in the scribe region SLR and forming the second bonding pad P2 in the device region DR, the difference in pattern density between the device region DR and the scribe region SLR can be reduced. Therefore, it is possible to suppress or / and prevent the occurrence of recess and erosion due to the difference in pattern density during the CMP process.

[0095] Although the disclosed technology shows that the second dummy bonding pad DP2 is formed only in the scribe lane region SLR, the second dummy bonding pad may also be formed in the device region DR.

[0096] Reference Figure 7 , a wafer bonding step of bonding the first wafer W1 and the second wafer W2 is performed.

[0097] The wafer bonding step may include turning the second wafer W2 upside down and bonding the first bonding layer 12 of the first wafer W1 and the second bonding layer 21 of the second wafer W2 through a hybrid bonding process.

[0098] When performing the hybrid bonding process, the first bonding insulating layer D1 and the second bonding insulating layer D2 may be bonded first. As the metal materials in the first bonding pad P1 and the second bonding pad P2 expand by the heat subsequently applied, the first bonding pad P1 and the second bonding pad P2 may be bonded. As the first bonding pad P1 and the second bonding pad P2 are bonded, the peripheral circuit PERI and the memory cell array may be electrically connected.

[0099] Reference Figure 8 , performing a step of removing the support structure 40 .

[0100] The support structure 40 may be removed using an etching material capable of selectively etching the support structure 40. As the support structure 40 is removed, the cell plugs CP and the second dummy interconnection structures DCB2 may be exposed on the top surface of the second wafer W2.

[0101] Reference Fig. 9 , performing the step of forming the source plate 224 and the fourth insulating layer 225 .

[0102] After forming the source plate 224 connected to the cell plugs CP on the stack 222 and forming the fourth insulating layer 225 on the third insulating layer 223 and the source plate 224 , the fourth insulating layer 225 may be planarized to expose the second dummy interconnection structure DCB2 and the source plate 224 .

[0103] Reference Fig.10 , a step of removing the first bonding layer 12 and the second wafer W2 from the scribe line region SLR is performed.

[0104] The scribe lane region SLR on the second wafer W2 may be exposed by forming a mask pattern on the source plate 224. The second wafer W2 and the first bonding layer 12 may be etched using the mask pattern as an etching mask, and a trench TH may be formed. The trench TH may be formed to expose the uppermost first dummy contact DCT1 of the first dummy interconnect structure DCB1.

[0105] During the etching process, the first bonding layer 12 and the second bonding layer 21 of the scribe line region SLR may be removed.

[0106] Reference Fig.11 , a step of forming the insulating member 30 is performed.

[0107] The trench TH may be filled by forming an insulating member 30 on the first wafer W1 and the second wafer W2. The insulating member 30 may include an insulating material having a rupture modulus smaller than that of the first bonding pad P1 and the second bonding pad P2. For example, the insulating member 30 may include at least one of oxide, nitride, SiCOH, N-doped SiC (NDC), and any combination thereof.

[0108] Then, the top surface of the insulation member 30 may be planarized through a CMP process.

[0109] Reference Fig.12 , a step of forming a third contact CT3 and a third interconnection ML3 is performed.

[0110] The third contact CT3 may be formed by forming a contact hole exposing the source plate 224 in the device region DR of the insulating member 30 through a photolithography process and filling the contact hole with a conductive material. In the process of forming the third contact CT3, a third dummy contact DCT3 may be formed in the scribe region SLR. Additionally or alternatively, in the process of forming the third contact CT3 and the third dummy contact DCT3, a guard ring contact GCT3 connected to the second guard ring portion GD2 may be formed.

[0111] A third interconnect ML3 connected to the third contact CT3 may be formed on the device region DR of the insulating member 30. In the process of forming the third interconnect ML3, a third dummy interconnect DML3 may be formed in the scribe region SLR. Additionally or alternatively, in the process of forming the third interconnect ML3 and the third dummy interconnect DML3, a guard ring interconnect GML3 connected to the guard ring contact GCT3 may be formed.

[0112] In addition, a step of cutting the scribe lane region SLR through a dicing process may be performed During the dicing process, the insulating member 30 , the first insulating layer 112 , and the substrate 111 of the scribe lane region SLR may be cut.

[0113] The first and second dummy bonding pads DP1 and DP2 of the scribe line region SLR serve to prevent recessing and erosion during a process of forming the first and second bonding pads P1 and P2 , but may become a delamination source.

[0114] In detail, the metal material including the first dummy bonding pad DP1 and the second dummy bonding pad DP2 has a large modulus of rupture. This characteristic may lead to poor cuttability and abnormal profiles. For example, a step-shaped surface may be created on the surface after the dicing process. As stress is concentrated on the abnormal profile created on the cut surface, the first chip and the second chip ( Figure 2 10 and 20) may be delaminated in a subsequent process such as a molding process. As metal ions included in the first bonding pad P1 and the second bonding pad P2 migrate along the delaminated surface, bonding pads that should not be connected to each other may be short-circuited, thereby deteriorating the reliability of the semiconductor device.

[0115] According to an embodiment of the disclosed technology, since the cuttability of the scribe lane region SLR can be increased by removing the first dummy bonding pad DP1 and the second dummy bonding pad DP2 of the scribe lane region SLR after wafer bonding, the creation of an abnormal profile on the cut surface during the dicing process can be suppressed or / and prevented. Therefore, by preventing delamination of the bonded chips and preventing the migration phenomenon accompanying the delamination, the reliability of the semiconductor device can be improved.

[0116] Fig.13is a schematic cross-sectional view of a semiconductor device according to an embodiment of the disclosed technology.

[0117] Reference Fig.13 , a top surface of the scribe line region SLR of the first chip body 11 may be disposed to be lower than a top surface of the device region DR of the first chip body 11 .

[0118] During the etching process for removing the second chip 20 and the first bonding layer 12 of the scribe region SLR, the first chip body 11 of the scribe region SLR may be partially etched. As a result of the etching process, an inner side surface SS1b may be created on the first chip body 11. The inner side surface SS1b of the first chip body 11 may be disposed on the same surface as the side surface SS2 of the first bonding layer 12 and the side surface SS3 of the second chip 20.

[0119] Fig.14 yes Fig.13 Detailed view of section B.

[0120] Reference Fig.14 , a top surface of the scribe lane region SLR of the first chip body 11 may be disposed lower than a top surface of the device region DR of the first chip body 11. The first dummy interconnection DML1 may be located on the top surface of the scribe lane region SLR of the first chip body 11.

[0121] As described above, the first interconnect ML1 and the first dummy interconnect DML1 may be formed of copper, and the first contact CT1 and the first dummy contact DCT1 may be formed of tungsten. Since tungsten has a faster oxidation rate than copper and is easily oxidized, the uppermost first dummy contact DCT1 may be formed of copper. Fig.10 Described for forming the groove ( Fig.10 Therefore, by removing the uppermost first dummy contact DCT1, the first dummy interconnect DML1 below the uppermost first dummy contact DCT1 can be exposed. To this end, by controlling the groove ( Fig.10 By performing an etching process of the first dummy interconnection DML1 such that the etching stops at the first dummy interconnection DML1, the scribe lane region SLR of the first chip body 11 may be partially etched. In this case, the top surface of the scribe lane region SLR of the first chip body 11 may be set at the same height as the top surface of the first dummy interconnection DML1.

[0122] Fig.15 is a cross-sectional view showing a portion of a semiconductor device according to an embodiment of the disclosed technology.

[0123] Reference Fig.15The moisture permeation prevention member 50 may be disposed between the first bonding layer 12 and the insulating member 30 and between the side surface of the second chip 20 and the insulating member 30. The moisture permeation prevention member 50 may include a nitride. Fig.10 After forming the insulating member 30, the insulating member 30 may be formed by the groove ( Fig.10 The moisture permeation preventing member 50 is formed on the side surfaces of the first bonding layer 12 and the second chip 20 exposed in the TH.

[0124] The moisture-proof member 50 may surround the side surfaces of the first bonding layer 12 and the second chip 20. Although not shown in detail in the figure, the edge of the bonding interface BS between the first chip 10 and the second chip 20 may be surrounded by the moisture-proof member 50 and blocked relative to the outside. Therefore, it is possible to suppress or / and prevent moisture from penetrating into the bonding interface BS. When moisture penetrates into the bonding interface BS and heat is applied to the bonding interface BS, the first bonding pad P1 and the second bonding pad P2 are likely to oxidize. Since the bonding interface BS is blocked relative to the outside by the moisture-proof member 50 to suppress or / and prevent moisture from penetrating into the bonding interface BS, a semiconductor device with high reliability can be provided.

[0125] Although the embodiments of the present disclosure are described for illustrative purposes, it will be appreciated by those skilled in the art that various modifications, additions and substitutions are possible without departing from the scope of the present disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered only in a descriptive sense, rather than for limiting the technical scope. The technical scope of the present disclosure is not limited by these embodiments and drawings.

[0126] CROSS-REFERENCE TO RELATED APPLICATIONS

[0127] This application claims the priority of Korean Patent Application No. 10-2023-0132318 filed on October 5, 2023 in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: A first chip, the first chip comprising a first chip body and a first bonding layer disposed on the first chip body, the first bonding layer comprising a first bonding pad; as well as a second chip, the second chip being bonded to the first bonding layer, the second chip comprising a second chip body and a second bonding layer disposed below the second chip body, wherein the second bonding layer includes a second bonding pad bonded to the first bonding pad, The side surface of the first bonding layer and the side surface of the second chip are retracted into the side surface of the first chip body.

2. The semiconductor device according to claim 1, further comprising: An insulating member is provided on edge portions of a side surface of the first chip body protruding beyond the first bonding layer and a side surface of the second chip.

3. The semiconductor device according to claim 2, wherein: The insulating member includes an insulating material having a rupture modulus smaller than those of the first and second bonding pads.

4. The semiconductor device according to claim 2, wherein: The insulating member includes at least one of oxide, nitride, SiCOH, N-doped SiC NDC, and any combination thereof.

5. The semiconductor device according to claim 2, further comprising: A moisture permeation preventing member is provided between a side surface of the first bonding layer and the insulating member and between a side surface of the second chip and the insulating member.

6. The semiconductor device according to claim 5, wherein: The moisture permeation preventing member includes a nitride.

7. The semiconductor device according to claim 1, wherein A top surface of an edge portion of the first chip body protruding beyond side surfaces of the first bonding layer and the second chip is set lower than a top surface of a central portion of the first chip body overlapping the first bonding layer and the second chip.

8. A semiconductor device, comprising: A first chip, the first chip comprising a first chip body and a first bonding layer, the first chip body comprising a device area defining a peripheral circuit and a scribe area surrounding the device area, the first bonding layer being disposed on the first chip body and comprising a first bonding pad; as well as a second chip bonded to the first bonding layer and comprising a second bonding layer and a second chip body, the second bonding layer comprising a second bonding pad bonded to the first bonding pad, the second chip body being disposed on the second bonding layer and comprising a memory cell array, The first bonding layer and the second chip overlap with the device region of the first chip body, and do not overlap with the scribe line region of the first chip body.

9. The semiconductor device according to claim 8, further comprising: An insulating member is disposed on the scribe area of ​​the first chip body and the second chip and covers a side surface of the first bonding layer and a top surface and a side surface of the second chip.

10. The semiconductor device according to claim 8, wherein The first chip body comprises: substrate; The peripheral circuit is arranged on the substrate; a first insulating layer, which is disposed on the substrate and covers the peripheral circuit; a contact disposed in the device region of the first insulating layer and directly connected to the first bonding pad; and a dummy contact, which is arranged in the scribe area of ​​the first insulating layer and is located at the same height as the contact, Wherein, the top surface of the scribe area of ​​the first chip body is set at the same height as the top surface of the dummy contact.

11. The semiconductor device according to claim 8, wherein The first chip body comprises: substrate; The peripheral circuit is arranged on the substrate; a first insulating layer, the first insulating layer covering the peripheral circuit; an interconnection disposed in the device region of the first insulating layer; and a dummy interconnection, which is arranged in the scribe area of ​​the first insulating layer and is located at the same height as the interconnection, Wherein, a top surface of the scribe area of ​​the first chip body is set at the same height as a top surface of the dummy interconnection.

12. The semiconductor device according to claim 8, wherein The second chip body comprises: a first insulating layer, the first insulating layer being disposed on the second bonding layer; a stack disposed on the first insulating layer and including a plurality of interlayer insulating layers and a plurality of electrode layers alternately stacked along a cell plug extending in a vertical direction; a second insulating layer disposed on the first insulating layer and surrounding a side surface of the stack; a source plate disposed on the stack; and A third insulating layer is disposed on the second insulating layer and surrounds a side surface of the source plate.

13. The semiconductor device according to claim 12, further comprising: a contact connected to the source plate by passing through an insulating member in the device region; a top interconnect disposed on the insulating member and connected to the contact; a dummy contact passing through the top surface of the insulating member in the scribe area and disposed at the same height as the contact; as well as A dummy top interconnect is disposed on the insulating member and connected to the dummy contact.

14. A method for manufacturing a semiconductor device, the method comprising the steps of: Providing a first wafer and a second wafer including a device region and a scribe lane region surrounding the device region; forming a bonding layer and a chip body disposed on the bonding layer in each of the first wafer and the second wafer, the bonding layer comprising bonding pads disposed in the device region and dummy bonding pads disposed in the scribe lane region; bonding the first bonding layer of the first wafer and the second bonding layer of the second wafer; forming a groove by removing the first bonding layer and the second chip of the second wafer in the scribe area; forming an insulating member filling the trench; as well as The scribe area is cut.

15. The method according to claim 14, wherein: The step of forming the bonding layer comprises the following steps: forming a bonding insulating layer having a first opening exposing the device region and a second opening exposing the scribe lane region on one surface of each of the first wafer and the second wafer; forming a metal material filling the first opening and the second opening; and The bonding pad is formed in the first opening and the dummy bonding pad is formed in the second opening by removing the metal material formed outside the first opening and the second opening.

16. The method according to claim 14, wherein: The insulating member includes an insulating material having a rupture modulus smaller than those of the bonding pad and the dummy bonding pad.

17. The method according to claim 14, wherein: The first wafer includes contacts disposed in the device region and directly connected to the bonding pads of the first wafer and dummy contacts disposed in the scribe lane region and located at the same height as the contacts, and The trench is formed to expose the dummy contact.

18. The method according to claim 14, wherein: The first wafer further includes an interconnection disposed in the device region and a dummy interconnection disposed in the scribe lane region and located at the same height as the interconnection, and The trench is formed to expose the dummy interconnection.

19. The method according to claim 14, further comprising the steps of: Before forming the insulating member, a moisture permeation preventing member is formed on a side wall of the groove.

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