AI computing power chip vertical power supply structure

Abstract

The application discloses an AI computing power chip vertical power supply structure, which comprises an AI computing power chip, a through silicon via adapter plate, an organic adapter plate and a low-inductance gallium nitride module; the AI computing power chip, the through silicon via adapter plate, the organic adapter plate and the low-inductance gallium nitride module are sequentially arranged from top to bottom; a plurality of output capacitors are arranged between the organic adapter plate and the through silicon via adapter plate; first soldering balls are arranged between adjacent output capacitors; a first chip inductor and a second chip inductor are further arranged below the organic adapter plate; and second soldering balls are arranged between the first chip inductor and the organic adapter plate, between the second chip inductor and the organic adapter plate and between the low-inductance gallium nitride module and the organic adapter plate; and the structure can avoid the problems of line loss and large voltage dynamic oscillation amplitude caused by a long power supply loop.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor integrated chip power supply, and relates to an AI computing power chip vertical power supply structure. BACKGROUND

[0002] With the continuous development of modern information technology, artificial intelligence, data centers, automatic driving and other applications usually need to process massive data, which puts forward new requirements for the computing power of CPU, GPU and other computing devices; with the improvement of the scale and types of computing device chips, the power supply system of CPU, GPU and other integrated chips faces major challenges; taking an AI computing power chip GB200 as an example, the power consumption of a single chip reaches 1000W, the power supply voltage is as low as 0.6V, and the power supply current exceeds 1000A, which greatly increases the conduction loss of the power distribution network and reduces the power supply voltage variation tolerance; for future integrated chips with hundreds of chip scales, the power supply demand will reach several kilowatts or even ten kilowatts, therefore, combined with the characteristics of integrated chips, developing a new type of vertical low-power power supply current is a key problem to solve the challenges faced by large-scale chip integration.

[0003] The existing power supply circuit adopts a discrete power supply architecture; for the discrete case, limited by the lower switching frequency of silicon power devices, the volume of passive devices such as inductors and capacitors is large, and they cannot be directly integrated to the back of the CPU, GPU and other computing power chips, resulting in a long power supply loop, which causes large line loss and voltage dynamic oscillation amplitude, thereby affecting the reliable application of AI high computing power chips. SUMMARY

[0004] The purpose of the present application is to overcome the shortcomings of the prior art, and to provide an AI computing power chip vertical power supply structure which can avoid the problem of large line loss and voltage dynamic oscillation amplitude caused by a long power supply loop.

[0005] To achieve the above purpose, the present application discloses an AI computing power chip vertical power supply structure, which comprises an AI computing power chip, a through silicon via adapter board, an organic adapter board and a low-inductance gallium nitride module.

[0006] The AI computing power chip, the through silicon via adapter board, the organic adapter board and the low-inductance gallium nitride module are arranged in sequence from top to bottom, a plurality of output capacitors are arranged between the organic adapter board and the through silicon via adapter board, a first group of solder balls is arranged between adjacent output capacitors, and a first chip inductor and a second chip inductor are further arranged below the organic adapter board, wherein a second group of solder balls is arranged between the first chip inductor and the organic adapter board, between the second chip inductor and the organic adapter board, and between the low-inductance gallium nitride module and the organic adapter board.

[0007] Further, the low-inductance gallium nitride module comprises a fourth conductive layer, a fifth conductive layer and a plurality of decoupling capacitors.

[0008] One side of each decoupling capacitor is connected with the fourth conductive layer, and the other side of each decoupling capacitor is connected with the fifth conductive layer.

[0009] Further, one side of the first conductive layer is a first comb-shaped structure, one side of the second conductive layer is a second comb-shaped structure, the other side of the second conductive layer is a third comb-shaped structure, one side of the third conductive layer is a fourth comb-shaped structure, and each comb in the first comb-shaped structure and each comb in the second comb-shaped structure are distributed in turn.

[0010] Further, it further comprises a plurality of first vias and a plurality of second vias, and one decoupling capacitor corresponds to one comb in the first comb-shaped structure, one comb in the fourth comb-shaped structure, one first via and one second via.

[0011] Further, the current direction of each comb in the first comb-shaped structure is opposite to the current direction of each comb in the second comb-shaped structure.

[0012] Further, the current direction of each comb in the third comb-shaped structure is opposite to the current direction of each comb in the fourth comb-shaped structure.

[0013] Further, the low-inductance gallium nitride module, the first chip inductor and the second chip inductor constitute a voltage regulation module.

[0014] Further, the thickness of the voltage regulation module is less than or equal to 5mm.

[0015] Further, the output voltage of the voltage regulation module passes through the organic adapter board, the output capacitor, the solder ball and the through-silicon via adapter board in turn, and finally reaches the AI computing chip.

[0016] Further, when applied to a high-power AI computing chip, a plurality of gallium nitride devices and a plurality of chip inductors are integrated on the bottom surface of the organic adapter board.

[0017] The present application has the following advantages:

[0018] The AI computing chip vertical power supply structure provided by the application has the advantages that, compared with the traditional power supply mode, the power supply distance is significantly shortened, the line loss can be reduced, the amplitude of voltage dynamic oscillation can be reduced, and the dynamic response characteristics of the power supply voltage can be improved; and the volume of the whole system is reduced, higher density integration is achieved, and the development of technologies in the fields of artificial intelligence, cloud computing, data center, automatic driving and the like is greatly promoted.

[0019] Further, the current on the low-inductance gallium nitride module flows out from one end of the decoupling capacitor, sequentially passes through the fourth conductive layer, the first via, the first conductive layer, the first gallium nitride device, the second conductive layer, the second gallium nitride device, the third conductive layer, the second via and the fifth conductive layer, and finally flows back to the other end of the decoupling capacitor. This interconnection form can significantly reduce the parasitic inductance of the gallium nitride module, can improve the switching frequency of the gallium nitride device, and thus reduce the volume of the passive device. The voltage regulation module composed of the low-inductance gallium nitride module and the small-volume passive device is directly integrated on the back of the AI computing chip, and the power supply voltage output by the voltage regulation module directly passes through the organic adapter plate, the output capacitor, the solder ball and the through silicon via adapter plate to supply power to the AI computing chip. The power supply loop is greatly shortened, the line loss is reduced, the voltage dynamic oscillation amplitude is reduced, and the AI computing chip can work reliably and stably. BRIEF DESCRIPTION OF DRAWINGS

[0020] The drawings accompanying the specification of the present application serve to provide a further understanding of the present application, and the illustrative embodiments of the present application and their descriptions serve to explain the present application, and do not constitute an improper limitation on the present application. In the drawings:

[0021] Figure 1 It is a schematic diagram of the main structure of the present application;

[0022] Figure 2 It is a schematic diagram of the low-inductance interconnection structure of the gallium nitride device in the present application.

[0023] In the drawings, 100 is a first gallium nitride device, 101 is a second gallium nitride device, 102 is a first conductive layer, 103 is a second conductive layer, 104 is a third conductive layer, 105 is a first via, 106 is a second via, 107 is a fourth conductive layer, 108 is a fifth conductive layer, 109 is a decoupling capacitor, 200 is a low-inductance gallium nitride module, 201 is a first chip inductor, 202 is a second chip inductor, 203 is an output capacitor, 204 is an AI computing chip, 205 is an organic adapter plate, 207 is a solder ball, and 208 is a through silicon via adapter plate. DETAILED DESCRIPTION

[0024] Clearly, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments of the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative effort are within the protection scope of the present application.

[0025] In the description of the present application, it should be understood that the terms "comprising" and "including" indicate the presence of the described features, integers, steps, operations, elements, and / or components, but do not exclude one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0026] It should also be understood that the terms used in the present application specification are only for the purpose of describing particular embodiments and are not intended to limit the present application. As used in the present application specification and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0027] It should be further understood that the term "and / or" used in the present application specification is intended to mean one or more of any combination of the associated listed items and all possible combinations thereof, and includes these combinations, for example, A and / or B can mean the existence of A alone, the existence of B alone, or the existence of both A and B. In addition, the character " / " in the present application generally represents an "or" relationship between the front and rear associated objects.

[0028] It should be understood that although the terms first, second, third, etc. can be used in the embodiments of the present application to describe preset ranges, etc., these preset ranges should not be limited to these terms. These terms are only used to distinguish the preset ranges from each other. For example, the first preset range can also be referred to as the second preset range, and similarly, the second preset range can also be referred to as the first preset range without departing from the scope of the embodiments of the present application.

[0029] Depending on the context, the word "if" as used herein can be interpreted as meaning "when" or "while" or "in response to determining" or "in response to detecting". Similarly, depending on the context, the phrase "if determined" or "if detecting (a stated condition or event)" can be interpreted as meaning "when determined" or "in response to determining" or "when detecting (a stated condition or event)" or "in response to detecting (a stated condition or event)".

[0030] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of protection of the present application.

[0031] Various structural schematic diagrams according to the disclosed embodiments of the present application are shown in the drawings. These diagrams are not drawn to scale, in which some details are exaggerated for the purpose of clear expression, and some details can be omitted. The shapes of various regions, layers and their relative size and positional relationship shown in the drawings are only exemplary, and in actuality, there can be deviations due to manufacturing tolerances or technical limitations, and regions / layers with different shapes, sizes and relative positions can be additionally designed by those skilled in the art according to actual needs.

[0032] The AI computing power chip vertical power supply structure described in the present application aims to reduce the size of the voltage regulation module and realize vertical power supply at the back. First, the parasitic inductance, parasitic capacitance and thermal resistance of different interconnection structures of gallium nitride devices are analyzed to obtain a quantitative description method. The influence of different interconnection structures on the dynamic characteristics and electro-thermal characteristics of gallium nitride devices is analyzed, and a new interconnection structure with low parasitic parameters and high thermal conductivity is researched, and combined with advanced packaging technology, high-frequency, high-efficiency and reliable application of gallium nitride devices is realized. The increase of the switching frequency of power devices can reduce the size of passive devices, so the second step is to research the structure of passive devices for high-density power supply, establish a mathematical model of electromagnetic analysis, and combine simulation to study the influence of device structure and magnetic core material on direct current resistance, magnetic core loss and other parameters, research the optimization direction of device structure, and realize the preparation of ultra-thin, high-current and low-loss passive devices combined with existing technology; finally, combined with advanced packaging technology, the CPU and GPU direct power supply circuit integration with low parasitic effect and fast dynamic response is realized.

[0033] By optimizing the layout and interconnection of gallium nitride devices, low inductance reliable interconnection of gallium nitride devices is realized, thereby promoting high-frequency application of gallium nitride devices; high-frequency of power devices can significantly reduce the size of passive devices, high-density integration of ultra-thin chip inductance array and low inductance gallium nitride module 200 is adopted to realize miniaturization and lightness of voltage regulation module, new ultra-thin voltage regulation module is integrated into the back of CPU, GPU and other AI computing chip 204 to realize ultra-short distance vertical power supply, reduce the amplitude of voltage dynamic oscillation and improve power supply efficiency and voltage dynamic response speed.

[0034] Embodiment one

[0035] Reference Figure 1 Based on the above analysis, the embodiment discloses an AI computing chip vertical power supply structure, which comprises an AI computing chip 204, a through silicon via adapter plate 208, an organic adapter plate 205 and a low inductance gallium nitride module 200; the AI computing chip 204, the through silicon via adapter plate 208, the organic adapter plate 205 and the low inductance gallium nitride module 200 are sequentially distributed from top to bottom, a plurality of output capacitors 203 are arranged between the organic adapter plate 205 and the through silicon via adapter plate 208, a first group of solder balls 207 is arranged between adjacent output capacitors 203, and a first chip inductor 201 and a second chip inductor 202 are further arranged below the organic adapter plate 205, wherein a second group of solder balls 207 is arranged between the first chip inductor 201 and the organic adapter plate 205, between the second chip inductor 202 and the organic adapter plate 205, and between the low inductance gallium nitride module 200 and the organic adapter plate 205.

[0036] Embodiment two

[0037] Reference Figure 1 The AI computing chip vertical power supply structure disclosed by the application comprises a low inductance gallium nitride module 200, a first chip inductor 201, a second chip inductor 202, an output capacitor 203, an AI computing chip 204, an organic adapter plate 205, a solder ball 207 and a through silicon via adapter plate 208;

[0038] The AI computing chip 204, the through silicon via adapter plate 208, the organic adapter plate 205 and the low inductance gallium nitride module 200 are sequentially distributed from top to bottom, a plurality of output capacitors 203 are arranged between the organic adapter plate 205 and the through silicon via adapter plate 208, a first group of solder balls 207 is arranged between adjacent output capacitors 203, and a first chip inductor 201 and a second chip inductor 202 are further arranged below the organic adapter plate 205, wherein a second group of solder balls 207 is arranged between the first chip inductor 201 and the organic adapter plate 205, between the second chip inductor 202 and the organic adapter plate 205, and between the low inductance gallium nitride module 200 and the organic adapter plate 205.

[0039] Reference Figure 2The low-susceptibility gallium nitride module 200 comprises a first gallium nitride device 100, a second gallium nitride device 101, a first conductive layer 102, a second conductive layer 103, a third conductive layer 104, a first via hole 105, a second via hole 106, a fourth conductive layer 107, a fifth conductive layer 108, and a decoupling capacitor 109.

[0040] One side of each decoupling capacitor 109 is connected with the fourth conductive layer 107, and the other side of each decoupling capacitor 109 is connected with the fifth conductive layer 108.

[0041] The first conductive layer 102, the second conductive layer 103, the third conductive layer 104, the first gallium nitride device 100, and the second gallium nitride device 101 are arranged below the decoupling capacitor 109, wherein the first conductive layer 102, the second conductive layer 103, and the third conductive layer 104 are sequentially distributed and located in the same plane.

[0042] As an embodiment of the present application, one side of the first conductive layer 102 is a first comb-shaped structure, one side of the second conductive layer 103 is a second comb-shaped structure, the other side of the second conductive layer 103 is a third comb-shaped structure, one side of the third conductive layer 104 is a fourth comb-shaped structure, each comb in the first comb-shaped structure and each comb in the second comb-shaped structure are sequentially and alternately distributed, and each comb in the third comb-shaped structure and each comb in the fourth comb-shaped structure are sequentially and alternately distributed.

[0043] As an embodiment of the present application, one side of the first gallium nitride device 100 is connected with the third conductive layer 104, the other side of the first gallium nitride device 100 is connected with the second conductive layer 103, one side of the second gallium nitride device 101 is connected with the second conductive layer 103, and the other side of the second gallium nitride device 101 is connected with the first conductive layer 102.

[0044] As an embodiment of the present application, one decoupling capacitor 109 corresponds to one comb in the first comb-shaped structure, one comb in the fourth comb-shaped structure, one first via hole 105, and one second via hole 106, wherein one side of each decoupling capacitor 109 is connected with the corresponding comb in the first comb-shaped structure through the corresponding first via hole 105, and the other side of each decoupling capacitor 109 is connected with the corresponding comb in the fourth comb-shaped structure through the corresponding second via hole 106.

[0045] As an embodiment of the present application, the current direction of each comb tooth in the first comb structure is opposite to that of each comb tooth in the second comb structure; the current direction of each comb tooth in the third comb structure is opposite to that of each comb tooth in the fourth comb structure, realizing magnetic cancellation, significantly reducing the interconnection parasitic inductance of the gallium nitride device; at the same time, by using advanced packaging technology, the length of the first via 105 and the second via 106 can be reduced, the area of the current loop is minimized, thereby reducing the interconnection parasitic inductance of the gallium nitride device, promoting the high-frequency application of the gallium nitride device, and further reducing the volume of the inductance and other passive devices.

[0046] As an embodiment of the present application, it should be noted that the low-inductance gallium nitride module 200, the first chip inductor 201 and the second chip inductor 202 constitute a voltage regulation module, and the thickness of the voltage regulation module is less than or equal to 5 mm.

[0047] As an embodiment of the present application, in addition, when applied to a high-power AI computing chip 204, a plurality of gallium nitride devices and a plurality of chip inductors are integrated on the bottom surface of the organic adapter plate 205.

[0048] Due to the above-mentioned low-inductance gallium nitride module 200, the switching frequency can reach several megahertz or even higher, so a super-thin chip inductor array (first chip inductor 201, second chip inductor 202) can be used to prepare a voltage regulation module, and after the above optimization, the maximum thickness of the voltage regulation module is less than 5 mm; the power supply voltage output by the voltage regulation module successively passes through the organic adapter plate 205, the output capacitor 203, the solder ball 207, the through-silicon via adapter plate 208, and finally reaches the AI computing chip 204, which significantly shortens the power supply distance compared to the traditional power supply method, reduces the line loss, reduces the amplitude of voltage dynamic oscillation, and improves the dynamic response characteristics of the power supply voltage; and reduces the volume of the entire system, realizing higher density integration.

[0049] The present application is applicable to all information chips, including but not limited to CPU, GPU, NPU, HBM, FPGA, etc.; at the same time, the vertical power supply structure of the present application can supply power to multiple information chips in the computing system at the same time, and when the power supply power demand is large, the number of gallium nitride devices and chip inductors can be increased.

[0050] The present application greatly reduces the volume of the voltage regulation module by optimizing the layout of the gallium nitride device and the volume of the magnetic component, and can be integrated into the back of the CPU and GPU to realize vertical power supply, shorten the power supply distance, improve the power supply efficiency and the dynamic response characteristics of the power supply voltage; at the same time, it ensures the reliable and stable operation of the CPU, GPU and other computing chips, and provides bottom-level technical support for the further development of CPU, GPU and other computing chips, promotes the development of related fields such as artificial intelligence, cloud computing, data center and autonomous driving.

[0051] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the application being indicated by the following claims.

[0052] It is to be understood that the application is not limited to the precise construction herein described and as shown in the attached drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the application. The scope of the application is limited only by the claims that follow.

[0053] The above description is only the preferred embodiment of the present application, not any limitation to the present application, any simple modification, change and equivalent structure change according to the technical essence of the present application to the above embodiment, still belongs to the protection scope of the technical scheme of the present application.

Claims

1. An AI computing power chip vertical power supply structure, characterized in that, The application relates to an AI computing chip (204), a through-silicon via adapter plate (208), an organic adapter plate (205) and a low-inductance gallium nitride module (200). The AI computing chip (204), the through-silicon via adapter plate (208), the organic adapter plate (205) and the low-inductance gallium nitride module (200) are sequentially arranged from top to bottom, a plurality of output capacitors (203) are arranged between the organic adapter plate (205) and the through-silicon via adapter plate (208), a first group of solder balls (207) are arranged between adjacent output capacitors (203), a first chip inductor (201) and a second chip inductor (202) are further arranged below the organic adapter plate (205), and a second group of solder balls (207) are arranged between the first chip inductor (201) and the organic adapter plate (205), between the second chip inductor (202) and the organic adapter plate (205) and between the low-inductance gallium nitride module (200) and the organic adapter plate (205). The low-inductance gallium nitride module (200) comprises a fourth conductive layer (107), a fifth conductive layer (108) and a plurality of decoupling capacitors (109). One side of each decoupling capacitor (109) is connected with the fourth conductive layer (107), the other side of each decoupling capacitor (109) is connected with the fifth conductive layer (108), a first conductive layer (102), a second conductive layer (103), a third conductive layer (104), a first gallium nitride device (100) and a second gallium nitride device (101) are arranged below the decoupling capacitor (109), the first conductive layer (102), the second conductive layer (103) and the third conductive layer (104) are sequentially arranged and located in the same plane, one side of the first gallium nitride device (100) is connected with the third conductive layer (104), the other side of the first gallium nitride device (100) is connected with the second conductive layer (103), one side of the second gallium nitride device (101) is connected with the second conductive layer (103), and the other side of the second gallium nitride device (101) is connected with the first conductive layer (102). One side of the first conductive layer (102) is a first comb-shaped structure, one side of the second conductive layer (103) is a second comb-shaped structure, the other side of the second conductive layer (103) is a third comb-shaped structure, one side of the third conductive layer (104) is a fourth comb-shaped structure, the combs in the first comb-shaped structure and the combs in the second comb-shaped structure are sequentially and alternately arranged, and the combs in the third comb-shaped structure and the combs in the fourth comb-shaped structure are sequentially and alternately arranged. The application further comprises a plurality of first vias (105) and a plurality of second vias (106), one decoupling capacitor (109) corresponds to one comb in the first comb-shaped structure, one comb in the fourth comb-shaped structure, one first via (105) and one second via (106), one side of each decoupling capacitor (109) is connected with the corresponding comb in the first comb-shaped structure through the corresponding first via (105), and the other side of each decoupling capacitor (109) is connected with the corresponding comb in the fourth comb-shaped structure through the corresponding second via (106).

2. The AI computing chip vertical power supply structure of claim 1, wherein, The current direction of each tooth in the first comb structure is opposite to the current direction of each tooth in the second comb structure. 3.The AI computing power chip vertical power supply structure of claim 2, characterized in that, The current direction of each tooth in the third comb structure is opposite to the current direction of each tooth in the fourth comb structure. 4.The AI computing power chip vertical power supply structure of claim 1, wherein, The low-susceptance gallium nitride module (200), the first chip inductance (201), and the second chip inductance (202) form a voltage regulation module. 5.The AI computing power chip vertical power supply structure of claim 4, characterized in that, The thickness of the voltage regulation module is less than or equal to 5 mm. 6.The AI computing power chip vertical power supply structure of claim 5, characterized in that, The power supply voltage output by the voltage regulation module sequentially passes through an organic adapter plate (205), an output capacitor (203), a solder ball (207), a through-silicon via adapter plate (208), and finally reaches an AI computing chip (204). 7.The AI computing power chip vertical power supply structure of claim 1, wherein, When applied to a high-power AI computing chip (204), multiple gallium nitride devices and multiple chip inductances are integrated on the bottom surface of the organic adapter plate (205).

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