Semiconductor device including through vias and wiring layers

Abstract

The invention provides a semiconductor device including a through via and a wiring layer. The semiconductor device comprises a semiconductor substrate; the first insulating layer is arranged on the first surface of the semiconductor substrate; a through via passing through both the semiconductor substrate and the first insulating layer; a protective barrier wall pattern disposed within the first insulating layer and on a sidewall of the through via; a first wiring structure disposed within the first insulating layer and including a first via portion and a first wiring portion; and a second insulating layer disposed on an upper surface of the first insulating layer and at least partially covering an upper surface of the first wiring structure and an upper surface of the protective barrier wall pattern.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device including a through via and a wiring layer. Background Art

[0002] A stacked semiconductor device is a device in which multiple semiconductor chips are stacked in a single package. Compared with a semiconductor device in which the chips are not stacked, a stacked semiconductor device can provide higher integration and performance. Here, each chip of the stacked semiconductor device may include a through-path, and may be electrically connected to another semiconductor chip or a printed circuit board through the through-path. As semiconductor devices become miniaturized, large-capacity, and highly integrated, the pitch of metal wires in semiconductor devices has been reduced. In this case, the reliability of the metal wires or through-paths may be degraded due to errors that occur during the manufacturing process of the metal wires and through-paths. Summary of the invention

[0003] A semiconductor device includes: a semiconductor substrate; a first insulating layer, which is arranged on a first surface of the semiconductor substrate; a through-via, which passes through both the semiconductor substrate and the first insulating layer; a protective barrier wall pattern, which is arranged in the first insulating layer and on the sidewalls of the through-via; a first wiring structure, which is arranged in the first insulating layer and includes a first via portion and a first wiring portion; and a second insulating layer, which is arranged on an upper surface of the first insulating layer and at least partially covers an upper surface of the first wiring structure and an upper surface of the protective barrier wall pattern.

[0004] A semiconductor device, comprising: a substrate; a first insulating layer, the first insulating layer being disposed on a first surface of the substrate; a through via, the through via penetrating the substrate and the first insulating layer; a protective barrier wall pattern, the protective barrier wall pattern being disposed in the first insulating layer and at least partially covering a sidewall of an upper portion of the through via; and a first wiring structure, the first wiring structure being disposed in the first insulating layer and comprising a first via portion and a first wiring portion. The outer sidewall of the protective barrier wall pattern is laterally spaced apart from the sidewall of the first wiring portion.

[0005] A semiconductor device comprises: a semiconductor substrate; an integrated circuit, the integrated circuit being arranged on a first surface of the semiconductor substrate; a lower insulating layer, the lower insulating layer being arranged on the first surface of the semiconductor substrate and at least partially covering the integrated circuit; a first insulating layer, the first insulating layer being arranged on the lower insulating layer and comprising a first etch stop layer and a first interlayer insulating layer, the first interlayer insulating layer being arranged on an upper surface of the first etch stop layer; a first wiring structure, the first wiring structure being arranged in the first insulating layer and comprising a first via portion and a first wiring portion, the first wiring structure being electrically connected to the integrated circuit; a through via, the through via being arranged in the semiconductor substrate, the lower insulating layer and the first insulating layer; a protective barrier wall pattern, the protective barrier wall pattern being arranged on the first etch stop layer and in the first interlayer insulating layer and at least partially covering a sidewall of an upper portion of the through via; a second insulating layer, the second insulating layer at least partially covering an upper surface of the first insulating layer, an upper surface of the first wiring structure and an upper surface of the protective barrier wall pattern; a second wiring structure, the second wiring structure being arranged in the a second insulating layer, and including a second via portion and a second wiring portion; a third insulating layer, the third insulating layer at least partially covering the upper surface of the second insulating layer and the upper surface of the second wiring structure; a third wiring structure, the third wiring structure is arranged in the third insulating layer and includes a third via portion and a third wiring portion; a back insulating layer, the back insulating layer is arranged on the second surface of the semiconductor substrate; and a lower pad, the lower pad is arranged in the back insulating layer, wherein the through-via includes: a conductive path, the conductive path is electrically connected to the lower pad; a barrier layer, the barrier layer is arranged on the side wall of the conductive path; and an isolation layer, the isolation layer is arranged between the semiconductor substrate and the barrier layer, between the lower insulating layer and the barrier layer, and between the first insulating layer and the barrier layer, and the second wiring structure includes a second circuit wiring structure and a second through-wiring structure, the second circuit wiring structure is arranged on the upper surface of the first wiring structure and is electrically connected to the first wiring structure; and a second through-wiring structure, the second through-wiring structure is arranged on the upper surface of the through-via and is electrically connected to the through-via. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0007] Figure 1A is a cross-sectional view showing a semiconductor device according to an embodiment;

[0008] Figure 1Bis a top view showing a through via and a protection barrier wall pattern of a semiconductor device;

[0009] Figure 1C It is shown Figure 1A is an enlarged cross-sectional view of a region I of a semiconductor device, and corresponds to a region along Figure 1B A section taken along line II-II';

[0010] Figure 1D yes Figure 1C An enlarged cross-sectional view of region III;

[0011] Figure 1E is a top view showing a planar arrangement of a through via and a second via portion of a second through wiring structure according to the embodiment;

[0012] Figure 2 is a cross-sectional view showing a semiconductor device according to an embodiment; and

[0013] FIG. 3A to FIG. 3O is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0014] As used herein, like reference numerals may refer to like components throughout the specification and drawings. A semiconductor device and a method of manufacturing the same according to the inventive concept will be described below.

[0015] Figure 1A is a cross-sectional view showing a semiconductor device according to an embodiment.

[0016] refer to Figure 1A, the semiconductor device 10 may include a substrate 100, a solder ball terminal 600, an upper pad 360, a through via 500, a front insulating layer 110, a wiring structure 300, a protective barrier wall pattern 400, a back insulating layer 120, and a lower pad 200. The semiconductor device 10 may be a semiconductor chip including a memory chip, a logic chip, or a combination thereof. The substrate 100 may be a semiconductor substrate. The substrate 100 may include, for example, a semiconductor material such as silicon, germanium, or silicon germanium. The substrate 100 may have a first surface 100a and a second surface 100b opposite to the first surface 100a. The second surface 100b of the substrate 100 may be substantially parallel to the first surface 100a. The first surface 100a of the substrate 100 may be a front surface. The second surface 100b of the substrate 100 may be a back surface. The through via 500 may be disposed in the substrate 100. The through via 500 may pass through the first surface 100a and the second surface 100b of the substrate 100. The through via 500 may further extend into a portion of the front insulating layer 110 and a portion of the back insulating layer 120. The first direction D1 may be an extension direction of the first surface 100a of the substrate 100. The second direction D2 may be an extension direction of the first surface 100a of the substrate 100 and may intersect the first direction D1. The third direction D3 may be substantially perpendicular to the first surface 100a of the substrate 100. The third direction D3 may be a vertical direction.

[0017] The back insulating layer 120 may be disposed on the second surface 100b of the substrate 100. The second surface 100b of the substrate 100 may be a lower surface. The back insulating layer 120 may include a silicon-based insulating material. The silicon-based insulating material may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide oxide, tetraethyl orthosilicate (TEOS) and / or a combination thereof. The lower pad 200 may be disposed on the lower surface of the back insulating layer 120 or in the back insulating layer 120. The lower surface of the lower pad 200 may be exposed by the back insulating layer 120. The lower pad 200 may be disposed on the lower surface of the through-via 500 and may be electrically connected to the through-via 500, respectively. The lower pad 200 may include copper, aluminum, titanium, tantalum and / or a combination thereof. In the specification, electrical coupling / electrical connection may include direct coupling / connection or indirect coupling / connection through other conductive components.

[0018] The front insulating layer 110 may be disposed on the first surface 100a of the substrate 100. The front insulating layer 110 may be multilayered. The front insulating layer 110 may include a silicon-based insulating material. The wiring structure 300 may be disposed in the front insulating layer 110 and may be electrically connected to the through via 500. The wiring structure 300 may include a metal. The upper pad 360 may be disposed on the front insulating layer 110 and may be electrically connected to the wiring structure 300. The upper pad 360 may include a metal.

[0019] The solder ball terminals 600 may be respectively disposed on the upper surfaces of the upper pads 360 and may be respectively connected to the upper pads 360. Hereinafter, the through via 500, the front insulating layer 110, and the wiring structure 300 will be described in more detail. To simplify the description, a single through via 500, a single upper pad 360, a single solder ball terminal 600, and a single lower pad 200 will be described.

[0020] Figure 1B is a top view showing a through via and a protection barrier pattern of a semiconductor device. Figure 1C It is shown Figure 1A is an enlarged cross-sectional view of a region I of the semiconductor device 10, and corresponds to a region I along Figure 1B A cross section taken along line II-II'. Figure 1D yes Figure 1C An enlarged cross-sectional view of region III. Figure 1E 1 is a top view showing a planar arrangement of a through via and a second through wiring structure according to an embodiment. In the following, if an element in this figure is not described in detail, it can be understood that the element is at least similar to a corresponding element that has been described elsewhere in the present disclosure.

[0021] refer to Figure 1A , Figure 1B , Figure 1C and Figure 1D , the semiconductor device 10 may include a substrate 100 , a lower pad 200 , a back insulating layer 120 , an integrated circuit 115 , a through via 500 , a front insulating layer 110 , a wiring structure 300 , an upper pad 360 , and a solder ball terminal 600 .

[0022] like Figure 1C As shown, the integrated circuit 115 may be disposed on the first surface 100a of the substrate 100. The first surface 100a of the substrate 100 may be an upper surface. The integrated circuit 115 may include a logic circuit, a memory circuit, or a combination thereof. The integrated circuit 115 may include a transistor. For example, the integrated circuit 115 may include a device having a three-dimensional structure, such as a fin field effect transistor (FinFET), but is not necessarily limited thereto.

[0023] The front insulating layer 110 and the wiring structure 300 may be disposed on the first surface 100a of the substrate 100. The front insulating layer 110 may include a lower insulating layer 101, a first insulating layer 111, a second insulating layer 112, a third insulating layer 113, and a fourth insulating layer 114. The wiring structure 300 may include a conductive pattern 305, a first wiring structure 315, a second wiring structure 325, a third wiring structure 335, and a fourth wiring structure 345.

[0024] The lower insulating layer 101 may be disposed on the first surface 100a of the substrate 100 and may cover the integrated circuit 115. The lower insulating layer 101 may include, for example, silicon oxide, tetraethyl orthosilicate (TEOS), silicon nitride, silicon oxynitride, silicon carbide oxide, and / or silicon carbonitride. The lower insulating layer 101 may be multi-layered.

[0025] The semiconductor device 10 may further include a conductive pattern 305. The conductive pattern 305 may be disposed within the lower insulating layer 101 and may be electrically connected to the integrated circuit 115. For example, the conductive pattern 305 may include a contact plug. Each conductive pattern 305 may further include a metal line, a metal path, and / or a combination thereof. The conductive pattern 305 may include cobalt, tungsten, copper, and / or a combination thereof.

[0026] The first insulating layer 111 may be disposed on the upper surface of the lower insulating layer 101. Figure 1D As shown, the first insulating layer 111 may include a first etch stop layer 111A and a first interlayer insulating layer 111B. The first etch stop layer 111A may cover an upper surface of the first lower insulating layer 101. The first etch stop layer 111A may include, for example, TEOS, but is not necessarily limited thereto.

[0027] The first interlayer insulating layer 111B may be disposed on an upper surface of the first etch stop layer 111A. The first interlayer insulating layer 111B may include a silicon-based insulating material. An upper surface of the first insulating layer 111 may correspond to an upper surface of the first interlayer insulating layer 111B.

[0028] The first wiring structure 315 may be disposed within the first insulating layer 111 and respectively disposed on the conductive patterns 305. The first wiring structures 315 may be spaced apart from each other laterally. When any two components are spaced apart from each other laterally, it may be indicated that the two components are spaced apart from each other horizontally. The term "horizontally" may mean parallel to the first surface 100a of the substrate 100. The first wiring structure 315 may be a circuit wiring structure. The first wiring structure 315 may be electrically connected to the integrated circuit 115 through the conductive pattern 305.

[0029] Each first wiring structure 315 may include a first via portion V1 and a first wiring portion W1. The first via portion V1 may pass through the first etch stop layer 111A. The first via portion V1 may further pass through the lower portion of the first interlayer insulating layer 111B. The first via portion V1 may be disposed on a conductive pattern 305 corresponding to the first via portion V1 and may be electrically connected to the conductive pattern 305. The first wiring portion W1 may be disposed on the first via portion V1 and may be connected to the first via portion V1. The width of the first wiring portion W1 may be greater than the width of the first via portion V1. The first wiring portion W1 may be disposed within the first interlayer insulating layer 111B. For example, the first wiring portion W1 may pass through the upper surface of the first interlayer insulating layer 111B, and the first via portion V1 may be disposed within the upper portion of the first interlayer insulating layer 111B. In the specification, a via may be a component for vertical connection, and a wiring may be a component for horizontal connection. The term "vertical" may mean perpendicular to the first surface 100a of the substrate 100.

[0030] The upper surface of the first wiring structure 315 may be coplanar with the upper surface of the first interlayer insulating layer 111B. The upper surface of each first wiring structure 315 may correspond to the upper surface of the first wiring portion W1. The first wiring structure 315 may include, for example, copper, titanium, tantalum, and / or alloys thereof.

[0031] The through via 500 may be disposed in the substrate 100. Figure 1C As shown, the lower portion of the through via 500 may extend into the back insulating layer 120, and the upper portion of the through via 500 may extend into the lower insulating layer 101. Figure 1C As shown, the width of the upper surface of the through via 500 may be greater than the width of the lower surface of the through via 500. The upper surface of the through via 500 may be coplanar with the upper surface of the first interlayer insulating layer 111B.

[0032] The through via 500 may include a conductive via 530, a barrier layer 520, and an isolation layer 510. The conductive via 530 may include a metal such as copper. The barrier layer 520 may be disposed on the sidewall of the conductive via 530 and may extend along the sidewall of the conductive via 530. For example, the barrier layer 520 may be disposed between the conductive via 530 and the substrate 100, and may be disposed between the conductive via 530 and the lower insulating layer 101 and between the conductive via 530 and the first insulating layer 111. The barrier layer 520 may prevent the metal included in the conductive via 530 from diffusing into the substrate 100. The barrier layer 520 may include a metal different from the conductive via 530. For example, the barrier layer 520 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), and / or tantalum nitride (TaN). Being electrically connected to the through via 500 may mean being electrically connected to the conductive via 530 or the barrier layer 520.

[0033] The isolation layer 510 may be disposed along the outer sidewall of the barrier layer 520. For example, the isolation layer 510 may be disposed between the barrier layer 520 and the substrate 100, and may be disposed between the barrier layer 520 and the lower insulating layer 101, and between the barrier layer 520 and the first insulating layer 111. The isolation layer 510 may include a silicon-containing insulating material. For example, the isolation layer 510 may include a low dielectric material such as porous silicon oxide, siloxane, or a silsesquioxane-based material. The isolation layer 510 may electrically isolate the conductive path 530 from the substrate 100.

[0034] The protection barrier wall pattern 400 may be disposed between the first insulating layer 111 and the through via 500. The protection barrier wall pattern 400 may cover at least a portion of the sidewall 500c of the upper portion of the through via 500. Figure 1D As shown, the protection barrier wall pattern 400 may be disposed on an upper surface of the first etch stop layer 111A, and may be disposed between the first interlayer insulating layer 111B and the through via 500 .

[0035] The protection barrier wall pattern 400 may have an inner sidewall and an outer sidewall facing each other. The inner sidewall of the protection barrier wall pattern 400 may be in physical contact with the through-path 500. The outer sidewall of the protection barrier wall pattern 400 may be covered by the first interlayer insulating layer 111B. The width W of the protection barrier wall pattern 400 may be in the range of 450 μm to 550 μm. The width W of the protection barrier wall pattern 400 may correspond to the distance between the outer sidewall and the inner sidewall of the protection barrier wall pattern 400. The outer sidewall of the protection barrier wall pattern 400 may have a first outer sidewall and a second outer sidewall facing each other. The outer diameter A1 of the protection barrier wall pattern 400 may be the distance between the first outer sidewall and the second outer sidewall of the protection barrier wall pattern 400. The outer diameter A1 of the protection barrier wall pattern 400 may be greater than the width A2 of the through-path 500. The difference between the outer diameter A1 of the protection barrier wall pattern 400 and the width A2 of the through-path 500 may be in the range of 0.5 μm to 2 μm.

[0036] like Figure 1B As shown, in a top view, the protection barrier wall pattern 400 may at least partially surround the through via 500. The planar shape of the protection barrier wall pattern 400 may correspond to the planar shape of the through via 500. For example, the through via 500 may have a circular planar shape or an elliptical planar shape. The protection barrier wall pattern 400 may have a closed loop shape or a ring shape.

[0037] like Figure 1D As shown, the protection barrier wall pattern 400 may be laterally spaced apart from the first wiring structure 315. For example, an outer sidewall of the protection barrier wall pattern 400 may be horizontally spaced apart from a sidewall of the first wiring portion W1. A first interlayer insulating layer 111B may be disposed between the protection barrier wall pattern 400 and the first wiring structure 315.

[0038] The lower surface of the protection barrier wall pattern 400 may be in contact with the upper surface of the first etch stop layer 111A. The upper surface of the protection barrier wall pattern 400 may be coplanar with the upper surface of the through via 500, the upper surface of the first interlayer insulating layer 111B, and the upper surface of the first wiring structure 315. The upper surface of the through via 500 may include the upper surface 530a of the conductive via 530. The upper surface of the through via 500 may further include the upper surface of the barrier layer 520 and the upper surface of the isolation layer 510. The surfaces of certain components being coplanar with each other may include the surfaces of the components being substantially at the same level, and the difference in the levels of the surfaces of the components being within a process error range.

[0039] The protection barrier wall pattern 400 may include an insulating material different from the first etch stop layer 111A and the first interlayer insulating layer 111B. For example, the protection barrier wall pattern 400 may include silicon nitride. For example, the protection barrier wall pattern 400 may include silicon oxynitride.

[0040] The second insulating layer 112 may be disposed on the first insulating layer 111. The second insulating layer 112 may include a second etch stop layer 112A and a second interlayer insulating layer 112B. The second etch stop layer 112A may cover the upper surface of the first insulating layer 111, the upper surface of the first wiring structure 315, and the upper surface of the protective barrier wall pattern 400. For example, the second etch stop layer 112A may be in physical contact with the upper surface of the first insulating layer 111, the upper surface of the first wiring structure 315, and the upper surface of the protective barrier wall pattern 400. The second etch stop layer 112A may further cover the upper surface of the through via 500. For example, the second etch stop layer 112A may include a high dielectric material. The dielectric constant of the high dielectric material may be higher than that of silicon oxide. For example, the dielectric constant of the second etch stop layer 112A may be higher than that of the first interlayer insulating layer 111B and the second interlayer insulating layer 112B. For example, the second etch stop layer 112A may include aluminum oxide. However, the material of the second etch stop layer 112A is not necessarily limited thereto.

[0041] The second interlayer insulating layer 112B may be disposed on the upper surface of the second etch stop layer 112A. The second interlayer insulating layer 112B may include a silicon-based insulating material. The upper surface of the second insulating layer 112 may correspond to the upper surface of the second interlayer insulating layer 112B. Different from the illustration, the second etch stop layer 112A may be omitted, and the second interlayer insulating layer 112B may cover the upper surface of the first insulating layer 111, the upper surface of the first wiring structure 315, the upper surface of the through via 500, and the upper surface of the protective barrier wall pattern 400.

[0042] The second wiring structure 325 may be disposed within the second insulating layer 112. Each second wiring structure 325 may include a second via portion V2 and a second wiring portion W2. The second via portion V2 may pass through the second etch stop layer 112A. The second via portion V2 may further pass through the lower portion of the second interlayer insulating layer 112B. The second wiring portion W2 may be disposed on the second via portion V2 and may be connected to the second via portion V2. The width of the second wiring portion W2 may be greater than the width of the second via portion V2. The second wiring portion W2 may be disposed within the second interlayer insulating layer 112B. For example, the second wiring portion W2 may pass through the upper portion of the second interlayer insulating layer 112B. The upper surface of each second wiring structure 325 may correspond to the upper surface of the corresponding second wiring portion W2. The second wiring structure 325 may include a metal as described in the example of the first wiring structure 315. For example, the second wiring structure 325 may include copper, titanium, tantalum and / or an alloy thereof.

[0043] The second wiring structure 325 may include a second circuit wiring structure 325C and a second through wiring structure 325T. The second circuit wiring structure 325C may be disposed on the first wiring structure 315 and may be electrically connected to the first wiring structure 315, respectively. For example, the second via portion V2 of each second circuit wiring structure 325C may be disposed between a first wiring portion W1 corresponding to the second via portion V2 and a second wiring portion W2 corresponding to the second via portion V2. Therefore, the second circuit wiring structure 325C may be electrically connected to the integrated circuit 115 through the first wiring structure 315. The upper surface of the second circuit wiring structure 325C may be coplanar with the upper surface of the second insulating layer 112.

[0044] The second through wiring structure 325T may be disposed on the upper surface of the through via 500 and may be electrically connected to the through via 500. The second through wiring structure 325T may be laterally spaced apart from the second circuit wiring structure 325C. For example, the second interlayer insulating layer 112B may be disposed between the second through wiring structure 325T and the second circuit wiring structure 325C.

[0045] The second through wiring structure 325T may include a plurality of second via portions V2 and second wiring portions W2. The second via portions V2 of the second through wiring structure 325T may be disposed on the upper surface 530a of the conductive path 530 and may be electrically connected to the conductive path 530. The second via portions V2 of the second through wiring structure 325T may be laterally spaced apart from each other. The second insulating layer 112 may be disposed between the second via portions V2 of the second through wiring structure 325T. The second insulating layer 112 may be disposed between the upper surface of the through via 500 (e.g., the upper surface 530a of the conductive path 530) and the second wiring portion W2. Therefore, the upper surface 530a of the conductive path 530 may be covered by the second etch stop layer 112A and may be in physical contact with the second etch stop layer 112A. For example, the second etch stop layer 112A may cover at least a portion of the upper surface of the central region of the conductive path 530. When the second insulating layer 112 does not include the second etch stop layer 112A, the second interlayer insulating layer 112B may cover the upper surface 530a of the conductive via 530. The central region of the conductive via 530 may correspond to the central region of the through via 500.

[0046] Another component may not be disposed between the second through wiring structure 325T and the conductive via 530. For example, the second through wiring structure 325T may be in direct contact with the upper surface 530a of the conductive via 530. Therefore, the resistance between the conductive via 530 and the second through wiring structure 325T may be reduced. The semiconductor device 10 may exhibit enhanced electrical characteristics.

[0047] The level of the upper surface 530a of the conductive path 530 may be uniformly distributed. Therefore, the second through wiring structure 325T and the conductive path 530 may be well electrically connected to each other, so that the electrical characteristics between the second through wiring structure 325T and the conductive path 530 may be further enhanced. In addition, the electrical characteristics between the second circuit wiring structure 325C and the first wiring structure 315 may be enhanced.

[0048] like Figure 1E As shown, the second via portions V2 of the second through wiring structure 325T may form a stripe pattern in a top view. For example, in a top view, each second via portion V2 of the second through wiring structure 325T may extend along the second direction D2. Each second via portion V2 of the second through wiring structure 325T may have a stripe shape, a rectangular shape, or a rectangular shape with rounded corners. The second via portions V2 of the second through wiring structure 325T may be spaced apart from each other in the first direction D1. However, the arrangement of the second via portions V2 of the second through wiring structure 325T may be modified differently.

[0049] like Figure 1D As shown, the second wiring portion W2 of the second through wiring structure 325T may be disposed on the second via portion V2 of the second through wiring structure 325T. The second wiring portion W2 of the second through wiring structure 325T may be connected to the second via portion V2 of the second through wiring structure 325T. The lower surface of the second wiring portion W2 of the second through wiring structure 325T may contact the second interlayer insulating layer 112B. The upper surface of the second through wiring structure 325T may be coplanar with the upper surface of the second insulating layer 112 and the upper surface of the second circuit wiring structure 325C.

[0050] The third insulating layer 113 may be disposed on the upper surface of the second insulating layer 112, the upper surface of the second circuit wiring structure 325C, and the upper surface of the second through wiring structure 325T. The third insulating layer 113 may include a third etch stop layer 113A and a third interlayer insulating layer 113B. The third etch stop layer 113A may cover the upper surface of the second insulating layer 112, the upper surface of the second circuit wiring structure 325C, and the upper surface of the second through wiring structure 325T. The third etch stop layer 113A may include a high dielectric material. For example, the dielectric constant of the third etch stop layer 113A may be greater than the dielectric constant of the third interlayer insulating layer 113B. The third interlayer insulating layer 113B may be disposed on the third etch stop layer 113A. The third interlayer insulating layer 113B may include a silicon-based insulating material. Unlike the illustration, the third insulating layer 113 may not include the third etch stop layer 113A. In this case, the third interlayer insulating layer 113B may be in physical contact with an upper surface of the second insulating layer 112 , an upper surface of the second circuit wiring structure 325C, and an upper surface of the second through wiring structure 325T.

[0051] The third wiring structure 335 may be disposed within the third insulating layer 113. Each of the third wiring structures 335 may include a third via portion V3 and a third wiring portion W3. The third via portion V3 may pass through the third etch stop layer 113A. The third via portion V3 may further pass through the lower portion of the third interlayer insulating layer 113B. The third wiring portion W3 may be disposed on the third via portion V3 and may be connected to the third via portion V3. The width of the third wiring portion W3 may be greater than the width of the third via portion V3. The third wiring portion W3 may be disposed within the third interlayer insulating layer 113B. The upper surface of each of the third wiring structures 335 may correspond to the upper surface of the third wiring portion W3. The third wiring structure 335 may include a metal as described in the example of the second wiring structure 325.

[0052] The third wiring structure 335 may include a third circuit wiring structure 335C and a third through wiring structure 335T. The third circuit wiring structure 335C may be disposed on the second circuit wiring structure 325C and may be electrically connected to the second circuit wiring structure 325C. For example, the third via portion V3 of each third circuit wiring structure 335C may be disposed between the second wiring portion W2 and the third wiring portion W3 of the corresponding second circuit wiring structure 325C. Therefore, the third circuit wiring structure 335C may be electrically connected to the integrated circuit 115 through the second circuit wiring structure 325C. The upper surface of the third circuit wiring structure 335C may be coplanar with the upper surface of the third insulating layer 113.

[0053] The third through wiring structure 335T may be disposed on the upper surface of the second through wiring structure 325T. The third through wiring structure 335T may be spaced apart from the third circuit wiring structure 335C laterally. For example, the third interlayer insulating layer 113B may be disposed between the third through wiring structure 335T and the third circuit wiring structure 335C. For example, the third through wiring portion V3 of the third through wiring structure 335T may be disposed between the second wiring portion W2 of the second through wiring structure 325T and the third wiring portion W3 of the third through wiring structure 335T. The third through wiring structure 335T may be electrically connected to the through via 500 through the second through wiring structure 325T. The upper surface of the third through wiring structure 335T may be coplanar with the upper surface of the third insulating layer 113 and the upper surface of the third circuit wiring structure 335C, but is not necessarily limited thereto.

[0054] like Figure 1C As shown, the fourth insulating layer 114 may be disposed on the third insulating layer 113, the third circuit wiring structure 335C, and the third through wiring structure 335T. The fourth insulating layer 114 may include a silicon-based insulating material, but is not necessarily limited thereto. The fourth insulating layer 114 may further include an etching stop layer. A plurality of fourth insulating layers 114 may be provided. A plurality of fourth insulating layers 114 may be stacked on the third insulating layer 113. The lowermost fourth insulating layer 114 may cover the upper surface of the third insulating layer 113, the upper surface of the third circuit wiring structure 335C, and the upper surface of the third through wiring structure 335T.

[0055] The fourth wiring structure 345 may be disposed within the fourth insulating layer 114. Each of the fourth wiring structures 345 may include a fourth via portion and / or a fourth wiring portion. The fourth wiring portion may be disposed on the fourth via portion and may be connected to the fourth via portion. The width of the fourth wiring portion may be greater than the width of the fourth via portion. The fourth wiring structure 345 may include a metal as described in the example of the third wiring structure 335. The fourth wiring structure 345 may include a plurality of stacked fourth wiring structures 345. The number of stacked fourth wiring structures 345 is not necessarily limited to the illustration, and various modifications may be made. The fourth wiring structure 345 may be electrically connected to the third wiring structure 335. The third through wiring structure 335T may be electrically connected to the third circuit wiring structure 335C through the fourth wiring structure 345. Therefore, the through via 500 may be electrically connected to the integrated circuit 115 through the wiring structure 300. For example, the through via 500 may be electrically connected to the integrated circuit 115 through the second through wiring structure 325T, the third through wiring structure 335T, the fourth wiring structure 345 , the second and third circuit wiring structures 325C and 335C, and the conductive pattern 305 . Figure 1CIt is shown that the third through wiring structure 335T and the at least one third circuit wiring structure 335C are electrically connected to each other through any one of the lowermost fourth wiring structures 345, but the inventive concept is an example and is not necessarily limited thereto. For example, the third through wiring structure 335T and the at least one third circuit wiring structure 335C may be electrically connected to each other through at least one fourth wiring structure 345 on the lowermost fourth wiring structure 345.

[0056] The upper pad 360 may be disposed on any one of the uppermost fourth wiring structures 345 and the uppermost fourth insulating layer 114. The upper pad 360 may be electrically connected to the integrated circuit 115 and the through-path 500 through the wiring structure 300. For example, the upper pad 360 may be electrically connected to the integrated circuit 115 through the fourth wiring structure 345, the second circuit wiring structure 325C and the third circuit wiring structure 335C, the first wiring structure 315 and the conductive pattern 305. The upper pad 360 may be electrically connected to the through-path 500 through the fourth wiring structure 345 and the second through-path 325T and the third through-path 335T. Here, the electrical connection between the upper pad 360 and the through-path 500 may be performed via the third circuit wiring structure 335C and / or the second circuit structure 325C in addition, but is not necessarily limited thereto. The upper pad 360 may include a metal different from the fourth wiring structure 345. For example, the upper pad 360 may include aluminum, chromium, nickel, or a combination thereof, but is not necessarily limited thereto. The upper pad 360 may be a welding pad, but is not necessarily limited thereto.

[0057] The semiconductor device 10 may further include a solder ball terminal 600. The solder ball terminal 600 may be disposed on the upper pad 360. The solder ball terminal 600 may be electrically connected to the integrated circuit 115 and the through-path 500 through the wiring structure 300. The solder ball terminal 600 may include a metal such as a solder material. The solder material may include, for example, tin (Sn), silver (Ag), zinc (Zn) and / or their alloys. As another example, the semiconductor device 10 may not include the solder ball terminal 600.

[0058] The semiconductor device 10 may further include a protective insulating layer 130. The protective insulating layer 130 may be disposed on an upper surface of the uppermost fourth insulating layer 114, and may expose the upper pad 360 and the solder ball terminal 600. The protective insulating layer 130 may include an insulating polymer or silicon nitride.

[0059] The lower pad 200 and the back insulating layer 120 may be disposed on the second surface 100b of the substrate 100. The upper surface and sidewall of the lower pad 200 may be covered by the back insulating layer 120. The lower surface of the lower pad 200 may be exposed by the back insulating layer 120. The lower pad 200 may be disposed on the lower surface of the conductive path 530 and may be electrically connected to the conductive path 530. For example, the lower pad 200 may be electrically connected to the through path 500. The barrier layer 520 and the isolation layer 510 may not extend between the conductive path 530 and the back insulating layer 120. In this case, the back insulating layer 120 may further cover the sidewall of the lower portion of the conductive path 530. However, the inventive concept is not necessarily limited thereto. The lower pad 200 may be electrically connected to the integrated circuit 115 and the solder ball terminal 600 through the conductive path 530 and the wiring structure 300. The lower pad 200 may be electrically connected to another semiconductor device or semiconductor chip.

[0060] Figure 2 is a cross-sectional view showing a semiconductor device according to an embodiment, and corresponds to Figure 1C Hereinafter, if an element in the figure is not described in detail, it can be understood that the element is at least similar to the corresponding element described elsewhere in the present disclosure.

[0061] refer to Figure 2 as well as Figures 1A to 1C , the semiconductor device may include a substrate 100, an integrated circuit 115, a through via 500, a front insulating layer 110, and a wiring structure 300. Figure 1B and Figure 1C As shown, the semiconductor device may include an upper pad 360, a back insulating layer 120, and a lower pad 200. The wiring structure 300 may include first to fourth wiring structures 315 to 345. The second wiring structure 325 may include a second through wiring structure 325T and a second circuit wiring structure 325C.

[0062] The second through wiring structure 325T may include a single second via portion V2 and a single second wiring portion W2. For example, the second via portion V2 of the second through wiring structure 325T may be disposed between the conductive via 530 and the second wiring portion W2 of the second through wiring structure 325T, and may be electrically connected to the conductive via 530 and the second wiring portion W2. The second via portion V2 of the second through wiring structure 325T may have a circular shape in a top view. The second insulating layer 112 may be spaced apart from the central area of ​​the upper surface of the through via 500.

[0063] FIG. 3A to FIG. 3O is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment, and corresponds to Figure 1A Magnified view of region I.

[0064] refer to Figure 3A , a substrate 100 may be provided. An integrated circuit 115, a lower insulating layer 101, and a first etch stop layer 111A may be formed on a first surface 100a of the substrate 100. A protective layer 401 may be formed on the first etch stop layer 111A. The protective layer 401 may be formed by, for example, a deposition process, but is not necessarily limited thereto. For example, the protective layer 401 may include silicon nitride and / or silicon oxynitride. The thickness of the protective layer 401 may be relatively large.

[0065] The through hole 590 may be formed in the protective layer 401, the first etch stop layer 111A, the lower insulating layer 101, and the substrate 100. The through hole 590 may be formed by an etching process. The through hole 590 may not pass through the second surface 100b' of the substrate 100. The bottom surface of the through hole 590 may be disposed in the substrate 100. The sidewalls of the through hole 590 may correspond to the inner sidewalls of the protective layer 401, the inner sidewalls of the first etch stop layer 111A, the inner sidewalls of the lower insulating layer 101, and the inner sidewalls of the substrate 100. For example, the through hole 590 may be formed by a via-middle process. For example, after the integrated circuit 115 is formed, the through hole 590 may be formed. Figure 3D The through hole 590 and the through passage 500 are provided.

[0066] refer to Figure 3B , a preliminary isolation layer 510P may be conformally formed on the sidewall of the through hole 590 and the upper surface 401a of the protective layer 401. A preliminary barrier layer 520P may be formed in the through hole 590 and on the upper surface 401a of the protective layer 401 to conformally cover the preliminary isolation layer 510P. A preliminary conductive path 530P may be formed on the preliminary isolation layer 510P. Forming the preliminary conductive path 530P may include forming a seed layer and performing an electroplating process using the seed layer as an electrode. The through hole 590 may be filled with a conductive material by an electroplating process to form the preliminary conductive path 530P. The preliminary conductive path 530P may have a first upper surface 531a and a second upper surface 532a. In a top view, the first upper surface 531a of the preliminary conductive path 530P may overlap with the through hole 590. The second upper surface 532a of the preliminary conductive path 530P may be disposed on the upper surface 401a of the protective layer 401 in a top view, and the second upper surface 532a of the preliminary conductive path 530P may be spaced apart from the through hole 590 in a top view. The second upper surface 532a of the preliminary conductive path 530P may be disposed at a different level from the first upper surface 531a. The first upper surface 531a of the preliminary conductive path 530P may not be flat.

[0067] refer to Figure 3C, the preliminary conductive via 530P, the preliminary barrier layer 520P, and the preliminary isolation layer 510P may be planarized to form a conductive via 530, a barrier layer 520, and an isolation layer 510, respectively. The conductive via 530, the barrier layer 520, and the isolation layer 510 may be formed in the through hole 590, respectively. Thus, the through via 500 may be manufactured. The upper sidewall of the through via 500 may be covered by the protective layer 401.

[0068] The planarization process can be performed by using a chemical mechanical polishing (CMP) process. The protective layer 401 can be used as a stop layer for the planarization process. For example, after the upper surface 401a of the protective layer 401 is exposed, the planarization process is completed. The through-path 500 can be located in the through-hole 590. During the planarization process, the preliminary conductive path 530P, the preliminary barrier layer 520P, and the preliminary isolation layer 510P can be removed from the upper surface 401a of the protective layer 401. Therefore, after the planarization process is completed, the upper surface 530aa of the conductive path 530, the upper surface of the barrier layer 520, and the upper surface of the isolation layer 510 can be exposed. In the process of planarizing the preliminary conductive path 530P, non-uniformity within a small error range may occur in the process. The preliminary conductive path 530P may have a relatively large width and height, and therefore, the upper surface 530aa of the conductive path 530 after the planarization process may become uneven due to non-uniformity within a small error range in the process. The level of the upper surface 530aa of the conductive path 530 may have a relatively uniform distribution. For example, the upper surface 530aa of the conductive path 530 may include a protruding portion and / or a recessed portion. Figure 3C As shown, the upper surface 530aa of the conductive path 530 may protrude. The upper surface 530aa of the conductive path 530 may be convex upward. In a top view, the conductive path 530 may have a central area and an edge area. In a top view, the edge area of ​​the conductive path 530 may at least partially surround the central area. The edge area of ​​the conductive path 530 may be disposed between the central area of ​​the conductive path 530 and the barrier layer 520. The upper surface of the central area of ​​the conductive path 530 may be disposed at a higher level than the upper surface of the edge area.

[0069] Figure 3D is a cross-sectional view illustrating a through via after a planarization process according to an embodiment. Figure 3E is a cross-sectional view illustrating a through via after a planarization process according to an embodiment.

[0070] refer to Figure 3D, the upper surface 530aa of the through-path 500 may have a disc-like shape (e.g., a bowl-like shape). For example, the upper surface 530aa of the conductive path 530 may be convex downward. The upper surface 530aa of the central region of the conductive path 530 may be disposed at a lower level than the upper surface 530aa of the edge region of the conductive path 530. The upper surface 530aa of the central region of the conductive path 530 may be disposed at a lower level than the upper surface 401a of the protective layer 401.

[0071] refer to Figure 3E , the upper surface 530aa of the through via 500 may not be flat. The upper surface 530aa of the conductive via 530 may have a protruding portion and a recessed portion. The protruding portion of the upper surface 530aa of the conductive via 530 may be disposed at a higher level than the recessed portion of the upper surface 530aa.

[0072] In the following, for convenience, FIG. 3F to FIG. 3I Shows Figure 3C The upper surface 530aa of the conductive path 530 protrudes, but the present inventive concept is not necessarily limited thereto. FIG. 3F to FIG. 3O The manufacturing method can basically be applied to Figure 3D The conductive path 530 and Figure 3E The conductive path 530 is provided.

[0073] refer to Figure 3F , a mask pattern 490 may be formed on an upper surface 530aa of the through via 500. For example, the mask pattern 490 may cover the upper surface 530aa of the conductive via 530 and may cover a portion of the upper surface 401a of the protective layer 401. The width of the mask pattern 490 may be greater than the width of the through via 500. The difference between the width of the mask pattern 490 and the width of the through via 500 may be in the range of 0.5 μm to 2 μm. The mask pattern 490 may include, for example, silicon carbonitride, silicon oxycarbonitride, and / or a combination thereof. The protective layer 401 may include a first portion and a second portion. The first portion of the protective layer 401 may be covered by the mask pattern 490. The second portion of the protective layer 401 may be exposed by the mask pattern 490.

[0074] Refer to Figure 3F and Figure 3G, an etching process may be performed on the protective layer 401 to form a preliminary protective barrier wall pattern 400P. The etching process may be performed by a dry etching process. The second portion of the protective layer 401 may be removed by the etching process, and the upper surface of the first etch stop layer 111A may be exposed. In the etching process, the first etch stop layer 111A may have an etching selectivity relative to the protective layer 401. The etching rate of the first etch stop layer 111A may be lower than the etching rate of the protective layer 401. Therefore, the first etch stop layer 111A may not be removed. After the etching process is completed, the upper surface of the first etch stop layer 111A may be exposed.

[0075] The mask pattern 490 may not be removed in the etching process. In the etching process, the first portion of the protective layer 401 may not be exposed by the mask pattern 490. After the etching process is completed, the remaining first portion of the protective layer 401 may form a preliminary protective barrier wall pattern 400P. The preliminary protective barrier wall pattern 400P may cover the upper sidewall of the through via 500. Due to the preliminary protective barrier wall pattern 400P, the upper sidewall of the through via 500 may not be exposed in the etching process. Therefore, damage to the through via 500 can be prevented.

[0076] The width of the mask pattern 490 may be substantially the same as the outer diameter A1′ of the preliminary protective barrier wall pattern 400P. The outer diameter A1′ of the preliminary protective barrier wall pattern 400P may be substantially the same as the outer diameter A1′ of the reference Figure 1B and Figure 1D The outer diameter A1 of the protective barrier wall pattern 400P described above is substantially the same. The outer diameter A1' of the preliminary protective barrier wall pattern 400P may be 0.5 μm or more greater than the width A2' of the through via 500, and thus, the preliminary protective barrier wall pattern 400P may sufficiently protect the through via 500. The difference between the outer diameter A1' of the preliminary protective barrier wall pattern 400P and the width A2' of the through via 500 may be 2 μm or less, and thus, the thickness of the preliminary protective barrier wall pattern 400P used to form the reference 500 below may be ensured. Fig. 3I and Figure 3J The space of the first wiring structure 315 is described. Therefore, the semiconductor device can be miniaturized and can be highly integrated.

[0077] The width W' of the preliminary protection barrier wall pattern 400P may be the same as the reference Figure 1B and Figure 1D The width W of the protection barrier wall pattern 400 described is substantially the same. The width W' of the preliminary protection barrier wall pattern 400P may be 450 μm or more, and thus the through via 500 may be stably protected. The width W' of the preliminary protection barrier wall pattern 400P may be 550 μm or less, and thus the semiconductor device may be miniaturized.

[0078] After the etching process is completed, a cleaning process may be further performed. Residues of the etching process may be removed by the cleaning process. Hydrofluoric acid (HF), dilute hydrofluoric acid (DHF) or aerosol may be used in the cleaning process.

[0079] refer to Figure 3H The mask pattern 490 may be removed to expose the upper surface of the through via 500 and the upper surface of the preliminary protection barrier wall pattern 400P. For example, the upper surface 530aa of the conductive via 530, the upper surface of the barrier layer 520, and the upper surface of the isolation layer 510 may be exposed.

[0080] refer to Fig. 3I , a first interlayer insulating layer 111B may be formed on the first etch stop layer 111A, the preliminary protection barrier wall pattern 400P, and the through via 500 to cover the upper surface of the first etch stop layer 111A, the outer sidewall and upper surface of the preliminary protection barrier wall pattern 400P, and the upper surface of the through via 500. For example, the first interlayer insulating layer 111B may cover the upper surface 530aa of the conductive via 530. Thus, the first insulating layer 111 including the first etch stop layer 111A and the first interlayer insulating layer 111B may be manufactured.

[0081] The first opening 105 may be formed in the first etch stop layer 111A and in the first interlayer insulating layer 111B. Each first opening 105 may have a first via hole and a first trench. The first via hole may be formed in the first etch stop layer 111A to expose the conductive pattern 305. The first via hole may correspond to the lower portion of the corresponding first opening 105. The first trench may be formed in the upper portion of the first interlayer insulating layer 111B and may be connected to the first via hole. The first trench may correspond to the upper portion of the corresponding first opening 105. The width of the first trench may be greater than the width of the first via hole. The first opening 105 may be formed by an etching process. For example, the first opening 105 may be formed by a dual damascene process. The first interlayer insulating layer 111B may further expose at least a portion of the upper surface 530aa of the conductive path 530.

[0082] A first conductive layer 315P may be formed on the first interlayer insulating layer 111B. The first conductive layer 315P may be formed in the first opening 105 to fill the first opening 105. The first conductive layer 315P may extend onto the upper surface of the first interlayer insulating layer 111B. For example, forming the first conductive layer 315P may include conformally forming a seed layer in the first opening 105 and on the first interlayer insulating layer 111B, and performing an electroplating process using the seed layer as an electrode. The first conductive layer 315P may be electrically connected to the conductive pattern 305. The first conductive layer 315P may cover the upper surface 530aa exposed by the conductive path 530.

[0083] Refer to Fig. 3I and Figure 3J , a planarization process may be performed on the first conductive layer 315P to form the first wiring structure 315. The planarization process may be performed by using a CMP process. The upper portion of the first conductive layer 315P may be removed by the planarization process. The upper portion of the first conductive layer 315P may be disposed on the upper surface of the first interlayer insulating layer 111B, the upper surface of the preliminary protection barrier wall pattern 400P, and the upper surface of the through-via 500. Therefore, the first wiring structure 315 may be located within the first opening 105, and the upper surface of the first interlayer insulating layer 111B may be exposed. Each first wiring structure 315 may include a first via portion V1 and a first wiring portion W1. The first via portion V1 may be disposed within the first via hole of the first opening 105, and the first wiring portion W1 may be disposed within the first trench of the first opening 105.

[0084] During the planarization process, the first interlayer insulating layer 111B may be removed from the upper surface of the preliminary protection barrier wall pattern 400P and the upper surface of the through via 500. Subsequently, the preliminary protection barrier wall pattern 400P and the through via 500 may be planarized. The upper portion of the through via 500 may be removed by the planarization process. Before the planarization process, the height of the through via 500 and the height of the preliminary protection barrier wall pattern 400P may be relatively high. For example, the height of the preliminary protection barrier wall pattern 400P ( Fig. 3I H1 in the figure may be the height of the first wiring structure 315 ( Figure 3J The thickness of the conductive path 530 may be 2 to 2.5 times of H2 in (H2 in (H2). Therefore, the through via 500 and the preliminary protective barrier wall pattern 400P may be fully planarized. After the planarization process is completed, the upper surface of the through via 500 may be substantially flat. For example, the upper surface 530a of the conductive path 530 may be flat. The preliminary protective barrier wall pattern 400P may be planarized to form the protective barrier wall pattern 400. The height of the protective barrier wall pattern 400 may be less than the height of the preliminary protective barrier wall pattern 400P ( Fig. 3I The upper surface of the through via 500 may be coplanar with the upper surface of the protection barrier wall pattern 400 , the upper surface of the first interlayer insulating layer 111B, and the upper surface of the first wiring structure 315 .

[0085] According to an embodiment, the height of the preliminary protection barrier wall pattern 400P ( Fig. 3I The height H1 of the preliminary protection barrier wall pattern 400P may be twice or more the height of the first wiring structure 315, and thus, the horizontal height distribution of the upper surface 530a of the conductive path 530 may be made more uniform. The height H1 of the preliminary protection barrier wall pattern 400P may not exceed 2.5 times the height of the first wiring structure 315, and thus, the efficiency of the manufacturing process of the semiconductor device may be improved.

[0086] refer to Figure 3K , a second etch stop layer 112A may be formed on the first interlayer insulating layer 111B, the first wiring structure 315, and the protective barrier wall pattern 400. The second etch stop layer 112A may further cover the upper surface 530a of the conductive path 530. For example, the second etch stop layer 112A may be formed by a deposition process. The second interlayer insulating layer 112B may be formed on the second etch stop layer 112A by a deposition process. Therefore, a second insulating layer 112 including the second etch stop layer 112A and the second interlayer insulating layer 112B may be formed. A second opening 106 and a third opening 107 may be formed in the second insulating layer 112. The second opening 106 may be formed in the second etch stop layer 112A and the second interlayer insulating layer 112B to expose the first wiring structure 315. The third opening 107 may be formed in the second etch stop layer 112A and the second interlayer insulating layer 112B to expose the through via 500. The second opening 106 and the third opening 107 may each have a second via hole and a second trench. The second trench may be disposed on the second via hole and may be connected to the second via hole. A width of the second trench may be greater than a width of the second via hole.

[0087] The second wiring structure 325 may be formed in the second opening 106 and the third opening 107. For example, the second wiring structure 325 may include a second circuit wiring structure 325C and a second through wiring structure 325T. The second circuit wiring structure 325C may be formed in the second opening 106. The second through wiring structure 325T may be formed in the third opening 107.

[0088] The second wiring structure 325 may be formed in the same or similar manner as the method of previously forming the first wiring structure 315. For example, the second wiring structure 325 may include forming a second conductive layer within the second opening 106 and the third opening 107 and on the second interlayer insulating layer 112B, and performing a planarization process on the second conductive layer. The second conductive layer may be formed by an electroplating process.

[0089] The planarization process may be performed by using a CMP process. The upper portion of the second conductive layer may be removed by the planarization process. Therefore, the second wiring structure 325 may be located within the second opening 106 and the third opening 107, and the upper surface of the second interlayer insulating layer 112B may be exposed. Each second wiring structure 325 may include a second via portion V2 and a second wiring portion W2. The second via portion V2 may be disposed within the second via hole, and the second wiring portion W2 may be disposed within the second trench.

[0090] According to an embodiment, the level distribution of the upper surface 530a of the conductive via 530 can be made more uniform, and thus, the electrical characteristics between the through via 500 and the second through wiring structure 325T and the electrical characteristics between the first wiring structure 315 and the second circuit wiring structure 325C can be enhanced. Therefore, the reliability can be improved and the electrical characteristics of the semiconductor device can be enhanced.

[0091] refer to Figure 3L , a third insulating layer 113 may be formed on both the second interlayer insulating layer 112B and the second wiring structure 325. Forming the third insulating layer 113 may include forming a third etch stop layer 113A and forming a third interlayer insulating layer 113B. The third etch stop layer 113A may be formed by a deposition process. The third interlayer insulating layer 113B may be formed by a deposition process.

[0092] A third wiring structure 335 may be formed within the third insulating layer 113. The formation of the third wiring structure 335 may be performed the same or similar to the method of previously forming the second wiring structure 325. For example, a fourth opening 108 may be formed within the third insulating layer 113. The fourth opening 108 may expose the second wiring structure 325. For example, forming the third wiring structure 335 may include forming a third conductive layer within the fourth opening 108 and on the third interlayer insulating layer 113B, and performing a planarization process on the third conductive layer. The third wiring structure 335 may include a third circuit wiring structure 335C and a third through wiring structure 335T. Each third wiring structure 335 may include a third wiring portion W3 and at least one third via portion V3.

[0093] refer to Figure 3M , a fourth insulating layer 114 may be formed on the third interlayer insulating layer 113B and the third wiring structure 335. The fourth insulating layer 114 may be formed by a deposition process. Subsequently, a fourth wiring structure 345 may be formed in the fourth insulating layer 114 and may be electrically connected to the third wiring structure 335. Figure 3L The described method of forming the third wiring structure 335 is performed identically or similarly to forming the fourth wiring structure 345 .

[0094] The process of forming the fourth insulating layer 114 and the process of forming the fourth wiring structure 345 may be repeatedly performed to form a plurality of stacked fourth insulating layers 114 and a plurality of stacked fourth wiring structures 345 .

[0095] An upper pad 360 may be formed on the uppermost fourth wiring structure 345 and the uppermost fourth insulating layer 114. A protective insulating layer 130 may be formed on the uppermost fourth insulating layer 114. A pad hole may be formed in the protective insulating layer 130 to expose the upper pad 360.

[0096] refer to Figure 3N , a thinning process may be performed on the second surface 100b' of the substrate 100, and thus the end of the through via 500 may be exposed. The thinning process may be performed by a CMP process, an etch-back process, or a combination thereof. A portion of the isolation layer 510 may be exposed on the thinned second surface 100b of the substrate 100. The exposed portion of the isolation layer 510 and a portion of the barrier layer 520 may be removed to expose the end of the conductive via 530. The removal of the exposed portion of the isolation layer 510 and the portion of the barrier layer 520 may be performed by an etch-back process or an etching process.

[0097] refer to Fig.3O , a back side insulating layer 120 may be formed on the second surface 100b of the substrate 100 to cover the second surface 100b of the substrate 100 and the end of the conductive path 530. The lower pad 200 may be formed on the lower surface of the back side insulating layer 120 or in the back side insulating layer 120 and may be electrically connected to the conductive path 530. The lower surface of the lower pad 200 may be exposed by the back side insulating layer 120.

[0098] Return to reference Figure 1A and Figure 1C , solder ball terminals 600 may be formed on the upper pads 360 of the substrate 100. As described above, the manufacture of the semiconductor device 10 may be completed.

[0099] According to an embodiment, a preliminary protection barrier wall pattern and a through-path can be formed at a relatively high height. The preliminary protection barrier wall pattern can form a protection barrier wall pattern by a planarization process. The through-path can be fully planarized by the planarization process. After the planarization process is completed, the horizontal height distribution of the upper surface of the through-path can be more uniform. Therefore, the electrical connection characteristics between the through-path and the wiring structure can be enhanced. The semiconductor device can have increased reliability and enhanced electrical characteristics.

[0100] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; a first insulating layer, the first insulating layer being disposed on a first surface of the semiconductor substrate; a through via that passes through both the semiconductor substrate and the first insulating layer; a protection barrier wall pattern disposed in the first insulating layer and on a sidewall of the through via; a first wiring structure disposed within the first insulating layer and including a first via portion and a first wiring portion; as well as A second insulating layer is disposed on an upper surface of the first insulating layer and at least partially covers an upper surface of the first wiring structure and an upper surface of the protection barrier wall pattern.

2. The semiconductor device according to claim 1, further comprising a second through wiring structure provided in the second insulating layer and electrically connected to the through via, in, The second through wiring structure includes: a plurality of second passage portions, the plurality of second passage portions being laterally spaced apart from one another; and A second wiring portion is provided on the plurality of second via portions and is electrically connected to the plurality of second via portions.

3. The semiconductor device according to claim 2, wherein: The second insulating layer is also provided between the plurality of second via portions.

4. The semiconductor device according to claim 3, wherein: The second insulating layer also covers at least a portion of an upper surface of the through via.

5. The semiconductor device according to claim 1, wherein An upper surface of the protection barrier wall pattern is coplanar with an upper surface of the through via.

6. The semiconductor device according to claim 1, further comprising a lower insulating layer disposed between the semiconductor substrate and the first insulating layer, wherein The through via further passes through the lower insulating layer, and the protection barrier wall pattern does not extend between the lower insulating layer and the through via.

7. The semiconductor device according to claim 1, wherein The first insulating layer comprises: a first etch stop layer; and a first interlayer insulating layer, the first interlayer insulating layer being disposed on the first etch stop layer, The protection barrier wall pattern is disposed on an upper surface of the first etch stop layer, and the first via portion passes through the first etch stop layer.

8. The semiconductor device according to claim 7, wherein: The first etch stop layer includes a material different from a material of the protection barrier wall pattern.

9. The semiconductor device according to claim 1, further comprising a second wiring structure, in, The second wiring structure comprises: a second circuit wiring structure disposed within the second insulating layer and located on an upper surface of the first wiring structure and electrically connected to the first wiring structure; and a second through wiring structure, the second through wiring structure being disposed in the second insulating layer and on the through via and being electrically connected to the through via, The second through wiring structure is laterally spaced apart from the second circuit wiring structure.

10. The semiconductor device according to claim 9, further comprising an integrated circuit disposed on the first surface of the semiconductor substrate, wherein: The second circuit wiring structure is electrically connected to the integrated circuit through the first wiring structure.

11. A semiconductor device, comprising: substrate; a first insulating layer, the first insulating layer being disposed on a first surface of the substrate; a through via, the through via penetrating the substrate and the first insulating layer; a protection barrier wall pattern disposed in the first insulating layer and at least partially covering a sidewall of an upper portion of the through via; as well as a first wiring structure disposed in the first insulating layer and including a first via portion and a first wiring portion, Wherein, an outer sidewall of the protection barrier wall pattern is laterally spaced apart from a sidewall of the first wiring portion.

12. The semiconductor device according to claim 11, further comprising a second insulating layer disposed on the first insulating layer, wherein: The second insulating layer covers an upper surface of the first wiring structure and an upper surface of the protection barrier wall pattern.

13. The semiconductor device according to claim 12, wherein: The second insulating layer includes a second etch stop layer and a second interlayer insulating layer disposed on the second etch stop layer, wherein the second etch stop layer is in physical contact with an upper surface of both the first wiring structure and an upper surface of the protection barrier wall pattern.

14. The semiconductor device according to claim 12, further comprising a second through wiring structure provided in the second insulating layer and electrically connected to the through via, in, The second through wiring structure includes: a second wiring portion; and A plurality of second via portions are provided between the through via and the second wiring portion and are laterally spaced apart from each other.

15. The semiconductor device according to claim 14, wherein: The second insulating layer is further provided between the plurality of second via portions and between an upper surface of the through via and a lower surface of the second wiring portion.

16. The semiconductor device according to claim 11, wherein An upper surface of the protection barrier wall pattern is coplanar with an upper surface of the first insulating layer.

17. A semiconductor device, comprising: Semiconductor substrate; an integrated circuit, the integrated circuit being disposed on a first surface of the semiconductor substrate; a lower insulating layer, the lower insulating layer being disposed on the first surface of the semiconductor substrate and at least partially covering the integrated circuit; a first insulating layer, the first insulating layer being disposed on the lower insulating layer and comprising a first etch stop layer and a first interlayer insulating layer, the first interlayer insulating layer being disposed on an upper surface of the first etch stop layer; a first wiring structure disposed within the first insulating layer and comprising a first via portion and a first wiring portion, the first wiring structure being electrically connected to the integrated circuit; a through via, the through via being disposed in the semiconductor substrate, the lower insulating layer and the first insulating layer; a protection barrier wall pattern disposed on the first etch stop layer and in the first interlayer insulating layer and at least partially covering a sidewall of an upper portion of the through via; a second insulating layer at least partially covering an upper surface of the first insulating layer, an upper surface of the first wiring structure, and an upper surface of the protection barrier wall pattern; a second wiring structure disposed within the second insulating layer and including a second via portion and a second wiring portion; a third insulating layer, the third insulating layer at least partially covering an upper surface of the second insulating layer and an upper surface of the second wiring structure; a third wiring structure disposed in the third insulating layer and including a third via portion and a third wiring portion; a back insulating layer, the back insulating layer being disposed on the second surface of the semiconductor substrate; as well as a lower pad, the lower pad being arranged in the back insulating layer, The through-via includes a barrier layer electrically connected to the lower pad conductive path, disposed on the sidewall of the conductive path, and an isolation layer, wherein the isolation layer is disposed between the semiconductor substrate and the barrier layer, between the lower insulating layer and the barrier layer, and between the first insulating layer and the barrier layer, and Among them, the second wiring structure includes a second circuit wiring structure and a second through wiring structure, the second circuit wiring structure is arranged on the upper surface of the first wiring structure and is electrically connected to the first wiring structure, and the second through wiring structure is arranged on the upper surface of the through via and is electrically connected to the through via.

18. The semiconductor device according to claim 17, wherein: The second through wiring structure is laterally spaced apart from the second circuit wiring structure.

19. The semiconductor device according to claim 17, wherein: The protection barrier wall pattern is laterally spaced apart from the first wiring portion, and the first via portion is disposed within the first etch stop layer.

20. The semiconductor device according to claim 17, wherein The protection barrier wall pattern has a width in a range of 450 μm to 550 μm, the protection barrier wall pattern includes silicon nitride, and the first etch stop layer includes tetraethyl orthosilicate.

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