Semiconductor device

Abstract

A semiconductor device including a high-side circuit region having a plurality of high-side circuits operating at a plurality of mutually different power supply voltages can be obtained without increasing the size of the device. In a semiconductor device (101), an N-type diffusion layer (31a) is provided in a first high-side circuit region (RH1), and an N-type diffusion layer (32a) is provided in a second high-side circuit region (RH2). Structural elements for a first high-side circuit (CH1) and a second high-side circuit (CH2) are provided in the N-type diffusion layers (31a, 32a). A separation trench (70) is provided between the N-type diffusion layer (31a) and the N-type diffusion layer (32a). The deepest part of the separation trench (70) reaches the P-type substrate region of the P-type substrate (10). The N-type diffusion layer (31a) and the N-type diffusion layer (32a) are electrically separated by a separation trench (70) having an embedded insulating film (78) therein.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device having a high-side circuit region and a low-side circuit region. Background Art

[0002] An HVIC (High Voltage Integrated Circuit) for power control, which is mainly used to drive the gate of a power semiconductor device, usually comprises: a low-side circuit that operates using the ground (GND) potential as a reference potential, a high-side circuit that operates using a potential different from the GND potential, such as a floating potential, as a reference potential, and a level conversion circuit that performs signal transmission between the low-side circuit and the high-side circuit.

[0003] As a conventional HVIC, there is a semiconductor device disclosed in Patent Document 1, for example. In the semiconductor device with an HVIC structure disclosed in Patent Document 1, a high-withstand voltage terminal structure of a high-side circuit region where a high-side circuit is provided is electrically separated from a high-withstand voltage level conversion element by trench isolation.

[0004] Patent Document 1: Japanese Patent No. 7001050

[0005] Although the conventional semiconductor device of HVIC structure can separate the high-voltage terminal structure and high-voltage level conversion of the high-side circuit area, the internal structure of the high-side circuit area is usually a structure in which the elements are arranged in the same N-type diffusion area, so the power supply voltage of the high-side circuit area is a single power supply voltage. In addition, even if a plurality of high-side circuits operating at different power supply voltages are arranged in the high-side circuit area, the element voltage must be designed to be the maximum voltage in the circuit, so there is a problem of large-scale device.

[0006] As described above, conventional semiconductor devices having an HVIC structure have a problem that a plurality of high-side circuits that operate at different power supply voltages cannot be provided in a high-side circuit region without increasing the size of the device. Summary of the invention

[0007] The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to obtain a semiconductor device having a high-side circuit region including a plurality of high-side circuits operating at a plurality of power supply voltages different from each other without increasing the size of the device.

[0008] The semiconductor device involved in the present disclosure includes: a semiconductor substrate; a low-side circuit region, which is arranged on the above-mentioned semiconductor substrate and receives a first reference potential; a high-side circuit region, which is arranged on the above-mentioned semiconductor substrate and receives a second reference potential different from the above-mentioned first reference potential; and a first separation region, which electrically separates the above-mentioned low-side circuit region from the above-mentioned high-side circuit region, the above-mentioned semiconductor substrate has a circuit base region where the above-mentioned low-side circuit region and the above-mentioned high-side circuit region are not arranged, the above-mentioned high-side circuit region includes a first high-side circuit region and a second high-side circuit region, a first high-side circuit is arranged in the above-mentioned first high-side circuit region, and a second high-side circuit is arranged in the above-mentioned second high-side circuit region, the above-mentioned first high-side circuit operates at a first power supply voltage based on the above-mentioned second reference potential, and the above-mentioned second high-side circuit operates at a second power supply voltage based on the above-mentioned second reference potential, and the above-mentioned first power supply voltage and the second power supply voltage are different voltage values, and the above-mentioned semiconductor device also includes a second separation region, which electrically separates the above-mentioned first high-side circuit region from the above-mentioned second high-side circuit region.

[0009] Since the semiconductor device disclosed in the present invention has a second separation region that electrically separates the first high-side circuit region from the second high-side circuit region, no obstacles will occur even if the first high-side circuit arranged in the first high-side circuit region is operated at a first power supply voltage and the second high-side circuit arranged in the second high-side circuit region is operated at a second power supply voltage different from the first power supply voltage.

[0010] Therefore, the semiconductor device of the present disclosure can provide the first high-side circuit region including the first high-side circuit and the second high-side circuit region including the second high-side circuit in a structure that maintains miniaturization in the high-side circuit region. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is an explanatory diagram schematically showing a planar structure of the semiconductor device according to the first embodiment.

[0012] Figure 2 It is schematically indicated Figure 1 An explanatory diagram of the circuit structure of the semiconductor device shown.

[0013] Figure 3 This is a cross-sectional view showing a cross section of the semiconductor device according to the first mode of the first embodiment.

[0014] Figure 4 This is a cross-sectional view showing a cross section of a semiconductor device according to a second aspect of the first embodiment.

[0015] Figure 5 This is a cross-sectional view showing a cross section of a semiconductor device according to a third aspect of the first embodiment.

[0016] Figure 6This is a cross-sectional view showing a cross section of a semiconductor device according to a first aspect of the second embodiment.

[0017] Figure 7 This is a cross-sectional view showing a cross section of a semiconductor device according to a second aspect of the second embodiment.

[0018] Figure 8 This is a cross-sectional view showing a cross section of a semiconductor device according to a third aspect of the second embodiment.

[0019] Fig. 9 This is a cross-sectional view showing a cross section of a semiconductor device according to a first aspect of the third embodiment.

[0020] Fig.10 It is a cross-sectional view showing a cross section of a semiconductor device according to a second aspect of the third embodiment.

[0021] Fig.11 This is a cross-sectional view showing a cross section of a semiconductor device according to a first aspect of the fourth embodiment.

[0022] Fig.12 This is a cross-sectional view showing a cross section of a semiconductor device according to a second aspect of the fourth embodiment.

[0023] Description of Reference Numerals

[0024] 7...separation region; 9...SOI substrate; 10...P-type substrate; 10a...support substrate; 11-13...P-type layer; 20-23...N + buried diffusion layer; 30a~30c, 31a~31c, 32a~32c, 33a~33c, 34a~34c...N-type diffusion layer; 40, 41a~41c, 42a~42c, 110~112...P-type diffusion layer; 70~73...separation groove; 101~108, 201, 202...semiconductor device; 120...buried oxide film; 130...SOI layer; CH1...first high-side circuit; CH2...second high-side circuit; RH...high-side circuit area; RH1...first high-side circuit area; RH2...second high-side circuit area; RL...low-side circuit area. DETAILED DESCRIPTION

[0025] <Implementation method 1>

[0026] (Top view of structure and circuit structure)

[0027] Figure 1 1 is an explanatory diagram schematically showing a top view structure of a semiconductor device 100 according to Embodiment 1 of the present invention. The semiconductor device 100 is used as a general term including semiconductor devices 101 to 108 and semiconductor devices 201 and 202. Among them, the semiconductor devices 102 to 108, 201 and 202 will be described in detail later. That is, Figure 1The structure shown is a planar structure common to the semiconductor devices 101 to 108 and the semiconductor devices 201 and 202 shown in Embodiments 1 to 4.

[0028] like Figure 1 As shown, an N-type diffusion layer 30a is provided on the periphery of the high-side circuit region RH, and a P-type diffusion layer 40 is provided around the N-type diffusion layer 30a when viewed from above. The combination of the N-type diffusion layer 30a and the P-type diffusion layer 40 forms a first separation region. The low-side circuit region RL and the high-side circuit region RH are electrically separated by the N-type diffusion layer 30a and the P-type diffusion layer 40 as the first separation region. Therefore, the N-type diffusion layer 30a and the P-type diffusion layer 40 respectively become the first separation diffusion regions included in the first separation region. In this specification, the first conductivity type represents the P type, and the second conductivity type represents the N type.

[0029] The high-side circuit region RH includes a first high-side circuit region RH1 and a second high-side circuit region RH2. A first high-side circuit CH1 is provided in the first high-side circuit region RH1, and a second high-side circuit CH2 is provided in the second high-side circuit region RH2.

[0030] Figure 2 1 is an explanatory diagram schematically showing a circuit configuration of the semiconductor device 100. As shown in the figure, the circuit configuration of the semiconductor device 100 includes a low-side circuit CL, a first high-side circuit CH1, a second high-side circuit CH2, and a level shifter circuit 6 as main components.

[0031] As described above, the low-side circuit CL is a circuit disposed in the low-side circuit region RL, the first high-side circuit CH1 is a circuit disposed in the first high-side circuit region RH1, and the second high-side circuit CH2 is a circuit disposed in the second high-side circuit region RH2.

[0032] The low-side circuit CL receives the ground potential GND as a reference potential, and receives the low-side power supply voltage VCC as an operating voltage with the ground potential GND as a reference potential. The ground potential GND is a first reference potential for the low-side circuit CL. Therefore, the low-side circuit CL performs circuit operation at the low-side power supply voltage VCC with the ground potential GND as a reference. The level conversion circuit 6 performs signal transmission between the low-side circuit CL and the first high-side circuit region RH1.

[0033] The first high-side circuit CH1 receives the high-side reference potential VS as a reference potential and receives the high-side power supply voltage VB1 as an operating voltage. Therefore, the first high-side circuit CH1 performs circuit operation at the high-side power supply voltage VB1 based on the high-side reference potential VS.

[0034] The second high-side circuit CH2 receives the high-side reference potential VS as a reference potential, and receives the high-side power supply voltage VB2 as an operating voltage. Therefore, the second high-side circuit CH2 performs circuit operation at the high-side power supply voltage VB2 based on the high-side reference potential VS. The high-side power supply voltage VB2 is set to a voltage value different from the high-side power supply voltage VB1.

[0035] The high-side reference potential VS is a second reference potential common to the first high-side circuit CH1 and the second high-side circuit CH2. The high-side reference potential VS is a potential different from the ground potential GND and is normally floating because it is electrically separated from the ground potential GND.

[0036] As described above, the first high-side circuit CH1 performs circuit operation using the high-side power supply voltage VB1 as an operating voltage, and the second high-side circuit CH2 performs circuit operation using the high-side power supply voltage VB2 as an operating voltage.

[0037] The high-side power supply voltage VB1 received by the first high-side circuit CH1 becomes the first power supply voltage, and the high-side power supply voltage VB2 received by the second high-side circuit CH2 becomes the second power supply voltage. As described above, the high-side power supply voltage VB1 that becomes the first power supply voltage and the high-side power supply voltage VB2 that becomes the second power supply voltage are set to different voltage levels.

[0038] Figure 1 The top view mainly shows the periphery of the high-side circuit region RH in the semiconductor device 100. Figure 1 In order to simplify the drawings, the following parts are omitted. Figure 3 The cross-sectional structure of the diffusion layer is shown in FIG. Figure 2 FIG. 6 is a diagram of a high withstand voltage MOS of the level conversion circuit 6 shown.

[0039] like Figure 1 As shown, in the high side circuit region RH, a separation region 7 is provided on the outer periphery of the second high side circuit region RH2. The separation region 7 electrically separates the first high side circuit region RH1 and the second high side circuit region RH2.

[0040] Figure 2 The semiconductor device 100 shown controls IGBT2 and IGBT3 connected in series. The collector of IGBT2 receives high voltage HV, the emitter of IGBT2 and the collector of IGBT3 are connected at a node N1, and the emitter of IGBT3 is set to ground potential GND.

[0041] The low-side circuit CL receives an input signal IN from the outside and outputs a low-side control signal SL to the gate of the IGBT3. In addition, the first high-side circuit CH1 outputs a high-side control signal SH to the gate of the IGBT2. The signal obtained at the node N1 is provided to the first high-side circuit CH1 and the second high-side circuit CH2, respectively. In addition, signals are also sent and received between the first high-side circuit CH1 and the second high-side circuit CH2.

[0042] The low-side circuit region RL and the high-side circuit region RH are separated by a high withstand voltage of more than 100 V by the N-type diffusion layer 30a and the P-type diffusion layer 40, which are respectively the first diffusion regions for separation. The low-side circuit region RL and the high-side circuit region RH are separated by a reduced surface field (RESURF) separation structure based on the N-type diffusion layer 30a, which is an N-type diffusion layer of the second conductivity type.

[0043] In this way, the N-type diffusion layer 30a and the P-type diffusion layer 40, which respectively serve as the first isolation diffusion regions, separate the low-side circuit region RL from the high-side circuit region RH in a manner that does not cause any obstacles even when the voltage difference between the low-side circuit region RL and the high-side circuit region RH is greater than 100V.

[0044] The isolation region 7, which serves as the second isolation region, isolates the first high-side circuit region RH1 from the second high-side circuit region RH2 at a withstand voltage of several tens of volts. Figure 1 In the figure, the high withstand voltage MOS, which is not described, is provided in the N-type diffusion layer 30a and in the low-side circuit region RL.

[0045] Thus, the isolation region 7 serving as the second isolation region isolates the first high-side circuit region RH1 from the second high-side circuit region RH2 so that no obstacle occurs as long as the voltage difference between the first high-side circuit region RH1 and the second high-side circuit region RH2 is approximately 10V.

[0046] (First method)

[0047] Figure 3 1 is a cross-sectional view schematically showing a cross-sectional structure of a semiconductor device 101 according to a first mode of embodiment 1. Figure 3 Shown with Figure 1 The AA section is equivalent to the cross-sectional structure. Figure 3 and the following Figures 4 to 12 The cross-sectional structure shown is a schematic diagram, and the shape, scale, etc. do not necessarily correspond to the cross-sectional structure of actual production.

[0048] like Figure 3 As shown in FIG. 1 , a first high-side circuit region RH1 and a second high-side circuit region RH2 are provided on the upper layer of a first conductive type semiconductor substrate, namely, a P-type substrate 10. Figure 3As shown, as a first separation region for separating the high-side circuit region RH from the low-side circuit region RL, an N-type diffusion layer 30a and a P-type diffusion layer 40 are provided on the upper layer of the P-type substrate 10. The P-type diffusion layer 40 is provided so as to surround the high-side circuit region RH when viewed from above. The N-type diffusion layer 30a satisfies the reduced surface electric field condition.

[0049] A portion of the surface of the P-type diffusion layer 40 is provided with a P + Diffusion layer 60. P + The diffusion layer 60 is used to obtain the P-type diffusion layer 40 and the Figure 3 A portion of the surface of the N-type diffusion layer 30a is provided with N + Diffusion layer 50. N + The diffusion layer 50 is used to obtain the N-type diffusion layer 30a and the Figure 3 The metal wiring layer shown in the contact layer. + The diffusion layer 50 is provided in the surface of the N-type diffusion layer 30 a at a position separated from the P-type diffusion layer 40 by a certain distance of several tens of μm or more.

[0050] In the P-type diffusion layer 40 and N + A thermal oxide film 81 is provided on the surface of the N-type diffusion layer 30a between the diffusion layers 50. A field plate composed of polysilicon and a metal wiring layer is provided on the upper layer of the thermal oxide film 81. Figure 3 In order to simplify the drawing, the field plate is omitted. The field plate may also be provided across the end of the thermal oxide film 81 .

[0051] In the first high side circuit region RH1 , an N type diffusion layer 31 a is provided on the upper portion of the P type substrate 10 which is the first conductive type semiconductor substrate. In the second high side circuit region RH2 , an N type diffusion layer 32 a is provided on the upper portion of the P type substrate 10 .

[0052] The N-type diffusion layer 31a and the N-type diffusion layer 32a are formed at the same time, and the N-type diffusion layer 30a is formed after the N-type diffusion layers 31a and 32a are formed. The formation depth of each of the N-type diffusion layers 31a and 32a is deeper than the diffusion depth of the N-type diffusion layer 30a as the first diffusion region for separation. The N-type diffusion layer 31a becomes the first circuit diffusion region, and the N-type diffusion layer 32a becomes the second circuit diffusion region. Therefore, the N-type diffusion layer 31a that becomes the first circuit diffusion region and the N-type diffusion layer 32a that becomes the second circuit diffusion region meet the requirement that "the formation depth of each of the first circuit diffusion region and the second circuit diffusion region is deeper than the formation depth of the first diffusion region for separation", that is, the diffusion region depth requirement.

[0053] The components of the first high-side circuit CH1 are provided on the upper layer of the N-type diffusion layer 31a, and the components of the second high-side circuit CH2 are provided on the upper layer of the N-type diffusion layer 32a. Figure 3 In FIG. 1 , for example, a case where a CMOS structure is provided as a structural element is shown.

[0054] In the first high-side circuit region RH1, a P-type diffusion layer 41a is selectively provided on the upper layer portion of the N-type diffusion layer 31a, and an N-type diffusion layer 41a is selectively provided on the surface of the P-type diffusion layer 41a. + Diffusion layers 51 and 52, N + Diffusion layer 51 and N + The diffusion layers 52 are provided at a certain interval of 0.1 μm or more. + Diffusion layer 51 and N + A polysilicon gate 90 is provided on the P-type diffusion layer 41a between the diffusion layers 52 via a gate oxide film (not shown). In addition, a P + Diffusion layer 61, P + The diffusion layer 61 is used to obtain the P-type diffusion layer 41a and the Figure 3 The metal wiring layer shown in the contact layer is arranged with N + The diffusion layers 51 are adjacent.

[0055] Therefore, the P-type diffusion layer 41a and the N-type diffusion layer 31a provided on the upper layer portion of the N-type diffusion layer 31a + The diffusion layers 51 and 52 , the gate oxide film, and the polysilicon gate 90 constitute an NMOS transistor as a structural element for the first high-side circuit CH1 .

[0056] In the first high-side circuit region RH1, P is selectively provided in the surface of the N-type diffusion layer 31a. + Diffusion layers 62 and 63, P + Diffusion layer 62 and P + The diffusion layers 63 are provided at a certain interval of 0.1 μm or more. + Diffusion layer 62 and P + A polysilicon gate 91 is provided on the N-type diffusion layer 31a between the diffusion layers 63 via a gate oxide film (not shown). In addition, an N + Diffusion layer 53. N + The diffusion layer 53 is used to obtain the N-type diffusion layer 31a and the Figure 3 The metal wiring layer shown in the contact layer is arranged to be connected to the P + The diffusion layer 63 is adjacent.

[0057] Therefore, the P provided in the upper layer portion of the N-type diffusion layer 31a+ The diffusion layers 62 and 63 , the gate oxide film, and the polysilicon gate 91 constitute a PMOS transistor as a structural element for the first high-side circuit CH1 .

[0058] The combination of the NMOS transistor and the PMOS transistor is configured as a CMOS structure provided in the first high-side circuit region RH1. The first high-side circuit CH1 includes the CMOS structure.

[0059] On the other hand, in the second high side circuit region RH2, a P type diffusion layer 42a is selectively provided on the upper layer portion of the N type diffusion layer 32a, and an N type diffusion layer 42a is selectively provided on the surface of the P type diffusion layer 42a. + Diffusion layers 55 and 56, N + Diffusion layer 55 and N + The diffusion layers 56 are provided at a certain interval of 0.1 μm or more. + Diffusion layer 55 and N + A polysilicon gate 93 is provided on the P-type diffusion layer 42a between the diffusion layers 56 via a gate oxide film (not shown). In addition, a P + Diffusion layer 66. P + The diffusion layer 66 is used to obtain the P-type diffusion layer 42a and the Figure 3 The metal wiring layer shown in the contact layer is arranged with N + The diffusion layer 56 is adjacent.

[0060] Therefore, the P-type diffusion layer 42a and the N-type diffusion layer 32a provided on the upper layer portion of the N-type diffusion layer 32a are + The diffusion layers 55 and 56 , the gate oxide film, and the polysilicon gate 93 constitute an NMOS transistor as a structural element for the second high-side circuit CH2 .

[0061] In the second high side circuit region RH2, P is selectively provided in the surface of the N type diffusion layer 32a. + Diffusion layers 64 and 65, P + Diffusion layer 64 and P + The diffusion layers 65 are provided at a certain interval of 0.1 μm or more. + Diffusion layer 64 and P + A polysilicon gate 92 is provided on the N-type diffusion layer 32a between the diffusion layers 65 via a gate oxide film (not shown). In addition, an N + Diffusion layer 54. N + The diffusion layer 54 is used to obtain the N-type diffusion layer 32a and the Figure 3 The metal wiring layer shown in the contact layer is arranged to be connected to the P +The diffusion layer 64 is adjacent.

[0062] Therefore, the P provided in the upper layer portion of the N-type diffusion layer 32a + The diffusion layers 64 and 65 , the gate oxide film, and the polysilicon gate 92 constitute a PMOS transistor as a structural element for the second high-side circuit CH2 .

[0063] The combination of the NMOS transistor and the PMOS transistor is configured as a CMOS structure provided in the second high-side circuit region RH2. The second high-side circuit CH2 includes the CMOS structure.

[0064] exist Figure 3 In the CMOS structure, the drain and source of the MOS transistor are N + Diffusion layers 51, 52, 55 and 56, P + The diffusion layers 62 to 65 are each formed as a single drain structure. In consideration of the drain-source withstand voltage, a DDD (Doublediffused Drain) structure or an LDD (Lightly Doped Drain) structure may be used instead of the single drain structure.

[0065] In the P-type substrate 10, the area where the first high-side circuit CH1 and the second high-side circuit CH2 are not provided becomes the circuit base area. The first high-side circuit CH1 is provided in and on the N-type diffusion layer 31a, and the second high-side circuit CH2 is provided in and on the N-type diffusion layer 32a.

[0066] In Embodiment 1, the substrate region of the first conductivity type, i.e., the P-type, in the P-type substrate 10 below the P-type diffusion layer 40, the N-type diffusion layer 30a, the N-type diffusion layer 31a, and the N-type diffusion layer 32a becomes the circuit base region. In addition, the P-type substrate region in the P-type substrate 10 is set to the ground potential GND as the first reference potential.

[0067] In the semiconductor device 101, a separation trench 70 is provided in the separation region 7. The separation trench 70 is provided between the N-type diffusion layer 31a which becomes the first circuit diffusion region and the N-type diffusion layer 32a which becomes the second circuit diffusion region, and is provided so that the deepest part reaches the P-type substrate region in the P-type substrate 10.

[0068] The N-type diffusion layer 31a and the N-type diffusion layer 32a are electrically separated by the separation trench 70. The separation trench 70 is formed, for example, as follows.

[0069] After forming a temporary N-type diffusion layer in the upper layer of the P-type substrate 10 including the first high-side circuit region RH1, the second high-side circuit region RH2, and the separation region 7, a separation groove 70 is formed in the separation region 7 so as to reach the substrate region from the surface of the P-type substrate 10 including the temporary N-type diffusion layer. The temporary N-type diffusion layer is separated between the first high-side circuit region RH1 and the second high-side circuit region RH2 by the separation groove 70 formed in this way.

[0070] In addition, in this specification, "temporary..." is used as a term indicating a structure in an intermediate stage rather than a completed stage.

[0071] As a result, the temporary N-type diffusion layer remaining in the first high-side circuit region RH1 becomes the N-type diffusion layer 31a, and the temporary N-type diffusion layer remaining in the second high-side circuit region RH2 becomes the N-type diffusion layer 32a. Therefore, the N-type diffusion layer 31a and the N-type diffusion layer 32a are electrically separated by the separation trench 70.

[0072] The separation trench 70 has an embedded insulating film 78 for insulating and separating the first high-side circuit region RH1 from the second high-side circuit region RH2. As a method of embedding the embedded insulating film 78, a first embedding method and a second embedding method can be considered. The first embedding method is a method of filling the separation trench 70 with the embedded insulating film 78. The second embedding method is a method of selectively forming the embedded insulating film 78 on the sidewall in the separation trench 70, and filling the separation trench 70 including the embedded insulating film 78 with polysilicon (not shown).

[0073] The formation depth of the isolation trench 70 is set to, for example, several μm to about 20 μm, and the formation width is set to, for example, 1 to 2 μm. Here, several μm means 2 to 3 μm.

[0074] When the buried insulating film 78 is provided in the first buried manner, the withstand voltage between the first high-side circuit region RH1 and the second high-side circuit region RH2 is ensured by the insulation withstand voltage of the buried insulating film 78 filled in the separation trench 70. In this case, the film thickness of the buried insulating film 78 is equivalent to the formation width of the separation trench 70. When the buried insulating film 78 is provided in the second buried manner, the withstand voltage between the first high-side circuit region RH1 and the second high-side circuit region RH2 is ensured by the insulation withstand voltage of the buried insulating film 78 provided on the side wall of the separation trench 70.

[0075] The N-type diffusion layer 31a as the first circuit diffusion region is connected via N + The high-side power supply voltage VB1 is applied to the diffusion layer 53, and the N-type diffusion layer 32a as the second circuit diffusion region is electrically connected to the N-type diffusion layer 32a via the N +The high-side power supply voltage VB2 is applied to the diffusion layer 54. Both the high-side power supply voltages VB1 and VB2 are high voltages of 100V or more, and the potential difference between the high-side power supply voltage VB1 and the high-side power supply voltage VB2 is several volts to several tens of volts.

[0076] An insulating layer 88 is provided to cover the entire surface of the semiconductor device 101. A metal wiring layer is provided on the insulating layer 88, and the metal wiring layer is connected to the N + Diffusion layer 50~56, P + The diffusion layers 60 to 66 and the polysilicon gate electrodes 90 to 93 are connected independently. Figure 3 In order to simplify the drawings, the illustration of metal wiring layers and contact holes is omitted.

[0077] (Effect)

[0078] The N-type diffusion layer 31a arranged in the first high-side circuit area RH1 and the N-type diffusion layer 32a arranged in the second high-side circuit area RH2 are separated in the horizontal direction by the reduced surface electric field separation structure of the first separation area including the N-type diffusion layer 30a, and are separated in the vertical direction into the ground potential GND and a high voltage of more than 100V by the reverse bias of the P-type substrate area of ​​the P-type substrate 10 and the PN junction of the N-type diffusion layers 31a and 32a.

[0079] The first high-side circuit region RH1 and the second high-side circuit region RH2 are both separated into the ground potential GND and the high voltage, and the N-type diffusion layer 31a of the first high-side circuit region RH1 and the N-type diffusion layer 32a of the second high-side circuit region RH2 are electrically separated by a separation trench 70 having an embedded insulating film 78 as a dielectric.

[0080] The high-side power supply voltage VB1 applied to the N-type diffusion layer 31a is equivalent to the first power supply voltage for the first high-side circuit CH1 set in the first high-side circuit area RH1, and the high-side power supply voltage VB2 applied to the N-type diffusion layer 32a is equivalent to the second power supply voltage for the second high-side circuit CH2 set in the second high-side circuit area RH2.

[0081] In this way, the semiconductor device 101 of the first mode of implementation mode 1 electrically separates the N-type diffusion layer 31a and the N-type diffusion layer 32a through the separation trench 70, so that the high-side reference potential VS can be used as a common second reference potential, and the first high-side circuit CH1 and the second high-side circuit CH2 can be operated by the high-side power supply voltages VB1 and VB2.

[0082] The semiconductor device 101 of the first mode of the first embodiment has a separation groove 70 as a separation region 7 for electrically separating the first high-side circuit region RH1 from the second high-side circuit region RH2. Therefore, in the semiconductor device 101, even if the first high-side circuit CH1 provided in the first high-side circuit region RH1 is operated at the high-side power supply voltage VB1 as the first power supply voltage, and the second high-side circuit CH2 provided in the second high-side circuit region RH2 is operated at the high-side power supply voltage VB2 as the second power supply voltage, no problem occurs.

[0083] Therefore, in the semiconductor device 101 of the first mode of implementation mode 1, a first high-side circuit CH1 and a second high-side circuit CH2 that operate at different high-side power supply voltages VB1 and VB2 can be provided in the high-side circuit area RH that receives the high-side reference potential VS as a common second reference potential while maintaining a miniaturized structure.

[0084] The N-type diffusion layer 31a as the first circuit diffusion region and the N-type diffusion layer 32a as the second circuit diffusion region in the semiconductor device 101 both meet the diffusion region depth requirement, that is, the requirement that the formation depth is deeper than the N-type diffusion layer 30a as the first isolation diffusion region. Therefore, the semiconductor device 101 can achieve an improvement in the horizontal withstand voltage due to the N-type diffusion layer 30a constituting the first isolation region and an improvement in the vertical withstand voltage due to the N-type diffusion layers 31a and 32a.

[0085] The semiconductor device 101 can suppress the parasitic operation between the first high-side circuit CH1 and the second high-side circuit CH2 by having the isolation trench 70 with the buried insulating film 78 therein.

[0086] (Second method)

[0087] Figure 4 1 is a cross-sectional view schematically showing a cross-sectional structure of a semiconductor device 102 according to a second mode of the first embodiment. Figure 4 Shown with Figure 1 In addition, the top view structure and circuit structure of the semiconductor device 102 are similar to those of the AA section. Figure 1 and Figure 2 The structure is the same as the structure shown.

[0088] The following is about Figure 3 The same reference numerals are used to denote common parts of the semiconductor device 101 of the first embodiment, and description thereof is appropriately omitted. The description will focus on characteristic parts of the semiconductor device 102 of the second embodiment.

[0089] In the semiconductor device 102, an N-type N-type substrate in contact with the substrate region of the P-type substrate 10 is provided as a lower layer structure of the first high-side circuit region RH1 and the second high-side circuit region RH2. + In other words, N-type diffusion layers 20 and 21 are selectively provided as the first buried diffusion layer on the P-type substrate region of the P-type substrate 10. + The buried diffusion layer 20 and the N + The diffusion layer 21 is buried.

[0090] Hereinafter, a case where a temporary N-type epitaxial layer is formed as an intermediate stage is described as a first method, and a case where a temporary P-type epitaxial layer is formed as an intermediate stage is described as a second method.

[0091] In the case of the first method, Figure 4 In the cross-sectional structure shown in FIG. 1 , N-type substrate 10 is formed on the upper layer of P-type substrate 10. + After the diffusion layers 20 and 21 are buried, the + A temporary N-type epitaxial layer is formed on the P-type substrate 10 in which the diffusion layers 20 and 21 are buried. Thereafter, a P-type diffusion layer 40 is selectively formed in the temporary N-type epitaxial layer outside the high-side circuit region RH. The temporary N-type epitaxial layer remaining after the P-type diffusion layer 40 is formed outside the high-side circuit region RH becomes the N-type epitaxial layer 30b. The P-type diffusion layer 40 is provided so as to surround the high-side circuit region RH in a plan view.

[0092] The N-type epitaxial layer 30b functions as one of the first separation diffusion regions, and the P-type diffusion layer 40 and the N-type epitaxial layer 30b constitute the first separation region. The low-side circuit region RL and the high-side circuit region RH are electrically separated by the P-type diffusion layer 40 and the N-type epitaxial layer 30b. At this time, the N-type epitaxial layer 30b satisfies the surface electric field reduction condition.

[0093] Furthermore, a P-type diffusion layer 41b and an N-type diffusion layer 31b are selectively formed in the temporary N-type epitaxial layer in the first high-side circuit region RH1, and a P-type diffusion layer 42b and an N-type diffusion layer 32b are selectively formed in the temporary N-type epitaxial layer in the second high-side circuit region RH2. + The diffusion layers 20 and 21 are formed by embedding them.

[0094] In the temporary N-type epitaxial layer, a remaining region after the P-type diffusion layer 40 , the P-type diffusion layers 41 b and 42 b , and the N-type diffusion layers 31 b and 32 b are formed becomes the N-type epitaxial layer 30 b .

[0095] On the other hand, when the second manufacturing method is adopted, N + After the diffusion layers 20 and 21 are buried, the+ A temporary P-type epitaxial layer is formed on the P-type substrate 10 in which the diffusion layers 20 and 21 are buried. Then, an N-type diffusion layer 30b2 (not shown) is selectively formed in the temporary P-type epitaxial layer. The N-type diffusion layer 30b2 corresponds to Figure 4 The N-type epitaxial layer 30b is shown and forms a surface electric field reduction region.

[0096] Furthermore, a P-type diffusion layer 40 is selectively formed in the temporary P-type epitaxial layer. The P-type impurity concentration of the P-type diffusion layer 40 is set higher than the P-type impurity concentration of the temporary P-type epitaxial layer. Therefore, the region surrounded by the P-type diffusion layer 40 becomes the N-type diffusion layer 30b2 when viewed from above.

[0097] In addition, a P-type diffusion layer 41b and an N-type diffusion layer 31b are selectively formed in the temporary P-type epitaxial layer in the first high-side circuit region RH1, and a P-type diffusion layer 42b and an N-type diffusion layer 32b are formed in the temporary P-type epitaxial layer in the second high-side circuit region RH2. + The diffusion layers 20 and 21 are formed by embedding them.

[0098] In the case of the first method, in the intermediate stage, N + The buried diffusion layers 20 and 21 are in contact with the lower surface of the temporary N-type epitaxial layer. + The buried diffusion layers 20 and 21 are in contact with the lower surface of the temporary P-type epitaxial layer.

[0099] As described above, the N-type diffusion layers 31 b and 32 b and the P-type diffusion layers 41 b and 42 b are provided in the temporary N-type epitaxial layer or the temporary P-type epitaxial layer.

[0100] In addition, in the case of the first manufacturing method, a part of the temporary N-type epitaxial layer can also be used as the N-type diffusion layers 31b and 32b. In this case, the temporary N-type epitaxial layer remaining after the P-type diffusion layer 41b is formed in the first high-side circuit region RH1 becomes the N-type diffusion layer 31b, and the temporary N-type epitaxial layer remaining after the P-type diffusion layer 42b is formed in the second high-side circuit region RH2 becomes the N-type diffusion layer 32b.

[0101] In addition, in the case of the second manufacturing method, a part of the temporary P-type epitaxial layer can also be used as the P-type diffusion layers 41b and 42b. In this case, the temporary P-type epitaxial layer remaining after the N-type diffusion layer 31b is formed in the first high-side circuit region RH1 becomes the P-type diffusion layer 41b, and the temporary P-type epitaxial layer remaining after the N-type diffusion layer 32b is formed in the second high-side circuit region RH2 becomes the P-type diffusion layer 42b.

[0102] The semiconductor device 102 has a separation trench 71 in the separation region 7. The separation trench 71 penetrates the N-type diffusion layers 31b and 32b and the N + The diffusion layers 20 and 21 are buried and reach the P-type substrate region in the P-type substrate 10 .

[0103] The N-type diffusion layer 31b and the N-type diffusion layer 32b are electrically separated by the separation trench 71. The separation trench 71 is formed, for example, as follows.

[0104] In the case of the first method, in the separation region 7, the temporary N-type epitaxial layer and the N + The isolation trench 71 is formed so that the surface of the P-type substrate 10 in which the diffusion layers 20 and 21 are buried reaches the substrate region. + The buried diffusion layer 20 and N + The buried diffusion layers 21 are electrically isolated from each other.

[0105] In the case of the second method, in the separation region 7, the temporary P-type epitaxial layer and the N + The isolation trench 71 is formed so that the surface of the P-type substrate 10 in which the diffusion layers 20 and 21 are buried reaches the substrate region. + The buried diffusion layer 20 and N + The buried diffusion layers 21 are electrically isolated from each other.

[0106] In addition, the N-type diffusion layers 31 b and 32 b may be separated by the separation trench 71 in the same manner as the N-type diffusion layers 31 a and 32 a formed in the semiconductor device 101 .

[0107] Thus, the semiconductor device 102 includes an N-type diffusion region provided on the substrate region of the P-type substrate 10 as a first circuit diffusion region. + The buried diffusion layer 20 and the selectively disposed N + The N-type diffusion layer 31b is formed on the buried diffusion layer 20. + The buried diffusion layer 20 becomes a first buried diffusion layer, and the N-type diffusion layer 31 b becomes a first surface diffusion layer.

[0108] The semiconductor device 102 further includes an N-type diffusion region provided on the substrate region of the P-type substrate 10 as a second circuit diffusion region. + The buried diffusion layer 21 is selectively provided on the N + The N-type diffusion layer 32b on the buried diffusion layer 21. + The buried diffusion layer 21 becomes a second buried diffusion layer, and the N-type diffusion layer 32 b becomes a second surface diffusion layer.

[0109] In addition, similarly to the N-type diffusion layer 31a, N-type diffusion layer 31b is selectively provided on the surface thereof. + Diffusion layer 53, P + Diffusion layers 62 and 63. In addition, similarly to the N-type diffusion layer 32a, N-type diffusion layers 32b are selectively provided on the surface thereof. + Diffusion layer 54, P + Diffusion layers 64 and 65.

[0110] In addition, similarly to the P-type diffusion layer 41a, P-type diffusion layer 41b is selectively provided on its surface. + Diffusion layer 61, N + Diffusion layers 51 and 52. In addition, similarly to the P-type diffusion layer 42a, a P-type diffusion layer 42b is selectively provided on its surface. + Diffusion layer 66, N + Diffusion layers 55 and 56.

[0111] In the semiconductor device 102, a separation trench 71 is provided in the separation region 7. The separation trench 71 is provided in the N-type diffusion layer 31b and the N-type diffusion layer 31b to be the first circuit diffusion region. + The buried diffusion layer 20 and the N-type diffusion layer 32b and N + It is buried between the diffusion layers 21 and is provided so that the deepest portion reaches the P-type substrate region in the P-type substrate 10 .

[0112] The N-type diffusion layer 31b and N + The buried diffusion layer 20 and the N-type diffusion layer 32b and N + The buried diffusion layer 21 is electrically isolated by the isolation trench 71 .

[0113] The isolation trench 71 has a buried insulating film 78 therein for insulating and isolating the first high-side circuit region RH1 and the second high-side circuit region RH2 , similarly to the isolation trench 70 .

[0114] The semiconductor device 102 according to the second aspect of the first embodiment includes a separation trench 71 as the separation region 7 for electrically separating the first high-side circuit region RH1 and the second high-side circuit region RH2 .

[0115] Therefore, the semiconductor device 102 of the second mode of the first embodiment can provide the first high-side circuit CH1 and the second high-side circuit CH2 operating at the high-side power supply voltages VB1 and VB2 in the high-side circuit region RH while maintaining a compact structure, similarly to the semiconductor device 101 .

[0116] The first buried diffusion layer forming part of the first circuit diffusion region in the semiconductor device 102, that is, N +The buried diffusion layer 20 and the second buried diffusion layer N + The buried diffusion layer 21 is formed to have a depth deeper than the N-type diffusion layer 30 a which is the first isolation diffusion region.

[0117] By N + The buried diffusion layer 20 and the N-type diffusion layer 31b constitute a first circuit diffusion region. + The buried diffusion layer 21 and the N-type diffusion layer 32b constitute the second circuit diffusion region. Therefore, the semiconductor device 102 also satisfies the requirement of "the formation depth of the first circuit diffusion region and the second circuit diffusion region is deeper than the formation depth of the first isolation diffusion region" similarly to the semiconductor device 101, that is, the diffusion region depth requirement.

[0118] Therefore, the semiconductor device 102 can realize the improvement of the horizontal withstand voltage due to the N-type diffusion layer 30a constituting the first isolation region and the improvement of the N-type diffusion layer 31b and the N-type diffusion layer 31c. + The combination of the buried diffusion layer 20 and the N-type diffusion layer 32b and the N + The combination of the buried diffusion layer 21 improves the withstand voltage in the vertical direction.

[0119] Similar to the semiconductor device 101 , the semiconductor device 102 can suppress the parasitic operation between the first high-side circuit CH1 and the second high-side circuit CH2 by having the isolation trench 71 in which the insulating film 78 is buried.

[0120] In addition, in the semiconductor device 102, N + The first combination structure of the buried diffusion layer 20 and the type diffusion layer 31b can easily meet the above-mentioned diffusion region depth requirements and can be + The second combination structure of the buried diffusion layer 21 and the N-type diffusion layer 32 b can easily meet the above-mentioned diffusion region depth requirement.

[0121] (Third Method)

[0122] Figure 5 FIG. 1 schematically shows a cross-sectional structure of a semiconductor device 103 according to a third aspect of the first embodiment. Figure 5 Shown with Figure 1 The cross-sectional structure is equivalent to the AA cross-sectional structure of FIG. 1. In addition, the top view structure and circuit structure of the semiconductor device 103 are similar to those of FIG. Figure 1 and Figure 2 The structure is the same as the structure shown.

[0123] The following is about Figure 4Components common to the semiconductor device 102 of the second embodiment are denoted by the same reference numerals and description thereof is appropriately omitted, and description will focus on characteristic components of the semiconductor device 103 of the third embodiment.

[0124] The semiconductor device 103 of the third embodiment is characterized in that the N + The buried diffusion layers 20 and 21 are replaced by N + The diffusion layers 22 and 23 are buried, and the separation trench 71 is replaced with a separation trench 72 .

[0125] Therefore, N + The buried diffusion layer 22 becomes the first buried diffusion layer, N + The buried diffusion layer 23 is a second buried diffusion layer. That is, an N-type substrate 10 is selectively provided on the substrate region. + Diffusion layers 22 and 23 are buried.

[0126] In addition, similarly to the second embodiment, the N-type diffusion layer 31b becomes the first surface diffusion layer, and the N-type diffusion layer 32b becomes the second surface diffusion layer. + An N-type diffusion layer 31b is selectively provided on the buried diffusion layer 22. + An N-type diffusion layer 32 b is selectively provided on the buried diffusion layer 23 .

[0127] exist Figure 4 In the semiconductor device 102 of the second embodiment shown in FIG. + The buried diffusion layer 20 and N + The buried diffusion layers 21 are separated by the separation trenches 71. + The buried diffusion layer 20 and N + The buried diffusion layers 21 are in contact with the side walls of the isolation trenches 71 .

[0128] On the other hand, Figure 5 As shown, the third type semiconductor device 103 forms N + When the diffusion layers 22 and 23 are buried, they are separated by patterns, and the N + The buried diffusion layers 22 and 23 are formed discretely from each other. + The buried diffusion layer 22 and N + A P-type substrate region exists between the buried diffusion layers 23 .

[0129] In addition, in addition to discretely forming N + In addition to the buried diffusion layers 22 and 23, N + The buried diffusion layers 22 and 23 are connected to N + The buried diffusion layers 20 and 21 are formed by the same method.

[0130] In the semiconductor device 103, a separation trench 72 is provided in the separation region 7. The separation trench 72 penetrates through the N-type diffusion layers 31b and 32b and reaches the N + The buried diffusion layer 22 and N + The substrate region of the P-type substrate 10 between the diffusion layers 23 is buried.

[0131] like Figure 5 As shown, due to N + The buried diffusion layer 22 and N + The buried diffusion layers 23 have a certain interval wider than the formation width of the isolation trench 72, so the side wall portion of the isolation trench 72 does not contact the N + The buried diffusion layer 22 and N + Any one of the buried diffusion layers 23 is in contact.

[0132] The separation trench 72 reaches the P-type substrate region in the P-type substrate 10, but the deepest portion of the separation trench 72 is set to be deeper than the N-type substrate 10. + The buried diffusion layer 22 and N + The deepest part of each buried diffusion layer 23 is shallow.

[0133] That is, the separation trench 72 and the N + The buried diffusion layer 22 and N + The buried diffusion layers 23 do not have any contact relationship. Furthermore, the separation trench 72 of the semiconductor device 103 satisfies the requirement that "the formation depth of the separation trench 72 is greater than the N layer as the first buried diffusion layer" + The buried diffusion layer 22 and the N + The requirement that each buried diffusion layer 23 be formed at a shallow depth is also a requirement for the trench depth.

[0134] The isolation trench 72 has a buried insulating film 78 therein for insulating and isolating the first high-side circuit region RH1 and the second high-side circuit region RH2 , similarly to the isolation trenches 70 and 71 .

[0135] The semiconductor device 103 of the third aspect of the first embodiment includes a separation trench 72 as the separation region 7 for electrically separating the first high-side circuit region RH1 and the second high-side circuit region RH2 .

[0136] Therefore, similar to the semiconductor devices 101 and 102, the third-type semiconductor device 103 of the first embodiment can be provided with the first high-side circuit CH1 and the second high-side circuit CH2 operating at the high-side power supply voltages VB1 and VB2 in the high-side circuit region RH while maintaining a compact structure.

[0137] The first buried diffusion layer forming part of the first circuit diffusion region in the semiconductor device 103, that is, N + The buried diffusion layer 22 and the second buried diffusion layer forming part of the second circuit diffusion region, that is, N + The buried diffusion layer 23 is formed to a depth deeper than the first isolation diffusion region, that is, the N-type epitaxial layer 30 b .

[0138] By N + The buried diffusion layer 22 and the N-type diffusion layer 31b constitute a first circuit diffusion region. + The buried diffusion layer 23 and the N-type diffusion layer 32b constitute the second circuit diffusion region. Therefore, similar to the semiconductor devices 101 and 102, the semiconductor device 103 also satisfies the requirement that "the first circuit diffusion region and the second circuit diffusion region are each formed deeper than the first isolation diffusion region", i.e., the diffusion region depth requirement.

[0139] Therefore, the semiconductor device 103 can realize the improvement of the horizontal withstand voltage due to the N-type epitaxial layer 30b constituting the first separation region and the improvement of the N-type diffusion layer 31b and the N-type diffusion layer 31b. + The first combination of the buried diffusion layer 22 and the N-type diffusion layer 32b and the N + The second combination of the buried diffusion layers 23 improves the withstand voltage in the vertical direction.

[0140] The semiconductor device 103 , similarly to the semiconductor devices 101 and 102 , can suppress parasitic operation between the first high-side circuit CH1 and the second high-side circuit CH2 by having the isolation trench 72 with the buried insulating film 78 therein.

[0141] In addition, in the semiconductor device 103, N + The first combination structure of the buried diffusion layer 22 and the N-type diffusion layer 31b can easily meet the above-mentioned diffusion region depth requirements and can be formed by N + The second combination structure of the buried diffusion layer 23 and the N-type diffusion layer 32 b can easily meet the above-mentioned diffusion region depth requirement.

[0142] Furthermore, since the separation trench 72 of the third type semiconductor device 103 of the first embodiment satisfies the above-mentioned trench depth requirement, the separation trench 72 can be formed to a shallow depth, thereby reducing the process load when forming the separation trench 72 accordingly.

[0143] In the semiconductor device 103, the sidewall portion of the isolation trench 72 does not contact the N + The buried diffusion layer 22 and N + Any contact in the buried diffusion layer 23, N + The buried diffusion layer 22 and N+ The discrete distance between the buried diffusion layers 23 is set to be long. Therefore, the semiconductor device 103 can further improve the N + The buried diffusion layer 22 and N + The degree of electrical isolation between the buried diffusion layers 23.

[0144] <Implementation method 2>

[0145] (First method)

[0146] Figure 6 It is a cross-sectional view schematically showing the cross-sectional structure of the semiconductor device 104 according to the first mode of the second embodiment. Figure 6 Shown with Figure 1 The cross-sectional structure is equivalent to the AA cross-sectional structure of FIG. In addition, the top view structure and circuit structure of the semiconductor device 104 are similar to those of FIG. Figure 1 and Figure 2 The structure is the same as the structure shown.

[0147] The following is about Figure 3 The same reference numerals are used for the common parts of the semiconductor device 101 according to the first embodiment of the present invention, and the description thereof is appropriately omitted. The description will focus on the characteristic parts of the semiconductor device 104 according to the first embodiment of the present invention.

[0148] The semiconductor device 104 is characterized in that, in addition to the structure of the semiconductor device 101, it further includes a P-type diffusion layer 110, which is provided in the substrate region of the P-type substrate 10 and around the deepest portion of the separation trench 70 so as to contact the deepest portion of the separation trench 70. The P-type diffusion layer 110 forms a trench bottom diffusion region. Figure 6 In the structure shown, the upper surface of the P-type diffusion layer 110 is located higher than the lower surfaces of the N-type diffusion layers 31 a and 32 a , and the P-type diffusion layer 110 and the N-type diffusion layers 31 a and 32 a are also in contact with each other.

[0149] The P-type impurity concentration in the P-type diffusion layer 110 is set higher than the P-type impurity concentration in the substrate region of the P-type substrate 10 .

[0150] In the process of forming the separation trench 70, after forming an empty trench for the separation trench 70 by trench etching, a process of manufacturing the P-type diffusion layer 110 is performed before forming the buried insulating film 78 in the separation trench 70. The P-type diffusion layer 110 is formed by ion implantation and diffusion of P-type impurities from above the P-type substrate 10 through the empty separation trench 70.

[0151] The semiconductor device 104 according to the first embodiment of the second embodiment has the same effects as those of the semiconductor device 101 according to the first embodiment of the first embodiment, and further has the following inherent effects.

[0152] The semiconductor device 104 of the first aspect of the second embodiment includes the P-type diffusion layer 110 as the trench bottom diffusion region, and thus can suppress leakage current generated by the parasitic bipolar transistor through the P-type substrate region in the P-type substrate 10 .

[0153] The parasitic bipolar transistor in the semiconductor device 101 of the first embodiment of the first embodiment is a parasitic NPN bipolar transistor formed by the N-type diffusion layer 31a, the P-type substrate region in the P-type substrate 10, and the N-type diffusion layer 32a. That is, the parasitic action considered in the semiconductor device 101 can be considered to be the action of the above-mentioned parasitic NPN bipolar transistor. On the other hand, in the semiconductor device 104 of the first embodiment of the second embodiment, the P-type diffusion layer 110 is provided in the base region of the parasitic NPN bipolar transistor.

[0154] In this way, the semiconductor device 104 can reduce the current amplification factor hFE of the NPN bipolar transistor through the P-type substrate region in the P-type substrate 10 by setting a P-type diffusion layer 110 with a higher P-type impurity concentration at the bottom of the separation trench 70, thereby suppressing the leakage current between the first high-side circuit region RH1 and the second high-side circuit region RH2 generated by the operation of the parasitic NPN bipolar transistor.

[0155] (Second method)

[0156] Figure 7 FIG. 1 is a cross-sectional view schematically showing a cross-sectional structure of a semiconductor device 105 according to a second mode of the second embodiment. Figure 7 Shown with Figure 1 The cross-sectional structure is equivalent to the AA cross-sectional structure of FIG. In addition, the top view structure and circuit structure of the semiconductor device 105 are similar to those of FIG. Figure 1 and Figure 2 The structure is the same as the structure shown.

[0157] The following is about Figure 4 Components common to the semiconductor device 102 according to the second embodiment of the first embodiment are denoted by the same reference numerals and description thereof is appropriately omitted, and description will focus on characteristic components of the semiconductor device 105 according to the second embodiment of the second embodiment.

[0158] The semiconductor device 105 is characterized in that, in addition to the structure of the semiconductor device 102, it further includes a P-type diffusion layer 111, which is provided in the substrate region of the P-type substrate 10 and around the deepest portion of the separation trench 71 so as to contact the deepest portion of the separation trench 71. The P-type diffusion layer 111 becomes a trench bottom diffusion region. Figure 7 In the structure shown, the upper surface of the P-type diffusion layer 111 is located at a lower surface than the N-type diffusion layer 111. + The lower surfaces of the buried diffusion layers 20 and 21 are high, and the P-type diffusion layer 111 and the N + The buried diffusion layers 20 and 21 also have a contact relationship.

[0159] The P-type impurity concentration in the P-type diffusion layer 111 is set higher than the P-type impurity concentration in the substrate region of the P-type substrate 10 .

[0160] In the process of forming the separation trench 71, after forming an empty trench for the separation trench 71 by trench etching, a process of manufacturing the P-type diffusion layer 111 is performed before forming the buried insulating film 78 in the separation trench 71. The P-type diffusion layer 111 is formed by ion implantation and diffusion of P-type impurities from above the P-type substrate 10 through the empty separation trench 71.

[0161] As another manufacturing process of the P-type diffusion layer 111, when the first manufacturing method is used when manufacturing the semiconductor device 102, it can be considered to selectively form the P-type diffusion layer 111 as a buried diffusion layer on the upper layer of the P-type substrate 10 before forming the temporary N-type epitaxial layer.

[0162] The semiconductor device 105 according to the second embodiment of the second embodiment has the same effects as the semiconductor device 102 according to the second embodiment of the first embodiment, and further has the following inherent effects.

[0163] The semiconductor device 105 of the second embodiment of the second embodiment has a P-type diffusion layer 111 as a trench bottom diffusion region. Therefore, similar to the first embodiment of the second embodiment, it is possible to suppress leakage current generated by the parasitic bipolar transistor through the P-type substrate region in the P-type substrate 10.

[0164] The parasitic bipolar transistor in the semiconductor device 102 of the second embodiment of the first embodiment is composed of N + The buried diffusion layer 20, the P-type substrate region of the P-type substrate 10, and the N +The parasitic NPN bipolar transistor is formed by the buried diffusion layer 21. That is, the parasitic action considered in the semiconductor device 102 can be considered to be the action of the above-mentioned parasitic NPN bipolar transistor. On the other hand, in the semiconductor device 105 of the second mode of the second embodiment, a P-type diffusion layer 111 is provided in the base region of the parasitic NPN bipolar transistor.

[0165] (Third Method)

[0166] Figure 8 FIG. 1 is a cross-sectional view schematically showing a cross-sectional structure of a semiconductor device 106 according to a third aspect of the second embodiment. Figure 8 Shown with Figure 1 The cross-sectional structure is equivalent to the AA cross-sectional structure of FIG. In addition, the top view structure and circuit structure of the semiconductor device 106 are similar to those of FIG. Figure 1 and Figure 2 The structure is the same as the structure shown.

[0167] The following is about Figure 5 Components common to the semiconductor device 103 of the third embodiment of the first embodiment are denoted by the same reference numerals and description thereof is appropriately omitted, and description will focus on characteristic components of the semiconductor device 106 of the third embodiment of the second embodiment.

[0168] The semiconductor device 106 is characterized in that, in addition to the structure of the semiconductor device 103, it further includes a P-type diffusion layer 112, which is provided in the substrate region of the P-type substrate 10 and around the deepest portion of the separation trench 72 so as to be in contact with the deepest portion of the separation trench 72. The P-type diffusion layer 112 serves as a trench bottom diffusion region.

[0169] exist Figure 8 In the structure shown, the P-type diffusion layer 112 is also in contact with the N-type diffusion layers 31b and 32b. + The buried diffusion layer 22 and N + The diffusion layers 23 are buried in the substrate region of the P-type substrate 10 .

[0170] The P-type impurity concentration in the P-type diffusion layer 112 is set higher than the P-type impurity concentration in the substrate region of the P-type substrate 10 .

[0171] In the process of forming the separation trench 72, after forming an empty trench for the separation trench 72 by trench etching, a process of manufacturing the P-type diffusion layer 112 is performed before forming the buried insulating film 78 in the separation trench 72. The P-type diffusion layer 112 is formed by ion implantation and diffusion of P-type impurities from above the P-type substrate 10 through the empty separation trench 72.

[0172] As another manufacturing process of the P-type diffusion layer 112, when the first method of forming a temporary N-type epitaxial layer in an intermediate stage is adopted when manufacturing the semiconductor device 103, it can be considered to selectively form a P-type diffusion layer 112 as a buried diffusion layer on the upper portion of the P-type substrate 10 before forming the temporary N-type epitaxial layer.

[0173] The semiconductor device 106 of the third aspect according to the second embodiment has the same effects as those of the semiconductor device 103 of the third aspect according to the first embodiment, and further has the following inherent effects.

[0174] Since the semiconductor device 106 of the third mode of embodiment 2 has a P-type diffusion layer 112 as a trench bottom diffusion region, it can suppress the leakage current generated by the parasitic bipolar transistor through the P-type substrate region in the P-type substrate 10 in the same way as the first and second modes of embodiment 2.

[0175] The parasitic bipolar transistor in the semiconductor device 103 of the third aspect of the first embodiment is composed of N + The buried diffusion layer 22, the P-type substrate region in the P-type substrate 10, and the N + The parasitic NPN bipolar transistor is formed by burying the diffusion layer 23. That is, the parasitic action considered in the semiconductor device 103 can be considered to be the action of the parasitic NPN bipolar transistor. On the other hand, in the semiconductor device 106 of the third embodiment of the second embodiment, a P-type diffusion layer 112 is provided in the base region of the parasitic NPN bipolar transistor.

[0176] <Implementation method 3>

[0177] (First method)

[0178] Fig. 9 It is a cross-sectional view schematically showing the cross-sectional structure of the semiconductor device 107 according to the first mode of the third embodiment. Fig. 9 Shown with Figure 1 The cross-sectional structure is equivalent to the AA cross-sectional structure of FIG. In addition, the top view structure and circuit structure of the semiconductor device 107 are similar to those of FIG. Figure 1 and Figure 2 The structure is the same as the structure shown.

[0179] The following is about Figure 3 Components common to the semiconductor device 101 according to the first embodiment of the present invention are denoted by the same reference numerals and description thereof is appropriately omitted, and description will focus on characteristic components of the semiconductor device 107 according to the first embodiment of the present invention.

[0180] In the semiconductor device 107 , a P-type layer 11 is provided instead of the isolation trench 70 of the semiconductor device 101 , an N-type diffusion layer 33 a is provided instead of the N-type diffusion layer 31 a , and an N-type diffusion layer 34 a is provided instead of the N-type diffusion layer 32 a .

[0181] The semiconductor device 107 of the first mode of the third embodiment has a P-type layer 11 serving as a second isolation diffusion region as the isolation region 7. The P-type layer 11 is provided between the N-type diffusion layer 33a serving as the first circuit diffusion region and the N-type diffusion layer 34a serving as the second circuit diffusion region so as to be in contact with the N-type diffusion layer 33a and the N-type diffusion layer 34a, respectively.

[0182] The first method and the second method for forming the P-type layer 11 are described below. The first method is a method for selectively forming the N-type diffusion layers 33a and 34a on the upper layer of the P-type substrate 10. The remaining area on the surface of the P-type substrate 10 where the N-type diffusion layers 33a and 34a are not formed becomes the P-type layer 11.

[0183] The second method is a method of forming a P-type layer 11 having a higher P-type impurity concentration than the substrate region of the P-type substrate 10 on the upper layer portion of the P-type substrate 10 by ion implantation and diffusion processing.

[0184] When the second manufacturing method is adopted, the N-type diffusion layers 33 a and 34 a can be manufactured by the same manufacturing method as that of the N-type diffusion layers 31 a and 32 a .

[0185] In addition, similarly to the N-type diffusion layers 31a and 31b, N-type diffusion layers are selectively provided in the surface of the N-type diffusion layer 33a. + Diffusion layer 53, P + Diffusion layers 62 and 63. In addition, similarly to the N-type diffusion layers 32a and 32b, N-type diffusion layers 34a are selectively provided on the surface of the N-type diffusion layer 34a. + Diffusion layer 54, P + Diffusion layers 64 and 65. After the N-type diffusion layer 30a is formed, the thermal oxide film 84 provided on the P-type layer 11 is formed simultaneously with the thermal oxide film 81.

[0186] The semiconductor device 107 according to the first embodiment of the third embodiment has the same effects as those of the semiconductor device 101 according to the first embodiment of the first embodiment, and further has the following inherent effects.

[0187] The semiconductor device 107 has a P-type layer 11 which is a second isolation diffusion region provided between an N-type diffusion layer 33a serving as a first circuit diffusion region and an N-type diffusion layer 34a serving as a second circuit diffusion region and in contact with the N-type diffusion layer 33a and the N-type diffusion layer 34a, respectively.

[0188] The semiconductor device 107 of the first mode of the third embodiment includes the P-type layer 11 as the second isolation diffusion region in the isolation region 7 , thereby being able to electrically isolate the first high-side circuit region RH1 from the second high-side circuit region RH2 with a relatively simple structure.

[0189] Since the P-type layer 11 is electrically connected to the P-type substrate region of the P-type substrate 10, its potential is the ground potential GND. Since the N-type diffusion layers 33a and 34a receiving the high-side power supply voltages VB1 and VB2 become high voltages above 100V, the PN junctions between the N-type diffusion layers 33a and 34a and the P-type substrate 10 and the P-type layer 12 are set to a reverse bias state.

[0190] Therefore, the first high side circuit region RH1 and the second high side circuit region RH2 are electrically separated from each other by the reverse bias of the PN junction.

[0191] The formation of the P-type layer 11 can be achieved without adding a step in the WP (Wafer Process) process, or by adding a few steps such as photolithography, ion implantation, and subsequent diffusion processing. That is, the formation step of the P-type layer 11 can reduce the process load compared to the formation step of the separation trenches 70 to 72 described in the first and second embodiments.

[0192] (Second method)

[0193] Fig.10 It is a cross-sectional view schematically showing a cross-sectional structure of a semiconductor device 108 according to a second mode of the third embodiment. Fig.10 Shown with Figure 1 The cross-sectional structure is equivalent to the AA cross-sectional structure of FIG. In addition, the top view structure and circuit structure of the semiconductor device 108 are similar to those of FIG. Figure 1 and Figure 2 The structure is the same as the structure shown.

[0194] The following is about Figure 5 The same reference numerals are used for the common parts of the semiconductor device 103 according to the third embodiment of the first embodiment, and the description thereof is appropriately omitted. The description will focus on the characteristic parts of the semiconductor device 108 according to the second embodiment of the third embodiment.

[0195] The semiconductor device 108 is provided with a P-type layer 12 instead of the isolation trench 72 of the semiconductor device 103, an N-type diffusion layer 33b is provided instead of the N-type diffusion layer 31b, and an N-type diffusion layer 34b is provided instead of the N-type diffusion layer 32b. Therefore, the N-type diffusion layer 33b becomes the first surface diffusion layer, and the N-type diffusion layer 34b becomes the second surface diffusion layer.

[0196] The semiconductor device 108 of the second mode of the third embodiment has a P-type layer 12 as the second isolation diffusion region as the isolation region 7. The P-type layer 12 is provided between the N-type diffusion layer 33b and the N-type diffusion region as the first circuit diffusion region. + The first combined structure of the buried diffusion layer 22 and the N-type diffusion layer 34b and N-type diffusion layer 34b that form the second circuit diffusion region + The second combination structure of the buried diffusion layer 23. The P-type layer 12 and the N-type diffusion layers 33b and 34b and the N + The buried diffusion layers 22 and 23 are in contact with each other and function as a second isolation diffusion region.

[0197] In addition, similarly to the N-type diffusion layers 31a, 31b, and 33a, N-type diffusion layers 33b are selectively provided on the surface thereof. + Diffusion layer 53, P + Diffusion layers 62 and 63. In addition, similarly to the N-type diffusion layers 32a, 32b, and 34a, N-type diffusion layers 34b are selectively provided on the surface of the N-type diffusion layer. + Diffusion layer 54, P + Diffusion layers 64 and 65.

[0198] The following describes the first and second methods for forming the P-type layer 12. The first method is a method of forming a temporary N-type epitaxial layer on the P-type substrate 10 and then forming the P-type layer 12 by ion implantation and diffusion from the temporary N-type epitaxial layer into the substrate region of the P-type substrate 10.

[0199] The second method is to form a temporary P-type epitaxial layer on the P-type substrate 10, and form a P-type layer 12 in the temporary P-type epitaxial layer as a residual region after forming the N-type diffusion layers 33b and 34b. In this case, it is necessary to set the P-type impurity concentration of the temporary P-type epitaxial layer to a concentration that is the same as or higher than the P-type impurity concentration of the substrate region of the P-type substrate 10.

[0200] The N-type diffusion layers 33 b and 34 b can be manufactured in the same manner as the N-type diffusion layers 31 b and 32 b of the semiconductor device 103 .

[0201] The semiconductor device 108 according to the second aspect of the third embodiment has the same effects as the semiconductor device 103 according to the third aspect of the first embodiment, and further has the following inherent effects.

[0202] The semiconductor device 108 has an N-type diffusion layer 33b and an N-type diffusion layer 33b that become a first circuit diffusion region. + The first combined structure of the buried diffusion layer 22 and the N-type diffusion layer 34b and N-type diffusion layer 34b that form the second circuit diffusion region +The second combined structure of the buried diffusion layer 23 has a P-type layer 12 between them. The P-type layer 12 and the N-type diffusion layers 33b and 34b and the N + The buried diffusion layers 22 and 23 are in contact with each other.

[0203] The semiconductor device 108 of the second mode of the third embodiment includes the P-type layer 12 as the second isolation diffusion region in the isolation region 7 , thereby being able to electrically isolate the first high-side circuit region RH1 from the second high-side circuit region RH2 with a relatively simple structure.

[0204] Since the P-type layer 12 is electrically connected to the P-type substrate region in the P-type substrate 10, its potential is the ground potential GND. The N-type diffusion layers 33b and 34b receiving the high-side power supply voltages VB1 and VB2 become a high voltage of more than 100V, so the PN junctions of the N-type diffusion layers 33b and 34b and the P-type substrate 10 and the P-type layer 12 are set to a reverse bias state.

[0205] Therefore, the first high side circuit region RH1 and the second high side circuit region RH2 are electrically separated from each other by the reverse bias of the PN junction.

[0206] Similar to the P-type layer 11, the formation of the P-type layer 12 can be achieved without adding a step to the WP process, or can be achieved by adding a few steps such as photolithography, ion implantation, and subsequent diffusion processing. That is, the formation step of the P-type layer 12 can reduce the process load compared to the formation step of the separation trenches 70 to 72 described in the first and second embodiments.

[0207] <Implementation method 4>

[0208] (First method)

[0209] Fig.11 It is a cross-sectional view schematically showing the cross-sectional structure of a semiconductor device 201 according to the first mode of the fourth embodiment. Fig.11 Shown with Figure 1 The cross-sectional structure is equivalent to the AA cross-sectional structure of FIG. 201. In addition, the top view structure and circuit structure of the semiconductor device 201 are similar to those of FIG. Figure 1 and Figure 2 The structure is the same as the structure shown.

[0210] The following is about Figure 3 The same reference numerals are used for the common parts of the semiconductor device 101 according to the first embodiment of the present invention, and the description thereof is appropriately omitted. The description will focus on the characteristic parts of the semiconductor device 201 according to the first embodiment of the present invention.

[0211] In the semiconductor device 201, an SOI substrate 9, which is generally called an SOI wafer, is used as a semiconductor substrate instead of the P-type substrate 10 of the semiconductor device 101. The SOI substrate 9 is composed of a stacked structure of a support substrate 10a, a buried oxide film 120, and an SOI layer 130, and the top layer of the SOI substrate 9 is the SOI layer 130. Fig.11 In the embodiment, the conductivity type of the support substrate 10a is set to P type, but it may be N type. The SOI layer 130 as a silicon active layer is composed of N type, for example.

[0212] like Fig.11 As shown, a first high-side circuit region RH1 and a second high-side circuit region RH2 are provided in the SOI layer 130. Fig.11 As shown in FIG. 1 , as a first separation region for separating the high-side circuit region RH from the low-side circuit region RL, an N-type diffusion layer 30c and a P-type diffusion layer 40 are provided in the SOI layer 130. The P-type diffusion layer 40 is provided so as to surround the high-side circuit region RH when viewed from above. The N-type diffusion layer 30c satisfies the surface electric field reduction condition. In addition, the N-type diffusion layer 30c is provided with an N-type diffusion layer in the surface similarly to the N-type diffusion layer 30a. + Diffusion layer 50.

[0213] An N-type diffusion layer 31 c is provided in the first high-side circuit region RH1 and in the SOI layer 130 , and an N-type diffusion layer 32 c is provided in the second high-side circuit region RH2 and in the SOI layer 130 .

[0214] The N-type diffusion layer 31c and the N-type diffusion layer 32c are formed at the same time. The N-type diffusion layer 30c becomes the first isolation diffusion region, the N-type diffusion layer 31c becomes the first circuit diffusion region, and the N-type diffusion layer 32c becomes the second circuit diffusion region.

[0215] and Figure 4 Similar to the N-type diffusion layer 31b and the P-type diffusion layer 41b of the semiconductor device 102 shown in FIG. 1 , components of the first high-side circuit CH1 are provided on the upper layer of each of the N-type diffusion layer 31c and the P-type diffusion layer 41c. Figure 4 Similar to the N-type diffusion layer 32 b and the P-type diffusion layer 42 b of the semiconductor device 102 shown, components of the second high-side circuit CH2 are provided on the upper layer portions of the N-type diffusion layer 32 c and the P-type diffusion layer 42 c .

[0216] In the SOI substrate 9 serving as the semiconductor substrate of the fourth embodiment, the region where the first high-side circuit CH1 and the second high-side circuit CH2 are not provided becomes the circuit base region. The first high-side circuit CH1 is provided in the N-type diffusion layer 31c, in the P-type diffusion layer 41c, on the N-type diffusion layer 31c, and on the P-type diffusion layer 41c. The second high-side circuit CH2 is provided in the N-type diffusion layer 32c, in the P-type diffusion layer 42c, on the N-type diffusion layer 32c, and on the P-type diffusion layer 42c.

[0217] In the semiconductor device 201, the support substrate 10a and the buried oxide film 120 form a circuit base region. The P-type diffusion layer 40, the N-type diffusion layer 30c, the N-type diffusion layer 31c, the N-type diffusion layer 32c, the P-type diffusion layer 41c, and the P-type diffusion layer 42c are provided in the SOI layer 130, but are not provided in the support substrate 10a and the buried oxide film 120. Therefore, the support substrate 10a and the buried oxide film 120 form a circuit base region.

[0218] In addition, when the conductivity type of the SOI layer 130 as the silicon active layer is N-type, the remaining area after forming the P-type diffusion layer 40, the P-type diffusion layer 41c and the P-type diffusion layer 42c in the SOI layer 130 can also be set as the N-type diffusion layer 30c, the N-type diffusion layer 31c and the N-type diffusion layer 32c.

[0219] In addition, similarly to the N-type diffusion layers 31a, 31b, 33a, and 33b, N-type diffusion layers 31c are selectively provided on the surface of the N-type diffusion layer 31c. + Diffusion layer 53, P + Diffusion layers 62 and 63. In addition, similar to the N-type diffusion layers 32a, 32b, 34a, and 34b, N-type diffusion layers 32c are selectively provided on the surface of the N-type diffusion layer. + Diffusion layer 54, P + Diffusion layers 64 and 65.

[0220] In addition, similarly to the P-type diffusion layers 41a and 41b, P-type diffusion layers 41c are selectively provided on the surface of the P-type diffusion layer 41c. + Diffusion layer 61, N + Diffusion layers 51 and 52. In addition, similarly to the P-type diffusion layers 42a and 42b, P-type diffusion layers 42c are selectively provided on the surface of the P-type diffusion layer. + Diffusion layer 66, N + Diffusion layers 55 and 56.

[0221] In the semiconductor device 201, a separation trench 73 is provided in the separation region 7. The separation trench 73 is provided between the N-type diffusion layer 31c serving as the first circuit diffusion region and the N-type diffusion layer 32c serving as the second circuit diffusion region, and is provided so that the deepest portion reaches the upper surface of the buried oxide film 120.

[0222] The N-type diffusion layer 31c and the N-type diffusion layer 32c are electrically separated by the separation trench 73. The separation trench 73 is formed, for example, as follows.

[0223] After forming a temporary N-type diffusion layer in the SOI layer 130 in the region including the first high-side circuit region RH1, the second high-side circuit region RH2, and the separation region 7, a separation trench 73 is formed in the separation region 7 so as to reach the upper surface of the buried oxide film 120 from the surface of the SOI layer 130 including the temporary N-type diffusion layer. The temporary N-type diffusion layer is separated between the first high-side circuit region RH1 and the second high-side circuit region RH2 by the separation trench 73.

[0224] As a result, the temporary N-type diffusion layer remaining in the first high-side circuit region RH1 becomes the N-type diffusion layer 31 c , and the temporary N-type diffusion layer remaining in the second high-side circuit region RH2 becomes the N-type diffusion layer 32 c . Therefore, the N-type diffusion layer 31 c and the N-type diffusion layer 32 c are electrically separated by the separation trench 73 .

[0225] The isolation trench 73 has a buried insulating film 78 inside, similarly to the isolation trenches 70 to 72 in the first and second embodiments.

[0226] (Effect)

[0227] The semiconductor device 201 according to the first embodiment of the fourth embodiment has the same effects as those of the semiconductor device 101 according to the first embodiment of the first embodiment, and further has the following inherent effects.

[0228] The semiconductor device 201 of the first mode of the fourth embodiment is separated into the SOI layer 130 and the support substrate 10a in the depth direction by the buried oxide film 120 as a dielectric, so that the leakage current between the first high side circuit region RH1 and the second high side circuit region RH2 can be further reduced.

[0229] Furthermore, the semiconductor device 201 can suppress parasitic operation between the first high side circuit region RH1 and the second high side circuit region RH2 by providing the isolation trench 73 penetrating the SOI layer 130 and having the insulating film 78 buried therein.

[0230] (Second method)

[0231] Fig.12It is a cross-sectional view schematically showing the cross-sectional structure of a semiconductor device 202 according to the second mode of the fourth embodiment. Fig.12 Shown with Figure 1 In addition, the top view structure and circuit structure of the semiconductor device 202 are similar to those of the AA section. Figure 1 and Figure 2 The structure is the same as the structure shown.

[0232] The following is about Fig.11 Components common to the semiconductor device 201 of the first embodiment of the fourth embodiment are denoted by the same reference numerals and description thereof is appropriately omitted, and description will focus on characteristic components of the semiconductor device 202 of the second embodiment of the fourth embodiment.

[0233] The semiconductor device 202 has a P-type layer 13 instead of the isolation trench 73 of the semiconductor device 201 , an N-type diffusion layer 33 c instead of the N-type diffusion layer 31 c , and an N-type diffusion layer 34 c instead of the N-type diffusion layer 32 c .

[0234] In addition, similarly to the N-type diffusion layers 31a to 31c, 33a, and 33b, N-type diffusion layers 33c are selectively provided on the surface thereof. + Diffusion layer 53, P + Diffusion layers 62 and 63. In addition, similar to the N-type diffusion layers 32a to 32c, 34a and 34b, N-type diffusion layers 34c are selectively provided on the surface of the N-type diffusion layer. + Diffusion layer 54, P + Diffusion layers 64 and 65.

[0235] Thus, the semiconductor device 202 of the second mode of the fourth embodiment is provided with the P-type layer 13 which becomes the second isolation diffusion region as the isolation region 7. The P-type layer 13 is provided between the N-type diffusion layer 33c which becomes the first circuit diffusion region and the N-type diffusion layer 34c which becomes the second circuit diffusion region so as to be in contact with the N-type diffusion layers 33c and 34c. The P-type layer 13 functions as the second isolation diffusion region.

[0236] The following describes a method for manufacturing the P-type layer 13. For example, the P-type layer 13 is formed in the N-type SOI layer 130 by ion implantation and diffusion of P-type impurities. In this case, the P-type layer 13 needs to be provided in a manner that penetrates the SOI layer 130 and reaches the upper surface of the buried oxide film 120.

[0237] The semiconductor device 202 according to the second embodiment of the fourth embodiment has the same effects as the semiconductor device 101 according to the first embodiment of the first embodiment, and further has the following effects.

[0238] The semiconductor device 202 of the second mode of the fourth embodiment is separated into the SOI layer 130 and the support substrate 10a in the depth direction by the buried oxide film 120 as a dielectric, so that the leakage current between the first high side circuit region RH1 and the second high side circuit region RH2 can be further reduced.

[0239] The semiconductor device 202 has a P-type layer 13 as a second isolation diffusion region between the N-type diffusion layer 33c as the first circuit diffusion region and the N-type diffusion layer 34c as the second circuit diffusion region. The P-type layer 13 is provided in contact with the N-type diffusion layers 33c and 34a.

[0240] Therefore, the semiconductor device 202 of the second mode of embodiment 4 has a P-type layer 13 as a second separation diffusion region in the separation region 7, so that the first high-side circuit region RH1 and the second high-side circuit region RH2 can be electrically separated by a relatively simple structure, similar to the semiconductor devices 107 and 108 of embodiment 3.

[0241] <Other>

[0242] In the present disclosure, the P type is shown as the first conductivity type and the N type is shown as the second conductivity type, but a modified example in which the first conductivity type is the N type and the second conductivity type is the P type is also conceivable.

[0243] In addition, the present disclosure can freely combine the various embodiments within the scope of the disclosure, or can appropriately modify or omit the various embodiments.

Claims

1. A semiconductor device, wherein: have: Semiconductor substrates; A low-side circuit region, disposed on the semiconductor substrate, receiving a first reference potential; a high-side circuit region, disposed on the semiconductor substrate, receiving a second reference potential different from the first reference potential; as well as a first separation region, electrically separating the low-side circuit region from the high-side circuit region, The semiconductor substrate has a circuit base region where the low-side circuit region and the high-side circuit region are not provided. The high-side circuit region includes a first high-side circuit region and a second high-side circuit region, a first high-side circuit is provided in the first high-side circuit region, and a second high-side circuit is provided in the second high-side circuit region, the first high-side circuit operates at a first power supply voltage based on the second reference potential, and the second high-side circuit operates at a second power supply voltage based on the second reference potential, and the first power supply voltage and the second power supply voltage are different voltage values, The semiconductor device further includes a second isolation region that electrically isolates the first high-side circuit region from the second high-side circuit region.

2. The semiconductor device according to claim 1, wherein The circuit substrate region includes a substrate region of a first conductivity type, The first separation region includes a first separation diffusion region of the second conductivity type, and the first separation diffusion region is disposed on the substrate region. The first high-side circuit region includes a first circuit diffusion region of a second conductivity type, and the first circuit diffusion region is disposed on the substrate region. The second high-side circuit region includes a second circuit diffusion region of a second conductivity type, and the second circuit diffusion region is disposed on the substrate region. The first circuit diffusion region and the second circuit diffusion region satisfy a diffusion region depth requirement, wherein the first circuit diffusion region and the second circuit diffusion region are each formed to a depth deeper than a depth of the first isolation diffusion region.

3. The semiconductor device according to claim 2, wherein: The second separation region includes a separation trench, the separation trench is provided between the first circuit diffusion region and the second circuit diffusion region, and the deepest part of the separation trench reaches the substrate region. The isolation trench has an embedded insulating film therein for insulating and isolating the first high-side circuit region from the second high-side circuit region.

4. The semiconductor device according to claim 3, wherein: The first circuit diffusion region includes a second conductivity type first buried diffusion layer selectively provided on the substrate region, and a second conductivity type first surface diffusion layer selectively provided on the first buried diffusion layer. The second circuit diffusion region includes a second conductive type second buried diffusion layer selectively provided on the substrate region, and a second conductive type second surface diffusion layer selectively provided on the second buried diffusion layer.

5. The semiconductor device according to claim 4, wherein: The separation trench has no contact relationship with the first buried diffusion layer and the second buried diffusion layer. The separation trench satisfies a trench depth requirement, which is a requirement that a formation depth of the separation trench is shallower than a formation depth of each of the first buried diffusion layer and the second buried diffusion layer.

6. The semiconductor device according to any one of claims 3 to 5, wherein: A trench bottom diffusion region of the first conductivity type provided in the substrate region and around the deepest portion of the trench for isolation and in contact with the deepest portion of the trench for isolation is further provided.

7. The semiconductor device according to claim 2, wherein: The second isolation region includes a first conductivity type second isolation diffusion region provided between the first circuit diffusion region and the second circuit diffusion region and in contact with the first circuit diffusion region and the second circuit diffusion region.

8. The semiconductor device according to claim 1, wherein The semiconductor substrate includes an SOI substrate having a stacked structure including a support substrate, a buried oxide film, and an SOI layer. The circuit base region includes the support substrate and the buried oxide film, The low-side circuit region, the high-side circuit region, and the second separation region are disposed within the SOI layer.

9. The semiconductor device according to claim 8, wherein: The second separation region includes a separation trench, the separation trench is provided between the first high-side circuit region and the second high-side circuit region, and the deepest part of the separation trench reaches the buried oxide film. The isolation trench has an embedded insulating film therein for insulating and isolating the first high-side circuit region from the second high-side circuit region.

10. The semiconductor device according to claim 8, wherein The first high-side circuit region includes a first circuit diffusion region of a second conductivity type, and the first circuit diffusion region is provided in the SOI layer. The second high-side circuit region includes a second circuit diffusion region of a second conductivity type, and the second circuit diffusion region is provided in the SOI layer. The second isolation region includes a first conductivity type second isolation diffusion region provided between the first circuit diffusion region and the second circuit diffusion region and in contact with the first circuit diffusion region and the second circuit diffusion region.

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