Semiconductor device structure

Abstract

The invention discloses a semiconductor device structure. The semiconductor device structure includes a silicon substrate, a transistor, and an interconnect structure. The silicon substrate has a silicon surface. The transistor includes a gate structure, a first conduction region, a second conduction region, and a channel underlying the silicon surface. The interconnect structure extends out of the transistor and is coupled to a first conduction region of the transistor. The interconnect structure is disposed below the silicon surface and isolated from the silicon substrate by an isolation region. Compared with the prior art, since the well isolated interconnection structure / wire is introduced below the silicon surface, the interconnection structure / wire can be connected with the transistor at the bottom of the transistor in the silicon substrate in addition to only using the interconnection structure above the silicon surface, so that the transistor can be connected with the interconnection structure / wire at the bottom of the transistor in the silicon substrate. Therefore, the size of the transistor is effectively reduced, and the performance of the transistor is improved.

Description

[0001] The filing date of the original application is December 31, 2020, the application number is 202011633590.3, and the name of the invention is "Semiconductor device structure". Technical Field

[0002] The present invention relates to a semiconductor device structure, and more particularly to a semiconductor device structure in which an underground interconnection structure can be embedded in a silicon substrate and the underground interconnection structure has high conductivity and effectively and optimally isolates the silicon substrate. Background Art

[0003] In the most advanced integrated circuits available today, the integrated circuits are connected to multiple transistors through conductive interconnect structures (e.g., metal wires, polysilicon wires, etc.) to facilitate signal transmission between the gates, sources, and drains of the multiple transistors. The metal wires are connected to the gates, sources, and drains of the multiple transistors by means of a number of contact holes and connecting pins, respectively, which poses great challenges and difficulties to the chip design goals of reducing area, power consumption, and noise, and improving the performance of the integrated circuits, especially when the size of the integrated circuits must be significantly reduced on the chip to meet Moore's Law.

[0004] Next, taking the challenges and difficulties caused by the increase in area as an example, compared with the size of the contact hole used to connect the metal line to the source or drain, the source or drain in the multiple transistors must be designed to have a larger diffusion area so that the inevitable lithography misalignment due to the limitation of the lithography tool will not cause the contact hole to be formed outside the lower edge of the source or drain. However, the larger diffusion area will inevitably increase the diffusion area of ​​the multiple transistors and the chip area where the transistors are located, which will derive a larger parasitic capacitance so that the alternating current (AC) performance of the circuit containing the transistors is significantly reduced, causing the circuit of the transistor to consume higher power and have greater noise.

[0005] Therefore, how to introduce a self-aligned contact structure and technology that uses less area to connect a transistor to a first interconnect structure (metal) layer corresponding to the transistor to send and receive signals has become an important issue to further effectively reduce the size of the transistor and improve the performance of the transistor. Summary of the invention

[0006] The present invention discloses a structural invention of a transistor using new technology (including new process integration), wherein the technology realizes embedding a silicon subsurface interconnection structure in a silicon substrate, and the silicon subsurface interconnection structure has high conductivity and effectively optimizes the isolation of the silicon substrate. The silicon subsurface interconnection structure can be vertically (or bridged) connected to the source or drain of the transistor through a compact self-alignment invention, thereby leading to innovations in many component and circuit designs. For example, the silicon subsurface interconnection structure can be vertically connected to many different sources or drains, respectively, and the other ends of the silicon subsurface interconnection structure can be connected to different signal sources, such as a voltage source or a ground source. In addition, the chip architecture can further introduce power supply voltages of different layers or different levels vertically distributed in the silicon substrate, wherein necessary isolation must be embedded under the silicon surface to separate the power supplies of different layers or different levels, and the chip architecture can correspondingly improve the performance of transistors and circuits (such as speed, power and noise, etc.), and reduce the design complexity on the silicon surface (for example, the current complex chip design may need to use the tenth interconnection structure of the ten-layer interconnection structure on the silicon surface as a power supply, but the nine-layer interconnection structure below the tenth interconnection structure is required to transmit signals, wherein the ten-layer interconnection structure is very complex to stack and will occupy a considerable contact area, etc.). Take an example to describe the present invention: different steps are established between the wires below the silicon surface and the wires above the silicon surface, wherein the wires below the silicon surface can be designed to have different depths to allow the wires below the silicon surface to be distributed in the chip to provide various signals (such as the signal of the voltage source or the signal of the ground source) without colliding with each other in the silicon substrate with a considerable or excessive size.

[0007] An embodiment of the present invention discloses a semiconductor device structure. The semiconductor device structure includes a silicon substrate, a transistor, and an interconnection structure. The silicon substrate has a silicon surface. The transistor includes a gate structure, a first conductive region, a second conductive region, and a channel located below the silicon surface. The interconnection structure extends outside the transistor and is coupled to the first conductive region of the transistor. The interconnection structure is disposed below the silicon surface and isolated from the silicon substrate by an isolation region.

[0008] In another embodiment of the present invention, the semiconductor device structure further comprises another transistor and a signal line, wherein the signal line is electrically connected to the another transistor, and wherein the signal line is distributed below the silicon surface and separated from the interconnect structure.

[0009] In another embodiment of the present invention, a distance between the silicon surface and the upper surface of the interconnect structure is different from a distance between the silicon surface and the upper surface of the signal line.

[0010] In another embodiment of the present invention, the semiconductor device structure further comprises another transistor and a power line, wherein the power line is electrically connected to the another transistor, and wherein the power line is distributed below the silicon surface and separated from the interconnect structure.

[0011] In another embodiment of the present invention, the power line is coupled to a voltage source or a ground source.

[0012] Another embodiment of the present invention discloses a semiconductor device structure. The semiconductor device structure includes a silicon substrate, a transistor, and an interconnection structure. The silicon substrate has a silicon surface. The transistor includes a gate structure, a first conductive region, a second conductive region, and a channel located below the silicon surface. The interconnection structure extends outside the transistor and is coupled to the gate structure of the transistor. The interconnection structure includes an upper portion above the silicon surface, and the sidewall of the upper portion of the interconnection structure is aligned with the sidewall of the gate structure.

[0013] In another embodiment of the present invention, the semiconductor device structure further includes a first spacer layer and a second spacer layer, wherein the first spacer layer covers the first side wall of the gate structure and is located above the silicon surface; and the second spacer layer covers the second side wall of the gate structure and is located above the silicon surface.

[0014] In another embodiment of the present invention, the first spacer layer abuts against sidewalls of an upper portion of the interconnect structure.

[0015] In another embodiment of the present invention, the semiconductor device structure further comprises a dielectric layer, wherein the dielectric layer is disposed below the first spacer layer, the second spacer layer and the gate structure.

[0016] In another embodiment of the present invention, at least a portion of the gate structure extends downward from the silicon surface, and at least a portion of the channel is located below and extends along the bottom of the dielectric layer.

[0017] Another embodiment of the present invention discloses a semiconductor device structure. The semiconductor device structure includes a silicon substrate, a transistor, and an interconnection structure. The silicon substrate has a silicon surface. The transistor includes a gate structure, a first conduction region, a second conduction region, and a channel located below the silicon surface. The interconnection structure extends outside the transistor and is electrically connected to the first conduction region of the transistor through a bridge contact. A first sidewall of the bridge contact is aligned with an edge of the first conduction region and a second sidewall of the bridge contact is aligned with an edge of the interconnection structure.

[0018] In another embodiment of the present invention, the bridge contact includes an upper portion and a lower portion, wherein the upper portion of the bridge contact is adjacent to the silicon substrate and the lower portion of the bridge contact is separated from the silicon substrate.

[0019] In another embodiment of the present invention, the semiconductor device structure further includes a first isolation layer, wherein the first isolation layer at least covers the first sidewall, the second sidewall, and the bottom of the lower portion of the bridge contact.

[0020] In another embodiment of the present invention, the first isolation layer further covers a third side wall of the lower portion of the bridge contact, and a second isolation layer further covers a fourth side wall of the lower portion of the bridge contact, wherein the third side wall of the lower portion is parallel to the fourth side wall of the lower portion, and the width of the second isolation layer is different from the width of the first isolation layer.

[0021] In another embodiment of the present invention, the interconnect structure is disposed below the silicon surface, and a lower portion of the bridge contact abuts the interconnect structure.

[0022] Another embodiment of the present invention discloses a semiconductor device structure. The semiconductor device structure includes a silicon substrate, a first transistor, and an interconnection structure. The silicon substrate has a silicon surface. The first transistor includes a gate structure, a first conduction region, a second conduction region, and a channel located below the silicon surface. The interconnection structure is electrically connected to the first conduction region of the first transistor through a bridge contact. The interconnection structure is located below the silicon surface and an isolation cap is disposed on the bridge contact to isolate the bridge contact. The bridge contact includes an upper portion and a lower portion, and at least a first sidewall of the lower portion of the bridge contact is adjacent to an isolation layer, and an edge of the isolation cap is aligned with an edge of the isolation layer.

[0023] In another embodiment of the present invention, the semiconductor device structure further comprises a first spacer layer, wherein the first spacer layer is disposed between the first conduction region and the gate structure of the first transistor, and the isolation cap is in contact with the first conduction region of the first transistor.

[0024] In another embodiment of the present invention, the semiconductor device structure further includes a second transistor, wherein the second transistor is adjacent to the first transistor, the second transistor includes a gate structure, a first conductive region, and a second conductive region, and the first conductive region of the second transistor is in contact with the isolation cap and is electrically connected to the interconnect structure through the bridge contact.

[0025] In another embodiment of the present invention, the semiconductor device structure further includes a third transistor, wherein the third transistor is adjacent to the first transistor, the third transistor includes a gate structure, a first conductive region, and a second conductive region, and the second conductive region of the third transistor is separated from the second conductive region of the first transistor.

[0026] Another embodiment of the present invention discloses a semiconductor device structure. The semiconductor device structure includes a silicon substrate, a trench, and a first spacer and a second spacer. The silicon substrate has a silicon surface. At least a portion of the trench is formed below the silicon surface. The first spacer covers a first side of the trench, and the second spacer covers a second side of the trench. The material of the first spacer is different from the material of the second spacer.

[0027] In another embodiment of the present invention, the first side of the groove is symmetrical to the second side of the groove.

[0028] Another embodiment of the present invention discloses a semiconductor device structure. The semiconductor device structure includes a silicon substrate, a first interconnection structure, and a second interconnection structure. The silicon substrate has a silicon surface. The first interconnection structure is disposed below the silicon surface. The second interconnection structure is disposed below the silicon surface. The depth from the silicon surface to the first interconnection structure is the same as the depth from the silicon surface to the second interconnection structure, and the first interconnection structure and the second interconnection structure are separated.

[0029] In another embodiment of the present invention, the material of the first interconnect structure is the same as the material of the second interconnect structure.

[0030] Another embodiment of the present invention discloses a semiconductor device structure. The semiconductor device structure includes a silicon substrate, a first transistor, a bridge contact, and an interconnection structure. The silicon substrate has a silicon surface. The first transistor includes a gate structure, a first conductive region, a second conductive region, and a channel located below the silicon surface. The bridge contact includes an upper portion and a lower portion, wherein the bridge contact is electrically connected to the first conductive region of the first transistor. The interconnection structure is located below the silicon surface and contacts the lower portion of the bridge contact.

[0031] In another embodiment of the present invention, the first transistor is an n-type metal oxide semiconductor transistor and the first conductive region includes an n+ doped region.

[0032] In another embodiment of the present invention, the first transistor is a p-type metal oxide semiconductor transistor and the first conductive region includes a p+ doped region.

[0033] Another embodiment of the present invention discloses a semiconductor device structure. The semiconductor device structure includes a silicon substrate, an n-type metal oxide semiconductor transistor, a p-type metal oxide semiconductor transistor, a bridge contact, and an interconnection structure. The silicon substrate has a silicon surface. The n-type metal oxide semiconductor transistor includes a gate structure, a first conductive region, and a first channel located below the silicon surface. The p-type metal oxide semiconductor transistor includes a gate structure, a second conductive region, and a second channel located below the silicon surface. The bridge contact includes an upper portion and a lower portion, wherein the bridge contact is electrically connected to the first conductive region of the n-type metal oxide semiconductor transistor and the second conductive region of the p-type metal oxide semiconductor transistor. The interconnection structure is located below the silicon surface and contacts the lower portion of the bridge contact.

[0034] In another embodiment of the present invention, the first conductive region of the n-type metal oxide semiconductor transistor includes an n+ doped region and the second conductive region of the p-type metal oxide semiconductor transistor includes a p+ doped region.

[0035] In another embodiment of the present invention, the material of the bridge contact and the material of the interconnect structure are the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1A The invention is a flowchart of a method for manufacturing a dynamic random access memory storage cell array disclosed in an embodiment of the invention.

[0037] Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G Yes Description Figure 1A Schematic diagram of .

[0038] Figure 2 It is a schematic diagram illustrating a top view and a cross-sectional view along the X direction after depositing a pad nitride layer and a pad oxide layer and forming a shallow trench isolation.

[0039] Figure 3is a schematic diagram illustrating depositing the first nitride layer to form the first nitride spacer, and depositing the STI-first oxide layer and the photoresist layer.

[0040] Figure 4 It is a schematic diagram illustrating that the upper edge first nitride spacer layer is etched away and the photoresist layer does not cover the STI-first oxide layer.

[0041] Figure 5 It is a schematic diagram for explaining the stripping of the photoresist layer and the STI-first oxide layer, and the generation of the first oxide layer.

[0042] Figure 6 is a schematic diagram illustrating depositing the metal layer in the trench and planarizing it by the chemical mechanical planarization technique.

[0043] Figure 7 is a schematic diagram illustrating the deposition of the photoresist layer.

[0044] Figure 8 is a schematic diagram illustrating etching the end of the metal layer corresponding to the active region.

[0045] Fig. 9 is a schematic diagram illustrating that the photoresist layer is removed and the metal layer is etched back to form a bit line under the silicon surface.

[0046] Fig.10 is a schematic diagram illustrating depositing the second oxide layer in the trench.

[0047] Fig.11 is a schematic diagram illustrating depositing the third oxide layer, the second nitride layer, and the photoresist layer, and removing unnecessary portions of the third oxide layer, the second nitride layer, and the photoresist layer.

[0048] Fig.12 is a schematic diagram illustrating etching the pad nitride layer but retaining the pad oxide layer.

[0049] Fig.13 is a schematic diagram illustrating forming the U-shaped groove and forming the high dielectric constant insulating layer as the gate structure of the access transistor.

[0050] Fig.14 is a schematic diagram illustrating depositing the third nitride layer and the fourth oxide layer, and then polishing the third nitride layer and the fourth oxide layer.

[0051] Fig.15 It is a schematic diagram for explaining etching away the second nitride layer and the third oxide layer.

[0052] Fig.16is a schematic diagram illustrating depositing and etching the fourth nitride layer, the fifth oxide layer and the fifth nitride layer by the anisotropic etching technology, and depositing the sixth oxide layer.

[0053] Fig.17 is a schematic diagram illustrating the deposition of the spin-on dielectric material to create the hole.

[0054] Fig.18 is a schematic diagram illustrating depositing the seventh oxide layer in the hole and depositing the spin-on dielectric layer on the seventh oxide layer.

[0055] Fig.19 is a schematic diagram illustrating the removal of the spin-on dielectric layer, the pad oxide layer, and the silicon material to create another hole.

[0056] Fig. 20 It is a schematic diagram illustrating a cross-sectional view along the Y2 direction.

[0057] Fig.21 The figure is a schematic diagram for explaining the removal of the first nitride spacer layer at the lower edge on the other inner sidewall in the other hole.

[0058] Fig. 22 is a schematic diagram illustrating depositing and etching the n+ polysilicon to leave the n+ polysilicon plug in the other hole.

[0059] Fig.23 is a schematic diagram illustrating removing an upper portion of the eighth oxide layer to generate the eighth oxide spacer layer in the another hole.

[0060] Fig.24A 2 is a schematic diagram illustrating the generation of the neck-shaped surrounding conductive n+ polysilicon and the n+ polysilicon plug.

[0061] Fig. 24B is a schematic diagram illustrating another way to implement the vertical connection (bridge) and the W-2 latch.

[0062] Fig.25A is a schematic diagram illustrating thermal growth of the ninth oxide layer on the n+ polysilicon plug.

[0063] Fig.25B is a schematic diagram illustrating the local thermal growth of the ninth oxide layer on the W-2 pin.

[0064] Fig.26 is a schematic diagram illustrating removing the sixth oxide layer and the fifth nitride spacer layer, and then implanting the n-type dopant to generate the drain and source of the access transistor.

[0065] Fig. 27is a schematic diagram illustrating the principle of realizing the silicon subsurface interconnect structure.

[0066] Fig.28 is a schematic diagram illustrating a top view of the dynamic random access memory storage cell array.

[0067] The reference numerals are described as follows:

[0068] 202 p-type substrate

[0069] 204 Pad Oxide Layer

[0070] 206 pad nitride layer

[0071] 208, HSS-1 / 2, HSS-1 / 3 semiconductor surface

[0072] 210 Groove

[0073] 304 STI-first oxide layer

[0074] 306, 702, 1106 photoresist layer

[0075] 502 First Oxide Layer

[0076] 504 First Oxide / STI Layer

[0077] 602 Metal Layer

[0078] 902、UGBL Under-silicon bit line

[0079] 1002, CVD-STI-Oxide2 Second oxide layer

[0080] 1102 Third Oxide Layer

[0081] 1104 Second Nitride Layer

[0082] 1302 U-shaped channel

[0083] 1304 High dielectric constant insulation layer

[0084] 1402 Third nitride layer

[0085] 1404 Fourth Oxide Layer

[0086] 1602 Fourth Nitride Layer

[0087] 1604 Fifth Oxide Layer

[0088] 1606 Fifth Nitride Layer

[0089] 1608 Sixth Oxide Layer

[0090] 1702 Spin-on Dielectric

[0091] 1802 Seventh Oxide Layer

[0092] 1804 Spin-on dielectric layer

[0093] 1902 The Eighth Oxide Layer

[0094] 2202 n+ polysilicon plug

[0095] 2402 n+ polysilicon layer

[0096] 2502 Ninth Oxide Layer

[0097] AQ1, AQ2, AQ3 access transistors

[0098] Drain-1 First drain

[0099] Drain-2 Second drain

[0100] Drain-3 The third drain

[0101] Hole-1 / 2, Hole-1 / 3

[0102] NLDD n-type lightly doped drain

[0103] 2602, 2604 capacitors

[0104] Source-1 First source

[0105] Source-2 Second source

[0106] Source-3 The third source

[0107] STI Shallow Trench Isolation

[0108] Wordline-1 First wordline

[0109] Wordline-2 Second wordline

[0110] Wordline-3 The third wordline

[0111] Steps 10-80, 102-160 DETAILED DESCRIPTION

[0112] In order to illustrate that the present invention is applicable to integrated circuits including logic, digital, analog, memory, etc., the following description takes memory as an example to easily grasp the core technology of the present invention. Nowadays, there are many semiconductor memories using different types of memory cells (for example, dynamic random access memory (DRAM), static random access memory (SRAM), and nonvolatile flash memory including NOR, NAND, three-dimensional (3D) NAND, etc.) that require bit lines and word lines. In addition, the present invention further discloses a new architecture for arranging the bit lines and the word lines, wherein the core technology related to the new architecture is considered to be well applicable to the above-mentioned memory. In addition, in the subsequent embodiments of the present invention, the present invention takes dynamic random access memory as an example to illustrate the core technology of the present invention and the manufacturing method of the dynamic random access memory can be used as an implementation method of the present invention. One of the most commonly used memory cells in the dynamic random access memory is a 1T1C cell, wherein a gate structure of an access transistor (1T) in the 1T1C cell is connected to a word line, a drain of the access transistor (1T) is connected to a bit line, and a source of the access transistor (1T) is connected to a capacitor (1C) in the 1T1C cell.

[0113] In order to increase the density of memory on a chip, the 1T1C cell needs to be reduced as much as possible, that is, all geometric dimensions of the 1T1C cell need to be reduced to a smaller dimension and the design of the capacitor must also be developed to a three-dimensional (3D) structure to increase the capacitance value of the capacitor (for example, forming a stack capacitor on the access transistor (1T) or forming a trench capacitor under the silicon surface of the access transistor (1T)). However, as the 1T1C cell is required to be reduced, the following difficulties faced by semiconductor process technology will become more difficult to solve:

[0114] (1) As the geometric dimensions of the 1T1C cell are reduced, the total area of ​​the 1T1C cell is reduced, resulting in a much smaller surface area in the 1T1C cell to allow the formation of various necessary contacts (e.g., contacts between the capacitor and the source of the access transistor (1T), and contacts between the bit line and the drain of the access transistor (1T)). (2) Even if the capacitor (1C) is made of the three-dimensional (3D) structure, the capacitance value of the capacitor (1C) will still be reduced. For example, if the stack capacitor formed above the silicon surface of the access transistor (1T) is too high, the silicon surface of the 1T1C cell will be very rough and have a poor surface appearance, and if a trench capacitor is formed below the silicon surface of the access transistor (1T), the trench capacitor needs to be made very deep, making the associated etching and refilling processes difficult. (3) The three structures of the word line, the bit line and the capacitor are difficult to be laid out in the same plane, especially the geometric conduction mechanism requires that the three structures must be perpendicular or nearly perpendicular to each other, and the order of formation of the three structures (for example, the order of forming the capacitor after the bit line or the order of forming the bit line after the capacitor) will make the layout more difficult. (4) Because the connection area from the capacitor to the source of the access transistor (1T) is very small due to (3), some self-alignment is difficult to achieve between the different structures that need to be connected. (5) When the geometric scale of the 1T1C unit continues to shrink, since the reduction of the geometric shape of the 1T1C unit will not completely depend on the reduction of the lithographic scale (lithographic scaling) and alignment processes, it becomes increasingly difficult for the integration process used to manufacture the 1T1C unit to achieve critical layers and geometric patterns with self-alignment characteristics.

[0115] Therefore, the present invention discloses (1) a new structure in which the bit line is below the horizontal silicon surface (HSS), (2) a new structure for connecting the gate structure of the access transistor (1T) and the word line to a key vertical connection with self-alignment possibility, (3) a new structure for connecting the drain of the access transistor (1T) to the underground interconnection structure with a vertical bridge material, (4) a new structure for self-aligning the drain of the access transistor (1T) to a channel with a desired distance through a spacer layer surrounding the word line, wherein the desired distance is determined by the spacer layer surrounding the word line, (5) a new structure for making an insulating cap on the underground interconnection structure by self-alignment to isolate the underground interconnection structure from all other conductive layers, and (6) all novel process methods for implementing the present invention.

[0116] Next, please refer to Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 , Fig. 22 , Fig.23 , Fig.24A , Fig. 24B , Fig.25A , Fig.25B , Fig.26 , Fig. 27 , Fig.28 ,in Figure 1A This is a flow chart of a method for manufacturing a dynamic random access memory storage cell (1T1C cell) array disclosed in one embodiment of the present invention. The detailed steps are as follows:

[0117] Step 10: Start;

[0118] Step 20: Based on a p-type substrate, define an active region of the dynamic random access memory cell array and form a shallow trench isolation (STI);

[0119] Step 30: forming an asymmetric spacer layer along the sidewall of the active region;

[0120] Step 40: forming an underground bit line under the silicon surface of the asymmetric spacer layer and the p-type substrate;

[0121] Step 50: forming word lines and gate structures of U-type transistors (or access transistors) of the dynamic random access memory cell array;

[0122] Step 60: define and isolate the drain (i.e., the first conductive region) and the source (i.e., the second conductive region) of the U-type transistor of the dynamic random access memory cell array;

[0123] Step 70: forming a connection between a bit line and a drain of the U-type transistor (or the access transistor) below the silicon surface, and doping the drain and the source;

[0124] Step 80: End.

[0125] Please refer to Figure 1B and Figure 2 , step 20 comprises:

[0126] Step 102: depositing a pad oxide layer 204 and a pad nitride layer 206;

[0127] Step 104: define an active region of the DRAM cell array, and remove silicon material corresponding to the semiconductor surface 208 (ie, silicon surface) outside the active region to form a trench 210;

[0128] Step 106 : Deposit and etch back an oxide layer 214 in the trench 210 to form the shallow trench isolation below the semiconductor surface 208 .

[0129] Please refer to Figure 1C and Figure 3 , Figure 4 , Figure 5 , step 30 comprises:

[0130] Step 108: depositing and etching back a first nitride layer to form a first nitride spacer;

[0131] Step 110: Deposit STI-first oxide layer 304 in trench 210 and perform chemical mechanical planarization

[0132] (chemical mechanical polishing, CMP) technology planarization;

[0133] Step 112: depositing a photoresist layer 306 on the STI-first oxide layer 304 and the pad nitride layer 206;

[0134] Step 114: completely etch the upper edge first nitride spacer layer and the STI-first oxide layer 304 that are not covered by the photoresist layer 306;

[0135] Step 116: Strip the photoresist layer 306 and the STI-first oxide layer 304, and form the first oxide layer 502. Figure 1D and Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , step 40 comprises:

[0136] Step 118: depositing a metal layer 602 in the trench 210 and planarizing it by the chemical mechanical planarization technique;

[0137] Step 120: depositing a photoresist layer 702;

[0138] Step 122: Etching the metal layer 602 corresponding to the end of the active region to separate a plurality of conductive lines;

[0139] Step 124: remove the photoresist layer 702 and etch back the metal layer 602 to form a bit line 902 under the silicon surface;

[0140] Step 126: Deposit a second oxide layer 1002 in the trench 210 and planarize it by the chemical mechanical planarization technique.

[0141] Please refer to Figure 1E and Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , step 50 comprises:

[0142] Step 128: depositing a third oxide layer 1102, a second nitride layer 1104, and a patterned photoresist layer 1106, and removing unnecessary portions of the third oxide layer 1102 and the second nitride layer 1104; Step 130: removing the patterned photoresist layer 1106, the pad nitride layer 206, and the pad oxide layer 204;

[0143] Step 132: etching the semiconductor surface 208 to form a U-shaped groove, forming a high-k insulating layer 1304 in the U-shaped groove, and depositing a gate material 1306 and then etching back to form a word line and a gate structure of the access transistor;

[0144] Step 134: depositing a third nitride layer 1402, then depositing a fourth oxide layer 1404, and then etching back the fourth oxide layer 1404;

[0145] Step 136: Etch away the second nitride layer 1104 and the third oxide layer 1102.

[0146] Please refer to Figure 1F and Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , step 60 comprises:

[0147] Step 138: remove the pad nitride layer 206, and etch back the second oxide layer 1002 to the semiconductor surface 208; Step 140: deposit and anisotropically etch the fourth nitride layer 1602, the fifth oxide layer 1604, and the fifth nitride layer 1606, and deposit the sixth oxide layer 1608;

[0148] Step 142: depositing a spin-on dielectric (SOD) 1702, planarizing the deposited SOD 1702 by the chemical mechanical planarization technique, depositing a photoresist to expose the SOD 1702 in the region serving as the source, etching the SOD 1702, the pad oxide layer 204, and the silicon material in the region serving as the drain to generate a hole Hole-1 / 3, and removing the photoresist;

[0149] Step 144: deposit and etch back the seventh oxide layer 1802, then deposit and etch back the spin-on dielectric layer 1804;

[0150] Step 146 : deposit photoresist to expose the drain region, etch the spin-on dielectric 1702 , the pad oxide layer 204 , and the silicon material near the drain region to generate a hole Hole- 1 / 2 , remove the photoresist, and thermally grow the eighth oxide layer 1902 .

[0151] Please refer to Figure 1G and Fig.21 , Fig. 22 , Fig.23 , Fig.24A , Fig. 24B , Fig.25A , Fig.25B and Fig.26 , step 70 comprises:

[0152] Step 148: Remove the lower edge of the first nitride spacer to expose the sidewall of the under-silicon bit line 902 (UGBL);

[0153] Step 150: depositing a conductive material (e.g., n+ polysilicon 2202 or other metal material (e.g., tungsten)) to contact the sidewall of the bit line 902 (UGBL) under the silicon surface, and then etching back the n+ polysilicon 2202 to leave an n+ polysilicon plug;

[0154] Step 152: removing the upper portion of the eighth oxide layer 1902 to expose the sidewall of the drain;

[0155] Step 154: Generate a connection material that allows the drain to contact the n+ polysilicon 2202 so that the drain is electrically connected to the under-silicon bit line 902 (UGBL);

[0156] Step 156: Generate an isolation material (eg, a ninth oxide layer 2502 ) on the connection material;

[0157] Step 158: remove the spin-on dielectric layer 1804, the sixth oxide layer 1608 and the fifth nitride layer 1606, and then use n-type dopant implantation to manufacture the drain and the source of the access transistor;

[0158] Step 160: End.

[0159] The above manufacturing method is described in detail as follows. The above manufacturing method starts with a p-type silicon wafer (i.e., a p-type substrate 202). In step 102, as Figure 2 As shown in FIG. 5( a ), a pad oxide layer 204 is formed on a semiconductor surface 208 (ie, a horizontal silicon surface), and then a pad nitride layer 206 is deposited on the pad oxide layer 204 .

[0160] In step 104, a photolithographic mask technique may be used to define an active region of the DRAM cell array, such as Figure 2As shown in (a), since the active region of the dynamic random access memory cell array corresponds to the pad oxide layer 204 and the pad nitride layer 206, the semiconductor surface 208 outside the active region pattern will be exposed. Since the semiconductor surface 208 outside the active region pattern is exposed, the silicon material corresponding to the semiconductor surface 208 outside the active region pattern can be removed by anisotropic etching technology to produce a trench (or channel) 210, wherein, for example, the trench 210 can reach a depth of 250 nanometers below the semiconductor surface 208.

[0161] In step 106, an oxide layer 214 is deposited to fill the trench 210, and then the oxide layer 214 is etched back to form the shallow trench isolation below the semiconductor surface 208 in the trench 210. In addition, Figure 2 (b) corresponds to Figure 2 (a) a top view, and Figure 2 (a) is along the Figure 2 (b) is a cross-sectional view of the cutting line in the X direction. Figure 2 As shown in (a), in one embodiment of the present invention, the shallow trench isolation has a thickness of about 50 nanometers, and if the trench 210 below the semiconductor surface 208 has a depth of 250 nanometers, the upper surface of the shallow trench isolation is about 200 nanometers deep from the semiconductor surface 208.

[0162] In step 108, if Figure 3 As shown in (a), the first nitride layer is deposited and the first nitride layer is etched back using the anisotropic etching technique to form the first nitride spacer along the two edges (i.e., the upper edge and the lower edge) of the trench 210. In step 110, as shown in Figure 3 (a) Depositing a STI-first oxide layer 304 on the shallow trench isolation in the trench 210 to fill the trench 210. Then planarizing the STI-first oxide layer 304 by the chemical mechanical planarization technique to make the upper surface of the STI-first oxide layer 304 flush with the upper surface of the pad nitride layer 206.

[0163] In step 112, if Figure 3As shown in (a), the first nitride spacer along the lower edge of the groove 210 (that is, the first nitride spacer at the lower edge) is protected by the photoresist layer 306 using the photolithography technology, but the first nitride spacer along the upper edge of the groove 210 (that is, the first nitride spacer at the upper edge) is removed. That is to say, after the photoresist layer 306 is deposited on the STI-first oxide layer 304 and the pad nitride layer 206, because the photoresist layer 306 on the first nitride spacer at the upper edge is removed but the photoresist layer 306 on the first nitride spacer at the lower edge is retained, the first nitride spacer at the lower edge will not be removed but the first nitride spacer at the upper edge can be removed. In addition, Figure 3 (b) corresponds to Figure 3 (a) a top view, and Figure 3 (a) is along the Figure 3 (b) is a cross-sectional view of the cutting line in the Y direction shown in FIG. Figure 4 As shown, the upper edge first nitride spacer layer and the STI-first oxide layer 304 that are not covered by the photoresist layer 306 may be etched away by an etching process.

[0164] In step 116, if Figure 5 As shown, the photoresist layer 306 and the STI-first oxide layer 304 are stripped, wherein the STI-first oxide layer 304 has an etching rate much higher than that of the thermally generated oxide layer and the deposited oxide layer. Then, the first oxide layer 502 is thermally generated to form a first oxide spacer, wherein the first oxide spacer covers the upper edge of the trench 210, the first oxide layer 502 does not grow beyond the liner nitride layer 206, and only a very thin oxide layer (referred to as the first oxide / STI layer 504) is formed on the shallow trench isolation. Figure 5 As shown, step 116 results in an asymmetric spacer (i.e., the first nitride spacer at the lower edge (i.e., the first spacer as described in claim 20) and the first oxide spacer (i.e., the second spacer as described in claim 20)) being formed at two symmetrical edges of the trench 210 (i.e., the upper edge and the lower edge of the trench 210). For example, the thickness of the first oxide spacer is 4 nanometers and the thickness of the first nitride spacer at the lower edge is 3 nanometers. On the other hand, the asymmetric spacer is also formed along the sidewall of the active region. The asymmetric spacer (i.e., Figure 5 The structure of the present invention and the above-mentioned related steps are the first main technical features of the present invention, which are called asymmetric spacers on twosymmetricaledges of a trench or a canal (ASoSE).

[0165] In step 118, if Figure 6 As shown, a metal layer 602 (or a conductive material that needs to withstand subsequent process conditions) is deposited to fill the trench 210 and is planarized by the chemical mechanical planarization technique so that the upper surface of the metal layer 602 is flush with the upper surface of the liner nitride layer 206 (as shown in FIG. Figure 6 In addition, in one embodiment of the present invention, the metal layer 602 may be tungsten (abbreviated as W).

[0166] In step 120, if Figure 7 As shown, a photoresist layer 702 is deposited to cover the first nitride spacer and the first oxide spacer at the lower edge, but expose two edges of the first nitride spacer and the first oxide spacer at the lower edge corresponding to the ends of the active region.

[0167] In step 122, if Figure 8 As shown, the metal layer 602 is etched at the end corresponding to the active region until the upper surface of the first oxide / STI layer 504 is exposed to separate a plurality of conductive lines (ie, the metal layer 602 ).

[0168] In step 124, if Fig. 9 As shown in (a), after removing the photoresist layer 702, the metal layer 602 in the trench 210 is etched back to a reasonable thickness to form a sub-silicon surface bit line 902, wherein the upper surface of the sub-silicon surface bit line 902 is much lower than the semiconductor surface 208 (for example, the thickness of the sub-silicon surface bit line 902 is about 40 nanometers). Fig. 9 As shown in (a), the silicon surface bit line 902 is located on the upper surface of the shallow trench isolation and the two side walls of the silicon surface bit line 902 are respectively limited by the asymmetric spacer layer (that is, the first nitride spacer layer at the lower edge and the first oxide spacer layer). In addition, Fig. 9 (a) is along the Fig. 9 (b) is a cross-sectional view taken along the cutting line in the Y direction.

[0169] In step 126, if Fig.10 (Along as Fig. 9 As shown in (b) of the cross-sectional view of the cutting line in the Y direction, the second oxide layer 1002 (also called CVD-STI-oxide2) needs to have a sufficient thickness to fill the trench 210 above the bit line 902 under the silicon surface, and then the second oxide layer 1002 is polished by the chemical mechanical planarization technology to retain a portion of the second oxide layer 1002, wherein the height of the retained portion of the second oxide layer 1002 is flush with the upper surface of the liner nitride layer 206, limited by the liner nitride layer 206, and the first nitride spacer layer and the first oxide spacer layer covering the lower edge. Fig.10As shown, step 126 can make the bit line 902 under the silicon surface (that is, the interconnection structure described in claim 1) embedded in all insulators in the trench 210 (that is, the isolation region described in claim 1) and confined by all the insulators (later the bit line 902 under the silicon surface will be connected to the drain of the access transistor of the dynamic random access memory storage cell array), wherein as Fig.10 The structure shown is called underground bit-lines (UGBL) surrounded by insulator, and the underground bit-lines (UGBL) are the second main technical feature of the present invention.

[0170] The following description will introduce how to simultaneously form the access transistors and word lines of the dynamic random access memory storage cell (1T1C cell) array by a self-alignment method and form all related gate structures of the word lines connecting the access transistors. In this way, the gate structures of the access transistors and word lines of the dynamic random access memory storage cell (1T1C cell) array will be connected into a single metal (e.g., tungsten (W)).

[0171] In step 128, if Fig.11 As shown in (a), firstly, a third oxide layer 1102, a second nitride layer 1104, and a patterned photoresist layer 1106 are deposited. Then, unnecessary portions of the third oxide layer 1102 and the second nitride layer 1104 are removed by the photolithography technique. In addition, a transistor / word line pattern can be defined by a composite layer of the third oxide layer 1102 and the second nitride layer 1104, wherein the composite layer of the third oxide layer 1102 and the second nitride layer 1104 is composed of a plurality of strip-shaped third oxide layers 1102 and the second nitride layer 1104 in a direction perpendicular to the active region direction. Therefore, as Fig.11 (a) and Fig.11 As shown in (b), longitudinal (the Y direction) stripes (composed of the third oxide layer 1102 and the second nitride layer 1104) for defining the access transistor and the word line, and a cross-point square for defining the active region will be formed, wherein the cross-point square is the cross-point space between the two longitudinal stripes, and Fig.11 (a) is along the Fig.11 (b) is a cross-sectional view taken along the cutting line in the X direction.

[0172] like Fig.11 (b) Fig.11The top view shown in (b) shows a fabric-like checkerboard pattern with longitudinal stripes of the third oxide layer 1102 and the second nitride layer 1104 located above the pad nitride layer 206 and the pad oxide layer 204, and also shows the fabric-like checkerboard pattern in the horizontal direction (i.e., Fig.11 The active region (covered by the liner nitride layer 206 and the liner oxide layer 204) and the shallow trench isolation in the X direction (as shown in (b)). Fig.11 As shown in (b), the active region allows the access transistor to be made by a self-alignment technique. This fabric-like checkerboard pattern of the self-aligned structure for making the gate structure of the access transistor and the word line in one process step is the third main technical feature of the present invention.

[0173] In step 130, if Fig.12 As shown in (a), the photoresist layer 1106 is retained, the pad nitride layer 206 is etched away, and the pad oxide layer 204 is retained, and as shown in Fig.12 As shown in (b), the photoresist layer 1106 and the pad oxide layer 204 are removed. Therefore, the semiconductor surface 208 is exposed as shown in FIG. Fig.12 (b) The cross-point square area shown in FIG. 1 , wherein the cross-point square area corresponds to the active area (located at Fig.11 (a) and Fig.11 (b) The intersection point is shown as a square).

[0174] In step 132, if Fig.13 As shown, the semiconductor surface 208 exposed in the square area of ​​the intersection is etched by the anisotropic etching technology to form the U-shaped groove, wherein the U-shaped groove is used to form the U-shaped channel 1302 of the access transistor, and for example, the vertical depth of the U-shaped groove from the semiconductor surface 208 can reach about 60 nanometers, that is, the U-shaped channel 1302 is located below the semiconductor surface 208. Because the U-shaped groove of the access transistor is exposed, the U-shaped channel 1302 in the U-shaped groove can be doped with a properly designed concentration of boron (p-type dopant) to achieve channel doping, wherein the channel doping is to enable the access transistor to have a desired threshold voltage after the subsequent high-k metal-gate structure is formed. Then, a high-k dielectric constant insulating layer 1304 is formed at the bottom and sidewalls of the U-shaped groove, wherein the high-k dielectric constant insulating layer 1304 serves as the gate dielectric layer of the access transistor, and as shown in FIG. Fig.13 As shown, the upper surfaces of both edges of the high dielectric constant insulating layer 1304 are higher than the semiconductor surface 208. Then, a gate material 1306 suitable for the word line conductivity and capable of achieving a targeted work-function performance is selected so that the access transistor has a lower threshold voltage (the purpose of selecting the gate material 1306 is to reduce the boosted word line voltage as low as possible while still providing sufficient driving force to complete the restoration of sufficient charge amount of the capacitor (1C), and on the other hand, to facilitate faster charge transfer for signal detection).

[0175] Deposit gate material 1306 (ie, suitable gate material), wherein the gate material 1306 is sufficient to fill the U-shaped groove (eg, Fig.13 ). For example, the gate material 1306 may be tungsten (W) used to form the high-k metal-gate structure, wherein if the U-shaped channel 1302 has a suitable doping concentration, the high-k metal-gate structure may allow the access transistor to have a desired lower threshold voltage. The gate material 1306 is then etched to produce a longitudinal (the Y direction) word line sandwiched between the two adjacent longitudinal stripes (composed of the third oxide layer 1102 and the second nitride layer 1104).

[0176] The access transistor (hereinafter referred to as U-shaped transistor) with a U-shaped channel 1302 disclosed in the present invention is different from the recessed transistor commonly used in the buried word line design disclosed in the prior art. The body of the U-shaped transistor is limited by the second oxide layer 1002 (i.e., CVD-STI-Oxide2) on both sides along the Y direction (i.e., the channel width direction), and the channel length of the U-shaped transistor includes the depth of the U-shaped channel 1302 corresponding to the drain of the U-shaped transistor, the length of the bottom of the U-shaped channel 1302, and the depth of the U-shaped channel 1302 corresponding to the source of the U-shaped transistor. For example, if the vertical depth of the U-shaped groove is 60 nanometers and the opening of the U-shaped groove along the X direction (i.e., the channel length direction) is 7 nanometers, the total length of the U-shaped channel 1302 of the U-shaped transistor can reach 127 nanometers. In contrast, the channel length of the embedded transistor must be more dependent on the depth to which the gate material of the embedded transistor is embedded and the depth to which the source and drain junctions of the embedded transistor are formed.

[0177] Due to the structural difference between the U-shaped transistor and the embedded transistor, the channel length of the U-shaped channel 1302 can be better controlled (especially when the channel length of the U-shaped channel 1302 does not depend on the gate structure height of the U-shaped transistor). In addition, because the semiconductor surface 208 is fixed, the doping concentration distribution of the drain and source of the U-shaped transistor has less device-design-parameter variation and is more controllable, which will be described in more detail later on how to complete the drain and source of the U-shaped transistor. In addition, in the longitudinal direction, the gate structure and the word line of the U-shaped transistor are formed simultaneously by self-alignment between the two adjacent longitudinal stripes (composed of the third oxide layer 1102 and the second nitride layer 1104), which is a way to make the word line not lower than the semiconductor surface 208, wherein the word line not lower than the semiconductor surface 208 has a design and performance parameter that is quite different from the buried word line commonly used in the prior art. In addition, the height of the word line (that is, the gate material 1306) is designed to be lower than the height of the composite layer (composed of the third oxide layer 1102 and the second nitride layer 1104) by etching back. In addition, the structural design that the gate structure of the U-type transistor is self-alignedly connected to the word line is the fourth main technical feature of the present invention.

[0178] In step 134, if Fig.14 As shown, a third nitride layer 1402 is deposited, and then a fourth oxide layer 1404 is deposited, wherein the third nitride layer 1402 and the fourth oxide layer 1404 are stacked together so that their total thickness is sufficient to fill the space between the two adjacent longitudinal stripes (composed of the third oxide layer 1102 and the second nitride layer 1104). Then, the fourth oxide layer 1404 is etched back (or polished) so that the upper surface of the fourth oxide layer 1404 is flush with the upper surface of the second nitride layer 1104, thereby forming a composite layer composed of the fourth oxide layer 1404 and the third nitride layer 1402 directly above the word line (that is, the gate material 1306).

[0179] In step 136, if Fig.15 As shown, the second nitride layer 1104 is etched away by the anisotropic etching technique, and the fourth oxide layer 1404 / third nitride layer 1402 on the word line is retained. Then, the third oxide layer 1102 is also etched away by the anisotropic etching technique to expose the pad nitride layer 206. Fig.15 The gate structure shown (eg, fourth oxide layer 1404 / third nitride layer 1402 / gate material 1306 ) simultaneously implements the gate structure of the U-shaped transistor in the U-shaped groove and the word line in the longitudinal direction (ie, the Y direction).

[0180] In step 138, if Fig.16 As shown, the pad nitride layer 206 is removed to leave the pad oxide layer 204. The second oxide layer 1002 (ie, the second oxide layer) is etched back to make the upper surface of the second oxide layer 1002 flush with the upper surface of the pad oxide layer 204.

[0181] In step 140, if Fig.16 As shown, a fourth nitride layer 1602 is deposited and etched by the anisotropic etching technique to generate a fourth nitride spacer with a carefully designed thickness (that is, the first spacer and the second spacer as described in claim 7). Then, a fifth oxide layer 1604 is deposited and etched by the anisotropic etching technique to generate a fifth oxide spacer. Then, a fifth nitride layer 1606 is deposited and etched by the anisotropic etching technique to generate a fifth nitride spacer. Then, a sixth oxide layer 1608 is deposited as shown. Fig.16 Therefore, in summary, the sixth oxide layer 1608 is outside the fifth nitride spacer, the fifth nitride spacer is outside the fifth oxide spacer, and the fifth oxide spacer is outside the fourth nitride spacer, and all of the above spacers surround and are along the gate structure (fourth oxide layer 1404 / third nitride layer 1402 / gate material 1306).

[0182] like Fig.16 , as shown in 17, in order to conveniently and clearly describe the dynamic random access memory storage cell array having the word lines and the bit lines, the word line located in the center is marked as the first word line Wordline-1 (corresponding to the access transistor AQ1), the word line adjacent to the left of the first word line Wordline-1 is marked as the second word line Wordline-2 (corresponding to the access transistor AQ2 adjacent to the left of the access transistor AQ1), and the pad oxide layer 204 still covers the area between the first word line Wordline-1 and the second word line Wordline-2 as the drain to reserve the first drain Drain-1 of the access transistor AQ1 and the second drain Drain-2 of the access transistor AQ2. The word line adjacent to the right of the first word line Wordline-1 is marked as the third word line Wordline-3 (corresponding to the access transistor AQ3 adjacent to the right of the access transistor AQ1), and the pad oxide layer 204 still covers the area between the first word line Wordline-1 and the third word line Wordline-3 as the source to reserve the first source Source-1 of the access transistor AQ1 and the third source Source-3 of the access transistor AQ3. In addition, taking the first word line Wordline-1 and the access transistor AQ1 as an example, as Fig.16 As shown, the first word line Wordline-1 is obviously coupled to the gate structure of the access transistor AQ1, wherein the first word line Wordline-1 (that is, the interconnection structure described in claim 6) includes an upper portion located above the semiconductor surface 208 of the p-type substrate 202, and the sidewalls of the upper portion of the first word line Wordline-1 are obviously aligned with the sidewalls of the gate structure of the access transistor AQ1.

[0183] In step 142, if Fig.17 As shown, a spin-on dielectric 1702 is deposited, wherein the thickness of the spin-on dielectric 1702 is sufficient to fill the space between the above-mentioned word lines (the first word line Wordline-1, the second word line Wordline-2, and the third word line Wordline-3) (the region serving as the drain and the region serving as the source), and the spin-on dielectric 1702 is polished by the chemical mechanical planarization technology so that the upper surface of the spin-on dielectric 1702 is flush with the upper surface of the fourth oxide layer 1404. In addition, the sixth oxide layer 1608 is also polished so that the upper surface of the sixth oxide layer 1608 is also flush with the upper surface of the fourth oxide layer 1404. The photoresist is deposited to cover the spin-on dielectric 1702 in the region serving as the drain (the first drain Drain-1 and the second drain Drain-2), and to expose the spin-on dielectric 1702 in the region serving as the source (the first source Source-1 and the third source Source-3) for subsequent processing. Then, the sixth oxide layer 1608 surrounding the word lines (the first word line Wordline-1, the second word line Wordline-2, and the third word line Wordline-3) can be used as a self-alignment mask to remove the spin-on dielectric 1702 in the region serving as the source (the first source Source-1 and the third source Source-3), and to etch away the pad oxide layer 204 in the center of the region serving as the source to expose the semiconductor surface 208. Then, as Fig.17 As shown, the silicon material of the semiconductor surface HSS-1 / 3 (part of the semiconductor surface 208) serving as the source region is excavated and removed by the anisotropic etching to generate a hole Hole-1 / 3 (for example, the depth of the hole Hole-1 / 3 is 140 nanometers), wherein two pairs of sides of the hole Hole-1 / 3 are surrounded by the lower edge first nitride spacer and the first oxide spacer and the other two pairs of sides of the hole Hole-1 / 3 are surrounded by the p-type substrate 202.

[0184] like Fig.17As shown, the semiconductor surface HSS-1 / 2 (part of the semiconductor surface 208) between the first word line Wordline-1 and the second word line Wordline-2 is a region serving as the first drain Drain-1 (i.e., the drain of the access transistor AQ1) and the second drain Drain-2 (i.e., the drain of the access transistor AQ2), and is also a region for vertically connecting the access transistors AQ1 and AQ2 to the bit line 902 below the silicon surface. In addition, the semiconductor surface HSS-1 / 3 (part of the semiconductor surface 208) between the first word line Wordline-1 and the third word line Wordline-3 is a region serving as the first source Source-1 (i.e., the source of the access transistor AQ1) and the third source Source-3 (i.e., the source of the access transistor AQ3), but because the first source Source-1 and the third source Source-3 will be connected to the cell storage nodes CSN1 and CSN3, respectively, the first source Source-1 and the third source Source-3 must be separated and cannot be connected. In addition, the spin-on dielectric 1702 is used in step 142 because the spin-on dielectric 1702 has a very high etch rate without damaging other existing materials and the spin-on dielectric 1702 can resist other thermal processes other than photoresist. In addition, because the desired pattern has been transferred to the spin-on dielectric 1702, all unnecessary photoresist must be removed to planarize the spin-on dielectric 1702 (e.g., Fig.17 shown).

[0185] In step 144, if Fig.18 As shown, a seventh oxide layer 1802 is deposited, wherein the thickness of the seventh oxide layer 1802 is sufficient to fill the hole Hole-1 / 3, and the seventh oxide layer 1802 above the semiconductor surface 208 is accurately removed by an isotropic etch technique to form a seventh oxide layer vertical isolation in the hole Hole-1 / 3, wherein the upper surface of the seventh oxide layer vertical isolation is flush with the semiconductor surface 208. Then, a spin-on dielectric layer 1804 is deposited, wherein the thickness of the spin-on dielectric layer 1804 is sufficient to fill the space of the upper surface of the seventh oxide layer 1802 in the hole Hole-1 / 3, and the spin-on dielectric material on the top of the spin-on dielectric layer 1804 is removed by the chemical mechanical planarization technique until the upper surface of the spin-on dielectric layer 1804 is flush with the upper surface of the fourth oxide layer 1404.

[0186] In step 146, if Fig.19As shown, a patterned photoresist is deposited to cover the area serving as the drain and to expose the area serving as the drain. Then, the spin-on dielectric 1702 corresponding to the hole Hole-1 / 2 and the pad oxide layer 204 thereunder are removed to expose the semiconductor surface 208. Then, the silicon material corresponding to the semiconductor surface HSS-1 / 2 (a portion of the semiconductor surface 208) is excavated and removed by the anisotropic etching to generate a hole Hole-1 / 2 (for example, the depth of the hole Hole-1 / 2 is 200 nanometers), wherein two pairs of sides of the hole Hole-1 / 2 are respectively surrounded by the p-type substrate 202, the third side of the hole Hole-1 / 2 is surrounded by the first nitride spacer layer at the lower edge, and the fourth side of the hole Hole-1 / 2 is surrounded by the first oxide spacer layer, wherein the second oxide layer 1002 can additionally limit the third and fourth sides of the hole Hole-1 / 2 from the outside. Then, the photoresist and the thermally generated eighth oxide layer 1902 (that is, the first isolation layer described in claim 13) are removed to cover three inner sidewalls of the four inner sidewalls of the hole Hole-1 / 2 and the bottom of the hole Hole-1 / 2, wherein the other inner sidewall of the four inner sidewalls of the hole Hole-1 / 2 that is different from the three inner sidewalls is covered by the first nitride spacer layer at the lower edge. In addition, Fig. 20 is a cross-sectional view of the dynamic random access memory cell array along the Y2 direction, wherein the Y2 direction extends along the center of the hole Hole-1 / 2 and is perpendicular to the X direction. Fig. 20 As shown, the active region is sandwiched between the second oxide layer 1002 (CVD-STI-Oxide 2), the under-silicon bit line 902 (UGBL), the first oxide spacer, and the lower edge first nitride spacer.

[0187] In step 148, if Fig.21 As shown, the lower edge first nitride spacer on the other inner wall in the hole Hole-1 / 2 is removed by the isotropic etching technology (because the lower edge first nitride spacer is very thin and because the sixth oxide layer 1608 is a good protection for the fifth nitride spacer (corresponding to the fifth nitride layer 1606), the isotropic etching technology will not damage other structures on the semiconductor surface 208, and will not remove the eighth oxide layer 1902 in the hole Hole-1 / 2).

[0188] In step 150, if Fig. 22As shown, very heavily doped n+ polysilicon 2202 (or tungsten) is deposited, wherein the thickness of the n+ polysilicon 2202 (or tungsten) is sufficient to fill the hole Hole-1 / 2 so as to form a flat surface above the n+ polysilicon 2202 (or tungsten), and then the n+ polysilicon 2202 (or tungsten) on the semiconductor surface 208 is removed by the isotropic etching technology to leave an n+ polysilicon (or tungsten) plug in the hole Hole-1 / 2, wherein the upper surface of the n+ polysilicon (or tungsten) plug is flush with the semiconductor surface 208. Fig. 22 As shown, in the hole Hole-1 / 2, the n+ polysilicon (or tungsten) plug is connected to the side wall of the silicon surface bit line 902 (UGBL) through its side wall, and this connection method is the fifth main technical feature of the present invention, wherein the n+ polysilicon (or tungsten) plug and the silicon surface bit line 902 (UGBL) are conductive materials connected in a sidewall self-alignment way, but are completely isolated from the p-type substrate 202 by the eighth oxide layer 1902.

[0189] In step 152, if Fig.23 As shown, an appropriate amount of the upper portion of the eighth oxide layer 1902 is removed by the anisotropic etching technology (for example, the upper portion of the eighth oxide layer 1902 is removed to a height of 20 nanometers below the semiconductor surface 208) to produce an eighth oxide spacer in the hole Hole-1 / 2, wherein the height of the eighth oxide spacer is lower than the height of the n+ polysilicon (or tungsten) plug (for example, the height of the eighth oxide spacer is approximately 20 nanometers below the semiconductor surface 208).

[0190] In step 154, if Fig.24A As shown, when taking n+ polysilicon plug 2202 (i.e., the bridge contact described in claim 11) as an example, a thin layer of n+ polysilicon material can be grown by using the silicon seed provided by n+ polysilicon plug 2202 and the selective epitaxy growth (SEG) technology, so that the neck-type surrounding conductive n+ polysilicon (i.e., the thin layer of n+ polysilicon material) on the semiconductor surface 208 connected to both sides of the hole Hole-1 / 2 can be used as the first drain Drain-1 of the access transistor AQ1 and the second drain Drain-2 of the access transistor AQ2, respectively, and can also be used as a conductive bridge contact (conductive bridge contact) between the bit line 902 (UGBL) (i.e., the interconnection structure described in claim 11) under the silicon surface and the access transistors AQ1 and AQ2, wherein the neck-type surrounding conductive n+ polysilicon is also called an n+ collar. Then, in step 156, as Fig.25AAs shown, a ninth oxide layer 2502 (i.e., an isolation cap) is locally thermally grown on the n+ polysilicon plug 2202 to cover the semiconductor surface HSS-1 / 2 (part of the semiconductor surface 208), but the n+ ring is left as (or in contact with) the first drain Drain-1 of the access transistor AQ1 and the second drain Drain-2 of the access transistor AQ2. The above connection method of forming the conductive bridge contact between the silicon surface lower bit line 902 (UGBL) and the first drain Drain-1 (or the second drain Drain-2) is the sixth main technical feature of the present invention, wherein the first drain Drain-1 and the second drain Drain-2 are oxide (i.e., the isolation cap)-capped n+ drains.

[0191] In addition, please refer to Fig. 24B , Fig. 24B It is a schematic diagram illustrating another method of realizing a vertical connection (bridge) and a first drain Drain-1 of an access transistor AQ1 (or a second drain Drain-2 of an access transistor AQ2) disclosed in another embodiment of the present invention, and how the vertical connection (bridge) and the first drain Drain-1 of the access transistor AQ1 (or the second drain Drain-2 of the access transistor AQ2) are connected to a bit line 902 (UGBL) below the silicon surface. The eighth oxide layer 1902 is thermally grown by following the above steps and the first nitride spacer layer at the lower edge is removed in the hole Hole-1 / 2. However, the next step is not to deposit n+ polysilicon 2202 in the hole Hole-1 / 2, but to form a thick layer of tungsten or other metal material by deposition or any other method to fill the hole Hole-1 / 2, and then the tungsten or other metal material is etched back to leave a plug (called W-2 plug) in the hole Hole-1 / 2. The W-2 plug is connected to the silicon under-surface bit line 902 (UGBL) through its opening on the sidewall of the hole Hole-1 / 2. The height of the W-2 plug is a designed distance (e.g., 20 nanometers) lower than the semiconductor surface 208. The portion of the eighth oxide layer 1902 not covered by the W-2 plug in the hole Hole-1 / 2 is removed by the anisotropic etching technology. Then, an n+ polysilicon layer 2402 is deposited to fill the hole Hole-1 / 2, and then the n+ polysilicon layer 2402 is etched back to make the height of the n+ polysilicon layer 2402 flush with the semiconductor surface 208, so that the neck-shaped surrounding conductive n+ polysilicon (also called n+ ring) on ​​the semiconductor surface 208 connected to both sides of the hole Hole-1 / 2 can serve as the first drain Drain-1 of the access transistor AQ1 and the second drain Drain-2 of the access transistor AQ2, and can also serve as a conductive bridge contact between the bit line 902 (UGBL) under the silicon surface and the access transistors AQ1 and AQ2. Then, as shown in FIG. Fig.25BAs shown, a ninth oxide layer 2502 (i.e., the isolation cap) is locally thermally grown on the W-2 plug to cover the semiconductor surface HSS-1 / 2 (part of the semiconductor surface 208), but leaves the n+ ring as the first drain Drain-1 of the access transistor AQ1 and the second drain Drain-2 of the access transistor AQ2.

[0192] The advantages of using the W-2 plug to connect the silicon subsurface bit line 902 (UGBL) to the n-type doped drain or source (or p-type doped drain or source) are: (1) the same type of vertical bridge material (i.e., the W-2 plug) can be used in a complementary metal-oxide-semiconductor (CMOS) to connect the first conductive region (i.e., the drain) of an n-type metal-oxide-semiconductor (NMOS) included in the complementary metal-oxide-semiconductor and the second conductive region (i.e., the drain) of a p-type metal-oxide-semiconductor included in the complementary metal-oxide-semiconductor; and (2) because the same material is used, the contact between the W-2 plug and the silicon subsurface bit line 902 (UGBL) has a low resistance.

[0193] In step 158, if Fig.26 As shown, the sixth oxide layer 1608 and the fifth nitride spacer are removed, and then the n-type dopant injection can produce a drain or source with an np junction in the p-type substrate 202 through the pad oxide layer 204 (that is, the first drain Drain-1 and the first source Source-1 of the access transistor AQ1, the second drain Drain-2 of the access transistor AQ2, and the third source Source-3 of the access transistor AQ3). In addition, a rapid thermal annealing (RTA) process step is required to activate the n-type dopant to eliminate any defects caused by ion implantation. In addition, n-type lightly doped drains (NLDD) can be formed under the fifth oxide spacer and the fourth nitride spacer.

[0194] Fig. 27 and Fig.28 1 is a schematic diagram illustrating a cross-sectional view and a top view of the dynamic random access memory storage cell array. Fig. 27 and Fig.28 As shown, Fig. 27 and Fig.28Disclosed is a principle of realizing a silicon surface interconnection structure (underground interconnection) for connecting to the drains (e.g., the first drain Drain-1 and the second drain Drain-2) of the access transistors (e.g., the access transistors AQ1 and AQ2) by a self-aligned vertical connector. In addition, the first source Source-1 and the third source Source-3 are connected to capacitors 2602 and 2604, respectively, wherein the capacitors 2602 and 2604 can be generated using a method commonly used to manufacture stacked capacitors or trench capacitors to complete the dynamic random access memory cell (1T1C cell) in the dynamic random access memory storage cell array. In addition, Fig.28 Along the middle Fig. 20 The cross-sectional view of the DRAM cell array along the Y2 direction can show the location of the bit line 902 (UGBL) below the silicon surface. In addition, other transistors included in the DRAM cell array can be electrically connected to signal lines (not shown). Fig.28 , for example, the signal line may be a power line coupled to a voltage source or a ground source), wherein the signal line is distributed below the semiconductor surface 208 and is separated from the under-silicon-surface bit line 902 (UGBL), and the distance between the semiconductor surface 208 and the upper surface of the under-silicon-surface bit line 902 (UGBL) is different from the distance between the semiconductor surface 208 and the upper surface of the signal line.

[0195] Similarly, according to the above principles, many other memory cell or component structures may also consider using the silicon surface bit line 902 (UGBL) and / or the self-aligned gate structure and word line structure and effectively connect the access transistors AQ1 and AQ2 to any place on the same chip through the silicon surface interconnection structure, so as to achieve the required functions. This well-isolated interconnection structure / conducting wire in the p-type silicon substrate 202 may also be applied to other types of transistors, such as fin field-effect transistors (FinFET), tri-gate transistors and planar transistors.

[0196] In summary, because the present invention introduces the well-isolated interconnect structure / wire below the silicon surface, in addition to using the interconnect structure only above the semiconductor surface, the interconnect structure / wire can also connect the transistor at the bottom of the transistor within the silicon substrate.

[0197] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor device structure, characterized in that Includes: A semiconductor substrate having a semiconductor surface; An active region is located in the silicon substrate; A transistor is located in the active region, the transistor comprising a gate structure, a channel under the gate structure, a first conductive region located on one side of the gate structure, and a second conductive region located on another side of the gate structure; A shallow trench isolation is located next to the active region; as well as An interconnect structure is located within the shallow trench isolation, wherein the interconnect structure is disposed below the semiconductor surface.

2. The semiconductor device structure according to claim 1, wherein The shallow trench isolation comprises: a first spacer layer covering a first sidewall of the interconnect structure; and a second spacer layer covering a second sidewall of the interconnect structure; The first sidewall of the interconnect structure is isolated from the semiconductor substrate by the first spacer layer, and the second sidewall of the interconnect structure is isolated from the semiconductor substrate by the second spacer layer.

3. The semiconductor device structure according to claim 2, wherein : A material of the first spacer layer is different from a material of the second spacer layer.

4. The semiconductor device structure according to claim 2, wherein The shallow trench isolation further comprises a bottom spacer layer located on the bottom surface of the interconnect structure, wherein the bottom surface of the interconnect structure is isolated from the semiconductor substrate by the bottom spacer layer.

5. The semiconductor device structure according to claim 1, wherein The interconnect structure couples the transistors.

6. The semiconductor device structure according to claim 5, characterized in that Include: A bridge contact is located in the active region, and the interconnect structure is coupled to the transistor via the bridge contact.

7. The semiconductor device structure according to claim 1, wherein : The conductivity of the interconnect structure is higher than the conductivity of the shallow trench isolation.

8. The semiconductor device structure according to claim 1, wherein : The interconnect structure includes metal or polysilicon.

9. A semiconductor device structure, characterized in that Includes: A semiconductor substrate having a semiconductor surface; An active region is located in the silicon substrate; A transistor is located in the active region, the transistor comprising a gate structure, a channel under the gate structure, a first conductive region located on one side of the gate structure, and a second conductive region located on another side of the gate structure; A shallow trench isolation surrounds the active region, wherein the shallow trench isolation includes a first shallow trench isolation region located at one side of the active region and a second shallow trench isolation region located at the other side of the active region; a first interconnect structure located in the first shallow trench isolation region and disposed below the semiconductor surface; and A second interconnect structure is located in the second shallow trench isolation region and is disposed below the semiconductor surface.

10. The semiconductor device structure according to claim 9, wherein : The material of the first interconnect structure is the same as the material of the second interconnect structure.

11. The semiconductor device structure according to claim 9, wherein : The conductivity of the first interconnect structure is higher than the conductivity of the first shallow trench isolation region, and the conductivity of the second interconnect structure is higher than the conductivity of the second shallow trench isolation region.

12. The semiconductor device structure according to claim 9, wherein : The first interconnect structure and / or the second interconnect structure comprises metal or polysilicon.

13. The semiconductor device structure according to claim 9, wherein : The first interconnection structure and the second interconnection structure are separated and not connected to each other.

14. The semiconductor device structure according to claim 9, wherein : wherein a top surface of the first interconnect structure is below the semiconductor surface and covered by an insulating layer, wherein a top surface of the second interconnect structure is below the semiconductor surface and covered by the insulating layer.

15. The semiconductor device structure according to claim 9, wherein : The first interconnect structure and the second interconnect structure isolate the semiconductor substrate.

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