Semiconductor device and method of forming embedded trace substrate with barrier layer to suppress electromigration

Abstract

A semiconductor device has an interconnect substrate having a first conductive layer and a first barrier layer formed on a first portion of the first conductive layer, and a second barrier layer formed on a second portion of the first conductive layer. The first barrier layer and the second barrier layer substantially surround or enclose the first conductive layer. The first barrier layer is a conductive material, and the second barrier layer includes a non-conductive material. The interconnect structure also has a second conductive layer coupled to the first conductive layer, wherein an insulating layer is formed between the first conductive layer and the second conductive layer. A third barrier layer is formed on the first portion of the second conductive layer, and a fourth barrier layer is formed on the second portion of the second conductive layer. The electrical component is disposed on the interconnect substrate.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices and methods of forming an embedded trace substrate having a barrier layer to inhibit electromigration from a conductive layer. Background Art

[0002] Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide variety of functions such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, optoelectronics, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networking, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0003] Semiconductor wafers typically include multiple semiconductor dies separated by saw streets. Semiconductor wafers are singulated into multiple individual semiconductor dies. Semiconductor packages may include semiconductor dies mounted to an interconnect substrate. Electrical interconnect structures within an interconnect substrate may be subject to electromigration, particularly for small geometries, fine pitches, and minimum lines / spaces. Electromigration is the migration of materials caused by the gradual movement of ions in a conductive layer due to momentum transfer between conductive electrons and diffused metal atoms. Electromigration causes defects, such as the formation of voids and hillocks, which may cause reliability issues, such as open circuits or short circuits. The formation of defects is associated with the evolution of strain and stress within the conductive material. Electromigration can reduce reliability and yield, and increase defects and manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1a-1c illustrates a semiconductor wafer having a plurality of semiconductor dies separated by saw streets;

[0005] Figure 2a-2r A process for forming an interconnect substrate is illustrated wherein a barrier layer is formed around a conductive layer to inhibit electromigration;

[0006] Figure 3a-3k illustrates another process of forming an interconnect substrate, wherein a barrier layer is formed around a conductive layer to inhibit electromigration; and

[0007] Figure 4 A printed circuit board (PCB) is illustrated, with different types of packages arranged on a surface of the PCB. DETAILED DESCRIPTION

[0008] In the following description with reference to the accompanying drawings, the present invention is described in one or more embodiments, wherein the same numerals represent the same or similar elements. Although the present invention is described according to the best mode for achieving the purpose of the present invention, it will be appreciated by those skilled in the art that the present invention is intended to cover substitutions, modifications and equivalents that may be included within the spirit and scope of the present invention as defined by the appended claims and their equivalents, which are supported by the following disclosure and the accompanying drawings. The features shown in the figures are not necessarily drawn to scale. In the accompanying drawings, elements with similar functions are given the same reference numerals. The term "semiconductor die" as used herein refers to both the singular and plural forms of the word, and therefore may refer to both a single semiconductor device and a plurality of semiconductor devices.

[0009] Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components such as transistors and diodes have the ability to control the flow of current. Passive electrical components such as capacitors, inductors, and resistors create the relationship between voltage and current necessary to perform the circuit function.

[0010] Back-end manufacturing refers to cutting or singulating the completed wafer into individual semiconductor dies, and packaging the semiconductor dies for structural support, electrical interconnection, and environmental isolation. In order to singulate the semiconductor dies, the wafer is scribed and broken along the non-functional area of ​​the wafer (called saw road or scribe line). The wafer is singulated using a laser cutting tool or a saw blade. After singulation, the individual semiconductor dies are arranged on a package substrate, which includes pins or contact pads for interconnection with other system components. Then, the contact pads formed on the semiconductor die are connected to the contact pads (contact pad) in the package. Electrical connection can be achieved with a conductive layer, a bump, a columnar bump, a conductive glue, or a wire bond. Encapsulant or other molding materials are deposited on the package to provide physical support and electrical isolation. The completed package is then inserted into the electrical system, and the functions of the semiconductor device are made available to other system components.

[0011] Figure 1aA semiconductor wafer 100 is shown having a base substrate material 102 such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor dies or electrical components 104 are formed on the wafer 100, separated by non-active inter-die wafer regions or saw streets 106. The saw streets 106 provide dicing areas to singulate the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0012] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or inactive surface 108 and an active surface 110 that contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuits, such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), memory, or other signal processing circuits. The semiconductor die 104 may also include IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0013] Conductive layer 112 is formed on active surface 110 using physical vapor deposition (PVD), chemical vapor deposition (CVD), electrolytic plating, electroless plating process or other suitable metal deposition process. Conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag) or other suitable conductive materials. Conductive layer 112 operates as a contact pad electrically connected to the circuit on active surface 110.

[0014] Conductive bump material is deposited on conductive layer 112 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. A suitable attachment or bonding process is used to bond the bump material to conductive layer 112. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 114. In one embodiment, bump 114 is formed on an under-bump metallization (UBM) having a wetting layer, a barrier layer and an adhesive layer. Bump 114 can also be compression bonded or thermocompressively bonded to conductive layer 112. Bump 114 represents a type of interconnect structure that can be formed on conductive layer 112. The interconnect structure can also use bonding wires, conductive glue, columnar bumps, micro bumps or other electrical interconnects.

[0015] exist Figure 1c 1 , semiconductor wafer 100 is singulated through saw streets 106 using a saw blade or laser cutting tool 119 into individual semiconductor dies 104. Individual semiconductor dies 104 may be inspected and electrically tested to identify known good dies or units (KGD / KGU) after singulation.

[0016] Figure 2a-2r Illustrated is a process of forming a double-sided embedded trace substrate (ETS) in which a barrier layer is formed around a conductive layer to inhibit electromigration. Figure 2a The core substrate 120 made of base material 122 is shown as a multi-layer flexible laminate, ceramic, copper clad laminate (CCL), glass or epoxy molding compound. Base material 122 can include one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO and other materials with similar insulation and structural properties. The core substrate 120 may include one or more laminated layers of polytetrafluoroethylene (PTFE) prepreg (prepreg), FR-4, FR-1, CEM-1 or CEM-3 combined with phenolic cotton paper, epoxy resin, resin, woven glass, matte glass, polyester and other reinforcing fibers or fabrics. In another embodiment, the core substrate 120 can also be any suitable laminated insert, PCB, wafer form, strip insert, lead frame or other types of substrates. The core substrate 120 has a thickness of 150.0 micrometers (μm) and includes a first major surface 124 and a second major surface 126 opposite to the surface 124 .

[0017] exist Figure 2bIn the embodiment of the present invention, a conductive layer 130 is formed on the surface 124, and a conductive layer 132 is formed on the surface 126. The conductive layers 130 and 132 can be formed using PVD, CVD, electrolytic plating, electroless plating process or other suitable metal deposition process. The conductive layers 130 and 132 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. The combination of the core substrate 120 and the conductive layers 130 and 132 constitutes the CCL substrate.

[0018] exist Figure 2c , a photoresist layer 136 is formed on the conductive layers 130 and 132. The photoresist layer 136a is patterned and etched to form a circuit layout or pattern 137a on the conductive layer 130, and the photoresist layer 136b is patterned and etched to form a circuit layout or pattern 137b on the conductive layer 132. Alternatively, the circuit patterns 137a and 137b may be formed by laser direct ablation (LDA).

[0019] exist Figure 2d , a conductive layer 138 is formed in a circuit pattern 137a defined by a photoresist layer 136a, and a conductive layer 140 is formed in a circuit pattern 137b defined by a photoresist layer 136b. Conductive layers 138 and 140 may be formed using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. Conductive layers 138 and 140 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials.

[0020] exist Figure 2e , the photoresist layers 136a and 136b are removed, thereby leaving the conductive layers 138 and 140 in the circuit patterns 137a and 137b, respectively. Specifically, the conductive layer segment 138a has a gap 142a with the conductive layer segment 138b, and the conductive layer segment 138b has a gap 142b with the conductive layer segment 138c. The conductive layer segment 138c has a gap 142c with the conductive layer segment 138d, and the conductive layer segment 138d has a gap 142d with the conductive layer segment 138e. Similarly, the conductive layer segment 140a has a gap 143a with the conductive layer segment 140b, and the conductive layer segment 140b has a gap 143b with the conductive layer segment 140c. The conductive layer segment 140c has a gap 143c with the conductive layer segment 140d, and the conductive layer segment 140d has a gap 143d with the conductive layer segment 140e. Conductive layer segments 138a-138b with intervals 142a-142d define circuit pattern 137a. Conductive layer segments 140a-140b with intervals 143a-143d define circuit pattern 137b.

[0021] exist Figure 2f, a protective or barrier layer 144 is conformally applied over conductive layers 130 and 138, including spaces 142a-142d therebetween. A protective or barrier layer 146 is conformally applied over conductive layers 132 and 140, including spaces 143a-143d therebetween. Barrier layers 144 and 146 may be formed using PVD, CVD, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. Barrier layers 144 and 146 may be tantalum, tantalum nitride, tantalum silicon nitride, tungsten, tungsten nitride, tungsten silicon nitride, titanium, titanium nitride, titanium silicon nitride, or cobalt (Co). In another embodiment, barrier layers 144 and 146 may be Co, iridium (Ir), or ruthenium (Ru), or alloys thereof with tungsten (W), boron (B), phosphorus (P), molybdenum (Mo), or rhenium (Re).

[0022] exist Figure 2g , an insulating layer 148 is formed on the barrier layer 144, and an insulating layer 150 is formed on the barrier layer 146. The insulating layers 148 and 150 may be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The insulating layers 148 and 150 include one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), titanium dioxide (TiO2), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials having similar insulating and structural properties. In one embodiment, the insulating layers 148 and 150 may be dielectric materials such as Ajinomoto build-up film (ABF) or polytetrafluoroethylene (PTFE) pre-impregnated (prepreg or PPG) laminated on the circuit patterns 137a and 137b.

[0023] exist Figure 2h In the embodiment of the present invention, a portion of insulating layers 148 and 150 are removed by an etching process or LDA using a laser 154 to form openings or vias 152 and 156, respectively. Opening 152 extends to barrier layer 144, and opening 156 extends to barrier layer 146.

[0024] exist Figure 2i, a protective or barrier layer 160 is conformally applied over insulating layer 148 and into through hole 152 on barrier layer 144. Similarly, a protective or barrier layer 162 is conformally applied over insulating layer 150 and into through hole 156 on barrier layer 146. Barrier layers 160 and 162 may be formed using PVD, CVD, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. Barrier layers 160 and 162 may be tantalum, tantalum nitride, tantalum silicon nitride, tungsten, tungsten nitride, tungsten silicon nitride, titanium, titanium nitride, titanium silicon nitride, or cobalt. In another embodiment, barrier layers 160 and 162 may be cobalt, iridium, or ruthenium, or alloys thereof with tungsten, boron, phosphorus, molybdenum, or rhenium. An optional seed layer 161 may be conformally applied over barrier layer 160, and an optional seed layer 163 may be conformally applied over barrier layer 162.

[0025] exist Figure 2j , a conductive layer 164 is formed on a barrier layer 160 and into a through hole 152 extending to the barrier layer 144. Similarly, a conductive layer 166 is formed on a barrier layer 162 and into a through hole 156 extending to the barrier layer 146. Conductive layers 164 and 166 may be formed using PVD, CVD, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. Conductive layers 164 and 166 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Conductive layers 164 and 166 and barrier layers 160 and 162 are patterned and etched according to a circuit pattern or layout 168a and 168b of an interconnect substrate, i.e., conductive traces with routing to provide electrical functionality. Alternatively, circuit layouts 168a-168b may be formed by LDA. Portions of conductive layers 164 and 166 may be electrically shared or electrically isolated, depending on the design and functionality of the electrical components added later. There may be multiple conductive layers such as 164 and 166 separated by multiple insulating layers such as 148 and 150 .

[0026] exist Figure 2k , a protective or barrier layer 170 is conformally applied over the conductive layer 164 and the insulating layer 148. Likewise, a protective or barrier layer 172 is conformally applied over the conductive layer 166 and the insulating layer 150. The barrier layers 170 and 172 may be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The barrier layers 170 and 172 may be SiO2, Si3N4, SiON, Ta2O5, Al2O3, TiO2, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and / or non-conductive properties.

[0027] exist Figure 2l, insulating layer 176 is formed on barrier layer 170 and insulating layer 148, and insulating layer 178 is formed on barrier layer 172 and insulating layer 150. Insulating layers 176 and 178 may be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. Insulating layers 176 and 178 include one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, TiO2, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. Portions of insulating layers 176 and 178 are removed by an etching process or LDA to form openings or through holes 177 and 179, respectively. Opening 177 extends to conductive layer 164, and opening 179 extends to conductive layer 166.

[0028] Figure 2l The components in FIG. 1 are a double-sided interconnect substrate 180 as an ETS and also include internal barrier layers 144, 146, 160, 162, 170 and 172 to inhibit electromigration. Figure 2m In FIG. 1 , double-sided interconnect substrate 180 is singulated along line 181 by removing core substrate 120 , leaving interconnect substrate 182 a and interconnect substrate 182 b .

[0029] exist Figure 2n In the embodiment, a portion of the conductive layer 130 and the barrier layer 144 on the interconnect substrate or ETS 182a are removed by an etching process (e.g., acid etching) to isolate the circuit pattern 137a. A similar etching operation is performed to remove a portion of the conductive layer 132 and the barrier layer 146 and isolate the circuit pattern 137b on the interconnect substrate or ETS 182b. Alternatively, as Figure 2o As shown in FIG. 1 , a grinder 184 is used to subject an interconnect substrate or ETS 182a to a grinding operation to remove a portion of the conductive layer 130 and the barrier layer 144, thereby isolating the circuit pattern 137a. A similar grinding operation is performed on the interconnect substrate or ETS 182b to remove a portion of the conductive layer 132 and the barrier layer 146, thereby isolating the circuit pattern 137b. The conductive layer 138 having the circuit pattern 137a is exposed from the interconnect substrate or ETS 182a. The conductive layers 138 and 164 primarily provide electrical communication or signal propagation through the interconnect substrate or ETS 182a.

[0030] Figure 2p Shown from Figure 2n1 , wherein barrier layer 144 surrounds conductive layer 138, and barrier layer 160 is formed on a first portion of conductive layer 164, and barrier layer 170 is formed on a second portion of conductive layer 164. Electromigration is material migration caused by the gradual movement of ions in the conductive layer due to momentum transfer between conductive electrons and diffused metal atoms. In the interconnect substrate or ETS 182a, conductive layers 138 and 164 are subject to electromigration. As the structure and size of conductive layers in semiconductor devices decrease, the practical significance of electromigration becomes more apparent. Electromigration can cause defects, such as the formation of voids and hillocks, which can cause reliability problems, such as open circuits or short circuits. The formation of defects is related to the evolution of strain and stress within the conductive material. Electromigration between conductive layers 138 and 164 and portions thereof can adversely affect electrical communication and signal propagation through the interconnect substrate or ETS 182a. Barrier layers 144, 160, and 170 reduce or inhibit electromigration relative to conductive layers 138 and 164 in the interconnect substrate or ETS 182a. For example, barrier layers 160 and 170 substantially surround or enclose conductive layer 164, except for the direct conductive path, to reduce or inhibit electromigration. Barrier layers 144, 160, and 170 increase the reliability of interconnect substrate or ETS 182a by reducing or inhibiting electromigration between internal conductive layers 140 and 166. In a similar manner, barrier layers 146, 162, and 172 inhibit electromigration relative to conductive layers 140 and 166 to increase the reliability of interconnect substrate or ETS 182b.

[0031] exist Figure 2q In the embodiment, electrical components 188a and 188b are disposed on interconnect substrate 182a and are electrically and mechanically connected to conductive layer 138. For example, electrical components 188a-188b may be similar to or made similar to those from Figure 1c The semiconductor die 104 is shown with the bumps 114 oriented toward the conductive layer 138. The electrical components 188a-188b may be other semiconductor dies, semiconductor packages, surface mount devices, RF components, discrete electrical devices, or integrated passive devices (IPDs).

[0032] A pick and place operation is used to position electrical components 188a-188b on interconnect substrate or ETS 182a. Bumps 114 are reflowed to make mechanical and electrical connections with conductive layer 138. Figure 2r Electrical components 188a-188b are shown electrically and mechanically connected to the conductive layer 138 of the interconnect substrate or ETS 182a.

[0033] Conductive bump material is deposited into through hole 177 above conductive layer 164 on interconnect substrate or ETS 182a using evaporation, electrolytic plating, electroless plating, ball drop or screen printing process. Bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combination thereof, with optional flux solution. For example, bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. Use suitable attachment or bonding process to bond bump material to conductive layer 164. In one embodiment, bump material is reflowed by heating material above its melting point to form ball or bump 190. In one embodiment, bump 190 is formed on UBM having wetting layer, barrier layer and adhesive layer. Bump 190 can also be compression bonded or thermocompression bonded to conductive layer 164. Bump 190 represents a type of interconnect structure that can be formed on conductive layer 164. Interconnect structure can also use bonding wire, conductive glue, columnar bump, micro bump or other electrical interconnect. The combination of interconnect substrate or ETS 182 a and electrical components 188 a - 188 b forms a semiconductor package 194 .

[0034] In another embodiment, from Figure 2k Continuing, insulating layer 200 is formed on barrier layer 170, and insulating layer 206 is formed on barrier layer 172, as shown in FIG. Figure 3a . Elements having similar functions are given the same reference numerals. Insulating layers 200 and 206 may be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. Insulating layers 200 and 206 include one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, TiO2, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. Portions of insulating layers 200 and 206 are removed by an etching process or LDA to form openings or vias 202 and 208, respectively. Opening 202 extends to conductive layer 164, and opening 208 extends to conductive layer 166.

[0035] exist Figure 3b 1 , a protective or barrier layer 210 is conformally applied over insulating layer 200 and into via 202 on conductive layer 164. Similarly, a protective or barrier layer 212 is conformally applied over insulating layer 206 and into via 208 on conductive layer 166. Barrier layers 210 and 212 may be formed using PVD, CVD, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. Barrier layers 210 and 212 may be tantalum, tantalum nitride, tantalum silicon nitride, tungsten, tungsten nitride, tungsten silicon nitride, titanium, titanium nitride, titanium silicon nitride, or cobalt. In another embodiment, barrier layers 210 and 212 may be cobalt, iridium, or ruthenium, or alloys thereof with tungsten, boron, phosphorus, molybdenum, or rhenium.

[0036] exist Figure 3c 1 , a conductive layer 214 is formed on barrier layer 210 and into via 202. Similarly, a conductive layer 216 is formed on barrier layer 212 and into via 156. Conductive layers 214 and 216 may be formed using PVD, CVD, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. Conductive layers 214 and 216 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials.

[0037] exist Figure 3d In the embodiment of the present invention, conductive layers 214 and 216 and barrier layers 210 and 212 are patterned and etched according to the circuit pattern or layout 218a and 218b of the interconnect substrate, that is, conductive traces with routing to provide electrical functions. Alternatively, circuit layouts 218a and 218b can be formed by LDA. Portions of conductive layers 214 and 216 are electrically shared or electrically isolated, depending on the design and function of the electrical components added later. There can be multiple conductive layers such as 214 and 216 separated by multiple insulating layers such as 200 and 206.

[0038] exist Figure 3e , a protective or barrier layer 220 is conformally applied over the conductive layer 214 and the insulating layer 200. Likewise, a protective or barrier layer 222 is conformally applied over the conductive layer 216 and the insulating layer 206. The barrier layers 220 and 222 may be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The barrier layers 220 and 222 may be SiO2, Si3N4, SiON, Ta2O5, Al2O3, TiO2, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and non-conductive properties.

[0039] exist Figure 3f In the embodiment, insulating layer 226 is formed on barrier layer 220, and insulating layer 228 is formed on barrier layer 222. Insulating layers 226 and 228 may be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. Insulating layers 226 and 228 include one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, TiO2, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. Portions of insulating layers 226 and 228 are removed by an etching process or LDA to form openings or through holes extending to conductive layers 214 and 216.

[0040] Similar to Figure 2i, a protective or barrier layer 230 is conformally applied over insulating layer 226 and into the through hole on conductive layer 214. Similarly, a protective or barrier layer 232 is conformally applied over insulating layer 228 and into the through hole on conductive layer 216. Barrier layers 230 and 232 may be formed using PVD, CVD, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. Barrier layers 230 and 232 may be tantalum, tantalum nitride, tantalum silicon nitride, tungsten, tungsten nitride, tungsten silicon nitride, titanium, titanium nitride, titanium silicon nitride, or cobalt. In another embodiment, barrier layers 230 and 232 may be cobalt, iridium, or ruthenium, or alloys thereof with tungsten, boron, phosphorus, molybdenum, or rhenium.

[0041] Similar to Figure 2j , conductive layer 234 is formed on barrier layer 230. Similarly, conductive layer 236 is formed on barrier layer 232. Conductive layers 234 and 236 may be formed using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. Conductive layers 234 and 236 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials.

[0042] Similar to Figure 2j , conductive layers 234 and 236 and barrier layers 230 and 232 are patterned and etched according to the circuit pattern or layout of the interconnect substrate, that is, with conductive traces routed to provide electrical functions. Alternatively, the circuit layout can be formed by LDA. Portions of conductive layers 234 and 236 are electrically shared or electrically isolated, depending on the design and function of the electrical components added later. There may be multiple conductive layers such as 234 and 236 separated by multiple insulating layers such as 226 and 228.

[0043] Similar to Figure 2k , a protective or barrier layer 240 is conformally applied over the conductive layer 234 and the insulating layer 226. Likewise, a protective or barrier layer 242 is conformally applied over the conductive layer 236 and the insulating layer 228. The barrier layers 240 and 242 may be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The barrier layers 240 and 242 may be SiO2, Si3N4, SiON, Ta2O5, Al2O3, TiO2, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and non-conductive properties.

[0044] Similar to Figure 2l, insulating layer 246 is formed on barrier layer 240, and insulating layer 248 is formed on barrier layer 242. Insulating layers 246 and 248 may be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. Insulating layers 246 and 248 include one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, TiO2, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. Portions of insulating layers 246 and 248 are removed by an etching process or LDA to form openings or through holes 247 and 249, respectively. Opening 247 extends to conductive layer 234, and opening 249 extends to conductive layer 236.

[0045] Figure 3f The component in is a double-sided interconnect substrate 250 as an ETS, and also includes internal barrier layers 144, 146, 160, 162, 170, 172, 210, 212, 220, 222, 230, 232, 240 and 242 to inhibit electromigration. Figure 3g In FIG. 2 , double-sided interconnect substrate 230 is singulated along line 251 by removing core substrate 120 , leaving interconnect substrate 252 a and interconnect substrate 252 b .

[0046] exist Figure 3h In the embodiment, a portion of the conductive layer 130 and the barrier layer 144 on the interconnect substrate or ETS 252a are removed by an etching process (e.g., acid etching) to isolate the circuit pattern 137a. A similar etching operation is performed to remove a portion of the conductive layer 132 and the barrier layer 146 and isolate the circuit pattern 137b on the interconnect substrate or ETS 252b. Alternatively, as Figure 3i As shown in FIG. 1 , a grinder 254 is used to subject an interconnect substrate or ETS 252a to a grinding operation to remove a portion of the conductive layer 130 and the barrier layer 144, thereby isolating the circuit pattern 137a. A similar grinding operation is performed on the interconnect substrate or ETS 252b to remove a portion of the conductive layer 132 and the barrier layer 146, thereby isolating the circuit pattern 137b. The conductive layer 138 having the circuit pattern 137a is exposed from the interconnect substrate or ETS 252a. The conductive layers 138, 164, 214, and 234 primarily provide electrical communication or signal propagation through the interconnect substrate or ETS 252a.

[0047] Figure 3j Shown from Figure 3h14 is a schematic diagram of a semiconductor device of the present invention, wherein barrier layer 144 surrounds conductive layer 138, and barrier layer 160 is formed on a first portion of conductive layer 164, and barrier layer 170 is formed on a second portion of conductive layer 164. In interconnect substrate or ETS 252a, conductive layers 138, 164, 214, and 234 are subject to electromigration. As the structure and size of conductive layers in semiconductor devices decrease, the practical significance of electromigration becomes more apparent. Electromigration can cause defects, such as the formation of voids and hillocks, which can lead to reliability issues, such as open circuits or short circuits. The formation of defects is associated with the evolution of strain and stress within the conductive material. Electromigration between conductive layers 138, 164, 214, and 234 and portions thereof can adversely affect electrical communications and signal propagation through the interconnect substrate or ETS 182a. Barrier layers 144, 160, 170, 210, 220, 230, and 240 reduce or inhibit electromigration relative to conductive layers 138, 164, 214, and 234 in interconnect substrate or ETS 252a. For example, barrier layers 160 and 170 substantially surround or enclose conductive layer 164, in addition to a direct conductive path, to reduce or inhibit electromigration. Similarly, barrier layers 210 and 220 substantially surround or enclose conductive layer 214, in addition to a direct conductive path, to reduce or inhibit electromigration. Barrier layers 230 and 240 substantially surround or enclose conductive layer 234, in addition to a direct conductive path, to reduce or inhibit electromigration. Barrier layers 144, 160, 170, 210, 220, 230, and 240 increase the reliability of interconnect substrate or ETS 182a by reducing or inhibiting electromigration between internal conductive layers 138, 164, 214, and 234. In a similar manner, barrier layers 146, 162, 172, 212, 222, 232, and 242 inhibit electromigration relative to conductive layers 140, 166, 216, and 236 to increase the reliability of interconnect substrate or ETS 252b.

[0048] exist Figure 3k In, similar to Figure 2p-2q , electrical components 260a and 260b are disposed on interconnect substrate 182a and are electrically and mechanically connected to conductive layer 138 of ETS 252a. For example, electrical components 260a-260b may be similar to or made similar to those from Figure 1c The semiconductor die 104 is shown with the bumps 114 oriented toward the conductive layer 138. The electrical components 260a-260b may be other semiconductor dies, semiconductor packages, surface mount devices, RF components, discrete electrical devices, or integrated passive devices (IPDs).

[0049] Conductive bump material is deposited into through hole 247 above conductive layer 234 on interconnect substrate or ETS 252a using evaporation, electrolytic plating, electroless plating, ball drop or screen printing process. Bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combination thereof, with optional flux solution. For example, bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. Use suitable attachment or bonding process to bond bump material to conductive layer 234. In one embodiment, bump material is reflowed by heating material above its melting point to form ball or bump 264. In one embodiment, bump 264 is formed on UBM having wetting layer, barrier layer and adhesive layer. Bump 264 can also be compression bonded or thermocompression bonded to conductive layer 234. Bump 264 represents a type of interconnect structure that can be formed on conductive layer 234. Interconnect structure can also use bonding wire, conductive glue, columnar bump, micro bump or other electrical interconnect. The combination of interconnect substrate or ETS 252 a and electrical components 260 a - 260 b forms a semiconductor package 270 .

[0050] Figure 4 Electrical device 400 is illustrated having a chip carrier substrate or PCB 402 with a plurality of semiconductor packages disposed on a surface of PCB 402, including semiconductor packages 194 and 270. Electrical device 400 may have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application.

[0051] The electrical device 400 may be a stand-alone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, the electrical device 400 may be a subcomponent of a larger system. For example, the electrical device 400 may be a part of a tablet computer, a cellular phone, a digital camera, a communication system, or other electrical device. Alternatively, the electrical device 400 may be a graphics card, a network interface card, or other signal processing card that may be inserted into a computer. The semiconductor package may include a microprocessor, a memory, an ASIC, a logic circuit, an analog circuit, an RF circuit, a discrete device, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for the product to be accepted by the market. The distance between semiconductor devices may be reduced to achieve higher density.

[0052] exist Figure 4 In the embodiment of the present invention, PCB 402 provides a general substrate for structural support and electrical interconnection of semiconductor packages disposed on the PCB. Conductive signal traces 404 are formed on the surface or within the layers of PCB 402 using evaporation, electrolytic plating, electroless plating, screen printing or other suitable metal deposition processes. Signal traces 404 provide electrical communication between each semiconductor package, mounted components and other external system components. Traces 404 also provide power and ground connections to each semiconductor package.

[0053] In some embodiments, the semiconductor device has two packaging levels. The first level packaging is a technology for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second level packaging involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have only a first level packaging, wherein the die is mechanically and electrically directly disposed on the PCB. For purposes of illustration, several types of first level packaging are shown on PCB 402, including bond wire packaging 406 and flip chip 408. In addition, several types of second level packaging including ball grid array (BGA) 410, bump chip carrier (BCC) 412, land grid array (LGA) 416, multi-chip module (MCM) or SIP module 418, quad flat no-lead package (QFN) 420, quad flat package 422, embedded wafer level ball grid array (eWLB) 424 and wafer level chip scale package (WLCSP) 426 are shown to be disposed on PCB 402. In one embodiment, eWLB 424 is a fan-out wafer level package (Fo-WLP) and WLCSP 426 is a fan-in wafer level package (Fi-WLP). Depending on the system requirements, any combination of semiconductor packages configured with first and second level packaging styles and other electrical components can be connected to PCB 402. In some embodiments, electrical device 400 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electrical devices and systems. Because semiconductor packages include complex functions, electrical devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting device is less likely to fail and is less expensive to manufacture, resulting in a lower cost to the consumer.

[0054] While one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations may be made to those embodiments without departing from the scope of the invention as set forth in the following claims.

Claims

1. A semiconductor device, comprising: an interconnect substrate including a first conductive layer and a first barrier layer formed on a first portion of the first conductive layer, and a second barrier layer formed on a second portion of the first conductive layer; and Electrical components are disposed on an interconnect substrate.

2. The semiconductor device according to claim 1, wherein The first barrier layer includes a conductive material.

3. The semiconductor device according to claim 1, wherein The second barrier layer includes a non-conductive material.

4. The semiconductor device according to claim 1, wherein: The interconnect structure further comprises: a second conductive layer coupled to the first conductive layer; a third barrier layer formed on the first portion of the second conductive layer; and A fourth barrier layer is formed on the second portion of the second conductive layer.

5. The semiconductor device according to claim 4, wherein: The interconnect structure also includes an insulating layer formed between the first conductive layer and the second conductive layer.

6. A semiconductor device comprising: an interconnect substrate including a first conductive layer and a first barrier layer formed on the first conductive layer; and Electrical components are disposed on an interconnect substrate.

7. The semiconductor device according to claim 6, wherein: The interconnect substrate also includes a second barrier layer formed on the first conductive layer.

8. The semiconductor device according to claim 6, wherein: The first barrier layer includes a conductive material, and the second barrier layer includes a non-conductive material.

9. The semiconductor device according to claim 6, wherein: The interconnect structure further comprises: a second conductive layer coupled to the first conductive layer; a third barrier layer formed on the second conductive layer; and A fourth barrier layer is formed on the second conductive layer.

10. The semiconductor device according to claim 9, wherein The interconnect structure also includes an insulating layer formed between the first conductive layer and the second conductive layer.

11. A method for manufacturing a semiconductor device, comprising: providing an interconnect substrate comprising a first conductive layer and a first barrier layer formed on a first portion of the first conductive layer, and a second barrier layer formed on a second portion of the first conductive layer; and Electrical components are disposed on the interconnect substrate. The method of claim 11 , wherein the first barrier layer comprises a conductive material. The method of claim 11 , wherein the second barrier layer comprises a non-conductive material.

14. The method of claim 11, wherein providing the interconnect structure further comprises: providing a second conductive layer coupled to the first conductive layer; forming a third barrier layer on the first portion of the second conductive layer; and A fourth barrier layer is formed on the second portion of the second conductive layer.

15. The method of claim 14, wherein providing an interconnect structure further comprises forming an insulating layer between the first conductive layer and the second conductive layer.

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