Alignment mark manufacturing method and alignment mark

Abstract

The alignment mark manufacturing method comprises the steps that a substrate is provided, the front face of the substrate is provided with a chip area and a mark area, the chip area is used for manufacturing a semiconductor device, the mark area is used for alignment between film layers when the semiconductor device is manufactured in the chip area, and then a functional layer covering the chip area and the mark area is formed; determining a target duty ratio of a front-layer alignment mark according to the thickness of the target cover layer, then forming the front-layer alignment mark in the functional layer of the mark region according to the determined target duty ratio, forming an interlayer dielectric layer, filling the front-layer alignment mark, and exposing the front-layer alignment mark in the process of forming a current-layer pattern of the chip region on the interlayer dielectric layer, and finally, a target cover layer covering the exposed surface of the exposed front-layer alignment mark is formed, a current-layer alignment mark with a certain duty ratio and a certain groove depth is obtained, a diffraction signal of the current-layer alignment mark is enhanced, and the overlay accuracy is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to an alignment mark manufacturing method and an alignment mark. Background Art

[0002] With the development of semiconductor technology, the device size of integrated circuit manufacturing process has gradually decreased according to Moore's Law, and the device density has continued to increase. As a result, the requirements for overlay accuracy between layers have become increasingly higher. The alignment mark in the metal layer is an important part of achieving overlay accuracy of the metal interconnect layer.

[0003] However, due to the extinction coefficient characteristics of metal, metal of a certain thickness will make the lithography machine unable to detect the diffraction signal of the alignment mark under the metal, resulting in large wafer alignment errors and low overlay accuracy. Therefore, how to improve the alignment accuracy of the metal layer alignment mark is one of the problems that need to be solved urgently. Summary of the invention

[0004] Based on this, it is necessary to provide an alignment mark manufacturing method and an alignment mark to address the problem of large alignment error of the metal layer alignment mark in the prior art.

[0005] In order to achieve the above-mentioned purpose, on the one hand, the present invention provides a method for making an alignment mark, comprising the following steps: providing a substrate, wherein the front side of the substrate has a chip area and a mark area located outside the chip area; forming at least one functional layer covering the chip area and the mark area; then determining the target duty ratio of a front layer alignment mark to be formed in the mark area of ​​the substrate according to the thickness of the target cover layer; then forming a front layer alignment mark located in the mark area and having a target duty ratio in at least one functional layer, wherein the front layer alignment mark exposes the substrate; then forming an interlayer dielectric layer, which at least fills the front layer alignment mark; in the process of forming a current layer pattern located in the chip area on the interlayer dielectric layer, exposing the front layer alignment mark; finally forming a target cover layer covering the exposed surface of the exposed front layer alignment mark to obtain the current layer alignment mark.

[0006] In one embodiment, the alignment mark manufacturing method includes: the functional layer includes a first dielectric layer and a second dielectric layer that are conformally stacked, wherein an etching selectivity ratio between the first dielectric layer and the second dielectric layer is greater than 1.

[0007] In one embodiment, the method for manufacturing an alignment mark includes: an etching selectivity ratio between the interlayer dielectric layer and the second dielectric layer is greater than 1.

[0008] In one embodiment, the method for manufacturing an alignment mark includes: the first dielectric layer includes silicon oxide; and / or the second dielectric layer includes tungsten.

[0009] In one embodiment, the method for making an alignment mark includes: forming a front layer alignment mark in at least one functional layer and forming a front layer pattern located in a chip region in at least one functional layer.

[0010] In one of the embodiments, a current layer pattern located in a chip area is formed on an interlayer dielectric layer, including: forming a photoresist layer covering the interlayer dielectric layer; patterning the photoresist layer to obtain a graphic photoresist layer, wherein the graphic photoresist layer includes a first opening pattern for defining the current layer pattern and a second opening pattern for exposing a mark area; etching the interlayer dielectric layer using the graphic photoresist layer as a mask to form a current layer pattern on the interlayer dielectric layer and expose a front layer alignment mark.

[0011] In one embodiment, the alignment mark manufacturing method includes: the target cover layer thickness is related to the target duty cycle and the width of the previous layer alignment mark.

[0012] In one embodiment, the alignment mark manufacturing method includes: a target duty cycle B, a target cover layer thickness T, and a width W of the layer alignment mark satisfy the expression: B=0.5+(2T / W).

[0013] In one embodiment, the method for manufacturing an alignment mark includes: in the process of forming a current layer pattern located in a chip region on an interlayer dielectric layer, controlling the height of the exposed front layer alignment mark by controlling the etching time.

[0014] The present invention also provides an alignment mark structure, comprising: a substrate, a front side of which has a chip area and a mark area located outside the chip area; at least one functional layer, covering the chip area and the mark area, at least one functional layer including a front layer alignment mark located in the mark area and having a target duty ratio; an interlayer dielectric layer, at least covering the substrate where the front layer alignment mark is exposed; a target cover layer, at least covering the exposed surface of the front layer alignment mark; the front layer alignment mark and the target cover layer located directly above the front layer alignment mark are used to jointly constitute the current layer alignment mark, and the thickness of the target cover layer is related to the target duty ratio.

[0015] The alignment mark manufacturing method and the alignment mark of the present invention have the following beneficial effects:

[0016] The alignment mark manufacturing method and alignment mark of the present invention provide a substrate having a chip area and a mark area located outside the chip area on the front side, the chip area is used to manufacture semiconductor devices, and the mark area can assist in aligning each layer structure with the previous layer when manufacturing the device, thereby improving the reliability of the device; at least one functional layer covering the chip area and the mark area is formed, and then a target duty ratio of a front layer alignment mark to be formed in the mark area of ​​the substrate is determined according to the thickness of the target cover layer, and then a front layer alignment mark located in the mark area and having a target duty ratio is formed in the at least one functional layer, and the front layer alignment mark is used as a reference for manufacturing subsequent film layer alignment marks, thereby facilitating subsequent alignment of each layer The alignment mark is made and overprinted; then an interlayer dielectric layer is formed, the interlayer dielectric layer at least fills the previous layer alignment mark, and in the process of forming the current layer pattern located in the chip area on the interlayer dielectric layer, the previous layer alignment mark is exposed to make the current layer alignment mark; finally, a target cover layer is formed to cover the exposed surface of the exposed previous layer alignment mark to obtain the current layer alignment mark, so that the obtained current layer alignment mark is similar in shape to the previous layer alignment mark and has a certain duty cycle, which is convenient for identification during overprinting, avoiding direct deposition of the target cover layer on the interlayer dielectric layer, resulting in unclear identification due to extinction of the target cover layer being too thick, thereby improving the alignment accuracy and ensuring the accuracy of overprinting. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 is a flow chart of a method for making an alignment mark provided in an embodiment;

[0019] Figure 2 A schematic diagram of a top view of a structure obtained in step S1000 in a method for manufacturing an alignment mark provided in an embodiment;

[0020] Figure 3a A schematic diagram of a cross-sectional structure of a structure obtained in step S2000 in a method for manufacturing an alignment mark provided in an embodiment;

[0021] Figure 3b A schematic diagram of a top view of a structure obtained in step S2000 in a method for manufacturing an alignment mark provided in an embodiment;

[0022] Figure 4a A schematic diagram of a cross-sectional structure of a mark area structure obtained in step S4000 in a method for manufacturing an alignment mark provided in an embodiment;

[0023] Figure 4bA schematic diagram of a top view of a structure obtained in step S4000 in a method for manufacturing an alignment mark provided in an embodiment;

[0024] Figure 5a A schematic diagram of the cross-sectional structure of the chip region structure obtained in step S5000 of the alignment mark manufacturing method provided in one embodiment;

[0025] Figure 5b A schematic diagram of a cross-sectional structure of a mark area structure obtained in step S5000 in a method for manufacturing an alignment mark provided in an embodiment;

[0026] Figure 5c A schematic diagram of a top view of a structure obtained in step S5000 in a method for manufacturing an alignment mark provided in an embodiment;

[0027] Figure 6a A schematic diagram of a cross-sectional structure of a chip region structure obtained in step S6000 of a method for manufacturing an alignment mark provided in an embodiment;

[0028] Figure 6b A schematic diagram of a cross-sectional structure of a mark area structure obtained in step S6000 of a method for manufacturing an alignment mark provided in an embodiment;

[0029] Figure 6c A schematic diagram of a cross-sectional structure of a mark area structure obtained in step S6000 of a method for manufacturing an alignment mark provided in an embodiment;

[0030] Figure 6d A schematic diagram of a top view of a structure obtained in step S6000 of a method for manufacturing an alignment mark provided in an embodiment;

[0031] Figure 7a A schematic diagram of a cross-sectional structure of a chip region structure obtained in step S6000 of a method for manufacturing an alignment mark provided in an embodiment;

[0032] Figure 7b A schematic diagram of a cross-sectional structure of a mark area structure obtained in step S6000 of a method for manufacturing an alignment mark provided in an embodiment;

[0033] Figure 7c A schematic diagram of a cross-sectional structure of a mark area structure obtained in step S6000 of a method for manufacturing an alignment mark provided in an embodiment;

[0034] Figure 7d A schematic diagram of a top view of a structure obtained in step S6000 of a method for manufacturing an alignment mark provided in an embodiment;

[0035] Figure 8a A schematic diagram of the cross-sectional structure of a chip region structure obtained in step S7000 in a method for manufacturing an alignment mark provided in an embodiment;

[0036] Figure 8b A schematic diagram of a cross-sectional structure of a mark area structure obtained in step S7000 in a method for manufacturing an alignment mark provided in an embodiment;

[0037] Figure 8c A schematic diagram of a cross-sectional structure of a mark area structure obtained in step S7000 in a method for manufacturing an alignment mark provided in an embodiment;

[0038] Figure 8d A schematic diagram of a top view of a structure obtained in step S7000 in a method for manufacturing an alignment mark provided in an embodiment;

[0039] Fig. 9 A schematic diagram of the cross-sectional structure of a patterned photoresist in a mark area in a method for manufacturing an alignment mark provided in an embodiment;

[0040] Fig.10 is a schematic diagram of a cross-sectional structure of an alignment mark in a method for manufacturing an alignment mark provided in an embodiment;

[0041] Fig.11a and Fig.11b A schematic diagram of a cross-sectional structure of a front-layer alignment mark structure with different target duty ratios in an alignment mark manufacturing method provided in an embodiment;

[0042] Fig.12a and Figure 12b A schematic diagram of a cross-sectional structure of an alignment mark of a current layer with different target duty ratios in a method for manufacturing an alignment mark provided in an embodiment;

[0043] Fig.13 A diffraction efficiency diagram of an alignment mark of a current layer with different target duty ratios in a method for manufacturing an alignment mark provided in an embodiment;

[0044] Figure 14a-14b A schematic diagram of the cross-sectional structure of a front-layer alignment mark structure with different groove depths in an alignment mark manufacturing method provided in an embodiment;

[0045] Figure 15a-Figure 15b A schematic diagram of the cross-sectional structure of a layer of alignment marks with different groove depths in a method for manufacturing an alignment mark provided in an embodiment;

[0046] Fig.16 It is a diffraction efficiency diagram of the current layer alignment marks with different groove depths in the alignment mark manufacturing method provided in one embodiment.

[0047] Description of reference numerals:

[0048] 1. Chip area; 2. Marking area 2; 3. Marking area 3; 10. Substrate; 200. Functional layer; 201. First dielectric layer; 202. Second dielectric layer; 30. Interlayer dielectric layer; 40. Photoresist layer; 500. Target cover layer; 60. Patterned photoresist. DETAILED DESCRIPTION

[0049] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0051] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0052] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0053] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0054] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0055] Please refer to Figure 1 The present invention provides a method for making an alignment mark, comprising the following steps:

[0056] Step S1000: providing a substrate, wherein the front side of the substrate has a chip area and a marking area located outside the chip area;

[0057] Step S2000: forming at least one functional layer covering the chip area and the marking area;

[0058] Step S3000: determining a target duty ratio of a front layer alignment mark to be formed in a mark area of ​​the substrate according to a target cover layer thickness;

[0059] Step S4000: forming a front-layer alignment mark located in a mark area and having a target duty ratio in at least one functional layer, wherein the front-layer alignment mark exposes the substrate;

[0060] Step S5000: forming an interlayer dielectric layer, wherein the interlayer dielectric layer at least fills the front layer alignment mark;

[0061] Step S6000: during the process of forming the current layer pattern located in the chip area on the interlayer dielectric layer, exposing the front layer alignment mark;

[0062] Step S7000: forming a target cover layer covering the exposed surface of the previous layer alignment mark to obtain the current layer alignment mark.

[0063] In step S1000, the chip area is used to make semiconductor devices, the mark area is used to provide alignment marks during overlay, and the substrate is used to provide support for the device layer and the alignment mark film layer. The substrate can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be a silicon substrate, a silicon germanium substrate, a silicon germanium carbon substrate, a silicon carbide substrate, a gallium arsenide substrate, an indium arsenide substrate, an indium phosphide substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate can be a layered substrate including silicon / silicon carbide, silicon on insulator or silicon germanium on insulator. Therefore, the type of substrate should not limit the scope of protection of the present disclosure.

[0064] In the above embodiment, a substrate is first provided to provide support for subsequent film layers. The front side of the substrate has a chip area and a mark area. The chip area is used to make semiconductor devices, and the mark area is used to align film layers when making semiconductor devices in the chip area. Then, a functional layer covering the chip area and the mark area is formed. The target duty ratio of the front layer alignment mark is determined according to the thickness of the target cover layer to ensure the duty ratio of the current layer alignment mark finally formed. Then, according to the determined target duty ratio, a front layer alignment mark is formed in the functional layer of the mark area as a reference for forming the current layer alignment mark. Then, an interlayer dielectric layer is formed to fill the front layer alignment mark. In the process of forming the current layer pattern of the chip area on the interlayer dielectric layer, the front layer alignment mark is exposed. Finally, a target cover layer is formed to cover the exposed surface of the exposed front layer alignment mark, so as to obtain a current layer alignment mark with a certain duty ratio and a certain groove depth, so as to enhance the diffraction signal of the current layer alignment mark, avoid the decrease in diffraction efficiency caused by excessive thickness of the target cover layer and the extinction effect, and improve the accuracy of alignment.

[0065] In one embodiment, please continue to refer to Figure 1 , Figure 2 , Figure 3a as well as Figure 3b It should be noted that the thickness direction of the substrate 10 can be parallel to the OZ direction, the groove structure of the alignment mark extends in a direction parallel to OX, and the mark area 2 and the mark area 3 are on both sides of the chip area 1 in a direction parallel to OY. The following embodiments will not be repeated for simplicity. The functional layer 200 in step S2000 includes a conformally stacked first dielectric layer 201 and a second dielectric layer 202, wherein the etching selectivity ratio of the first dielectric layer 201 to the second dielectric layer 202 is greater than 1, so that the first dielectric layer 201 is etched and removed with the second dielectric layer 202 as an etching stop layer, and the larger the etching selectivity ratio of the first dielectric layer 201 to the second dielectric layer 202, the better the etching effect. The material of the first dielectric layer 201 includes but is not limited to one or more of silicon oxide, silicon, and silicon nitride; the material of the second dielectric layer 202 includes but is not limited to one or more of metal materials such as aluminum, chromium or copper. The use of metal materials can improve the reflectivity of the alignment mark and enhance the accuracy of overlay.

[0066] The step S2000 forms at least one functional layer 200 covering the chip area 1, the marking area 2 and the marking area 3, including:

[0067] Step S2100: depositing a first dielectric layer 201, wherein the first dielectric layer 201 covers the chip region 1, the marking region 2 and the marking region 3;

[0068] Step S2200: forming a second dielectric layer 202 on the first dielectric layer 201;

[0069] Step S2300: repeat steps S2100 and S2200 until the thickness of the functional layer 200 meets the requirement.

[0070] Please continue to refer to Figure 2 , Figure 3a and Figure 3b, chip area 1 is an area for making semiconductor devices, mark area 2 is an area for making alignment marks in a certain embodiment, and mark area 3 is an area for making alignment marks in another embodiment of the present application. As an example, a functional layer 200 of three layers of a first dielectric layer 201 and a second dielectric layer 202 can be formed on the substrate 10, and other layers of functional layers 200 can also be formed according to actual alignment requirements. The deposition process in step S2100 may include but is not limited to at least one of a chemical vapor deposition process (Chemical Vapor Deposition, CVD), an atomic layer deposition process (Atomic Layer Deposition, ALD), a high density plasma deposition (High Density Plasma, HDP) process, a plasma enhanced deposition process (Plasma Enhanced Chemical Vapor Deposition, PECVD) and a spin-on dielectric layer (Spin-on Dielectric, SOD) process.

[0071] In one embodiment, please refer to Figure 1 , Figure 4a and Figure 4b , forming a front layer alignment mark located in a mark area and having a target duty ratio in at least one functional layer 200, comprising:

[0072] Step S4100: forming a photoresist layer covering the functional layer 200;

[0073] Step S4200: patterning the photoresist layer to obtain a graphic photoresist layer;

[0074] Step S4300: etching the functional layer 200 with a patterned photoresist layer as a mask to form a front-layer alignment mark in the mark area.

[0075] Among them, in step S4200, patterning the photoresist layer includes: selecting a suitable mask to expose the photoresist layer according to the target duty cycle during exposure, and then using a developer to develop the exposed photoresist layer, the exposed area will be dissolved, so that the photoresist layer forms a groove structure corresponding to the alignment mark of the previous layer, and then using a suitable etching method to etch the functional layer 200, and transfer the groove structure to the functional layer 200. When etching the functional layer 200 using the patterned photoresist layer as a mask, dry etching can be used, such as plasma etching and electron beam etching, or wet etching can be used, such as using an acidic solution such as hydrofluoric acid and nitric acid to react with the functional layer 200, or using an alkaline solution such as potassium hydroxide and ammonia to etch. Because the functional layer is a conformal stacked film structure composed of the first dielectric layer 201 and the second dielectric layer 202, it can also be etched in a combination of multiple processes. In actual etching, it is necessary to select according to the materials of the first dielectric layer 201 and the second dielectric layer 202.

[0076] In one embodiment, please refer to Figure 2 as well as Figure 5a-5c The method for manufacturing the alignment mark includes: an etching selectivity ratio between the interlayer dielectric layer 30 and the second dielectric layer 212 is greater than 1.

[0077] The interlayer dielectric layer 30 may be made of silicon dioxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), aluminum oxide (Al2O3), aluminum oxynitride (AlON) and a combination thereof, and is used to isolate the target cap layer from the functional layer 200 in the chip region. When depositing the interlayer dielectric layer 30, the LPCVD process may be used to introduce the reaction gas into the reaction chamber, and the interlayer dielectric layer 30 may be deposited under a high temperature and low pressure environment. At the same time, the gas flow rate, temperature and pressure parameters may be controlled to control the growth rate and thickness of the interlayer dielectric layer 30. The LPCVD process may improve the growth uniformity and film quality of the interlayer dielectric layer 30.

[0078] In the above embodiment, the etching selectivity ratio of the interlayer dielectric layer 30 to the second dielectric layer 212 is made greater than 1, so as to avoid damaging the film structure of the second dielectric layer 212 when the layer pattern is subsequently made in the chip area, and also facilitate forming a groove of a certain depth when etching the interlayer dielectric layer 30 in the mark area.

[0079] In one embodiment, please continue to refer to Figure 3a , the alignment mark manufacturing method includes: the first dielectric layer 201 includes silicon oxide; and / or the second dielectric layer 202 includes tungsten.

[0080] In one embodiment, please continue to refer to Figure 4a and Figure 4b, while forming the front layer alignment mark in at least one functional layer 200, a front layer pattern located in the chip area is formed in at least one functional layer 200. In this embodiment, since there is no need for patterning of the front layer pattern of the semiconductor device, when the front layer alignment mark is formed by etching, the patterned photoresist needs to cover the functional layer 200 in the chip area to avoid etching the functional layer 200 in the chip area. In other embodiments, if the device requires the production of a front layer pattern with a certain pattern, a patterned photoresist with a certain pattern can also be used as needed to form the front layer pattern in the chip area while forming the front layer alignment mark.

[0081] In one embodiment, please refer to Figure 2 as well as Figure 6a-Figure 7d , forming a current layer pattern located in the chip area on the interlayer dielectric layer 30, including:

[0082] Step S6100: forming a photoresist layer 40 covering the interlayer dielectric layer 30;

[0083] Step S6200: patterning the photoresist layer 40 to obtain a patterned photoresist layer 40, wherein the patterned photoresist layer 40 includes a first opening pattern for defining a layer pattern and a second opening pattern for exposing a marking area;

[0084] Step S6300 : using the patterned photoresist layer 40 as a mask to etch the interlayer dielectric layer 30 , forming a current layer pattern on the interlayer dielectric layer 30 and exposing a previous layer alignment mark.

[0085] In step S6100, a photoresist material layer can be coated on the top surface of the interlayer dielectric layer 30, and after a series of steps such as exposure, development, photolithography and etching, the patterned photoresist layer 40 in step S6200 is obtained; in step S6200, in a certain embodiment, the patterned photoresist layer 40 has a first opening pattern that defines the current layer pattern, and the patterned photoresist layer 40 completely covers the mark area; in another embodiment of the present application, the patterned photoresist layer 40 has a first opening pattern that defines the current layer pattern, and a second opening pattern for exposing the mark area. Compared with completely covering the mark area with the patterned photoresist layer 40, exposing the mark area facilitates opening the previous layer alignment mark during subsequent etching, thereby further making the current layer alignment mark.

[0086] In step S6300, please continue to refer to Figure 7a-7dIt can be seen that, in a certain embodiment, a patterned photoresist layer 40 is used to completely cover the mark area, resulting in that when the current layer pattern 3 is formed on the interlayer dielectric layer 30, the interlayer dielectric layer 30 in the mark area is not etched, and the front layer alignment mark is completely blocked by the interlayer dielectric layer 30; in another embodiment of the present application, the patterned photoresist layer 40 has a first opening pattern that defines the current layer pattern, and a second opening pattern for exposing the mark area. While the current layer pattern is formed in the chip area, the interlayer dielectric layer 30 in the mark area is etched to expose the front layer alignment mark, and the etching depth of the etched interlayer dielectric layer 30 is associated with the wavelength of the diffracted light wave used during alignment.

[0087] In one embodiment, please refer to Figure 8a-8d In the chip area, a target capping layer 500 is used to fill the current layer pattern to form a metal interconnection layer. The material of the target capping layer 500 can be one or more of cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium TaTi, tungsten nitride (WN), copper (Cu) and aluminum (Al), which is not limited in the present disclosure. In a certain embodiment, the target capping layer 500 is deposited on the unetched interlayer dielectric layer 30 in the mark area, and the target capping layer 500 completely covers the interlayer dielectric layer 30. Since the target capping layer 500 has a certain The thickness is small and has an extinction effect, the diffraction efficiency during overlay is low, and the alignment accuracy is low; in another embodiment of the present application, a target cover layer 500 is deposited on the interlayer dielectric layer 30 etched in the mark area and the exposed front layer alignment mark, the front layer alignment mark and the target cover layer 500 covering the front layer alignment mark constitute a current layer alignment mark, the current layer alignment mark has a certain duty cycle and groove depth, and can be directly observed, avoiding unclear identification caused by the covering of the front layer alignment mark, facilitating identification and alignment during overlay, and improving the accuracy of overlay.

[0088] In one embodiment, please refer to Fig. 9 and Fig.10 For the mark area completely covered by the target cover layer 500, the patterned photoresist 60 can be used to etch the portion of the target cover layer 500 with the front-layer alignment mark under the film, exposing the interlayer dielectric layer 30 with the front-layer alignment mark under the film, thereby avoiding the decrease in diffraction efficiency caused by the target cover layer 500 covering the front-layer alignment mark, thereby improving the alignment accuracy.

[0089] In one embodiment, please continue to refer to Figure 8c The alignment mark manufacturing method includes: the target cover layer 500 thickness T is associated with the target duty ratio and the width W of the front layer alignment mark. The target duty ratio is the ratio of the groove width of the front layer alignment mark area to the width W of the front layer alignment mark, and the difference between the target duty ratio and the ratio of the target cover layer 500 thickness and the width W of the front layer alignment mark is a fixed value.

[0090] In one embodiment, please continue to refer to Figure 8c , the target duty cycle B and the target cover layer thickness T and the width W of the alignment mark of the layer satisfy the expression: B=0.5+(2T / W). For example, the target cover layer thickness T is 200nm, and the width W of the alignment mark is 3200nm. It can be known that the target duty cycle B is 0.625. In other embodiments, the target cover layer thickness T can be 50nm-2800nm, for example, it can be 100nm, 300nm, 500nm, 600nm, 700nm, 1000nm, 1500nm, 2000nm, 2500nm, etc.; the width W of the alignment mark area ranges from 3000nm-5000nm, for example, 3300nm, 3500nm, 3700nm, 4000nm, 4500nm, 4800nm, etc., so the target cover layer thickness T and the width W of the alignment mark area should not limit the protection scope of the present disclosure.

[0091] In one embodiment, please refer to Figure 11a-Figure 13 When the thickness of the target cover layer 500 is constant, the diffraction efficiency of the layer alignment mark is different for different target duty ratios. For example, when the target cover layer thickness 500 is 200nm and the width of the alignment mark is 3200nm, the target duty ratio is 0.775, and the diffraction efficiency for light with a wavelength of 633nm is 0.2. When the target duty ratio is 0.625, the diffraction efficiency for light with a wavelength of 633nm is the highest, that is, the higher the alignment accuracy.

[0092] In one embodiment, please refer to Figure 14a-Figure 16 When the target cap layer thickness is constant at 500, in the process of forming the current layer pattern located in the chip area on the interlayer dielectric layer 30, the height of the exposed front layer alignment mark changes in a sinusoidal function with the diffraction efficiency. The etching depth can be determined according to the diffraction wavelength during actual alignment, and the etching depth with the highest diffraction efficiency can be selected to improve the alignment accuracy.

[0093] In one embodiment, the alignment mark manufacturing method includes: in the process of forming the current layer pattern located in the chip area on the interlayer dielectric layer, controlling the height of the exposed front layer alignment mark by controlling the etching time. It can be known that the longer the etching time, the higher the height of the exposed front layer alignment mark. Since the height of the exposed alignment mark changes sinusoidally with the diffraction efficiency, the etching time is matched according to the thickness of the target cover layer to achieve a suitable diffraction efficiency.

[0094] It should be understood that although Figure 1The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0095] Please refer to Figure 8c The present invention also provides an alignment mark structure, comprising: a substrate 10, a front side of which has a chip area and a mark area located outside the chip area; at least one functional layer 200, covering the chip area and the mark area, at least one functional layer 200 including a front-layer alignment mark located in the mark area and having a target duty ratio; an interlayer dielectric layer 30, at least covering the substrate 10 where the front-layer alignment mark is exposed; a target cover layer 500, at least covering the exposed surface of the front-layer alignment mark; the front-layer alignment mark and the target cover layer 500 located directly above the front-layer alignment mark are used to jointly constitute the current-layer alignment mark, and the thickness of the target cover layer 500 is related to the target duty ratio.

[0096] Please continue to refer to Figure 8c, wherein the functional layer includes a conformally stacked first dielectric layer 201 and a second dielectric layer 202, and the number of stacked layers is related to the actual device requirements and the film thickness of the first dielectric layer 201 and the second dielectric layer 202. To ensure that the diffraction efficiency meets the requirements, the groove depth of the alignment mark needs to be controlled within a certain range, and the appropriate diffraction efficiency is achieved by the film thickness of the first dielectric layer 201 and the second dielectric layer 202 and the number of stacked layers. The material of the first dielectric layer 201 includes but is not limited to one or more of silicon, silicon oxide, and silicon nitride; the material of the second dielectric layer 202 includes but is not limited to one or more of metal materials such as aluminum, chromium or copper; the material of the interlayer dielectric layer 30 can be silicon dioxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), aluminum oxide (Al2O3), aluminum oxynitride (AlON) and combinations thereof. In addition, the etching selectivity ratio of the first dielectric layer 201 to the second dielectric layer 202 is greater than 1, and the etching selectivity ratio of the interlayer dielectric layer 30 to the second dielectric layer 202 is also greater than 1, so that the second dielectric layer 202 is used as an etching stop layer during etching to obtain a current layer alignment mark with a certain groove depth. For example, when the material of the second dielectric layer 202 is tungsten and the material of the interlayer dielectric layer 30 is silicon oxide, plasma etching can be used, and hydrogen fluoride is introduced into the reaction chamber, and a certain concentration of argon gas can also be introduced, wherein argon gas is used as a diluent of the etching gas, and the concentration of the etching gas is controlled to an appropriate concentration, thereby controlling the etching rate and the etching selectivity ratio. At the same time, argon gas has good thermal conductivity and can quickly take away the heat generated during plasma etching, thereby controlling the temperature of the etching process and ensuring the stability of the etching process. Hydrogen fluoride is used as an etching gas to ionize fluorine ions and hydrogen ions to react with silicon oxide to form volatile fluorides. The reaction rate of hydrogen fluoride with tungsten is slow, and the etching selectivity is relatively high, ensuring that the alignment mark of the previous layer will not be damaged when etching the interlayer dielectric layer 30.

[0097] Please continue to refer to Figure 8c and Fig.13 , the target duty cycle B of the front layer alignment mark, the thickness T of the target cover layer 500, and the width W of the current layer alignment mark satisfy the formula B=0.5+(2T / W). Under this relationship, the target cover layer 500 with a thickness of T is used to cover the exposed front layer alignment mark, and the duty cycle of the current layer alignment mark is 0.5. The diffraction efficiency is the highest for a wavelength of 633nm, that is, the higher the accuracy of the alignment mark. In addition, when the wavelength of the alignment light wave during overlay is other values, such as 852nm and 780nm, the corresponding duty cycle of the current layer alignment mark can also be selected according to the actual alignment wavelength.

[0098] In the above embodiment, the substrate provides support for subsequent film layers, and the substrate has a chip area for forming a device and a marking area for alignment marking, at least one functional layer covers the chip area and the marking area, at least one functional layer includes a front-layer alignment mark located in the marking area and having a target duty ratio, the interlayer dielectric layer at least covers the substrate exposed by the front-layer alignment mark; the target cover layer at least covers the exposed surface of the front-layer alignment mark; the front-layer alignment mark and the target cover layer located directly above the front-layer alignment mark are used to jointly constitute the current-layer alignment mark, and the thickness of the target cover layer is related to the target duty ratio, and a target cover layer of a certain thickness deposited on the interlayer dielectric layer according to the target duty ratio and the area width of the current-layer alignment mark improves the diffraction efficiency of the current-layer alignment mark, and the appropriate target duty ratio and target cover layer thickness can also be selected according to different diffraction wavelengths, thereby improving the flexibility of alignment mark production. In addition, the alignment mark production steps and the chip area production steps can be carried out simultaneously, which reduces the waste of manpower and material resources to a certain extent.

[0099] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0100] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for making an alignment mark, characterized in that: The steps include: Providing a substrate, wherein the front side of the substrate has a chip area and a marking area located outside the chip area; forming at least one functional layer covering the chip area and the marking area; determining a target duty cycle of a front layer alignment mark to be formed in the mark area according to a thickness of a target cover layer; forming a front layer alignment mark located in the mark area and having the target duty ratio in the at least one functional layer, wherein the front layer alignment mark exposes the substrate; forming an interlayer dielectric layer, wherein the interlayer dielectric layer at least fills the front layer alignment mark; During the process of forming the current layer pattern located in the chip area on the interlayer dielectric layer, exposing the front layer alignment mark; The target cover layer is formed to cover the exposed surface of the previous layer alignment mark, thereby obtaining the current layer alignment mark.

2. The method for making an alignment mark according to claim 1, wherein: The functional layer includes a first dielectric layer and a second dielectric layer which are conformally stacked, and an etching selectivity ratio between the first dielectric layer and the second dielectric layer is greater than 1.

3. The method for making an alignment mark according to claim 2, wherein: An etching selectivity ratio between the interlayer dielectric layer and the second dielectric layer is greater than 1.

4. The method for making an alignment mark according to claim 2, wherein: The first dielectric layer is / includes silicon oxide; and / or The second dielectric layer is / includes tungsten.

5. The method for making an alignment mark according to any one of claims 1 to 4, characterized in that: While the front layer alignment mark is formed in the at least one functional layer, a front layer pattern located in the chip region is formed in the at least one functional layer.

6. The method for making an alignment mark according to any one of claims 1 to 4, characterized in that: Forming the current layer pattern located in the chip area on the interlayer dielectric layer includes: forming a photoresist layer covering the interlayer dielectric layer; Patterning the photoresist layer to obtain a patterned photoresist layer, wherein the patterned photoresist layer includes a first opening pattern for defining the current layer pattern and a second opening pattern for exposing the marking area; The interlayer dielectric layer is etched using the patterned photoresist layer as a mask to form the current layer pattern on the interlayer dielectric layer and expose the front layer alignment mark.

7. The method for making an alignment mark according to any one of claims 1 to 4, characterized in that: The target capping layer thickness is related to the target duty cycle and the width of the front layer alignment mark.

8. The method for making an alignment mark according to claim 6, wherein: The target duty cycle B, the target cover layer thickness T, and the width W of the current layer alignment mark satisfy the following expression: B=0.5+(2T / W).

9. The method for making an alignment mark according to any one of claims 1 to 4, characterized in that: In the process of forming the current layer pattern located in the chip area on the interlayer dielectric layer, the height of the exposed front layer alignment mark is controlled by controlling the etching time.

10. An alignment mark, characterized in that: include: A substrate, the front side of which has a chip area and a marking area located outside the chip area; at least one functional layer, covering the chip area and the mark area, wherein the at least one functional layer includes a front-layer alignment mark located in the mark area and having a target duty ratio; an interlayer dielectric layer, at least covering the substrate where the front layer alignment mark is exposed; a target cover layer, covering at least the exposed surface of the front layer alignment mark; The front layer alignment mark and the target cover layer located directly above the front layer alignment mark are used to jointly constitute a current layer alignment mark, and the thickness of the target cover layer is associated with the target duty cycle.

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