Static frequency converter triggering method, controller, system, storage medium and product

Abstract

The present application discloses a static frequency converter triggering method, controller, system, storage medium and product, which relates to the technical field of static frequency converter, including: determining a pulse sequence signal of a static frequency converter; wherein the pulse sequence signal includes a grid-side pulse sequence signal and a unit-side pulse sequence signal; at the rising edge of the grid-side pulse sequence signal, clock synchronizing the unit-side pulse sequence signal with the grid-side pulse sequence signal to obtain a synchronized unit-side pulse sequence signal; based on the synchronized unit-side pulse sequence signal and the grid-side pulse sequence signal, triggering the static frequency converter. The present application can improve the stability of the generator set startup control.

Description

Technical Field

[0001] The present application relates to the technical field of static frequency converters, and in particular to a static frequency converter triggering method, controller, system, storage medium and product. Background Art

[0002] The synchronous generator units of pumped storage power stations are usually started by SFC (Static Frequency Converter). In the related technology, the thyristors of the three-phase rectifier bridge on the grid side and the three-phase inverter bridge on the unit side of the SFC are generally pulse-triggered and controlled. However, due to the frequency asynchronism between the grid side and the unit side, the current on the unit side cannot be started quickly for a long time, affecting the stability of the generator set start-up control. Therefore, it is necessary to seek a more stable SFC pulse triggering method. Summary of the invention

[0003] The main purpose of the present application is to provide a static inverter triggering method, controller, system, storage medium and product, aiming to solve the technical problem of poor stability of generator set starting control in related technologies.

[0004] To achieve the above object, the present application proposes a static frequency converter triggering method, the static frequency converter triggering method comprising:

[0005] Determine the pulse train signal of the static frequency converter; wherein the pulse train signal includes a grid-side pulse train signal and a unit-side pulse train signal;

[0006] At the rising edge of the grid-side pulse train signal, the unit-side pulse train signal is clock-synchronized with the grid-side pulse train signal to obtain a synchronized unit-side pulse train signal;

[0007] The static frequency converter is triggered based on the synchronized unit-side pulse train signal and the grid-side pulse train signal.

[0008] In one embodiment, the step of determining the pulse train signal of the static frequency converter comprises:

[0009] For each thyristor in the three-phase converter bridge on the grid side and the unit side of the static frequency converter, an initial pulse enable signal of the thyristor is obtained to obtain a first pulse enable signal;

[0010] Determine initial pulse enable signals respectively corresponding to two thyristors that are out of phase with the thyristor and do not share a common pole, and obtain a second pulse enable signal and a third pulse enable signal;

[0011] Performing an AND logic operation on the first pulse enable signal, the second pulse enable signal and the third pulse enable signal to obtain a first logic pulse signal and a second logic pulse signal;

[0012] Performing an OR logic operation on the first logic pulse signal and the second logic pulse signal to obtain a pulse signal corresponding to each thyristor;

[0013] Based on all pulse signals, a pulse train signal is determined.

[0014] In one embodiment, at the rising edge of the grid-side pulse train signal, the unit-side pulse train signal is clock-synchronized with the grid-side pulse train signal to obtain the synchronized unit-side pulse train signal, comprising:

[0015] At the rising edge of the grid-side pulse train signal, the timer corresponding to the unit-side pulse train signal is controlled to be reset to synchronize the clocks of the unit-side pulse train signal and the grid-side pulse train signal to obtain a synchronized unit-side pulse train signal.

[0016] In one embodiment, the step of triggering the static frequency converter based on the synchronized unit-side pulse train signal and the grid-side pulse train signal includes:

[0017] The synchronized pulse sequence signal of the unit side and the pulse sequence signal of the grid side are modulated to obtain a modulated pulse sequence signal of the unit side and a modulated pulse sequence signal of the grid side;

[0018] The static frequency converter is triggered based on the modulated pulse train signal on the unit side and the modulated pulse train signal on the grid side.

[0019] In one embodiment, the period of the modulated pulse train signal on the unit side and the modulated pulse train signal on the grid side is 1 ms, and the duty cycle is 50%.

[0020] In addition, to achieve the above objectives, the present application also proposes a controller, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the static frequency converter triggering method as described above.

[0021] In addition, to achieve the above purpose, the present application also proposes a static frequency converter triggering system, the static frequency converter triggering system comprising:

[0022] A controller such as the one described above;

[0023] Static frequency converter, connected to the controller.

[0024] In one embodiment, the static frequency converter triggering system further includes:

[0025] A signal input module, used for inputting a light trigger signal;

[0026] The level conversion module is connected to the signal input module and the controller respectively, and is used for converting the light trigger signal into an initial pulse enable signal, and outputting the initial pulse enable signal to the controller.

[0027] In addition, to achieve the above purpose, the present application also proposes a storage medium, which is a computer-readable storage medium. A computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the static frequency converter triggering method as described above are implemented.

[0028] In addition, to achieve the above-mentioned purpose, the present application also proposes a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of the static frequency converter triggering method as described above are implemented.

[0029] One or more technical solutions proposed in this application have at least the following technical effects:

[0030] The static frequency converter triggering method provided by the present application can synchronize the clock of the unit-side pulse sequence signal with the grid-side pulse sequence signal at the rising edge of the grid-side pulse sequence signal corresponding to the static frequency converter to obtain the synchronized unit-side pulse sequence signal; thereby, the static frequency converter can be triggered based on the synchronized unit-side pulse sequence signal and the grid-side pulse sequence signal. The present application ensures that the grid-side and the unit-side can operate synchronously when the thyristor of the SFC is triggered by forcibly synchronizing the pulse sequence signals on the grid side and the unit side, thereby avoiding the problem that the current cannot be started quickly due to the asynchronous frequency on both sides, thereby improving the stability of the generator set start-up control. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 A flow chart of the first embodiment of the static frequency converter triggering method of the present application;

[0034] Figure 2 It is a detailed flow chart of step S100;

[0035] Figure 3 The figure is a schematic diagram of the topological structure of a 12-6 pulse SFC main circuit;

[0036] Figure 4 The schematic diagram is a principle diagram of an exemplary static frequency converter triggering method;

[0037] Figure 5 A schematic diagram of the controller structure of the hardware operating environment involved in the static frequency converter triggering in the embodiment of the present application;

[0038] Figure 6 The schematic diagram of the structure of the static frequency converter trigger system corresponding to the 12-6 pulse SFC.

[0039] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0040] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0041] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0042] The main solution of the embodiment of the present application is: determining the pulse sequence signal of the static frequency converter; wherein the pulse sequence signal includes a grid-side pulse sequence signal and a unit-side pulse sequence signal; at the rising edge moment of the grid-side pulse sequence signal, performing clock synchronization on the unit-side pulse sequence signal and the grid-side pulse sequence signal to obtain a synchronized unit-side pulse sequence signal; triggering the static frequency converter based on the synchronized unit-side pulse sequence signal and the grid-side pulse sequence signal.

[0043] With the advancement of the construction of new wind and solar power systems, large-scale unstable electricity can be connected to the power grid through converters, which poses a great challenge to the balance of supply and demand of the power grid. Therefore, it is necessary to build a large number of pumped storage power stations for high-power energy storage. The synchronous machine units of pumped storage power stations are usually started by SFC.

[0044] In the related art, the thyristors of the three-phase rectifier bridge on the grid side and the three-phase inverter bridge on the unit side of the SFC are generally pulse-triggered and controlled. However, due to the frequency asynchrony between the grid side and the unit side, the current on the unit side cannot be started quickly for a long time, affecting the stability of the generator set starting control. Therefore, it is necessary to find an SFC pulse triggering method with higher stability.

[0045] The present application provides a solution that can force clock synchronization of the pulse sequence signals corresponding to the SFC grid side and the unit side, respectively, to ensure that when the thyristor in the SFC is triggered, the grid side and the unit side can be coordinated, thereby avoiding the problem of the current being unable to start quickly due to the frequency asynchrony between the grid side and the unit side, thereby improving the stability of the generator set starting control.

[0046] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication and program running functions, such as an embedded FPGA (Field-Programmable Gate Array) and other electronic devices that can realize the above functions. The controller is taken as an example to illustrate this embodiment and the following embodiments.

[0047] Based on this, the embodiment of the present application provides a static inverter triggering method, referring to Figure 1 , Figure 1 This is a flow chart of Embodiment 1 of the static frequency converter triggering method of the present application.

[0048] In this embodiment, the static frequency converter triggering method may include steps S100 to S300:

[0049] Step S100, determining a pulse sequence signal of a static frequency converter.

[0050] The pulse train signal includes a grid-side pulse train signal and a unit-side pulse train signal.

[0051] Step S200, at the rising edge moment of the grid side pulse train signal, the unit side pulse train signal is clock synchronized with the grid side pulse train signal to obtain a synchronized unit side pulse train signal.

[0052] Step S300: triggering the static frequency converter based on the synchronized pulse sequence signal on the unit side and the pulse sequence signal on the grid side.

[0053] It should be noted that the main circuit topology of SFC (Static Frequency Converter) can generally include multiple three-phase converter bridges (i.e., three-phase rectifier bridges on the grid side and three-phase inverter bridges on the unit side). The three-phase converter bridges can realize power conversion from the grid side to the unit side, and transmit electric energy from the grid to the generator set. The topology of SFC can be 12-6 pulses (i.e., the grid side includes two three-phase rectifier bridges and the unit side includes one three-phase inverter bridge), 12-12 pulses (i.e., the grid side includes two three-phase rectifier bridges and the unit side includes two three-phase inverter bridges), or 6-6 pulses (i.e., the grid side includes one three-phase rectifier bridge and the unit side includes one three-phase inverter bridge).

[0054] The pulse sequence signal of the static frequency converter is a collection of pulse signals for triggering the thyristors of the three-phase converter bridge in the SFC; the pulse sequence signal can be determined based on the control requirements of the SFC, and a hardware circuit (such as a pulse generator, a voltage-controlled oscillator, etc.) can be used to generate the pulse sequence signal required to trigger the thyristors in the SFC. Or as a feasible implementation, step S100 can specifically include steps S110 to S150, which are used to determine the pulse sequence signal of the static frequency converter. Figure 2 As shown, Figure 2 It is a detailed flowchart diagram of step S100.

[0055] Step S110, for each thyristor in the three-phase converter bridge on the grid side and the unit side of the static inverter, an initial pulse enable signal of the thyristor is obtained to obtain a first pulse enable signal.

[0056] Step S120, determining initial pulse enable signals respectively corresponding to two thyristors that are out of phase with the thyristor and do not share a common pole, and obtaining a second pulse enable signal and a third pulse enable signal.

[0057] Step S130 , performing an AND logic operation on the first pulse enable signal, the second pulse enable signal and the third pulse enable signal, respectively, to obtain a first logic pulse signal and a second logic pulse signal.

[0058] Step S140, performing an OR logic operation on the first logic pulse signal and the second logic pulse signal to obtain a pulse signal corresponding to each thyristor.

[0059] Step S150: determining a pulse sequence signal based on all pulse signals.

[0060] Specifically, each three-phase converter bridge in the SFC includes six thyristors, which are distributed in three phases, A, B, and C. Each thyristor corresponds to an initial pulse enable signal, which can be used to trigger the conduction of the thyristor. The initial pulse enable signal can be generated by an external control device (such as a dedicated SFC controller) according to the different stages of the motor and input into the static inverter trigger system; the initial pulse enable signal can be received in the form of an optical signal or by communication; the six initial pulse enable signals corresponding to the six thyristors in a three-phase converter bridge can be square wave signals with phase differences, and the initial pulse enable signal is generated according to a preset trigger angle, which can determine whether the thyristor is turned on, and the conduction angle range of each thyristor in one AC cycle is generally 120°.

[0061] However, in a three-phase converter bridge, at least two thyristors (two thyristors are in different phases and have no common poles) need to be turned on to form a closed loop for rectification and inversion operations. Therefore, the initial pulse enable signal (i.e., the first pulse enable signal) of the thyristor can be obtained for each thyristor in the three-phase converter bridge on the grid side and the unit side of the static frequency converter, and the initial pulse enable signals (i.e., the second pulse enable signal and the third pulse enable signal) corresponding to the two thyristors that are in different phases and have no common poles with the thyristor can be determined. The first pulse enable signal is respectively subjected to an AND logic operation with the second pulse enable signal and the third pulse enable signal to obtain a first logic pulse signal and a second logic pulse signal, and then the first logic pulse signal is subjected to an OR logic operation with the second logic pulse signal to obtain the pulse signal corresponding to each thyristor. This ensures that two thyristors with different phases and non-common poles are turned on in the same three-phase converter bridge, so as to ensure the normal and stable operation of the three-phase converter bridge. The set of pulse signals corresponding to all thyristors in the same three-phase converter bridge can be regarded as a set of pulse sequence signals.

[0062] To facilitate understanding of the above content, the following will be explained in detail using the example of 12-6 pulse SFC. Figure 3 FIG. 1 is a schematic diagram of a 12-6 pulse SFC main circuit topology structure. Figure 3 As shown, the SFC includes a three-phase rectifier bridge Y and a three-phase rectifier bridge O on the grid side and a three-phase inverter bridge M on the unit side. The three-phase rectifier bridge Y includes six thyristors y1 to y6, the three-phase rectifier bridge O includes six thyristors o1 to o6, and the three-phase inverter bridge M includes six thyristors m1 to m6. Taking the three-phase rectifier bridge Y as an example, for thyristor y1, its corresponding initial pulse enable signal Y1, as well as the initial pulse enable signals Y6 and Y2 corresponding to the thyristor y6 and thyristor y2 that are out of phase with the thyristor y1 and do not share a common pole, respectively, are obtained. The two signals Y1 and Y6 are subjected to an AND logic operation to obtain the corresponding first logic pulse signal Y1S, the two signals Y1 and Y2 are subjected to an AND logic operation to obtain the corresponding second logic pulse signal Y2S, and then the two signals Y1S and Y2S are subjected to an OR logic operation to obtain the pulse signal Y1E corresponding to the thyristor y1.

[0063] For thyristor y2, its corresponding initial pulse enable signal Y2 is obtained, as well as the initial pulse enable signals Y1 and Y3 corresponding to thyristor y1 and thyristor y3 which are different in phase and have no common pole with thyristor y2, respectively. An AND logic operation is performed on the two signals Y2 and Y1 to obtain the corresponding first logic pulse signal Y2S, and an AND logic operation is performed on the two signals Y2 and Y3 to obtain the corresponding second logic pulse signal Y3S. Then, an OR logic operation is performed on the two signals Y2S and Y3S to obtain the pulse signal Y2E corresponding to thyristor y2.

[0064] For thyristor y3, its corresponding initial pulse enable signal Y3 is obtained, as well as the initial pulse enable signals Y4 and Y2 corresponding to thyristor y4 and thyristor y2 which are different in phase and have no common pole with thyristor y3, respectively. The two signals Y3 and Y2 are subjected to an AND logic operation to obtain the corresponding first logic pulse signal Y3S, the two signals Y3 and Y4 are subjected to an AND logic operation to obtain the corresponding second logic pulse signal Y4S, and the two signals Y3S and Y4S are subjected to an OR logic operation to obtain the pulse signal Y3E corresponding to thyristor y3.

[0065] For thyristor y4, its corresponding initial pulse enable signal Y4 is obtained, as well as the initial pulse enable signals Y3 and Y5 corresponding to thyristor y3 and thyristor y5 which are different in phase and have no common pole with thyristor y4, respectively. An AND logic operation is performed on the two signals Y4 and Y3 to obtain the corresponding first logic pulse signal Y4S, and an AND logic operation is performed on the two signals Y4 and Y5 to obtain the corresponding second logic pulse signal Y5S. Then, an OR logic operation is performed on the two signals Y4S and Y5S to obtain the pulse signal Y4E corresponding to thyristor y4.

[0066] For thyristor y5, its corresponding initial pulse enable signal Y5 is obtained, as well as the initial pulse enable signals Y4 and Y6 corresponding to thyristor y4 and thyristor y6 which are different in phase and have no common pole with thyristor y5, respectively. An AND logic operation is performed on the two signals Y5 and Y4 to obtain the corresponding first logic pulse signal Y5S, and an AND logic operation is performed on the two signals Y5 and Y6 to obtain the corresponding second logic pulse signal Y6S. Then, an OR logic operation is performed on the two signals Y5S and Y6S to obtain the pulse signal Y5E corresponding to thyristor y5.

[0067] For thyristor y6, its corresponding initial pulse enable signal Y6 is obtained, as well as the initial pulse enable signals Y5 and Y1 corresponding to thyristor y5 and thyristor y1 which are different in phase and have no common pole with thyristor y6, respectively. An AND logic operation is performed on the two signals Y6 and Y5 to obtain the corresponding first logic pulse signal Y6S, and an AND logic operation is performed on the two signals Y6 and Y1 to obtain the corresponding second logic pulse signal Y1S. Then, an OR logic operation is performed on the two signals Y6S and Y1S to obtain the pulse signal Y6E corresponding to thyristor y6.

[0068] Thus, the pulse train signal (i.e., Y1E-Y6E) corresponding to the three-phase rectifier bridge Y on the grid side can be obtained. Similarly, the pulse train signal (i.e., O1E-O6E) corresponding to the three-phase rectifier bridge O on the grid side and the pulse train signal (i.e., M1E-M6E) corresponding to the three-phase inverter bridge M on the unit side can also be determined by referring to the above method, which will not be repeated here.

[0069] In practical applications, there may be a problem of asynchrony in the thyristor triggering moment of the three-phase converter bridge on the grid side and the unit side, so the current rising process is unstable, resulting in the unit side current may not be able to start quickly for a long time, thereby affecting the stability of the generator set start-up control. Therefore, after determining the pulse sequence signal corresponding to each three-phase converter bridge in the SFC, the rising edge moment of the grid side pulse sequence signal can be monitored, and it can be used as a reference moment to synchronize the unit side pulse sequence signal. The synchronized unit side pulse sequence signal and the grid side pulse sequence signal have the same frequency characteristics. Using the synchronized unit side pulse sequence signal and the grid side pulse sequence signal to trigger the static frequency converter can avoid equipment failure or performance fluctuation caused by asynchrony in triggering, thereby achieving rapid start of current and improving the stability of the generator set start-up control. In a feasible implementation, at the rising edge moment of the grid side pulse sequence signal, the timer corresponding to the unit side pulse sequence signal can be controlled to be cleared, so that the clocks of the unit side pulse sequence signal and the grid side pulse sequence signal are synchronized, and the synchronized unit side pulse sequence signal is obtained.

[0070] In addition, when the SFC is triggered using the synchronized unit-side pulse sequence signal and the grid-side pulse sequence signal, since the triggering system of the thyristor in the SFC cannot support long-term triggering, insufficient triggering energy and damage to the thyristor may occur easily. Therefore, in a feasible implementation manner, step S300 may specifically include steps S310 to S320, which are used to modulate the pulse sequence signal to control the triggering time of the thyristor.

[0071] Step S310, modulating the synchronized unit-side pulse sequence signal and the grid-side pulse sequence signal respectively to obtain a unit-side modulated pulse sequence signal and a grid-side modulated pulse sequence signal.

[0072] Step S320: triggering the static frequency converter based on the modulated pulse train signal on the unit side and the modulated pulse train signal on the grid side.

[0073] Specifically, the PWM (Pulse Width Modulation) technology can be used to adjust the duty cycle of the synchronized unit-side pulse train signal and the grid-side pulse train signal, respectively, so as to control the triggering time of the thyristor and avoid damage to the thyristor. The modulated pulse train signal on the unit side and the modulated pulse train signal on the grid side obtained after modulation can be sent to the thyristor TE driver board (a driver circuit board for controlling the gate of the thyristor) through optical fiber, etc., to control the opening of the corresponding thyristor in the SFC. Preferably, during the modulation process, the period of the modulation pulse train signal on the unit side and the modulation pulse train signal on the grid side can be 1ms, and the duty cycle can be 50%; the period of 1ms corresponds to the frequency of 1kHz, which is relatively high and can ensure the rapid response of the system; and the 50% duty cycle setting means that within one cycle, the time of the high level and the low level are equal, and this symmetry helps to reduce electromagnetic interference, because equal on and off time can reduce energy accumulation in the circuit, thereby reducing interference; in addition, because the trigger system has a 50% off rest time, sufficient energy acquisition time can be reserved for the trigger system to meet the next trigger requirement.

[0074] For ease of understanding, the above content is explained using the example of the 12-6 pulse SFC. Figure 4 FIG. 1 is a schematic diagram showing a principle of a static frequency converter triggering method. Figure 4As shown, the 6-way Y-type grid side signal (i.e. the aforementioned initial pulse enable signal Y1-Y6) is subjected to logic operation to obtain the corresponding grid side pulse sequence signal Y1E-Y6E. The specific logic operation process can refer to the aforementioned content and will not be repeated here. Similarly, the 6-way O-type grid side signal (initial pulse enable signal O1-O6) is subjected to logic operation to obtain the corresponding grid side pulse sequence signal O1E-O6E, and the 6-way unit side signal (initial pulse enable signal M1-M6) is subjected to logic operation to obtain the corresponding unit side pulse sequence signal M1E-M6E. Y1E-Y6E respectively have corresponding cycle timers TimeY1-TimeY6, O1E-O6E respectively have corresponding cycle timers TimeO1-TimeO6, and M1E-M6E also respectively have corresponding cycle timers TimeM1-TimeM6. At the rising edge of Y1E~Y6E, the timers TimeM1~TimeM6 corresponding to M1E~M6E are cleared; that is, at the rising edge of Y1E, the corresponding periodic timer TimeM1 on the unit side is cleared to force synchronization of Y1E and M1E; at the rising edge of Y2E, the corresponding periodic timer TimeM2 on the unit side is cleared to force synchronization of Y2E and M2E; at the rising edge of Y3E, the corresponding periodic timer TimeM3 on the unit side is cleared to force synchronization of Y3E and M3E; at the rising edge of Y4E, the corresponding periodic timer TimeM4 on the unit side is cleared to force synchronization of Y4E and M4E; at the rising edge of Y5E, the corresponding periodic timer TimeM5 on the unit side is cleared to force synchronization of Y5E and M5E; at the rising edge of Y6E, the corresponding periodic timer TimeM6 on the unit side is cleared to force synchronization of Y6E and M6E.

[0075] It should be noted that since O1E~O6E and Y1E~Y6E are both pulse train signals on the grid side, they have a fixed phase difference, so there is no need to perform clock synchronization between Y1E~Y6E and O1E~O6E. Then, pulse width modulation technology is used to modulate Y1E~Y6E, O1E~O6E and M1E~M6E after clock synchronization (modulated according to the setting of period 1ms and duty cycle 50%), so that during the effective period of Y1E~Y6E, the corresponding grid side modulated pulse train signals Y1L~Y6L with a period of 1ms and a duty cycle of 50% can be output; similarly, during the effective period of O1E~O6E, the corresponding grid side modulated pulse train signals O1L~O6L with a period of 1ms and a duty cycle of 50% can be output; during the effective period of M1E~M6E, the corresponding unit side modulated pulse train signals M1L~M6L with a period of 1ms and a duty cycle of 50% can be output. Finally, the controller can trigger the thyristors in the SFC according to the obtained Y1L~Y6L, O1L~O6L and M1L~M6L.

[0076] It is not difficult to understand that the static frequency converter triggering method provided in the embodiment of the present application can force clock synchronization of the pulse sequence signals corresponding to the SFC grid side and the unit side respectively, so as to ensure that when the thyristor in the SFC is triggered, the grid side and the unit side can be coordinated and consistent, thereby avoiding the problem of the current being unable to start quickly due to the frequency asynchrony between the grid side and the unit side, thereby improving the stability of the generator set starting control.

[0077] The present application provides a controller, which includes: at least one processor and a memory, wherein the memory is communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the static inverter triggering method in the above-mentioned embodiment one.

[0078] Reference below Figure 5 , which shows a schematic diagram of the structure of a controller suitable for implementing the embodiment of the present application. The controller in the embodiment of the present application may include but is not limited to an embedded FPGA (Field-Programmable Gate Array) or other electronic device that can implement the above functions. Figure 5 The controller shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0079] like Figure 5As shown, the controller may include a processing device 1001 (e.g., a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM: Read Only Memory) 1002 or a program loaded from a storage device 1003 to a random access memory (RAM: Random Access Memory) 1004. In RAM1004, various programs and data required for the operation of the controller are also stored. The processing device 1001, ROM1002, and RAM1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems can be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD: Liquid Crystal Display), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the controller to communicate with other devices wirelessly or by wire to exchange data. Although the figure shows a controller with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems can be implemented or have alternatively.

[0080] In particular, according to the embodiments disclosed in the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0081] The controller provided by the present application adopts the static frequency converter triggering method in the above embodiment, which can solve the technical problem of poor stability of the generator set startup control in the related art. Compared with the related art, the beneficial effects of the controller provided by the present application are the same as the beneficial effects of the static frequency converter triggering method provided by the above embodiment, and the other technical features in the controller are the same as the features disclosed in the previous embodiment method, which will not be repeated here.

[0082] The present application also provides a static frequency converter trigger system, which may include a controller and a static frequency converter as described above, wherein the static frequency converter is connected to the controller. In a feasible implementation, the static frequency converter trigger system may also include a signal input module and a level conversion module. The level conversion module is connected to the signal input module and the controller respectively, the signal input module is used to input a light trigger signal, and the level conversion module is used to convert the light trigger signal into an initial pulse enable signal, and output the initial pulse enable signal to the controller.

[0083] The following is an example to illustrate: Figure 6 The schematic diagram of the structure of the static inverter trigger system corresponding to the 12-6 pulse SFC is as follows: Figure 6 As shown, the signal input module of the 12-6 pulse SFC trigger system may include a Y-type grid-side 6-way signal input unit, an O-type grid-side 6-way signal input unit and a unit-side 6-way signal input unit; wherein, the above three signal input units may all adopt an optocoupler isolation circuit, the optocoupler isolation circuit may input the optical trigger signal into the static frequency converter trigger system and convert it into a corresponding electrical signal, the optocoupler isolation circuit may adopt a high-speed isolation optocoupler M601, the input side of the optocoupler is a DC24V signal input, and the output side of the optocoupler is a DC5V signal output, i.e., a 5V TTL (Transistor-Transistor Logic, thyristor-thyristor logic level) signal, and the supported signal frequency is 10Mbps. The 5V TTL signals outputted by the Y-type grid-side 6-way signal input unit, the O-type grid-side 6-way signal input unit and the unit-side 6-way signal input unit can be converted into 3.3V initial pulse enable signals (i.e., Y1~Y6, O1~O6 and M1~M6 mentioned above) through the level conversion module, and the level conversion module then outputs the converted multiple initial pulse enable signals to the controller. Figure 6 As shown, the level conversion module of the static frequency converter trigger system corresponding to the 12-6 pulse SFC may include three level conversion units, that is, one signal input unit is connected to one level conversion unit, and each level conversion unit may include an SN74LVC4245A chip, which can support the conversion of 8 signals.

[0084] The controller can be a FPGA controller (Field-Programmable Gate Array). The FPGA controller has the advantages of great flexibility and high stability. In the static frequency converter triggering system, the specific selection can be the EP3C10E144I7 chip of the Cyclone3 series. The aforementioned Y1~Y6, O1~O6 and M1~M6 signals can obtain corresponding Y1L~Y6L, O1L~O6L and M1L~M6L signals after the internal logic operation of the FPGA controller. The specific processing flow can refer to the explanation of the embodiment of the static frequency converter triggering method, which will not be repeated here. The Y1L~Y6L, O1L~O6L and M1L~M6L signals finally obtained can be converted into optical signal form and sent to the thyristor TE driver board through the multi-mode optical fiber head HFBR-1414T to trigger the thyristor of the SFC.

[0085] The beneficial effects of the static frequency converter triggering system provided in the present application are the same as the beneficial effects of the static frequency converter triggering method provided in the above embodiment, and other technical features of the above static frequency converter triggering system are the same as the features disclosed in the method of the previous embodiment, which will not be repeated here.

[0086] It should be understood that the various parts disclosed in this application can be implemented by hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0087] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0088] The present application provides a computer-readable storage medium having computer-readable program instructions (ie, computer programs) stored thereon, and the computer-readable program instructions are used to execute the static frequency converter triggering method in the above-mentioned embodiment.

[0089] The computer-readable storage medium provided in the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM: Random Access Memory), a read-only memory (ROM: Read Only Memory), an erasable programmable read-only memory (EPROM: Erasable Programmable Read Only Memory or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM: CD-Read Only Memory), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency: Radio Frequency), etc., or any suitable combination of the above.

[0090] The computer-readable storage medium may be included in the controller; or may exist independently without being assembled into the controller.

[0091] The above-mentioned computer-readable storage medium carries one or more programs. When the above-mentioned one or more programs are executed by the controller, the controller: determines the pulse sequence signal of the static frequency converter; wherein the pulse sequence signal includes a grid-side pulse sequence signal and a unit-side pulse sequence signal; at the rising edge moment of the grid-side pulse sequence signal, performs clock synchronization on the unit-side pulse sequence signal and the grid-side pulse sequence signal to obtain a synchronized unit-side pulse sequence signal; and triggers the static frequency converter based on the synchronized unit-side pulse sequence signal and the grid-side pulse sequence signal.

[0092] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0093] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0094] The modules involved in the embodiments described in this application may be implemented by software or hardware, wherein the name of the module does not constitute a limitation on the unit itself in some cases.

[0095] The readable storage medium provided by the present application is a computer-readable storage medium, which stores computer-readable program instructions (i.e., computer programs) for executing the above-mentioned static frequency converter triggering method, and can solve the technical problem of poor stability of generator set startup control in the related art. Compared with the related art, the beneficial effects of the computer-readable storage medium provided by the present application are the same as the beneficial effects of the static frequency converter triggering method provided by the above-mentioned embodiment, and will not be described in detail here.

[0096] The present application also provides a computer program product, including a computer program, wherein when the computer program is executed by a processor, the steps of the static frequency converter triggering method as described above are implemented.

[0097] The computer program product provided by the present application can solve the technical problem of poor stability of generator set startup control in the related art. Compared with the related art, the beneficial effects of the computer program product provided by the present application are the same as the beneficial effects of the static inverter triggering method provided by the above embodiment, which will not be repeated here.

[0098] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A static frequency converter triggering method, characterized in that: The static frequency converter triggering method comprises: Determine a pulse train signal of a static frequency converter; wherein the pulse train signal includes a grid-side pulse train signal and a unit-side pulse train signal; At the rising edge moment of the grid-side pulse train signal, performing clock synchronization on the unit-side pulse train signal and the grid-side pulse train signal to obtain a synchronized unit-side pulse train signal; The static frequency converter is triggered based on the synchronized unit-side pulse train signal and the grid-side pulse train signal.

2. The static frequency converter triggering method according to claim 1, characterized in that: The step of determining the pulse train signal of the static frequency converter comprises: For each thyristor in the three-phase converter bridge on the grid side and the unit side of the static frequency converter, an initial pulse enable signal of the thyristor is obtained to obtain a first pulse enable signal; Determine initial pulse enable signals respectively corresponding to two thyristors that are out of phase with the thyristor and do not share a common pole, and obtain a second pulse enable signal and a third pulse enable signal; Performing an AND logic operation on the first pulse enable signal, the second pulse enable signal and the third pulse enable signal respectively to obtain a first logic pulse signal and a second logic pulse signal; Performing an OR logic operation on the first logic pulse signal and the second logic pulse signal to obtain a pulse signal corresponding to each of the thyristors; Based on all of the pulse signals, the pulse train signal is determined.

3. The static frequency converter triggering method according to claim 1, characterized in that: The step of performing clock synchronization on the unit side pulse train signal and the grid side pulse train signal at the rising edge of the grid side pulse train signal to obtain the synchronized unit side pulse train signal comprises: At the rising edge moment of the grid-side pulse sequence signal, the timer corresponding to the unit-side pulse sequence signal is controlled to be reset to synchronize the clocks of the unit-side pulse sequence signal and the grid-side pulse sequence signal to obtain the synchronized unit-side pulse sequence signal.

4. The static frequency converter triggering method according to claim 1, characterized in that: The step of triggering the static frequency converter based on the synchronized unit-side pulse train signal and the grid-side pulse train signal comprises: Respectively modulating the synchronized unit-side pulse sequence signal and the grid-side pulse sequence signal to obtain a unit-side modulated pulse sequence signal and a grid-side modulated pulse sequence signal; The static frequency converter is triggered based on the unit-side modulated pulse train signal and the grid-side modulated pulse train signal.

5. The static frequency converter triggering method according to claim 4, characterized in that: The period of the unit-side modulation pulse sequence signal and the grid-side modulation pulse sequence signal is 1 ms, and the duty cycle is 50%.

6. A controller, characterized in that: The controller comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the static frequency converter triggering method according to any one of claims 1 to 5.

7. A static frequency converter triggering system, characterized in that: The static frequency converter triggering system comprises: The controller as claimed in claim 6; The static frequency converter is connected to the controller.

8. The static frequency converter triggering system according to claim 7, characterized in that: The static frequency converter triggering system also includes: A signal input module, used for inputting a light trigger signal; The level conversion module is connected to the signal input module and the controller respectively, and is used for converting the light trigger signal into an initial pulse enable signal, and outputting the initial pulse enable signal to the controller.

9. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the static frequency converter triggering method according to any one of claims 1 to 5 are implemented.

10. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the steps of the static frequency converter triggering method according to any one of claims 1 to 5 are implemented.

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