A low-side ideal diode based on a differential amplifier

Abstract

The present invention relates to the field of diode technology, and in particular to a low-end ideal diode based on a differential amplifier: the circuit is composed of an NMOS tube, a differential amplifier circuit, a voltage comparator, a negative bias power supply, etc.; the tube type in the differential amplifier circuit can be one of NPN, NMOS, PNP, and PMOS, and the differential amplifier circuit is used to compare the drain and source voltages of the NMOS tube, and the output signal is loaded into the voltage comparator again for amplification, and the voltage comparator outputs a signal to control the conduction and cutoff of the NMOS tube. The advantages are complemented by taking advantage of each other to achieve complementary advantages, and four low-end ideal diode circuits are designed. Software simulation verification shows that the designed circuit can realize the anti-backflow function, can meet the use occasions with a wide current range, and the circuit is simple, the cost is very low, and the practicability is strong.

Description

Technical Field

[0001] The invention relates to the technical field of power diodes, and in particular to a low-end ideal diode based on a differential amplifier. Background Art

[0002] Diodes are used more and more due to their unidirectional conduction characteristics and backflow prevention functions. In particular, Schottky diodes have a smaller voltage drop and are becoming more and more popular among designers. Since the voltage drop of Schottky diodes is still greater than that of MOS tubes, for some voltage-sensitive circuits, MOS tubes with low impedance characteristics are more preferred to improve product reliability.

[0003] At present, the Oring circuit is used in many occasions to ensure that each single power supply is independent of each other and does not have backflow. It is most commonly used in current sharing circuits to meet different power requirements. Therefore, a low-loss low-end ideal diode and an ultra-low-loss ideal diode are needed to further reduce the voltage drop and have the function of preventing backflow and protecting the front stage, so as to minimize the loss and extend the battery working time.

[0004] The main technical solutions for low-end ideal diodes implemented in the prior art are as follows.

[0005] The NMOS main tube + NPN auxiliary tube technical solution (one-way conduction device patent number: TW200537799A) is a low-end ideal diode with unidirectional conductivity. The circuit uses a dual NPN auxiliary tube combination logic control circuit to control the power NMOS main tube, and uses two NPN tubes from the same manufacturer and the same batch, so that the parameters of the two NPN tubes can be basically equal, or preferably two NPN pairs of tubes packaged together, the parameters of the two are almost equal, so as to ensure the proper switching and anti-backflow function, and its insertion conduction voltage drop is suitable for ultra-low power consumption applications, and can be used as a low-end low-power ideal power diode. The disadvantage is that the bias resistance of the NPN auxiliary tube is in the kilo-ohm level, and the static working current loss is in the milliampere level, the current loss is large, and the loss is large.

[0006] NMOS main tube + NMOS auxiliary tube technical solution: (an ultra-low loss low-end ideal diode, patent number: CN202020206261.X), belongs to the low-end ideal diode, with unidirectional conductivity. The circuit uses a dual NMOS auxiliary tube combination logic control circuit to control the NMOS main tube. The bias resistance of the NMOS auxiliary tube is in the megohm level, and the static working current loss is in the microampere level. The current loss is very small, and the current loss is much lower than the NMOS main tube + NPN auxiliary tube technical solution.

[0007] MOS supervisor + voltage comparator (operational amplifier) ​​technical solution: The voltage comparator collects the voltage difference between the source and drain of the MOS supervisor, and after comparison, the output signal controls the conduction and cutoff of the MOS supervisor. Since the on-resistance of the power-type MOS supervisor is relatively small, generally in the order of milliohms, if the on-current is relatively large, its on-voltage drop is large, and the voltage comparator works normally; if the on-current is relatively small, its on-voltage drop is small, and the voltage comparator may work unstably. In order to cope with small currents, a small current detection resistor can be inserted, but for large currents, additional voltage drops and losses are added, which is not worth the loss. Therefore, it is necessary to design a detection technology solution with a wide current range.

[0008] The voltage comparator used in the above technical solution is a single-limit voltage comparator: that is, the circuit has only one threshold voltage V T , any small change in the input voltage near the threshold voltage will cause a jump in the output voltage, regardless of whether the small change comes from the input signal or external interference. T When the output voltage Vo changes from V OH becomes V OL , or V OL becomes V OH The applied circuits include zero-crossing voltage comparator and general single-limit voltage comparator. Single-limit voltage comparator has high sensitivity but poor anti-interference ability.

[0009] The hysteresis voltage comparator has a hysteresis characteristic, that is, inertia, and thus has a certain anti-interference ability. Generally, a positive feedback circuit is introduced to form a double-threshold reverse input hysteresis voltage comparator (also known as a Schmitt trigger). However, due to the effect of positive feedback, the threshold voltage of this voltage comparator changes faster with the change of the output voltage, and the anti-interference ability is improved, thereby obtaining a more ideal voltage transmission characteristic. The hysteresis voltage comparator circuit has two threshold voltages. The input voltage Vi gradually increases, causing the output voltage Vo to produce a threshold voltage V T1 , the input voltage Vi gradually decreases, causing the output voltage Vo to produce a threshold voltage V T2 , V T1 ≠V T2 The circuit has hysteresis characteristics. The same as the single-limit voltage comparator is that when the input voltage changes in a single direction, the output voltage Vo only jumps once. The absolute value of the difference between the two threshold voltages is called the hysteresis voltage ΔV = V T2 -V T1 The larger the hysteresis voltage is, the stronger the anti-interference ability is, and the worse the sensitivity is. The relevant value should be set reasonably according to the application scenario.

[0010] The differential amplifier circuit evolved from the amplifier circuit with a stable static operating point. The analog electrical signal converted by the sensor in analog electronic technology is relatively weak and needs to be amplified. However, for non-periodic signals with slow analog changes, such as temperature, flow, liquid level and other analog quantities, it is generally amplified by a direct coupling amplifier circuit and then driven by the load. However, the direct coupling amplifier circuit will have a zero drift phenomenon (the input voltage is zero but the output voltage change is not zero). In order to suppress the zero drift, transistors with the same parameter characteristics (same layout size) are generally used, which is called a differential amplifier circuit.

[0011] The differential amplifier circuit is the basic component of the direct-coupled amplifier circuit. It has different effects on different input signals. It has a strong inhibitory effect on common-mode signals and amplifies differential-mode signals. The amplification capability of the circuit is related to the output mode. It is widely used in audio amplifiers, voltage comparators, data communication interfaces and other circuits.

[0012] Offset voltage, also known as input offset voltage (VIO), reflects the degree of symmetry of the circuit, and its value is generally ±1 to 10mV. Overdrive voltage (VOD) is the differential voltage generated between the positive and negative inputs of the voltage comparator on the offset voltage (VIO), and the absolute value of the voltage difference between the dual input ports of the voltage comparator. To achieve accurate comparison, the overdrive voltage (VOD) should be greater than the offset voltage (VIO). Overdrive voltage can also determine the response time of the voltage comparator, and the response time decreases as the overdrive voltage increases. The output curves of the voltage comparator under different overdrive voltages given in the chip data sheet are used to describe the response performance (or flip speed) of the voltage comparator. Generally, the larger the overdrive voltage, the faster the response of the voltage comparator.

[0013] The input offset voltage (VIO) of TI's voltage comparator chip LM393B is VIO = ±0.37mV (typical value), |VIO| ≤ 2.5mV; the input offset voltage (VIO) of the voltage comparator chip LMC7211AIM5 is VIO = 3mV (typical value), |VIO| ≤ 8mV. When selecting a voltage comparator, you should choose a comparator chip with a lower offset voltage.

[0014] Since the voltage comparator works in the nonlinear region: in the actual application circuit, the voltage comparator circuit is often connected to the hysteresis voltage comparator mode, which enhances the anti-interference ability of the circuit. If the circuit has hysteresis characteristics, it is generally required that the hysteresis voltage is greater than the offset voltage, that is, ΔV = |V T1 -V T2|≥VIO=2mV, which means that the current I is conducted through the drain-source channel of the MOS tube D >VIO / R DS(ON) .

[0015] NMOS tube drain-source channel on-resistance R DS(ON) Relatively small, assuming R DS(ON) =10mΩ, I D >VIO / R DS(ON) =2mV / 10mΩ=0.2A, which means that the voltage comparator can only work normally if the current is greater than 0.2A. Obviously, NMOS tubes are suitable for working environments with large currents.

[0016] PMOS tube drain-source channel on-resistance R DS(ON) Relatively large, assuming R DS(ON) =100mΩ, I D >VIO / R DS(ON) =2mV / 100mΩ=0.02A, which means that the voltage comparator can work normally when the current is greater than 0.02A. Obviously, PMOS tube is suitable for working occasions with small current.

[0017] If the working current is less than 0.2A, the first solution is to choose R DS(ON) >100mΩ PMOS tube model, meeting R DS(ON) ×I D >VIO, that is, R DS(ON) >VIO / I D ; Second, a current detection resistor R can be connected in series with the drain or source of the original PMOS tube to meet (R+R DS(ON) )×I D >VIO, that is, R>VIO / I D -R DS(ON) .

[0018] Whether it is an NMOS tube or a PMOS tube, there is a certain on-resistance when it is turned on. For example, the on-resistance of a power NMOS tube is about tens of milliohms, which is lower than the on-resistance of a PMOS tube under the same conditions. Once it is turned on, there is current, which will produce an on-voltage drop (the product of the on-current and the on-resistance). The on-voltage drop is the voltage difference between the drain and the source of the MOS tube. This voltage difference is loaded to the dual input ports of the differential amplifier circuit, and the differential amplifier circuit is used to amplify the signal (that is, the difference between the two signals). The differential signals output by the two output terminals are loaded again to the voltage comparator (the non-inverting terminal and the inverting terminal) to control the on and off of the tube and realize the function of an ideal diode. Summary of the invention

[0019] The technical problem to be solved by the present invention is to overcome the above technical defects and provide a low-end ideal diode based on a differential amplifier.

[0020] In order to solve the above technical problems, the technical solution provided by the present invention is: a low-end ideal diode based on a differential amplifier, including a circuit, wherein the circuit includes an NMOS tube, a differential amplifier circuit, a voltage comparator, and a negative bias power supply. The dual input ports of the differential amplifier circuit are respectively connected to the drain and source of the NMOS tube and compare the voltages. The voltage comparator receives the output signal of the differential amplifier circuit and outputs the conduction and cutoff of the NMOS tube.

[0021] Preferably, the transistor type in the differential amplifier circuit includes any one of NPN, NMOS, PNP, and PMOS.

[0022] Preferably, the voltage difference between the drain and source of the NMOS tube is loaded to the dual input ports of the differential amplifier circuit, and the differential amplifier circuit amplifies the signal.

[0023] Preferably, the signals of the dual output ports of the differential amplifier circuit are again loaded into the dual input ports of the voltage comparator for amplification;

[0024] When the source voltage of the NMOS supervisor is greater than the drain voltage, the voltage comparator outputs a high level to control the drain-source channel of the NMOS supervisor to be turned on;

[0025] When the source voltage of the NMOS supervisor is lower than the drain voltage, the voltage comparator outputs a low level to control the drain-source channel of the NMOS supervisor to be cut off;

[0026] Prevent external current from flowing back to VCC and protect the VCC power supply front-stage circuit.

[0027] Preferably, the differential amplifier comprises an NPN pair of tubes and resistors R1 to R5, wherein R2 = R3 and R4 = R5, forming a common emitter circuit.

[0028] Preferably, the differential amplifier comprises an NMOS pair of transistors and resistors R1 to R5, wherein R2 = R3 and R4 = R5, forming a common source circuit.

[0029] Preferably, the differential amplifier comprises a PNP pair of transistors and resistors R1 to R5, wherein R2 = R3 and R4 = R5.

[0030] Preferably, the differential amplifier comprises a PMOS pair of transistors and resistors R1 to R5, wherein R2 = R3 and R4 = R5, forming a common source circuit.

[0031] Preferably, the NMOS main drain channel on-resistance R DS(ON) A few milliohms.

[0032] The voltage comparator has a hysteresis loop transmission characteristic (also known as a Schmitt trigger). The threshold voltage of this voltage comparator changes with the output voltage at an accelerated rate, and its anti-interference ability is improved. The hysteresis voltage comparator has a hysteresis characteristic, that is, inertia, and thus has a certain anti-interference ability. The stronger the anti-interference ability, the worse the sensitivity.

[0033] NMOS supervisors can use NMOS tubes with different conduction currents. For high-power power control, NMOS supervisors can choose drain channel conduction impedance R DS(ON) A power tube device with a current of several milliohms and a large passing current has a small voltage drop when passing a large current, that is, it has a very low forward voltage and can be approximated as an ideal diode.

[0034] The advantages of the present invention compared with the prior art are: combining the characteristics of the differential amplifier circuit (dual input ports, dual output ports) and the hysteresis voltage comparator, taking advantage of each other's strengths to achieve complementary advantages, and software simulation verification shows that the designed circuit can realize the anti-backflow function, can meet the use occasions with a wide current range, the circuit is simple, the cost is very low, and the practicability is strong. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Schematic diagram of an NMOS type (main tube) low-side ideal diode implemented for an NPN pair differential amplifier;

[0036] Figure 2 Schematic diagram of an NMOS type (main tube) low-side ideal diode implemented for an NMOS pair differential amplifier;

[0037] Figure 3 Schematic diagram of an NMOS type (main tube) low-side ideal diode implemented for a PNP pair differential amplifier;

[0038] Figure 4 Schematic diagram of an NMOS type (main tube) low-side ideal diode implemented for a PMOS pair differential amplifier;

[0039] Figure 5 yes Figure 1 Forward conduction simulation;

[0040] Figure 6 yes Figure 1 Reverse cutoff simulation;

[0041] Figure 7 yes Figure 2 Forward conduction simulation;

[0042] Figure 8 yes Figure 2 Reverse cutoff simulation;

[0043] Fig. 9 yes Figure 3 Forward conduction simulation;

[0044] Fig.10 yes Figure 3 Reverse cutoff simulation;

[0045] Fig.11 yes Figure 4 Forward conduction simulation;

[0046] Fig.12 yes Figure 4 Reverse cutoff simulation. DETAILED DESCRIPTION

[0047] The present invention is further described in detail below in conjunction with the accompanying drawings.

[0048] Implementation Method 1

[0049] A low-side ideal diode based differential amplifier, the circuit is as follows Figure 1 As shown, it includes an NMOS main tube V1, a differential amplifier, a voltage comparator U1, a negative bias power supply VEE, etc. The differential amplifier is composed of NPN pair tubes V2 and V3, resistors R1 to R5, etc., and is a common emitter circuit, wherein R2 = R3, R4 = R5. The two bases of the NPN pair tubes V2 and V3 serve as the dual input ports of the differential amplifier, respectively detecting the source and drain voltages of the NMOS main tube V1. After the amplification of the pair tubes V2 and V3 of the differential amplifier, the two collector potential differences of the V2 tube and the V3 tube serve as dual output ports, respectively outputting differential signals U- and U+, respectively. U- and U+ are connected to the inverting terminal and the non-inverting terminal of the voltage comparator U1, respectively. The output signal V1G of the voltage comparator U1 controls the conduction and cutoff of the NMOS main tube V1.

[0050] The differential amplifier can overcome the problem of temperature drift. Under the action of differential mode signal, the current change of R1 is 0, that is, the resistor R1 has no feedback effect on the differential mode signal, which is equivalent to a short circuit. Therefore, the amplification ability of the differential mode signal is greatly improved, while simplifying the circuit and making the power supply and signal source "shared ground". The differential amplifier is also called a differential amplifier. The so-called "differential" means that the output voltage will change (change amount) only when there is a difference (change amount) in the potential between the dual input ports.

[0051] Differential amplifiers generally require ideal parameter symmetry, R2 = R3, R4 = R5, and the input characteristic curves and output characteristic curves of the NPN pair of tubes V2 and V3 completely overlap. Due to the dispersion of transistor characteristics, the parameters of any component cannot be ideally symmetrical, that is, the zero drift cannot be completely suppressed. However, in integrated circuits, since adjacent components have good symmetry and the parameters are basically equal, ideal parameter symmetry can generally be achieved approximately. Therefore, NPN tubes V2 and V3 are preferably packaged together with NPN auxiliary tube chips to ensure that the parameters of the two tubes are basically equal.

[0052] The specific working principle is as follows.

[0053] When the DC power supply VCC=VCC1 is powered on (forward conduction), the current output by VCC passes through the load RL and the body diode of the NMOS tube V1 (V1S=V F , V F is the body diode conduction voltage drop), when the output current gradually increases, the load RL low-end potential V1S is higher than GND (V1S>GND), the voltage VA>VC, and the NPN tube V2 is more completely turned on than the NPN tube V3 (the conduction impedance of the V2 tube is R2 CE R3 is the on-resistance of V3 tube CE The conduction degree depends on the base voltage), which means that the voltage U+>U-, the differential signal U-, U+ output by the differential amplifier is transmitted to the voltage comparator U1, and the voltage comparator U1 outputs a high level, that is, V1G≈VCC. When V1 GS =V1G-V1S=VCC-V F >V TN After the drain-source channel of NMOS tube V1 is turned on, V1S≈0V, and the VCC current flows through the drain-source low-impedance channel of NMOS tube V1 to the load RL (no longer through the body diode high-impedance channel of NMOS tube V1). The drain-source channel of NMOS tube V1 is less conductive, that is, the conduction loss is less than the diode V F , reduce power loss and improve power utilization efficiency.

[0054] When the external voltage VCC2 connected to GND is greater than the internal power supply VCC (VCC2>VCC), the voltage VC>VA, and the NPN tube V3 is more completely turned on than the NPN tube V2 (the on-resistance of the V3 tube is R3 CE R2 is the on-resistance of V2 tube CE The conduction degree depends on the base voltage), that is, the voltage U->U+, the differential signal U-, U+ output by the differential amplifier is transmitted to the voltage comparator U1, and the voltage comparator U1 outputs a low level, that is, V1G≈0V, V1S=VCC, when V1 GS =V1G-V1S≈-VCC<V TN, the drain-source channel of the NMOS tube V1 is cut off, the power supply VCC is isolated from the external power supply VCC2, and the current of the external power supply (other power supplies connected in parallel with the voltage VCC2) cannot flow back into the power supply VCC1, thereby achieving the purpose of protecting the power supply VCC1.

[0055] Furthermore, the voltage comparator has a hysteresis loop transmission characteristic (also known as a Schmitt trigger), and the threshold voltage of this voltage comparator changes with the change of the output voltage, and the anti-interference ability is improved. The hysteresis voltage comparator has a hysteresis characteristic, that is, inertia, and thus has a certain anti-interference ability. The stronger the anti-interference ability, the worse the sensitivity. The hysteresis voltage comparator circuit has two threshold voltages. The input voltage VCC gradually increases, causing the output voltage VCC2 to produce a threshold voltage V T1 , the input voltage VCC gradually decreases, causing the output voltage VCC2 to produce a transition threshold voltage V T2 , V T1 ≠V T2 The circuit has hysteresis characteristics. The same as the single-limit voltage comparator is that when the input voltage changes in a single direction, the output voltage VCC2 only jumps once.

[0056] Furthermore, the NMOS tube V1 can use NMOS tubes with different conduction currents. For high-power power supply control, the NMOS tube can choose a drain channel conduction impedance R DS(ON) A power tube device with a current of several milliohms and a large flow rate. When a large current flows through it, the conduction voltage drop is small, that is, it has a very low forward voltage and can be approximated as an ideal diode.

[0057] Implementation Method 2

[0058] Circuit such as Figure 2 As shown, the circuit structure is basically the same as that of Implementation Method 1, except that: the differential amplifier circuit of Implementation Method 1 uses an NPN pair of tubes, and Implementation Method 2 uses an NMOS pair of tubes to replace the NPN pair of tubes V2 and V3, wherein R2=R3, R4=R5, and it belongs to a common source circuit. The specific working principle is basically the same as that of Implementation Method 1, and is described in detail in Implementation Method 1.

[0059] Implementation Method 3

[0060] A low-side ideal diode based differential amplifier, the circuit is as follows Figure 3As shown, it includes an NMOS main body V1, a differential amplifier, a voltage comparator U1, a negative bias power supply VEE, etc. The differential amplifier is composed of a PNP pair of tubes V2 and V3, resistors R1 to R5, etc., wherein R2 = R3, R4 = R5. The two bases of the PNP pair of tubes V2 and V3 are used as dual input ports to detect the source and drain voltages of the NMOS main body V1 respectively. After the amplification of the PNP pair of tubes V2 and V3 of the differential amplifier, the two collectors of the V2 tube and the V3 tube are used as dual output ports to output differential signals U- and U+ respectively. U- and U+ are connected to the inverting terminal and the non-inverting terminal of the voltage comparator U1 respectively. The output signal V1G of the voltage comparator U1 controls the conduction and cutoff of the NMOS main body V1. The specific working principle is as follows.

[0061] When the DC power supply VCC=VCC1 is powered on (forward conduction), the current output by VCC passes through the load RL and the body diode of the NMOS tube V1 (V1S=V F , V F is the body diode conduction voltage drop), when the output current gradually increases, the load RL low-end potential V1S is higher than GND (V1S>GND), that is, the voltage VA>VC, and the PNP tube V3 is more thoroughly turned on than the PNP tube V2 (the conduction impedance of the V3 tube is R3 CE R2 is the on-resistance of V2 tube CE The conduction degree depends on the difference between the emitter and base voltage of V2 and V3 tubes), which means that the voltage U+>U-. The differential signals U- and U+ output by the differential amplifier are transmitted to the voltage comparator U1. The voltage comparator U1 outputs a high level, that is, V1G≈VCC. When V1 GS =V1G-V1S≈VCC-V F >V TN After the drain-source channel of NMOS tube V1 is turned on, V1S≈0V, and the VCC current flows through the load RL and the drain-source low-impedance channel of NMOS tube V1 to the negative pole of the power supply (no longer through the body diode high-impedance channel of NMOS tube V1). The drain-source channel of NMOS tube V1 is less conductive, that is, the conduction loss is less than the diode V F , reduce power loss and improve power utilization efficiency.

[0062] When the external voltage VCC2 connected to GND is greater than the internal power supply VCC (VCC2>VCC), the voltage VC>VA≈VCC, and the PNP tubes V2 and V3 are both cut off, that is, the voltage U->U+, and the differential signals U- and U+ output by the differential amplifier are transmitted to the voltage comparator U1. The voltage comparator U1 outputs a low level, that is, V1G≈0V, V1S=VCC. When V1 GS =V1G-V1S≈-VCC<V TN, the drain-source channel of the NMOS tube V1 is cut off, the power supply VCC is isolated from the external power supply VCC2, and the current of the external power supply (other power supplies connected in parallel with the voltage VCC2) cannot flow back into the power supply VCC1, thereby achieving the purpose of protecting the power supply VCC1.

[0063] Implementation Method 4

[0064] Circuit such as Figure 4 As shown, the circuit structure is basically the same as that of the third embodiment, except that the third embodiment uses a PNP pair of transistors as the differential amplifier circuit, while the fourth embodiment uses a PMOS pair of transistors to replace the PNP pair of transistors, wherein R2 = R3, R4 = R5, and it belongs to a common source circuit. The specific working principle is basically the same as that of the third embodiment, see the third embodiment for details, and will not be repeated here.

[0065] according to Figure 1 to Figure 4 The circuit schematic is simulated and tested using the National Instruments simulation software Multisim (version V14.0). The voltage comparator is LMC7211AIM5, a rail-to-rail op amp, and the output stage uses push-pull amplification to achieve an approximate full swing. The PMOS tube is NVTFS5124PLTAG from ON Semiconductor, with a minimum on-threshold voltage V TP(MIN) =-1.5V, maximum value V TP(MAX) =-2.5V, typical value V not given TP , the on-state current can reach -6A, and the on-state impedance R DS(ON) =0.26Ω(V GS =-10V), R DS(ON) =0.38Ω(V GS =-4.5V). The NMOS tube is made by NXP, model 2N7002E, and the minimum on-state voltage is V TN(MIN) =1V, maximum value V TN(MAX) =2.8V, typical value V is not given TN , conduction current I D 10A / 30V, on-resistance R DS(ON) ≤0.03Ω(V GS =10V), R DS(ON) ≤0.05Ω(V GS =4.5V), we can take the on-threshold voltage V TN =2.8V; the NPN tube is from Generic, model 2N2222A; the PNP tube is from Generic, model 2N2905; the load resistance RL=10Ω, the specific simulation test is as follows.

[0066] Implementation Method 1 Simulation

[0067] DC power supply forward conduction simulation test: Set R1 = R2 = R3 = 10kΩ, R4 = R5 = 100kΩ, VEE = -5V, VCC = VCC1 = 12V (switch J1 is closed), such as Figure 5 As shown, when forward conducting, the NMOS main tube V1 outputs a current of 1.20A; the base current of the NPN auxiliary tube V2 is 1.52μA (test point PR6), and the base voltage VA=-129mV(PR2), so it can be considered that the NPN auxiliary tube V2 is conducting; the base current of the NPN auxiliary tube V3 is 1.34μA(PR8), and the base voltage VC=-134mV(PR1), so it can be considered that the NPN auxiliary tube V3 is conducting, and the NPN tube V2 is conducting more thoroughly than the NPN tube V3; U+=10.0V(PR10), U-=9.72V(PR9), i.e. U+>U-, the voltage comparator U1 outputs a high level, i.e. V1G≈VCC=12.0V(PR4), V1S≈V F , V1 GS =V1G-V1S≈12V-V F =11.4V>V TN After the drain-source channel of NMOS V1 is turned on, the on-state voltage drop V1S = 22.726mV (measured by a multimeter), which is lower than the on-state voltage drop V of the diode. F =0.6V, the positive output current of the power supply is 1.20A, corresponding to the on-resistance R DS(ON) =22.726mV / 1.20A=18.9mΩ.

[0068] DC power supply reverse cutoff simulation test: GND is connected to power supply VCC2. After switch J1 is closed, switch J2 is also closed, that is, GND=VCC2=30V, VCC2>VCC, voltage VC=7.81V, VA=7.80V, U-=7.25V, U+=7.21V, that is, voltage U->U+, NPN tube V3 is more thoroughly turned on than NPN tube V2, and voltage comparator U1 outputs a low level, that is, V1G≈2.92mV, V1S≈VCC, V1 GS =V1G-V1S≈-12V<V TN , the drain-source channel of NMOS tube V1 is cut off, such as Figure 6 As shown, the power supply VCC2 has no backflow current (node ​​V1S: 42μA-42μA=0μA) output to the power supply VCC1, which can be ignored. It can be considered that VCC1 is isolated from the external power supply VCC2, thereby achieving the purpose of protecting the power supply VCC1.

[0069] According to the usage scenarios of different currents, the resistance value of the load resistor RL is changed, and the simulation test results are shown in Table 1.

[0070] Table 1 Load current simulation test

[0071]

[0072] According to the load current simulation test in Table 1, it can be seen that R1=R2=R3=R4=R5=10kΩ, and this set of parameters has a better magnification: load RL=12kΩ, load current is 1mA, and the conduction voltage drop V1 of NMOS V1 SD =18.93μV (corresponding on-resistance R DS(ON) =18.93mΩ), which is in line with the data sheet parameters. After the differential amplifier amplifies the output U+ and U-, the differential value is 913.301μV. The differential amplifier amplification factor is Au = 913.301μV / 18.93μV = 48.24. The other two sets of parameters are amplified by less than 15 times. The typical offset voltage of the voltage comparator chip LMC7211AIM5 is VIO = 3mV. If there is no differential amplifier, the drain-source conduction current I of the NMOS V1 that allows the LMC7211AIM5 to work properly is D =VIO / R DS(ON) =3mV / 21.933mΩ=0.1584A=158.4mA; if a differential amplifier is used, the corresponding on-state current I D =0.1584A / 48.24=3.28mA, theoretically the conduction current I D Greater than 3.28mA, the offset voltage of LMC7211AIM5 can be achieved. The combination circuit of the differential amplifier and the voltage comparator can be used in working environments with a relatively wide current range, expanding the scope of application.

[0073] Implementation Method 2 Simulation

[0074] DC power supply forward conduction simulation test: Set R1 = R2 = R3 = R4 = R5 = 10kΩ, VEE = -5V, VCC = VCC1 = 12V (switch J1 is closed), such as Figure 7 As shown, when forward conducting, the NMOS supervisor V1 outputs a current of 1.20A; the voltage VA=22.7mV>VC=-12.8μV, U+=10.6V, U-=10.3V, i.e. U+>U-, and the voltage comparator U1 outputs a high level, i.e. V1G=VCC=12.0V(PR4), V1S=V F , V1 GS =V1G-V1S≈12V-V F =11.4V>V TN , the drain-source channel of NMOS V1 is turned on, and the on-state voltage drop V1S = 22.726mV (measured by a multimeter), which is lower than the on-state voltage drop V of the diode F =0.6V, the positive output current of the power supply is 1.20A, corresponding to the on-resistance R DS(ON)=22.726mV / 1.20A=18.9mΩ.

[0075] DC power supply reverse cutoff simulation test: GND is connected to power supply VCC2, after switch J1 is closed, switch J2 is also closed, that is, GND=VCC2=30V, VCC2>VCC, voltage VA=12.0V, VC=30.0V, V2 tube and V3 tube are both turned on, V3 tube is more thoroughly turned on than V2 tube, U+=6.333V (measured by digital multimeter), U-=6.334V (measured by digital multimeter), U+≈U-, voltage comparator U1 outputs high level, that is, V1G=12.0V (PR4), at the beginning, the drain-source channel and body diode of NMOS supervisor V1 are both cut off, then V1S≈12.0V, V1 GS =V1G-V1S≈0V<V TN , the drain-source channel of NMOS V1 is cut off, such as Figure 8 As shown, the output current of the power supply VCC1 is 3.05nA, and the backflow current (node ​​V1S: 3.05nA+3.8nA=6.85nA) output by VCC2 to the power supply VCC1 can be ignored. It can be considered that VCC1 is isolated from the external power supply VCC2, thereby achieving the purpose of protecting the power supply VCC1.

[0076] Implementation Method 3 Simulation

[0077] DC power supply forward conduction simulation test: Set R1 = R2 = R3 = R4 = R5 = 10kΩ, VEE = -5V, VCC = VCC1 = 12V (switch J1 is closed), such as Fig. 9 As shown, when forward conducting, the NMOS V1 outputs a current of 1.20A; the voltages VA = 124mV, VC = 123mV, U+ = 564mV, and U- = 449mV, i.e., U+>U-, and the voltage comparator U1 outputs a high level, i.e., V1G≈VCC=12.0V(PR4), and V1S≈V F , V1 GS =V1G-V1S≈12V-V F =11.4V>V TN , the drain-source channel of NMOS V1 is turned on, and the on-state voltage drop V1S = 22.726mV (measured by a multimeter), which is lower than the on-state voltage drop V of the diode F =0.6V, the positive output current of the power supply is 1.20A, corresponding to the on-resistance R DS(ON) =22.726mV / 1.20A=18.9mΩ.

[0078] DC power supply reverse cutoff simulation test: GND is connected to power supply VCC2. After switch J1 is closed, switch J2 is also closed, that is, GND=VCC2=30V, VCC2>VCC, voltage VA=12.0V, VC=30.0V, that is, U-≈U+=-1.9V, voltage comparator U1 outputs low level, that is, V1G=2.92mV(PR4), V1 GS =V1G-V1S≈-12V<V TN , the drain-source channel of NMOS V1 is cut off, such as Fig.10 As shown, the backflow current (node ​​V1S: 579pA+157pA=736pA) output by VCC2 to the power supply VCC1 can be ignored. It can be considered that VCC1 is isolated from the external power supply VCC2, thereby achieving the purpose of protecting the power supply VCC1.

[0079] Implementation Method 4 Simulation

[0080] DC power supply forward conduction simulation test: Set R1 = R2 = R3 = R4 = R5 = 10kΩ, VEE = -5V, VCC = VCC1 = 12V (switch J1 is closed), such as Fig.11 As shown, when forward conducting, the NMOS V1 outputs a current of 1.20A; the voltages VA = 22.7mV, VC = 297pV, U+ = 1.03V, U- = -58.9mV, i.e., U+>U-, and the voltage comparator U1 outputs a high level, i.e., V1G≈VCC=12.0V(PR4), V1S≈V F , V1 GS =V1G-V1S≈12V-V F =11.4V>V TN , the drain-source channel of NMOS V1 is turned on, and the on-state voltage drop V1S = 22.726mV (measured by a multimeter), which is lower than the on-state voltage drop V of the diode F =0.6V, the positive output current of the power supply is 1.20A, corresponding to the on-resistance R DS(ON) =22.726mV / 1.20A=18.9mΩ.

[0081] DC power supply reverse cutoff simulation test: GND is connected to power supply VCC2. After switch J1 is closed, switch J2 is also closed, that is, GND = VCC2 = 30V, VCC2 > VCC, voltage VA = 12.0V, VC = 30.0V, that is, U->U+ = -1.9V, voltage comparator U1 outputs low level, that is, V1G = 2.92mV (PR4), V1S ≈ VCC, V1 GS =V1G-V1S≈-VCC<V TN , the drain-source channel of NMOS V1 is cut off, such as Fig.12As shown, the backflow current (node ​​V1S: 1.32nA+24pA≈1.32nA) output by VCC2 to the power supply VCC1 can be ignored. It can be considered that VCC1 is isolated from the external power supply VCC2, thereby achieving the purpose of protecting the power supply VCC1.

[0082] The beneficial effects of the present invention are as follows: under the same conditions, the voltage drop of the main tube of the high-end ideal diode, which is a PMOS tube, is about 0.3V, which is suitable for occasions with small working current; while the voltage drop of the main tube, which is an NMOS tube, can be as low as tens of millivolts, which is suitable for occasions with large working current. Due to the dual amplification of the differential amplifier and the voltage comparator, it is suitable for use in occasions with a wide current range. The circuit has a backflow prevention function, which can protect the previous stage circuit; it has low loss and small static current loss; the circuit is simple, the cost is very low, and the practicability is strong.

[0083] The present invention and its embodiments are described above, and such description is not restrictive. The drawings show only one embodiment of the present invention, and the actual structure is not limited thereto. In short, if ordinary technicians in the field are inspired by it, without departing from the purpose of the invention, they can design a structure and embodiment similar to the technical solution without creativity, which should belong to the protection scope of the present invention.

Claims

1. A low-side ideal diode based on a differential amplifier, comprising a circuit, characterized in that: The circuit includes an NMOS tube, a differential amplifier circuit, a voltage comparator, and a negative bias power supply. The dual input ports of the differential amplifier circuit are respectively connected to the drain and source of the NMOS tube and compare the voltages. The voltage comparator receives the output signal of the differential amplifier circuit and outputs the on and off control of the NMOS tube.

2. The low-end ideal diode based on a differential amplifier according to claim 1, characterized in that: The type of transistors in the differential amplifier circuit includes one of NPN, NMOS, PNP, and PMOS.

3. The low-end ideal diode based on a differential amplifier according to claim 1, characterized in that: The voltage difference between the drain and source of the NMOS main tube is loaded to the dual input ports of the differential amplifier circuit, and the differential amplifier circuit amplifies the signal.

4. The low-end ideal diode based on a differential amplifier according to claim 3, characterized in that: The signals of the dual output ports of the differential amplifier circuit are again loaded into the dual input ports of the voltage comparator for amplification; When the source voltage of the NMOS supervisor is greater than the drain voltage, the voltage comparator outputs a high level to control the drain-source channel of the NMOS supervisor to be turned on; When the source voltage of the NMOS supervisor is less than the drain voltage, the voltage comparator outputs a low level to control the drain-source channel of the NMOS supervisor to be cut off.

5. The low-end ideal diode based on a differential amplifier according to claim 2, characterized in that: The differential amplifier comprises an NPN pair of tubes and resistors R1 to R5, wherein R2 = R3 and R4 = R5, forming a common emitter circuit.

6. The low-end ideal diode based on a differential amplifier according to claim 2, characterized in that: The differential amplifier comprises a pair of NMOS tubes and resistors R1 to R5, wherein R2 = R3 and R4 = R5, forming a common source circuit.

7. The low-end ideal diode based on a differential amplifier according to claim 2, characterized in that: The differential amplifier comprises a PNP pair of transistors and resistors R1 to R5, wherein R2 = R3 and R4 = R5.

8. The low-end ideal diode based on a differential amplifier according to claim 2, characterized in that: The differential amplifier comprises a PMOS pair of tubes and resistors R1 to R5, wherein R2 = R3 and R4 = R5, forming a common source circuit.

9. A low-end ideal diode based on a differential amplifier according to any one of claims 1 to 8, characterized in that: The NMOS supervisor drain channel on-resistance R DS(ON) A few milliohms.

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