Power converter control circuit and power conversion chip

Abstract

The embodiments of the present disclosure provide a control circuit and a power conversion chip for a power converter. The control circuit includes a control module and a compensation module. The control module determines an intermediate control signal according to a slope compensation signal, a feedback voltage and a reference voltage, and determines a target control signal according to the intermediate control signal and a timing pulse signal. The compensation module generates a slope compensation signal according to the target control signal, which can improve the stability of the power converter. The target control signal is a low-voltage signal, which directly generates a slope compensation signal without the need for an additional high-voltage to low-voltage circuit, thereby reducing the cost of the power converter. In addition, the slope compensation signal has no DC quantity and does not require an additional filtering circuit, which not only improves the load transient response speed, but also further reduces the cost of the power converter.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular to a control circuit and a power conversion chip of a power converter. Background Art

[0002] As the integration of components and functional complexity of electronic devices increases, the requirements for multiple technical indicators of power converters also increase, including output voltage ripple, load dynamic response speed, stability and conversion efficiency. Among the many control methods of power converters, ripple-based constant on-time (RBCOT) control has great advantages in load dynamic response speed, but there is a delay between the output voltage ripple and the inductor current, which causes the power converter to easily generate subharmonic oscillations when the parasitic resistance of the output capacitor is small, and the output voltage ripple increases when the parasitic resistance of the output capacitor is large. Therefore, whether the parasitic resistance of the output capacitor is small or large, the application of power converters is limited.

[0003] In the existing scheme, when the parasitic resistance of the output capacitor is a small resistance, the stability of the power converter can be improved to a certain extent by filtering the signal at the switch end of the power converter, generating a ramp signal according to the filtered signal, and controlling the power converter according to the ramp signal. However, the ramp signal obtained by the existing scheme includes a direct current (DC) amount, which will affect the load transient response of the power converter. However, if the DC amount is filtered out, it will increase the cost, resulting in the inability to take into account both the load transient response speed and cost of the power converter. Summary of the invention

[0004] The present disclosure provides a control circuit and a power conversion chip of a power converter, which can improve the stability and load transient response speed of the power converter and also can reduce the cost of the power converter.

[0005] In a first aspect, the present disclosure provides a control circuit of a power converter, comprising a control module and a compensation module, wherein the output end of the control module is connected to the first input end of the control module through the compensation module, the second input end of the control module is used to receive a reference voltage, and the third input end of the control module is connected to the feedback end of the power converter.

[0006] The control module is configured to determine an intermediate control signal according to the slope compensation signal, the feedback voltage and the reference voltage, and to determine a target control signal according to the intermediate control signal and the timing pulse signal. The compensation module is configured to generate the slope compensation signal when the target control signal is a shutdown signal.

[0007] In some embodiments of the present disclosure, the compensation module includes a current source, a first transistor, a second transistor, a third transistor and a clamping capacitor, the first end of the first transistor and the first end of the second transistor are connected to an external power supply, the control end of the first transistor is connected to the control end of the second transistor, the second end of the first transistor and the output end of the current source, the second end of the second transistor is connected to the first plate of the clamping capacitor, the second end of the third transistor and the first input end of the control module, the control end of the third transistor is connected to the output end of the control module, and the output end of the current source, the second plate of the clamping capacitor and the first end of the third transistor are grounded.

[0008] The second transistor is configured to mirror a reference current provided by the current source, and when the target control signal is the shutdown signal, provide a mirror current of the reference current to the clamp capacitor to generate the slope compensation signal.

[0009] In some embodiments of the present disclosure, the compensation module also includes a fourth transistor, and the control circuit also includes a zero-crossing detection module, the input end of the zero-crossing detection module is connected to the switch end of the power converter, the output end of the zero-crossing detection module is connected to the control end of the fourth transistor, the first end of the fourth transistor is connected to the second end of the second transistor, and the second end of the fourth transistor is connected to the first plate of the clamping capacitor, the second end of the third transistor and the first input end of the control module.

[0010] The fourth transistor is configured to receive a zero-crossing detection signal output by the zero-crossing detection module, and when the zero-crossing detection signal is a zero-crossing signal, disconnect the second transistor from the clamping capacitor.

[0011] In some embodiments of the present disclosure, the compensation module also includes a clamping unit and an output unit, the input end of the clamping unit is used to receive a clamping reference voltage, the output end of the clamping unit is connected to the first end of the output unit, the second end of the output unit is connected to the first plate of the clamping capacitor, the second end of the third transistor, the second end of the fourth transistor and the first input end of the control module, and the control end of the output unit is connected to the output end of the zero-crossing detection module.

[0012] The clamping unit is configured to generate a slope clamping voltage according to the clamping reference voltage. The output unit is configured to, when the zero-crossing detection signal is the zero-crossing signal, turn on the clamping unit and the control module to limit the voltage of the slope compensation signal to the slope clamping voltage.

[0013] In some embodiments of the present disclosure, the clamping unit includes a fifth transistor, a sixth transistor, a seventh transistor, a first clamping resistor, and a second clamping resistor, the first end of the fifth transistor and the first end of the sixth transistor are connected to the external power supply, the control end of the fifth transistor is connected to the control end of the sixth transistor, the second end of the fifth transistor and the second end of the seventh transistor, the first end of the seventh transistor is grounded through the first clamping resistor, the control end of the seventh transistor is used to receive the clamping reference voltage, the second end of the sixth transistor is connected to the first end of the second clamping resistor and the first end of the output unit, and the second end of the second clamping resistor is grounded.

[0014] The clamping unit is further configured to determine the ramp clamping voltage according to the clamping reference voltage, a resistance value of the first clamping resistor, and a resistance value of the second clamping resistor.

[0015] In some embodiments of the present disclosure, the output unit includes an eighth transistor, a first end of the eighth transistor is connected to the output end of the clamping unit, a second end of the eighth transistor is connected to the first plate of the clamping capacitor, the second end of the third transistor, the second end of the fourth transistor and the first input end of the control module, and a control end of the eighth transistor is connected to the output end of the zero-crossing detection module.

[0016] In some embodiments of the present disclosure, the output unit further includes a delay device, an input end of the delay device is connected to an output end of the zero-crossing detection module, and an output end of the delay device is connected to a control end of the eighth transistor.

[0017] The delay device is configured to generate a clamp enable signal after delaying for a first preset time length when receiving the zero-crossing signal.

[0018] In some embodiments of the present disclosure, the output unit further includes an oscillator, an input end of the oscillator is connected to an output end of the zero-crossing detection module, and an output end of the oscillator is connected to a control end of the eighth transistor.

[0019] The oscillator is configured to generate a clamp enable signal every second preset time period when the zero-crossing signal is received.

[0020] In some embodiments of the present disclosure, the control module includes a feedback comparator, an RS trigger and a timer, the first positive input terminal of the feedback comparator is connected to the output terminal of the compensation module, the second positive input terminal of the feedback comparator is used to receive the reference voltage, the inverting input terminal of the feedback comparator is connected to the feedback terminal of the power converter, the output terminal of the feedback comparator is connected to the set terminal of the RS trigger, the reset terminal of the RS trigger is connected to the output terminal of the timer, and the output terminal of the RS trigger is connected to the input terminal of the timer and the input terminal of the compensation module.

[0021] In a second aspect, the present disclosure provides a power conversion chip, comprising any control circuit provided in the first aspect.

[0022] The technical solution disclosed in the present invention provides a control circuit of a power converter, including a control module and a compensation module. The control module determines an intermediate control signal according to a slope compensation signal, a feedback voltage and a reference voltage, and determines a target control signal according to the intermediate control signal and a timing pulse signal. The compensation module generates a slope compensation signal according to the target control signal, which can improve the stability of the power converter. The target control signal is a low-voltage signal, which directly generates a slope compensation signal without an additional high-voltage to low-voltage circuit, which can reduce the cost of the power converter. In addition, the slope compensation signal has no DC amount and does not require an additional filtering circuit, which not only improves the load transient response speed, but also further reduces the cost of the power converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, rather than limiting the present disclosure, wherein:

[0024] Figure 1 The present invention is a circuit diagram of a power converter provided in the prior art.

[0025] Figure 2 A circuit diagram of another power converter provided in the prior art.

[0026] Figure 3 A schematic diagram of the structure of a control circuit of a power converter provided in an embodiment of the present disclosure.

[0027] Figure 4 A circuit diagram of a control circuit of a power converter provided in an embodiment of the present disclosure.

[0028] Figure 5 A circuit diagram of a compensation module provided in an embodiment of the present disclosure.

[0029] Figure 6 A schematic diagram of the structure of another control circuit of a power converter provided in an embodiment of the present disclosure.

[0030] Figure 7 A circuit diagram of another compensation module provided in an embodiment of the present disclosure.

[0031] Figure 8 A circuit diagram of another compensation module provided in an embodiment of the present disclosure.

[0032] Fig. 9 A circuit diagram of another compensation module provided in an embodiment of the present disclosure.

[0033] Fig.10 A timing diagram of a control circuit of a power converter provided in an embodiment of the present disclosure.

[0034] Fig.11 A circuit diagram of another compensation module provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0036] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the disclosed subject matter belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" together shall mean that the parts are joined together directly or through one or more intermediate components.

[0037] Reference to "embodiments" in this disclosure means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiments" in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure may be combined with other embodiments.

[0038] In addition, the terms "first", "second", etc. in the specification and claims of the present disclosure or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0039] The term "and / or" in this disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0040] In the description of the present disclosure, unless otherwise specified, "plurality" and "at least two" mean more than two (including two), and similarly, "multiple groups" and "at least two groups" mean more than two groups (including two).

[0041] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0042] Figure 1 A circuit diagram of a power converter provided by the prior art, such as Figure 1 As shown, the power converter includes a voltage conversion circuit 10 and an RBCOT control circuit 20, wherein the voltage conversion circuit 10 includes a first switch tube Q1, a second switch tube Q2, an inverter INV, an inductor L, a first feedback resistor Rfb1, a second feedback resistor Rfb2, an output capacitor Cout, a parasitic resistor Resr of the output capacitor Cout, and a load RL.

[0043] Exemplarily, the first switch tube Q1 and the second switch tube Q2 may be N-type metal oxide semiconductor field effect transistors (NMOS), the drain of the first switch tube Q1 receives the input voltage Vin, the gate of the first switch tube Q1 is connected to the input end of the inverter INV, the source of the first switch tube Q1 is connected to the drain of the second switch tube Q2 and the first end of the inductor L, the gate of the second switch tube Q2 is connected to the output end of the inverter INV, and the source of the second switch tube Q2 is grounded. The connection point between the first switch tube Q1 and the inverter INV is the control end CTR of the power converter, and the connection point between the first switch tube Q1, the second switch tube Q2 and the inductor L is the switch end SW of the power converter.

[0044] The second end of the inductor L is connected to the first end of the first feedback resistor Rfb1, the first end of the parasitic resistor Resr and the first end of the load RL, the second end of the first feedback resistor Rfb1 is grounded through the second feedback resistor Rfb2, the second end of the parasitic resistor Resr is grounded through the output capacitor Cout, and the second end of the second counter-load RL is grounded. The connection point between the first feedback resistor Rfb1 and the second feedback resistor Rfb2 is the feedback terminal FB of the power converter.

[0045] In other implementations, the first switch tube Q1 and the second switch tube Q2 may also be PMOS, or other types of transistors such as triodes, and the present disclosure does not make any specific limitation on this.

[0046] The RBCOT control circuit 20 includes a first comparator CMP1, an RS trigger 21, a timer 22 and a driver 23, wherein a non-inverting input terminal of the first comparator CMP1 receives a reference voltage Vref, an inverting input terminal of the first comparator CMP1 is connected to a feedback terminal FB to receive a feedback voltage Vfb, an output terminal of the first comparator CMP1 is connected to a set terminal S of the RS trigger 21, a reset terminal R of the RS trigger 21 is connected to an output terminal of the timer 22, an output terminal Q of the RS trigger 21 is connected to an input terminal of the timer 22 and an input terminal of the driver 23, and an output terminal of the driver 23 is connected to a control terminal CTR.

[0047] Specifically, the first comparator CMP1 can compare the feedback voltage Vfb and the reference voltage Vref, and output a low level signal when the reference voltage Vref is less than the feedback voltage Vfb, and output a high level signal when the reference voltage Vref is greater than or equal to the feedback voltage Vfb. When the set end S of the RS trigger 21 receives a high level signal, the RS trigger 21 outputs a high level signal. At this time, the driver 23 can pull up the gate voltage of the first switch tube Q1 to turn on the first switch tube Q1, and the driver 23 and the inverter INV can cooperate to pull down the gate voltage of the second switch tube Q2 to turn off the second switch tube Q2, and the timer 22 starts timing.

[0048] After the constant time Ton, the output of the timer 22 is flipped to a high-level signal to generate a timing pulse signal, wherein the constant time Ton is the charging time of the power converter, that is, the constant on-time of the first switch tube Q1. At this time, the RS trigger 21 is reset, and the output of the RS trigger 21 is flipped to a low-level signal. The driver 23 can pull down the gate voltage of the first switch tube Q1 to turn off the first switch tube Q1, and the driver 23 and the inverter INV can cooperate to pull up the gate voltage of the second switch tube Q2 to turn on the second switch tube Q2.

[0049] However, under the action of the RBCOT control circuit 20, there is a delay between the output voltage ripple of the power converter and the inductor current, which results in subharmonic oscillations being easily generated when the parasitic resistance Resr is small, that is, the power converter is unstable. To address this problem, if the parasitic resistance Resr is increased, although the stability of the power converter can be improved to a certain extent, the output voltage ripple will be increased.

[0050] Under the premise of small output voltage ripple, in order to solve the problem of poor stability of the power converter when the parasitic resistance Resr is small, a RBCOT control circuit is proposed, such as Figure 2 As shown, Figure 2 The circuit diagram of another power converter provided in the prior art is as follows. The power converter includes a voltage conversion circuit 10 and an RBCOT control circuit 30 , wherein the RBCOT control circuit 30 includes a second comparator CMP2 , an RS trigger 21 , a timer 22 , a driver 23 and a ramp signal generator 24 .

[0051] The first positive phase input terminal of the second comparator CMP2 is connected to the output terminal of the ramp signal generator 24 to receive the slope compensation signal Ramp, the second positive phase input terminal of the second comparator CMP2 receives the reference voltage Vref, the negative phase input terminal of the second comparator CMP2 is connected to the feedback terminal FB, and the output terminal of the second comparator CMP2 is connected to the set terminal S of the RS trigger 21. The reset terminal R of the RS trigger 21 is connected to the output terminal of the timer 22, the output terminal Q of the RS trigger 21 is connected to the input terminal of the timer 22 and the input terminal of the driver 23, the output terminal of the driver 23 is connected to the control terminal CTR, and the input terminal of the ramp signal generator 24 is connected to the switch terminal SW.

[0052] Specifically, with Figure 1 Compared with the RBCOT control circuit 20 shown in the figure, the difference of the RBCOT control circuit 30 is that: the ramp signal generator 24 receives the signal of the switch end SW, filters the received switch end SW signal, and generates the slope compensation signal Ramp based on the filtered switch end SW signal. The second comparator CMP2 can compare the sum of the voltage of the slope compensation signal Ramp and the reference voltage Vref with the feedback voltage Vfb, and outputs a low level signal when the sum of the voltage of the slope compensation signal Ramp and the reference voltage Vref is less than the feedback voltage Vfb, and outputs a high level signal when the sum of the voltage of the slope compensation signal Ramp and the reference voltage Vref is greater than or equal to the feedback voltage Vfb.

[0053] Although the above RBCOT control circuit 30 can improve the stability of the power converter to a certain extent, the slope compensation signal Ramp includes a DC value, which will affect the load transient response. If the DC voltage is filtered from the slope compensation signal Ramp, the circuit cost will increase, resulting in the inability to balance the cost of the power converter and the load transient response speed. In addition, in high-voltage applications, the signal at the switch end SW needs to be converted from high voltage to low voltage, which increases the cost of the power converter.

[0054] In addition, when the power converter operates in discontinuous conduction mode (DCM), there is no inductor current information, that is, the inductor current is 0, and the slope compensation signal Ramp will disappear, resulting in instability of the power converter. Even if technical means such as sampling and holding are added, when the inductor current is 0, a resonant voltage will still be generated at the switch end SW. The resonant voltage will make the amplitude of the slope compensation signal Ramp difficult to control, so the power converter still has the problem of instability.

[0055] In view of this, the present disclosure provides a control circuit of a power converter, including a control module and a compensation module. The control module determines an intermediate control signal according to a slope compensation signal, a feedback voltage and a reference voltage, and determines a target control signal according to the intermediate control signal and a timing pulse signal. The compensation module generates a slope compensation signal according to the target control signal, which can improve the stability of the power converter. The target control signal is a low-voltage signal, which directly generates a slope compensation signal without an additional high-voltage to low-voltage circuit, which can reduce the cost of the power converter. In addition, the slope compensation signal has no DC amount and does not require an additional filtering circuit, which not only improves the load transient response speed, but also further reduces the cost of the power converter.

[0056] The technical solution of the present disclosure is described in detail below with reference to several specific embodiments.

[0057] Figure 3 A schematic diagram of a control circuit of a power converter provided by an embodiment of the present disclosure is shown in FIG. Figure 3 As shown, the power converter includes a voltage conversion circuit 10 and a control circuit 100, and the control circuit 100 includes a control module 110 and a compensation module 120. The output end of the control module 110 is connected to the first input end of the control module 110 through the compensation module 120, the second input end of the control module 110 receives the reference voltage Vref, and the third input end of the control module 110 is connected to the feedback end FB.

[0058] The control module 110 is configured to determine the intermediate control signal CTRL according to the slope compensation signal Ramp, the feedback voltage Vfb and the reference voltage Vref, and to determine the target control signal PWM according to the intermediate control signal CTRL and the timing pulse signal Pulse_on. The compensation module 120 is configured to generate the slope compensation signal Ramp when the target control signal PWM is an off signal.

[0059] For example, Figure 4 A circuit diagram of a control circuit of a power converter provided by an embodiment of the present disclosure, such as Figure 4 As shown, the control module 110 includes a feedback comparator CMP, an RS trigger 21 and a timer 22, a first positive input terminal of the feedback comparator CMP is connected to the output terminal of the compensation module 120, a second positive input terminal of the feedback comparator CMP receives a reference voltage Vref, an inverting input terminal of the feedback comparator CMP is connected to a feedback terminal FB, an output terminal of the feedback comparator CMP is connected to a set terminal S of the RS trigger 21, a reset terminal R of the RS trigger 21 is connected to the output terminal of the timer 22, and an output terminal Q of the RS trigger 21 is connected to an input terminal of the timer 22 and an input terminal of the compensation module 120.

[0060] The control circuit 100 further includes a driver 23, whose input end is connected to the output end Q of the RS trigger 21, and whose output end is connected to the control end CTR. The driver 23 can drive the first switch tube Q1 and the second switch tube Q2 to turn on and off according to the target control signal PWM.

[0061] The feedback comparator CMP can receive the reference voltage Vref, the feedback voltage Vfb and the slope compensation signal Ramp, and compare the sum of the voltage of the slope compensation signal Ramp and the reference voltage Vref with the feedback voltage Vfb to output the intermediate control signal CTRL, wherein the intermediate control signal CTRL includes a high level signal and a low level signal. For example, when the sum of the voltage of the slope compensation signal Ramp and the reference voltage Vref is less than the feedback voltage Vfb, the intermediate control signal CTRL is a low level signal, and when the sum of the voltage of the slope compensation signal Ramp and the reference voltage Vref is greater than or equal to the feedback voltage Vfb, the intermediate control signal CTRL is a high level signal.

[0062] The target control signal PWM includes an on signal and an off signal, wherein the on signal and the off signal are a pair of inverted signals, for example, the on signal is a high level signal, and the off signal is a low level signal. When the intermediate control signal CTRL is a high level signal, the set end S of the RS trigger 21 is a high level signal, and the RS trigger 21 outputs a high level signal, that is, the target control signal PWM is an on signal.

[0063] At this time, the driver 23 pulls up the gate voltage of the first switch tube Q1 according to the conduction signal to turn on the first switch tube Q1, and cooperates with the inverter INV to pull down the gate voltage of the second switch tube Q2 to turn off the second switch tube Q2. At the same time, the timer 22 is triggered, the timer 22 starts timing, the timer 22 outputs a low level signal, and the compensation module 120 does not generate the slope compensation signal Ramp.

[0064] After a constant time Ton, the output of the timer 22 flips from a low-level signal to a high-level signal to generate a timing pulse signal Pulse_on, and the reset terminal R of the RS trigger 21 is pulled high to reset the RS trigger 21. The output of the RS trigger 21 flips from a high-level signal to a low-level signal, that is, the target control signal PWM flips from an on signal to an off signal.

[0065] At this time, the driver 23 pulls down the gate voltage of the first switch tube Q1 according to the shutdown signal to turn off the first switch tube Q1, and cooperates with the inverter INV to pull up the gate voltage of the second switch tube Q2 to turn on the second switch tube Q2. At the same time, under the action of the shutdown signal, the compensation module 120 generates a slope compensation signal Ramp, so that the feedback comparator CMP performs comparison again, and the power converter enters the next working cycle.

[0066] Figure 5 A circuit diagram of a compensation module provided in an embodiment of the present disclosure is shown in FIG. Figure 5 As shown, the compensation module 120 includes a current source IB, a first transistor M1, a second transistor M2, a third transistor M3 and a clamping capacitor Cramp.

[0067] Combination Figure 3 and Figure 5 As shown, the first end of the first transistor M1 and the first end of the second transistor M2 are connected to an external power supply, the control end of the first transistor M1 is connected to the control end of the second transistor M2, the second end of the first transistor M1 and the output end of the current source IB, the second end of the second transistor M2 is connected to the first plate of the clamping capacitor Cramp, the second end of the third transistor M3 and the first input end of the control module 110, the control end of the third transistor M3 is connected to the output end of the control module 110, and the output end of the current source IB, the second plate of the clamping capacitor Cramp and the first end of the third transistor M3 are grounded.

[0068] Exemplarily, the first transistor M1 and the second transistor M2 are PMOS, the source of the first transistor M1 and the source of the second transistor M2 are connected to an external power supply to receive a power supply voltage Vcc provided by the external power supply, the gate of the first transistor M1 is connected to the drain of the first transistor M1 and the gate of the second transistor M2 to form a current mirror structure, the drain of the first transistor M1 is connected to the current source IB to receive the reference current Iref provided by the current source IB, and the drain of the second transistor M2 is connected to the first plate of the clamping capacitor Cramp.

[0069] The current flowing through the first transistor M1 is the reference current Iref, and the second transistor M2 can mirror the current flowing through the first transistor M1, for example, proportional mirroring, mirror amplification or mirror reduction, that is, mirroring the reference current Iref to obtain the mirror current, and transmit the mirror circuit to the first plate of the clamping capacitor Cramp.

[0070] The third transistor M3 is an NMOS, a drain of the third transistor M3 is connected to a first plate of the clamp capacitor Cramp, a source of the third transistor M3 and a second plate of the clamp capacitor Cramp are grounded, and a gate of the third transistor M3 receives a target control signal PWM.

[0071] When the target control signal PWM is a turn-on signal, the third transistor M3 is turned on, the clamping capacitor Cramp is short-circuited, and the drain voltage of the third transistor M3 is 0, that is, the output voltage of the compensation module 120 is 0, that is, the slope compensation signal Ramp is never generated. When the target control signal PWM is a turn-off signal, the third transistor M3 is turned off, and the mirror current flows into the clamping capacitor Cramp, and the clamping capacitor Cramp is in a charging state. As the amount of electricity in the clamping capacitor Cramp accumulates, the voltage of the clamping capacitor Cramp increases, thereby forming the slope compensation signal Ramp.

[0072] In summary, the control module 110 determines the intermediate control signal CTRL according to the slope compensation signal Ramp, the feedback voltage Vfb and the reference voltage Vref, determines the target control signal PWM according to the intermediate control signal CTRL and the timing pulse signal Pulse_on, and the compensation module 120 generates the slope compensation signal Ramp based on the target control signal PWM, which can improve the stability of the power converter.

[0073] The target control signal PWM is a low-voltage signal, which directly generates a slope compensation signal Ramp without the need for an additional high-voltage to low-voltage circuit, thereby reducing the cost of the power converter. In addition, the slope compensation signal Ramp has no DC quantity and does not require an additional filtering circuit, thereby not only improving the load transient response speed, but also further reducing the cost of the power converter.

[0074] In some embodiments, Figure 6 A structural diagram of another control circuit of a power converter provided by an embodiment of the present disclosure, such as Figure 6 As shown, the control circuit 100 further includes a zero-crossing detection module 130 , an input end of the zero-crossing detection module 130 is connected to the switch end SW, and an output end of the zero-crossing detection module 130 is connected to the control end of the compensation module 120 .

[0075] Figure 7 A circuit diagram of another compensation module provided in an embodiment of the present disclosure, combined with Figure 6 and Figure 7 As shown, the compensation module 120 also includes a fourth transistor M4, the control end of the fourth transistor M4 is connected to the output end of the zero-crossing detection module 130, the first end of the fourth transistor M4 is connected to the second end of the second transistor M2, and the second end of the fourth transistor M4 is connected to the first plate of the clamping capacitor Cramp, the second end of the third transistor M3 and the first input end of the control module 110.

[0076] The fourth transistor M4 is configured to receive the zero-crossing detection signal ZCD output by the zero-crossing detection module 130 , and disconnect the second transistor M2 from the clamping capacitor Cramp when the zero-crossing detection signal ZCD is a zero-crossing signal.

[0077] Exemplarily, the fourth transistor M4 is a PMOS, the source of the fourth transistor M4 is connected to the drain of the second transistor M2, and the drain of the fourth transistor M4 is connected to the first plate of the clamping capacitor Cramp, the second end of the third transistor M3 and the first input end of the control module 110.

[0078] When the power converter operates in DCM, the zero-crossing detection module 130 can generate a zero-crossing detection signal ZCD according to the received signal of the switch terminal SW to determine whether the inductor current is 0, wherein the zero-crossing detection signal ZCD includes a zero-crossing signal and a non-zero-crossing signal, for example, the zero-crossing signal is a high-level signal, and the non-zero-crossing signal is a low-level signal.

[0079] When the inductor current is 0, the zero-crossing detection signal ZCD is a zero-crossing signal, the fourth transistor M4 is turned off, and the clamping capacitor Cramp maintains the voltage of the slope compensation voltage signal Ramp so that when the inductor current is 0, the slope compensation voltage signal Ramp does not disappear, thereby improving the stability of the power converter.

[0080] In the embodiment of the present disclosure, the compensation module also includes a fourth transistor, and the control circuit also includes a zero-crossing detection module. The input end of the zero-crossing detection module is connected to the switch end, the output end of the zero-crossing detection module is connected to the control end of the fourth transistor, the first end of the fourth transistor is connected to the second end of the second transistor, the second end of the fourth transistor is connected to the first plate of the clamping capacitor, the second end of the third transistor and the first input end of the control module, the fourth transistor receives the zero-crossing detection signal output by the zero-crossing detection module, and when the zero-crossing detection signal is a zero-crossing signal, the connection between the second transistor and the clamping capacitor is disconnected to maintain the voltage of the slope compensation signal so that when the inductor current is 0, the slope compensation voltage signal will not disappear, thereby improving the stability of the power converter.

[0081] In some embodiments, Figure 8 A circuit diagram of another control circuit provided by an embodiment of the present disclosure is shown as follows: Figure 8 As shown, the compensation module 120 also includes a clamping unit 121 and an output unit 122, the input end of the clamping unit 121 receives the clamping reference voltage Vrclp, the output end of the clamping unit 121 is connected to the first end of the output unit 122, the second end of the output unit 122 is connected to the first plate of the clamping capacitor Cramp, the second end of the third transistor M3, the second end of the fourth transistor M4 and the first input end of the control module 110, and the control end of the output unit 122 is connected to the output end of the zero-crossing detection module 130.

[0082] The clamping unit 121 is configured to generate a slope clamping voltage Vclp according to the clamping reference voltage Vrclp, and the output unit 122 is configured to turn on the clamping unit 121 and the control module 110 when the zero-crossing detection signal ZCD is a zero-crossing signal to limit the voltage of the slope compensation signal Ramp to the slope clamping voltage Vclp.

[0083] For example, see Figure 8 The clamping unit 121 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, a first clamping resistor Rclp1 and a second clamping resistor Rclp2, wherein a first end of the fifth transistor M5 and a first end of the sixth transistor M6 are connected to an external power supply, a control end of the fifth transistor M5 is connected to a control end of the sixth transistor M6, a second end of the fifth transistor M5 and a second end of the seventh transistor M7, a first end of the seventh transistor M7 provides the first clamping resistor Rclp1 to be grounded, a control end of the seventh transistor M7 receives a clamping reference voltage Vrclp, a second end of the sixth transistor M6 is connected to a first end of the second clamping resistor Rclp2 and a first end of the output unit 122, and a second end of the second clamping resistor Rclp2 is grounded.

[0084] Specifically, the fifth transistor M5 and the sixth transistor M6 are PMOS, the seventh transistor M7 is NMOS, the drain of the seventh transistor M7 is connected to the drain of the fifth transistor M5, the source of the seventh transistor M7 is grounded through the first clamping resistor Rclp1, the gate of the seventh transistor M7 receives the clamping reference voltage Vrclp, the clamping reference voltage Vrclp generates a current I0 on the first clamping resistor Rclp1, the fifth transistor M5, the seventh transistor M7 and the first clamping resistor Rclp1 are located in the same branch, and the current flowing through the fifth transistor M5 is I0.

[0085] The source of the fifth transistor M5 and the source of the sixth transistor M6 are connected to an external power supply to receive a power supply voltage Vcc provided by the external power supply, and the gate of the fifth transistor M5 is connected to the drain of the fifth transistor M5 and the gate of the sixth transistor M6 to form a current mirror structure. The sixth transistor M6 can mirror the current flowing through the fifth transistor M5, that is, mirror the current I0 to obtain the current I1, and the voltage generated by the current I1 on the second clamping resistor Rclp2 is the clamping voltage Vclp, and Vclp=Vrclp*R" / R', where R" is the resistance value of the second clamping resistor Rclp2, and R' is the resistance value of the first clamping resistor Rclp1.

[0086] In this way, the clamping unit 121 can determine the ramp clamping voltage Vclp according to the clamping reference voltage Vrclp, the resistance value R′ of the first clamping resistor Rclp1 and the resistance value R″ of the second clamping resistor Rclp2 .

[0087] For example, see Figure 8 The output unit 122 includes an eighth transistor M8, a first end of the eighth transistor M8 is connected to the output end of the clamping unit 121, a second end of the eighth transistor M8 is connected to the first plate of the clamping capacitor Cramp, the second end of the third transistor M3, the second end of the fourth transistor M4 and the first input end of the control module 110, and a control end of the eighth transistor M8 is connected to the output end of the zero-crossing detection module 130.

[0088] Specifically, the eighth transistor M8 is an NMOS, the source of the eighth transistor M8 is connected to the drain of the sixth transistor M6 and the first end of the second clamping resistor Rclp2, the drain of the eighth transistor M8 is connected to the first plate of the clamping capacitor Cramp, the drain of the third transistor M3 and the drain of the fourth transistor M4, and the gate of the eighth transistor M8 receives the zero crossing detection signal ZCD.

[0089] When the power converter is in a light-load state or a no-load state, the output capacitor Cout has no discharge current, and the time that the feedback voltage Vfb is greater than the reference voltage Vref can reach the millisecond level. The clamping capacitor Cramp needs to maintain the slope compensation signal Ramp. However, in actual applications, the clamping capacitor Cramp has leakage, which causes the clamping capacitor Cramp to lose the slope compensation signal Ramp.

[0090] In the embodiment of the present disclosure, when the inductor current is 0, the zero-crossing detection signal ZCD is a zero-crossing signal, and the eighth transistor M8 is turned on, then the first plate of the clamping capacitor Cramp and the first end of the second clamping resistor Rclp2 can be turned on, and the slope clamping voltage Vclp is input to the clamping capacitor Cramp to limit the voltage of the slope compensation signal Ramp to the slope clamping voltage Vclp, so that within a wide load range, the power converter has higher stability and load transient response speed.

[0091] In some embodiments, Fig. 9 A circuit diagram of another compensation module provided in an embodiment of the present disclosure is shown in FIG. Fig. 9 As shown, the output unit 122 further includes a delayer 1221, the input end of the delayer 1221 is connected to the output end of the zero-crossing detection module 130, and the output end of the delayer 1221 is connected to the control end of the eighth transistor M8. The delayer 1221 is configured to generate a clamping enable signal after delaying the first preset Td1 time length when receiving the zero-crossing signal.

[0092] Exemplarily, the delay device 1221 is a rising edge delay device. When the zero-crossing detection signal ZCD flips from a non-zero-crossing signal to a zero-crossing signal, the delay device 1221 delays for a first preset time length Td1 from the moment the zero-crossing signal is received. Then, the output signal SH of the delay device 1221 flips from a low-level signal to a high-level signal, thereby generating a clamp enable signal.

[0093] Fig.10 A timing diagram of a control circuit of a power converter provided by an embodiment of the present disclosure, such as Fig.10 As shown, at time T1, the sum Vramp+Vref of the voltage Vramp of the slope compensation signal Ramp and the reference voltage Vref is equal to the feedback voltage Vfb, the target control signal PWM is flipped to a high-level signal, and the generation of the slope compensation signal Ramp is stopped. Then, the sum Vramp+Vref of the voltage Vramp of the slope compensation signal Ramp and the reference voltage Vref is equal to the reference voltage Vref, and is maintained until time T2.

[0094] At time T2, the timer 23 generates a timing pulse signal Pulse_on, the target control signal PWM flips to a low level signal, the compensation module 120 generates a slope compensation signal Ramp, and the sum Vramp+Vref of the voltage Vramp of the slope compensation signal Ramp and the reference voltage Vref starts to rise until time T3.

[0095] At time T3, the inductor current passes through zero, and the zero-crossing detection signal ZCD turns to a high-level signal, and the sum Vramp+Vref of the voltage Vramp of the slope compensation signal Ramp and the reference voltage Vref remains unchanged until time T4 which is delayed by the first preset time Td1 from time T3.

[0096] At time T4, the output signal SH of the delay device 1221 is flipped to a high-level signal, and the sum Vramp+Vref of the voltage Vramp of the slope compensation signal Ramp and the reference voltage Vref begins to rise until the voltage Vramp of the slope compensation signal Ramp reaches the ramp clamping voltage Vclp, that is, the sum Vramp+Vref of the voltage Vramp of the slope compensation signal Ramp and the reference voltage Vref reaches Vclp+Vref, and the sum Vramp+Vref of the voltage Vramp of the slope compensation signal Ramp and the reference voltage Vref maintains Vclp+Vref until entering the next working cycle.

[0097] In some embodiments, Fig.11 A circuit diagram of another compensation module provided in an embodiment of the present disclosure is shown in FIG. Fig.11 As shown, the output unit 122 further includes an oscillator 1222, the input end of the oscillator 1222 is connected to the output end of the zero-crossing detection module 130, and the output end of the oscillator 1222 is connected to the control end of the eighth transistor M8. The oscillator 1222 is configured to generate a clamping enable signal every second preset time length Td2 when receiving a zero-crossing signal.

[0098] Exemplarily, when the zero-crossing detection signal ZCD flips from a non-zero-crossing signal to a zero-crossing signal, the oscillator 1222 generates a pulse signal, ie, a clamping enable signal, every second preset time length Td2 from the moment the zero-crossing signal is received.

[0099] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural form and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive, unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, the "example" is merely illustrative and should not be considered exclusive or comprehensive.

[0100] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.

Claims

1. A control circuit of a power converter, characterized in that: include: Control module and compensation module; The output end of the control module is connected to the first input end of the control module through the compensation module, the second input end of the control module is used to receive a reference voltage, and the third input end of the control module is connected to the feedback end of the power converter; The control module is configured to determine an intermediate control signal according to the slope compensation signal, the feedback voltage and the reference voltage, and determine a target control signal according to the intermediate control signal and the timing pulse signal; The compensation module is configured to generate the slope compensation signal when the target control signal is a shutdown signal.

2. The control circuit according to claim 1, characterized in that: The compensation module includes a current source, a first transistor, a second transistor, a third transistor and a clamping capacitor; The first end of the first transistor and the first end of the second transistor are connected to an external power supply, the control end of the first transistor is connected to the control end of the second transistor, the second end of the first transistor and the output end of the current source, the second end of the second transistor is connected to the first plate of the clamping capacitor, the second end of the third transistor and the first input end of the control module, the control end of the third transistor is connected to the output end of the control module, and the output end of the current source, the second plate of the clamping capacitor and the first end of the third transistor are grounded; The second transistor is configured to mirror a reference current provided by the current source, and when the target control signal is the shutdown signal, provide a mirror current of the reference current to the clamp capacitor to generate the slope compensation signal.

3. The control circuit according to claim 2, characterized in that: The compensation module further includes a fourth transistor, and the control circuit further includes a zero-crossing detection module; The input end of the zero-crossing detection module is connected to the switch end of the power converter, the output end of the zero-crossing detection module is connected to the control end of the fourth transistor, the first end of the fourth transistor is connected to the second end of the second transistor, and the second end of the fourth transistor is connected to the first plate of the clamping capacitor, the second end of the third transistor and the first input end of the control module; The fourth transistor is configured to receive a zero-crossing detection signal output by the zero-crossing detection module, and when the zero-crossing detection signal is a zero-crossing signal, disconnect the second transistor from the clamping capacitor.

4. The control circuit according to claim 3, characterized in that: The compensation module also includes a clamping unit and an output unit; The input end of the clamping unit is used to receive the clamping reference voltage, the output end of the clamping unit is connected to the first end of the output unit, the second end of the output unit is connected to the first plate of the clamping capacitor, the second end of the third transistor, the second end of the fourth transistor and the first input end of the control module, and the control end of the output unit is connected to the output end of the zero-crossing detection module; The clamping unit is configured to generate a ramp clamping voltage according to the clamping reference voltage; The output unit is configured to, when the zero-crossing detection signal is the zero-crossing signal, turn on the clamping unit and the control module to limit the voltage of the slope compensation signal to the slope clamping voltage.

5. The control circuit according to claim 4, characterized in that: The clamping unit includes a fifth transistor, a sixth transistor, a seventh transistor, a first clamping resistor and a second clamping resistor; The first end of the fifth transistor and the first end of the sixth transistor are connected to the external power supply, the control end of the fifth transistor is connected to the control end of the sixth transistor, the second end of the fifth transistor and the second end of the seventh transistor, the first end of the seventh transistor is grounded through the first clamping resistor, the control end of the seventh transistor is used to receive the clamping reference voltage, the second end of the sixth transistor is connected to the first end of the second clamping resistor and the first end of the output unit, and the second end of the second clamping resistor is grounded; The clamping unit is further configured to determine the ramp clamping voltage according to the clamping reference voltage, a resistance value of the first clamping resistor, and a resistance value of the second clamping resistor.

6. The control circuit according to claim 4, characterized in that: The output unit includes an eighth transistor; The first end of the eighth transistor is connected to the output end of the clamping unit, the second end of the eighth transistor is connected to the first plate of the clamping capacitor, the second end of the third transistor, the second end of the fourth transistor and the first input end of the control module, and the control end of the eighth transistor is connected to the output end of the zero-crossing detection module.

7. The control circuit according to claim 6, characterized in that: The output unit also includes a delay device; The input end of the delay device is connected to the output end of the zero-crossing detection module, and the output end of the delay device is connected to the control end of the eighth transistor; The delay device is configured to generate a clamp enable signal after delaying for a first preset time length when receiving the zero-crossing signal.

8. The control circuit according to claim 6, characterized in that: The output unit also includes an oscillator; The input end of the oscillator is connected to the output end of the zero-crossing detection module, and the output end of the oscillator is connected to the control end of the eighth transistor; The oscillator is configured to generate a clamp enable signal every second preset time period when the zero-crossing signal is received.

9. The control circuit according to any one of claims 1 to 8, characterized in that: The control module includes a feedback comparator, an RS trigger and a timer; The first non-inverting input terminal of the feedback comparator is connected to the output terminal of the compensation module, the second non-inverting input terminal of the feedback comparator is used to receive the reference voltage, the inverting input terminal of the feedback comparator is connected to the feedback terminal of the power converter, the output terminal of the feedback comparator is connected to the set terminal of the RS trigger, the reset terminal of the RS trigger is connected to the output terminal of the timer, and the output terminal of the RS trigger is connected to the input terminal of the timer and the input terminal of the compensation module.

10. A power conversion chip, characterized in that: The control circuit comprises the control circuit described in any one of claims 1 to 9.

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