Peak current control circuit based on slope compensation signal superposition

Abstract

The present disclosure provides a peak current control circuit based on slope compensation signal superposition, which can be applied to the field of DC-DC converter technology. The circuit includes: a signal generation module, wherein a first capacitor is used to generate a calibration signal, a comparison unit is used to compare the calibration signal with a reference signal to obtain a clock control signal, and a first discharge switch is used to switch the charge / discharge state of the first capacitor according to the clock control signal; a signal superposition module, wherein a second capacitor is used to generate a compensation signal, the calibration signal is used to calibrate the voltage offset of the compensation signal so that the compensation signal is equal to the calibration signal, the second discharge switch is used to switch the charge / discharge state of the second capacitor according to the clock control signal, and an output unit is used to output a superposition signal obtained by adding the compensation signal and the inductor current information input by the input unit; and a signal calibration module is used to control the connection state of the first capacitor and the second capacitor according to the clock control signal.

Description

Technical Field

[0001] The present disclosure relates to the technical field of DC-DC converters, and more particularly to a peak current control circuit based on the superposition of slope compensation signals. Background Art

[0002] Peak current mode control is widely used in DC-DC converters due to its advantages of simple compensator design and direct implementation of overcurrent protection. To suppress subharmonic oscillations in peak current mode control, a ramp compensation signal is superimposed on the sampled inductor current signal.

[0003] In the process of realizing the concept of the present disclosure, the inventors found that the related art has at least one problem: it is difficult to adapt the DC-DC converter to a wide switching frequency range, or the superimposed signal is distorted, and the power consumption of the circuit is too high. Summary of the Invention

[0004] In view of this, the present disclosure provides a peak current control circuit based on the superposition of slope compensation signals.

[0005] One aspect of the present disclosure provides a peak current control circuit based on slope compensation signal superposition, comprising:

[0006] A signal generation module, comprising: a first tail current source, a first capacitor, a comparison unit, and a first discharge switch, wherein one end of the first capacitor is connected to the first tail current source and the other end is grounded, the first capacitor is used to generate a calibration signal, the comparison unit is used to compare the calibration signal with a reference signal to obtain a clock control signal, and the first discharge switch is used to switch the charge / discharge state of the first capacitor according to the clock control signal;

[0007] A signal superposition module, comprising: an output unit, an input unit, a second tail current source, a second capacitor, and a second discharge switch, wherein one end of the second capacitor is connected to the second tail current source and the other end is grounded, the second capacitor is used to generate a compensation signal, the calibration signal is used to calibrate the voltage offset of the compensation signal so that the compensation signal is equal to the calibration signal, the second discharge switch is used to switch the charge / discharge state of the second capacitor according to a clock control signal, and the output unit is used to output a superposition signal obtained by adding the compensation signal and the inductor current information input by the input unit;

[0008] A signal calibration module is used to control the connection state of the first capacitor and the second capacitor according to a clock control signal; wherein the ratio of the parameters of the first tail current source to the parameters of the second tail current source, the ratio of the parameters of the first capacitor to the parameters of the second capacitor, and the ratio of the parameters of the first discharge switch to the parameters of the second discharge switch are all equal.

[0009] According to an embodiment of the present disclosure, the comparison unit includes a first comparator and a trigger, the first input end of the trigger is connected to the output end of the first comparator, and the first comparator is used to compare the calibration signal and the rising reference signal; when the calibration signal rises to be greater than the rising reference signal, the first comparator is reversed, and the clock control signal is converted from the first level to the second level.

[0010] According to an embodiment of the present disclosure, the comparison unit also includes a second comparator, which is used to compare the calibration signal and the falling reference signal; when the calibration signal drops to less than the falling reference signal, the second comparator is reversed and the clock control signal is converted from the second level to the first level.

[0011] According to an embodiment of the present disclosure, the signal calibration module includes a first calibration switch and a second calibration switch, which controls the connection state of the first capacitor and the second capacitor according to a clock control signal, including: when the clock control signal is at a first level, the circuit is in a first working state, and the first calibration switch and the second calibration switch are disconnected; when the clock control signal is at a second level, the circuit is in a second working state, the first calibration switch and the second calibration switch are closed, and the first capacitor and the second capacitor are connected in parallel.

[0012] According to an embodiment of the present disclosure, in a first working state, the first discharge switch is disconnected from the second discharge switch, the first tail current source charges the first capacitor to generate a calibration signal, and the second tail current source charges the second capacitor to generate a compensation signal, wherein the slope of the calibration signal changes with the current size of the first tail current source, including: when the current size of the first tail current source decreases, the rising slope of the calibration signal decreases and the frequency of the clock control signal decreases; when the current size of the first tail current source increases, the rising slope of the calibration signal increases and the frequency of the clock control signal increases.

[0013] According to an embodiment of the present disclosure, in the second working state, the first discharge switch and the second discharge switch are closed, the first capacitor and the second capacitor are discharged, and the calibration signal and the compensation signal decrease at a fixed slope.

[0014] According to an embodiment of the present disclosure, the calibration signal is used to calibrate the voltage offset of the compensation signal, including: in the second working state, the first capacitor and the second capacitor connected in parallel form a closed loop, so that the compensation signal is equal to the calibration signal to achieve compensation for the voltage offset of the compensation signal.

[0015] According to an embodiment of the present disclosure, the first tail current source and the second tail current source are connected to a current regulation module, which includes: an adjustable resistor, an amplifier, a current mirror, and a first NMOS tube; wherein one end of the adjustable resistor is grounded and the other end is connected to the first input end of the amplifier, the second input end of the amplifier is a reference voltage signal, the output end of the amplifier is connected to the gate of the first NMOS tube, and the source of the first NMOS tube is connected to the current mirror, which is used to generate the first tail current source and the second tail current source in equal proportions.

[0016] According to an embodiment of the present disclosure, the current mirror includes a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor, wherein the first PMOS transistor is connected to the first NMOS transistor, the second PMOS transistor is connected to the first tail current source, the third PMOS transistor is connected to the second tail current source, and the sizes of the second PMOS transistor and the third PMOS transistor are proportional.

[0017] According to an embodiment of the present disclosure, the input unit includes a resistor and an inductor. When the inductor current is much larger than the current of the second tail current source, the resistor is used to generate an inductor signal according to the inductor current.

[0018] According to an embodiment of the present disclosure, the ratio of the parameters of the first capacitor in the signal generating module to the second capacitor in the signal superposition module is equal to the ratio of the parameters of the first tail current source in the signal generating module to the second tail current source in the signal superposition module, and the ratio of the parameters of the first discharge switch in the signal generating module to the second discharge switch in the signal superposition module. Therefore, the signal calibration module adjusts the connection state of the first capacitor and the second capacitor through the clock control signal generated by the comparison unit, so that the calibration signal generated by the first capacitor can correct the voltage offset of the compensation signal generated by the second capacitor, thereby realizing closed-loop control of the compensation signal, and then enabling the output unit to output a precise superposition signal of the compensation signal and the inductance signal; at the same time, the first tail current source and the second tail current source charge the first capacitor and the second capacitor respectively, therefore, the slope of the calibration signal and the compensation signal can be adaptively changed according to the switching frequency, effectively solving the technical problem in the related art that the DC-DC converter is difficult to apply to a wide switching frequency range. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0020] Figure 1a The figure schematically shows a compensation signal superposition circuit based on an operational amplifier in the related art.

[0021] Figure 1b Another compensation signal superposition circuit based on an operational amplifier in the related art is schematically shown.

[0022] Figure 2 The figure schematically shows a compensation signal superposition circuit based on capacitance and resistance in the related art.

[0023] Figure 3 The figure schematically shows a peak current control circuit based on the superposition of slope compensation signals according to an embodiment of the present disclosure.

[0024] Figure 4a The circuit diagram of the peak current control circuit based on the superposition of the slope compensation signal according to an embodiment of the present disclosure in the first working state is schematically shown.

[0025] Figure 4b The circuit diagram of the peak current control circuit based on the superposition of the slope compensation signal according to an embodiment of the present disclosure in the second working state is schematically shown.

[0026] Figure 5 The timing diagram of the peak current control circuit based on the superposition of the slope compensation signal according to the embodiment of the present disclosure is schematically shown.

[0027] Figure 6 The figure schematically shows a circuit diagram of a current regulation module according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0029] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0030] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0031] When expressions such as "at least one of A, B, and C, etc." are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0032] In a peak current mode controlled DC-DC converter, a slope compensation signal must be superimposed on the sampled inductor current to suppress subharmonic oscillations. The level of the compensation signal significantly affects the DC-DC converter's load capacity, loop stability, loop low-frequency gain, and ability to suppress subharmonic oscillations. The slope of the compensation signal should be greater than half the difference between the falling and rising slopes of the inductor current. If the level is too high, the converter's peak inductor current will be limited to a small value, affecting the converter's load capacity. If the level is too low, the low-frequency gain of the error amplifier in the control system will be reduced under light load conditions, making it difficult to fully suppress subharmonic oscillations.

[0033] Figure 1a The figure schematically shows a compensation signal superposition circuit based on an operational amplifier in the related art.

[0034] like Figure 1a As shown, the compensation signal V RAMP Connected to the negative input terminal of the operational amplifier 110 through the resistor R1, the inductor current information V SENSE The resistor R2 is connected to the negative input terminal of the operational amplifier 110. The positive input terminal of the operational amplifier 110 is grounded. The output terminal of the operational amplifier 110 is used to output the superimposed signal V SUM , and through the resistor R F Feedback is sent to the negative input terminal. At this point, the operational amplifier 110 implements a function similar to an adder in the circuit.

[0035] Figure 1b Another compensation signal superposition circuit based on an operational amplifier in the related art is schematically shown.

[0036] like Figure 1b As shown, the compensation signal V RAMP Connected to the first voltage-current converter 120, the inductor current information V SENSE connected to the second voltage-current converter 130 and connected to the second voltage-current converter 130 through the resistor R F The output current signals are superimposed to obtain the superimposed signal V SUM .

[0037] However, the above Figure 1a and Figure 1bThe superposition circuit shown uses an operational amplifier, which may cause distortion of the superposition signal and incur high costs in terms of circuit area and power consumption.

[0038] Figure 2 The figure schematically shows a compensation signal superposition circuit based on capacitance and resistance in the related art.

[0039] like Figure 2 As shown, the circuit 200 includes a capacitor C S , resistor R F , discharge switch S1, discharge switch S2 and constant current source I C Resistor R F With capacitor C S Series connection realizes the addition function.

[0040] When the clock signal CLK is at a low level, S1 and S2 are disconnected, and the constant current source I C For capacitor C S Charging, the capacitor C S A gradually increasing voltage drop is generated at both ends, which is the compensation signal V RAMP At the same time, the inductor current I SENSE With constant current source I C Parallel flow resistor R F , the resistor R F The voltage drop across the two ends is V SENSE Therefore, the capacitor C S The upper plate can directly obtain the superimposed signal V SUM .

[0041] Inductor current information V SENSE It can be expressed as the following formula (1).

[0042] (1)

[0043] Compensation signal V RAMP It can be expressed as the following formula (2).

[0044] (2)

[0045] Where t is time.

[0046] Superimposed signal V SUM It can be expressed as the following formula (3).

[0047] (3)

[0048] In addition, the superimposed signal V SUM It is also raised to a constant level (I C ·R F), which can be used as a DC bias to prevent the error amplifier of the subsequent stage from entering the nonlinear region.

[0049] When the clock signal CLK is high, S1 and S2 are closed, and the capacitor C S Rapid discharge completes the generation of compensation signal. However, at this time, the compensation signal is open-loop control, and the constant current I C The size of the capacitor C S Parameters such as the capacitance and the current capability of discharge switches S1 and S2 directly determine the level of the slope compensation signal. Since the capacitor charging current is constant, the slope of the compensation signal remains constant. However, at different switching frequencies, the selected inductor value varies, and the required compensation signal slope also varies. Therefore, this approach is difficult to apply to DC-DC converters with a wide switching frequency range.

[0050] However, in the actual manufacturing and operation of the circuit, the process, voltage, and temperature will fluctuate, and as a switching power supply, the noise in the circuit is also relatively serious, which will cause the various signals in the above formulas (1) to (3) to deviate from the set values. On the one hand, if the current I C Too large and the capacitor C S If it is too small, the compensation signal amplitude will be too high, which will overly limit the inductor current peak, affect the converter's load capacity, and affect the loop stability; on the contrary, the slope compensation signal amplitude will be too low, making it difficult to completely suppress subharmonic oscillation. On the other hand, if the current capacity of S1 and S2 is insufficient, the charging stage will be caused by I C To capacitor C S The charge provided cannot be completely discharged, and the capacitor C S Accumulate charge cycle by cycle. So that the compensation signal (i.e. capacitor C S The DC level of the voltage difference between the two ends is significantly high, which limits the inductor current peak and the converter's load capacity to a large extent, and even affects the normal operation of the subsequent error amplifier.

[0051] In view of this, an embodiment of the present disclosure provides a peak current control circuit based on the superposition of a slope compensation signal, comprising: a signal generating module, comprising: a first tail current source, a first capacitor, a comparing unit, and a first discharge switch, wherein one end of the first capacitor is connected to the first tail current source and the other end is grounded, the first capacitor is used to generate a calibration signal, the comparing unit is used to compare the calibration signal with a reference signal to obtain a clock control signal, and the first discharge switch is used to switch the charge / discharge state of the first capacitor according to the clock control signal; a signal superposition module, comprising: an output unit, an input unit, a second tail current source, a second capacitor, and a second discharge switch, wherein one end of the second capacitor is connected to the second A tail current source, the other end of which is grounded, a second capacitor is used to generate a compensation signal, a calibration signal is used to calibrate the voltage offset of the compensation signal so that the compensation signal is equal to the calibration signal, a second discharge switch is used to switch the charge / discharge state of the second capacitor according to a clock control signal, and an output unit is used to output a superimposed signal obtained by adding the compensation signal and the inductor current information input by the input unit; a signal calibration module is used to control the connection state of the first capacitor and the second capacitor according to the clock control signal; wherein the ratio of the parameters of the first tail current source to the parameters of the second tail current source, the ratio of the parameters of the first capacitor to the parameters of the second capacitor, and the ratio of the parameters of the first discharge switch to the parameters of the second discharge switch are all equal.

[0052] Figure 3 The figure schematically shows a peak current control circuit based on the superposition of slope compensation signals according to an embodiment of the present disclosure.

[0053] like Figure 3 As shown, the circuit includes a signal generating module 310, a signal superposition module 320 and a signal calibration module 330. The signal generating module 310 includes a first wake source I C0 , the first capacitor C S0 , comparison unit 331, first discharge switch S 10 ; The signal superposition module 320 includes a second tail current source I C , the second capacitor C S , the second discharge switch S1.

[0054] According to an embodiment of the present disclosure, the first wake source I C0 The parameters of the second wake source I C The ratio of the parameters of the first capacitor C S0 The parameters of the second capacitor C S The parameter ratio of the first discharge switch S 10 The ratio of the parameters of the second discharge switch S1 is equal to that of the second capacitor C S Voltage drop signal V RAMP With the first capacitor C S0 Voltage drop signal V RAMP0 equal.

[0055] According to an embodiment of the present disclosure, the first capacitor C S0 One end is connected to the first tail flow source I C0 , the other end is grounded, the first capacitor C S0 Used to generate the calibration signal V RAMP0 The comparison unit 311 is used to convert the calibration signal V RAMP0 With the reference signal V H or V L By comparison, the clock control signal CLK is obtained, and the first discharge switch S 10 Used to switch the first capacitor C according to the clock control signal CLK S0 charge / discharge status.

[0056] According to an embodiment of the present disclosure, the second capacitor C S One end is connected to the second tail flow source I C , the other end is grounded, the second capacitor C S Used to generate compensation signal V RAMP , calibration signal V RAMP0 Used to calibrate the compensation signal V RAMP The voltage offset is such that the compensation signal is equal to the calibration signal. The second discharge switch S1 is used to switch the second capacitor C according to the clock control signal CLK. S The output unit is used to output the compensation signal V RAMP The inductor current information V SENSE The superimposed signal V SUM .

[0057] According to an embodiment of the present disclosure, the first wake source I is changed C0 、Second wake source I C The current size can simultaneously change the slope of the compensation signal and the frequency of the clock signal CLK, that is, the switching frequency of the DC-DC converter, thereby realizing dynamic adjustment of the slope of the compensation signal adaptively as the switching frequency changes, and is therefore applicable to DC-DC converters with a wide switching frequency range.

[0058] According to the embodiment of the present disclosure, only the calibration V RAMP0 Closed-loop control is achieved through the comparison unit. Due to non-ideal factors such as process parameter deviation and switching noise in the actual circuit, the second capacitor C S The charge and discharge charges may be unequal in one cycle, that is, the compensation signal V RAMP The charge in each cycle may accumulate, resulting in a significant DC voltage deviation. In peak current mode control, the inductor current information V SENSE With the superimposed signal V SUM Only when the compensation signal VRAMP It plays a role in the loop control when it rises, and RAMP The signal falling process has no effect. Therefore, V RAMP The fall time of the closed loop calibration is performed, and the V RAMP0 Calibrate V RAMP , thereby eliminating the DC voltage offset.

[0059] According to an embodiment of the present disclosure, the ratio of the parameters of the first capacitor in the signal generating module to the second capacitor in the signal superposition module is equal to the ratio of the parameters of the first tail current source in the signal generating module to the second tail current source in the signal superposition module, and the ratio of the parameters of the first discharge switch in the signal generating module to the second discharge switch in the signal superposition module. Therefore, the signal calibration module adjusts the connection state of the first capacitor and the second capacitor through the clock control signal generated by the comparison unit, so that the calibration signal generated by the first capacitor can correct the voltage offset of the compensation signal generated by the second capacitor, thereby realizing closed-loop control of the compensation signal, and then enabling the output unit to output a precise superposition signal of the compensation signal and the inductance signal; at the same time, the first tail current source and the second tail current source charge the first capacitor and the second capacitor respectively, therefore, the slope of the calibration signal and the compensation signal can be adaptively changed according to the switching frequency, effectively solving the technical problem in the related art that the DC-DC converter is difficult to apply to a wide switching frequency range.

[0060] According to an embodiment of the present disclosure, the input unit includes a resistor R F and an inductor, where when the inductor current is much greater than the current of the second tail current source, the resistor is used to generate an inductor signal according to the inductor current.

[0061] According to an embodiment of the present disclosure, the resistor R F The voltage drop across the inductor is determined by the inductor current I SENSE Decision, in taking I C0 with I C Both are much smaller than I SENSE In this case, the second capacitor C S It can be regarded as a simple adder, with the upper plate voltage V SUM This is the desired superposition signal.

[0062] According to an embodiment of the present disclosure, the comparison unit includes a first comparator CMP H and a trigger SR, the first input of which is connected to the first comparator CMP H The output terminal of the first comparator CMP H For comparison with the calibration signal V RAMP0 and rising reference signal V H ; In the calibration signal V RAMP0 Rising to greater than the rising reference signal V HIn case of H Inverted, the clock control signal CLK is converted from the first level (1) to the second level (0).

[0063] According to an embodiment of the present disclosure, the trigger is used to store the output result of the first comparator, which can maintain the stable operation of the circuit.

[0064] According to an embodiment of the present disclosure, the comparison unit further includes a second comparator CMP L , the second comparator CMP L For comparison with the calibration signal V RAMP0 and the falling reference signal V L ; In the calibration signal V RAMP0 Falls to less than the falling reference signal V L In case of L Inverted, the clock control signal CLK is converted from the second level (0) to the first level (1).

[0065] According to an embodiment of the present disclosure, the compensation signal and the calibration signal are limited to the rising reference signal V H With the falling reference signal V L The slope of the compensation signal / calibration signal is changed according to the current of the first tail current source, and the frequency of the clock control signal is changed at the same time, so it is better suitable for DC-DC converters with a wide switching frequency range.

[0066] According to an embodiment of the present disclosure, the signal calibration module includes a first calibration switch S C1 and the second calibration switch S C2 , controls the first capacitor C according to the clock control signal CLK S0 With the second capacitor C S The connection state includes: when the clock control signal CLK is at the first level, the circuit is in the first working state, the first calibration switch S C1 and the second calibration switch S C2 When the clock control signal CLK is at the second level, the circuit is in the second working state, the first calibration switch S C1 and the second calibration switch S C2 Closed, the first capacitor C S0 With the second capacitor C S in parallel.

[0067] According to an embodiment of the present disclosure, the first capacitor and the second capacitor are directly connected in parallel in the second working state, and the calibration signal V is controlled by the closed loop. RAMP0 Calibration compensation signal V RAMP , thereby eliminating V RAMP Possible DC voltage offset.

[0068] According to an embodiment of the present disclosure, in a first working state, the first discharge switch is disconnected from the second discharge switch, the first tail current source charges the first capacitor to generate a calibration signal, and the second tail current source charges the second capacitor to generate a compensation signal, wherein the slope of the calibration signal changes with the current size of the first tail current source, including: when the current size of the first tail current source decreases, the rising slope of the calibration signal decreases and the frequency of the clock control signal decreases; when the current size of the first tail current source increases, the rising slope of the calibration signal increases and the frequency of the clock control signal increases.

[0069] According to an embodiment of the present disclosure, within a working cycle, the first working state and the second working state are alternately performed, corresponding to a first duration and a second duration, respectively.

[0070] According to an embodiment of the present disclosure, when the current of the first tail current source decreases, the rising slope of the calibration signal decreases, and V RAMP Rising to V H The time of the calibration signal increases, and thus the frequency of the clock control signal decreases; on the contrary, when the current of the first tail current source increases, the rising slope of the calibration signal increases, and V RAMP Rising to V H The time becomes shorter and the frequency of the CLK signal becomes higher.

[0071] According to the embodiments of the present disclosure, the current magnitude of the first tail current source directly affects the charging speed of the first capacitor, thereby determining the rising slope of the calibration signal. The rising slope of the calibration signal in turn affects the frequency of the clock control signal. A decrease in current leads to a decrease in frequency, and an increase in current leads to an increase in frequency, thereby achieving dynamic adjustment of the compensation signal slope as the switching frequency changes.

[0072] According to an embodiment of the present disclosure, in the second working state, the first discharge switch and the second discharge switch are closed, the first capacitor and the second capacitor are discharged, and the calibration signal and the compensation signal decrease at a fixed slope.

[0073] According to the embodiment of the present disclosure, since the DC-DC converter is applied to the peak current mode control, the magnitude of the superimposed signal in the second working state has no effect on the loop control.

[0074] According to an embodiment of the present disclosure, the calibration signal is used to calibrate the voltage offset of the compensation signal, including: in the second working state, the first capacitor and the second capacitor connected in parallel form a closed loop, so that the compensation signal is equal to the calibration signal to achieve compensation for the voltage offset of the compensation signal.

[0075] According to an embodiment of the present disclosure, by connecting the first capacitor and the second capacitor in parallel to form a closed loop in the second working state, the compensation signal and the calibration signal are made equal, and the voltage offset of the compensation signal is effectively eliminated, which is beneficial to improving the accuracy of the superimposed signal and optimizing the circuit performance.

[0076] The following will be passed Figure 4a and Figure 4b The connection status and working principle of the superimposed circuit in the first working state and the second working state are respectively shown.

[0077] Figure 4a The circuit diagram of the peak current control circuit based on the superposition of the slope compensation signal according to an embodiment of the present disclosure in the first working state is schematically shown.

[0078] Figure 4b The circuit diagram of the peak current control circuit based on the superposition of the slope compensation signal according to an embodiment of the present disclosure in the second working state is schematically shown.

[0079] like Figure 4a As shown, in the first working state, S 10 , S1, S C1 、S C2 Disconnect, I C0 with I C C S0 with C S Charging, compensation signal V RAMP With the calibration signal V RAMP0 Rising at a set slope, resistor R F The voltage drop across the inductor reacts to the inductor current I SENSE Size. C S Upper plate voltage V SUM It is the superposition result of the required compensation signal and the inductance signal. RAMP0 The signal rises to V H When the first comparator CMP H Flip, the CLK signal becomes high level (1), and the first working state ends.

[0080] like Figure 4b As shown, in the second working state, S 10 , S1, S C1 、S C2 Closed, C S0 with C S Discharge at a faster speed to compensate the signal V RAMP With the calibration signal V RAMP0 The second capacitor C S With the first capacitor C S0 In parallel, the closed-loop controlled calibration signal V RAMP0Calibration compensation signal V RAMP signal, eliminating V RAMP There may be a DC voltage offset on the RAMP0 The signal drops to V L When the second comparator CMP L Flip, the CLK signal becomes low level (0), and the second working state ends.

[0081] Figure 5 The timing diagram of the peak current control circuit based on the superposition of the slope compensation signal according to the embodiment of the present disclosure is schematically shown.

[0082] like Figure 5 As shown, Φ1 corresponds to the first working state, and Φ2 corresponds to the second working state. The rise and fall of each signal have been described above and will not be repeated here.

[0083] According to an embodiment of the present disclosure, the first tail current source and the second tail current source are connected to a current regulation module, which includes: an adjustable resistor, an amplifier, a current mirror, and a first NMOS tube; wherein, one end of the adjustable resistor is grounded and the other end is connected to the first input end of the amplifier, the second input end of the amplifier is a reference voltage signal, the output end of the amplifier is connected to the gate of the first NMOS tube, and the source of the first NMOS tube is connected to the current mirror, and the current mirror is used to generate the first tail current source and the second tail current source in equal proportions.

[0084] According to an embodiment of the present disclosure, the current mirror includes a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor, wherein the first PMOS transistor is connected to the first NMOS transistor, the second PMOS transistor is connected to the first tail current source, the third PMOS transistor is connected to the second tail current source, and the sizes of the second PMOS transistor and the third PMOS transistor are proportional.

[0085] Figure 6 The figure schematically shows a circuit diagram of a current regulation module according to an embodiment of the present disclosure.

[0086] like Figure 6 As shown, the adjustable resistor R RAMP One end is grounded and the other end is connected to the first input end of the amplifier 610. The second input end of the amplifier 610 is a reference voltage signal V REF , adjustable resistor R RAMP Voltage across both ends V RES Clamped to the reference voltage signal V REF , that is, V REF =V RES The output terminal of the amplifier 610 is connected to the gate of the first NMOS transistor 630, and the drain of the first NMOS transistor 630 is connected to the adjustable resistor R RAMP , that is, the adjustable resistor RRAMP The current flowing through the first NMOS transistor 630 enters the current mirror 620 and is amplified in proportion in the current mirror 620 to generate the first current source I C0 and the second current source I C For example, the size ratio of the first PMOS transistor 621, the second PMOS transistor 622, and the third PMOS transistor 623 in the current mirror 620 can be 1:N:N, which can be achieved by setting the gate lengths of the transistors to be consistent and the gate widths to be set in accordance with 1:N:N. Therefore, I C0 with I C are equal to N times the reference current of the first PMOS transistor 621, the reference current is V REF / R ramp Therefore, by changing R RAMP The resistance value of the first current source I C0 and the second current source I C The current size.

[0087] According to an embodiment of the present disclosure, a current mirror is used to generate a first tail current source and a second tail current source of equal proportions, ensuring that the current magnitudes of the first tail current source and the second tail current source change with the resistance value of the adjustable resistor, so that the calibration signal generated by the first tail current source can calibrate the DC voltage offset that occurs in the compensation signal generated by the second tail current source.

[0088] According to an embodiment of the present disclosure, the currents of the first tail current source and the second tail current source are kept equal, and may also be generated using a current regulation module other than a current mirror.

[0089] The circuit diagrams and timing diagrams in the accompanying drawings illustrate circuit operations according to various embodiments of the present disclosure. In this regard, those skilled in the art will appreciate that the features described in the various embodiments of the present disclosure may be combined and / or coupled in various ways, even if such combinations or couplings are not explicitly described in the present disclosure. In particular, the features described in the various embodiments of the present disclosure may be combined and / or coupled in various ways without departing from the spirit and teachings of the present disclosure. All such combinations and / or couplings fall within the scope of the present disclosure.

[0090] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A peak current control circuit based on slope compensation signal superposition, characterized in that: include: A signal generation module, comprising: a first tail current source, a first capacitor, a comparison unit, and a first discharge switch, wherein one end of the first capacitor is connected to the first tail current source and the other end is grounded, the first capacitor is used to generate a calibration signal, the comparison unit is used to compare the calibration signal with a reference signal to obtain a clock control signal, and the first discharge switch is used to switch the charge / discharge state of the first capacitor according to the clock control signal; A signal superposition module, comprising: an output unit, an input unit, a second tail current source, a second capacitor, and a second discharge switch, wherein one end of the second capacitor is connected to the second tail current source and the other end is grounded, the second capacitor is used to generate a compensation signal, the calibration signal is used to calibrate the voltage offset of the compensation signal so that the compensation signal is equal to the calibration signal, the second discharge switch is used to switch the charge / discharge state of the second capacitor according to the clock control signal, and the output unit is used to output a superposition signal obtained by adding the compensation signal and the inductor current information input by the input unit; a signal calibration module, configured to control a connection state between the first capacitor and the second capacitor according to the clock control signal; The ratio of the parameters of the first tail current source to the parameters of the second tail current source, the ratio of the parameters of the first capacitor to the parameters of the second capacitor, and the ratio of the parameters of the first discharge switch to the parameters of the second discharge switch are all equal.

2. The circuit according to claim 1, wherein: The comparison unit includes a first comparator and a trigger, wherein the first input terminal of the trigger is connected to the output terminal of the first comparator, and the first comparator is used to compare the calibration signal with the rising reference signal; When the calibration signal rises to be greater than the rising reference signal, the first comparator is inverted, and the clock control signal is converted from the first level to the second level.

3. The circuit according to claim 2, characterized in that The comparison unit further includes a second comparator, the second comparator being configured to compare the calibration signal with a falling reference signal; When the calibration signal falls below the falling reference signal, the second comparator is reversed, and the clock control signal is converted from the second level to the first level.

4. The circuit according to claim 2, characterized in that The signal calibration module includes a first calibration switch and a second calibration switch, and controlling the connection state of the first capacitor and the second capacitor according to the clock control signal includes: When the clock control signal is at a first level, the circuit is in a first working state, and the first calibration switch and the second calibration switch are disconnected; When the clock control signal is at the second level, the circuit is in the second working state, the first calibration switch and the second calibration switch are closed, and the first capacitor and the second capacitor are connected in parallel.

5. The circuit according to claim 4, characterized in that In the first working state, the first discharge switch and the second discharge switch are disconnected, the first tail current source charges the first capacitor to generate a calibration signal, and the second tail current source charges the second capacitor to generate a compensation signal, wherein the slope of the calibration signal changes with the current of the first tail current source, including: When the current of the first tail current source decreases, the rising slope of the calibration signal decreases and the frequency of the clock control signal decreases; When the current of the first tail current source increases, the rising slope of the calibration signal increases, and the frequency of the clock control signal increases.

6. The circuit according to claim 4, characterized in that In the second working state, the first discharge switch and the second discharge switch are closed, the first capacitor and the second capacitor are discharged, and the calibration signal and the compensation signal decrease at a fixed slope.

7. The circuit according to claim 4, characterized in that The calibration signal is used to calibrate the voltage offset of the compensation signal, including: In the second working state, the first capacitor and the second capacitor connected in parallel form a closed loop, so that the compensation signal is equal to the calibration signal, thereby compensating for the voltage offset of the compensation signal.

8. The circuit according to claim 1, wherein: The first tail current source and the second tail current source are connected to a current regulating module, which includes: an adjustable resistor, an amplifier, a current mirror, and a first NMOS transistor; One end of the adjustable resistor is grounded and the other end is connected to the first input end of the amplifier, the second input end of the amplifier is a reference voltage signal, the output end of the amplifier is connected to the gate of the first NMOS tube, and the source of the first NMOS tube is connected to the current mirror, and the current mirror is used to generate the first tail current source and the second tail current source in equal proportion.

9. The circuit according to claim 8, characterized in that The current mirror includes a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor, wherein the first PMOS transistor is connected to the first NMOS transistor, the second PMOS transistor is connected to the first tail current source, and the third PMOS transistor is connected to the second tail current source, and the sizes of the second PMOS transistor and the third PMOS transistor are proportional.

10. The circuit according to claim 1, wherein: The input unit includes a resistor and an inductor. When the inductor current is much larger than the current of the second tail current source, the resistor is used to generate an inductor signal according to the inductor current.

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