Line voltage sampling and compensating circuit for AC-DC

Abstract

The invention relates to the technical field of switching power supplies, and particularly discloses a line voltage sampling and compensating circuit for AC-DC (alternating current-direct current), which comprises a load detection module, a sampling pulse generation module, a current sampling module, a compensating current generator module, a driving control module and a power switch, wherein the load detection module is used for detecting a current load state; the sampling pulse generator module is used for dynamically adjusting the generation time of a sampling pulse signal according to the load state; the current sampling module is used for sampling the current change slope in the primary side inductor; the compensation current generator module is used for generating compensation current according to the current change slope; and the driving control module is used for adjusting driving time cycle by cycle according to the change of the compensation current and controlling the on-off of the power switch.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supplies, and in particular to a line voltage sampling and compensation circuit for AC-DC. Background Art

[0002] With the popularization of intelligent electronic devices, the demand for switching power supply products has increased. Intelligent electronic devices have certain requirements for the constant current consistency of switching power supply products. Since there is a system delay time Δt between the logic switch signal and the power switch completely completing the switching action of the switching power supply, the actual peak current of the primary inductor will appear as follows under different line voltages. Figure 1 The obvious error shown. The principle is as follows:

[0003] During the conduction phase of the primary inductor, the peak current Ipk in the primary inductor is as follows:

[0004] Ipk=√2*Vac / Lp*Ton (Formula 1)

[0005] When Lp is known to be fixed, the peak current Ipk in the primary inductor is only related to the line voltage Vac and the primary inductor conduction time Ton, and is a linear function. Due to the influence of the system delay time Δt, the actual primary inductor peak current Ipk_actual is as follows:

[0006] Ipk_actual=√2*Vac / Lp*(Ton+Δt) (Formula 2)

[0007] The primary inductor peak current error ΔI is as follows:

[0008] ΔI=√2*Vac / Lp*Δt (Formula 3)

[0009] It can be seen from Formula 3 that the primary inductance peak current error ΔI is strongly correlated with the line voltage Vac, which means that under different line voltages, the actual primary inductance peak current will have different errors, resulting in poor constant current consistency of the switching power supply. Summary of the invention

[0010] In view of the above problems, the purpose of the present invention is to provide a line voltage sampling and compensation circuit for AC-DC, which can achieve consistency of primary peak current under different line voltages, and thus achieve stability of the circuit overcurrent point.

[0011] The present invention provides a line voltage sampling and compensation circuit for AC-DC, comprising: a load detection module, a sampling pulse generation module, a current sampling module, a compensation current generator module, a drive control module and a power switch;

[0012] Wherein, the load detection module is used to detect the current load status;

[0013] The sampling pulse generator module is used to dynamically adjust the generation time of the sampling pulse signal according to the load state;

[0014] The current sampling module is used to sample the current change slope in the primary inductor;

[0015] The compensation current generator module is used to generate a compensation current according to the current change slope;

[0016] The drive control module is used to adjust the drive time cycle by cycle according to the change of the compensation current, and control the on and off of the power switch.

[0017] In a possible implementation, one end of the load detection module is connected to the load end of the whole machine, and the other end is connected to one end of the sampling pulse generator module; the other end of the sampling pulse generating module is connected to the first end of the current sampling module; the second end of the current sampling module is connected to the primary inductor, the third end of the current sampling module is connected to one end of the compensation current generator module, the other end of the compensation current generator module is connected to one end of the drive control module, and the other end of the drive control module is connected to the power switch.

[0018] In a possible implementation, during the primary conduction phase of the transformer in each switching cycle, the sampling pulse generator module generates two pulse signals, and during the generation phase of the two pulse signals, the primary inductor current is sampled by the current sampling module; the two pulse signals include a first pulse signal and a second pulse signal;

[0019] Furthermore, the load detection module dynamically adjusts the generation time of sampling the second pulse signal according to the load state of the current cycle;

[0020] After completing the sampling of the primary inductor current, the compensation current generator module processes the sampled primary inductor current to obtain the rising slope of the primary inductor current under the current line voltage, and outputs the compensation current according to the rising slope of the primary inductor current, so as to compensate the drive control module according to the compensation current.

[0021] In a possible implementation, the load detection module obtains a reference voltage that changes with the load state through an auxiliary winding in a PSR power system and an optocoupler and a three-terminal adjustable shunt shunt regulator in an SSR power system.

[0022] In a possible implementation, the sampling pulse generator module generates the first pulse signal after a preset fixed delay after the primary side of the transformer is turned on.

[0023] In a possible implementation, the preset fixed delay is in the order of hundreds of nanoseconds and exceeds the leading edge blanking time.

[0024] In a possible implementation, the sampling pulse generation module includes: a first current mirror, a first switch, a second switch, an amplifier, a first resistor and a pulse generator;

[0025] The positive input terminal of the amplifier is connected to one end of the first switch and one end of the first resistor; the other end of the first switch is connected to the first current mirror; the second switch is connected in parallel to both ends of the first resistor;

[0026] The reverse input end of the amplifier is connected to the load detection module; the output end of the amplifier is connected to one end of the pulse generator, and the other end of the pulse generator is connected to the current sampling module.

[0027] In a possible implementation, in the primary conduction phase of any switching cycle, the compensation current generator module dynamically adjusts the compensation current according to two pulse signals output by the sampling pulse generator module and the sampled current value output by the current sampling module.

[0028] In a possible implementation, the compensation current generator module includes: a second current mirror, a plurality of switches, a plurality of capacitors, a plurality of PMOS tubes and a plurality of NMOS tubes;

[0029] The output end of the current sampling module is respectively connected to one end of the fifth switch and the sixth switch; the other end of the fifth switch is respectively connected to the second capacitor, the third switch and the gate of the sixth PMOS tube; the gate of the sixth PMOS tube; the other end of the sixth switch is respectively connected to the third capacitor, the fourth switch and the gate of the seventh PMOS tube;

[0030] The drains of the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, and the fifth PMOS tube are connected respectively; the gates of the first PMOS tube, the second PMOS tube, and the third PMOS tube are connected respectively; the gates of the fourth PMOS tube and the fifth PMOS tube are connected respectively; the source of the first PMOS tube is connected to the second current mirror and the gate of the first PMOS tube respectively; the source of the second PMOS tube is connected to the drain of the sixth PMOS tube and one end of the first resistor respectively; the source of the third PMOS tube is connected to the drain of the seventh PMOS tube and the other end of the first resistor; the drain of the fourth PMOS tube is connected to the gate of the fourth PMOS tube and the drain of the third NMOS tube respectively; the drain of the fifth PMOS tube is connected to the drain of the fourth NMOS tube and the input end of the drive control module;

[0031] The sources of the first NMOS tube, the second NMOS tube, the third NMOS tube, and the fourth NMOS tube are connected respectively; the gate of the first NMOS tube is connected to the gate of the second NMOS tube; the gate of the third NMOS tube is connected to the gate of the fourth NMOS tube; the drain of the first NMOS tube is connected to the gate of the first NMOS tube and the source of the sixth PMOS tube respectively; the drain of the second NMOS tube is connected to the gate of the second NMOS tube and the source of the seventh PMOS tube respectively.

[0032] In a possible implementation, the primary inductor peak current Icomp is calculated according to the following formula:

[0033] Icomp=k*(Vcs2-Vcs1) / R1

[0034] Wherein, k is the amplification factor of the current mirror, Vcs1 is the voltage of the primary inductor current stored in the second capacitor C2 when sampling the first pulse signal, Vcs2 is the voltage of the primary inductor current stored in the third capacitor when sampling the second pulse signal, and R1 is the resistance value of the first resistor of the sampling pulse generating module (11).

[0035] The line voltage sampling and compensation circuit for AC-DC provided by the present invention can achieve the consistency of primary peak current under different line voltages, thereby achieving the stability of the circuit overcurrent point. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a peak current curve diagram of the primary inductance of the prior art;

[0037] Figure 2 The line voltage sampling and compensation circuit provided by the embodiment of the present invention;

[0038] Figure 3 is a timing diagram of a current sampling signal provided by an embodiment of the present invention;

[0039] Figure 4 is a schematic diagram of the structure of a sampling signal generator provided by an embodiment of the present invention;

[0040] Figure 5 is a schematic structural diagram of a compensation current generator module provided in an embodiment of the present invention;

[0041] Figure 6 4 is a peak current curve diagram of the compensated primary inductance provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The following detailed description of the embodiments of the present invention is further described in detail in conjunction with the accompanying drawings and examples. The detailed description of the following embodiments and the accompanying drawings are used to exemplarily illustrate the principles of the present invention, but cannot be used to limit the scope of the present invention, that is, the present invention is not limited to the preferred embodiments described, and the scope of the present invention is defined by the claims.

[0043] In the description of the present invention, it should be noted that, unless otherwise specified, “plurality” means two or more than two; the terms “first”, “second”, etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance; for ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0044] Figure 2 The line voltage sampling and compensation circuit provided by the embodiment of the present invention is as follows: Figure 2 As shown, the present invention provides a line voltage sampling and compensation circuit for AC-DC, comprising: a load detection module 10, a sampling pulse generation module 11, a current sampling module 12, a compensation current generator module 13, a drive control module 14 and a power switch 15;

[0045] One end of the load detection module 10 is connected to the load end of the whole machine, and the other end is connected to one end of the sampling pulse generator module 11; the other end of the sampling pulse generator module 11 is connected to the first end of the current sampling module 12; the second end of the current sampling module 12 is connected to the primary inductance, and the third end of the current sampling module 12 is connected to one end of the compensation current generator module 13, and the other end of the compensation current generator module 13 is connected to one end of the drive control module 14, and the other end of the drive control module 14 is connected to the power switch 15.

[0046] Among them, the load detection module 10 is used to detect the current load state; the load state is used to dynamically adjust the generation of the sampling pulse. In addition, the load inspection method is compatible with any PSR or SSR power supply system, such as auxiliary winding sampling in the common PSR power supply system and optocoupler and TL431 sampling in the SSR power supply system;

[0047] The sampling pulse generator module 11 is used to dynamically adjust the generation time of the sampling pulse signal according to the load state;

[0048] The current sampling module 12 is used to sample the current change slope in the primary inductor. Usually, we convert the current value in the primary inductor into a voltage form for output, so that other modules can process the sampled current value.

[0049] The compensation current generator module 13 is used to generate a compensation current according to the current change slope; wherein the compensation current is controlled by the current change slope in the primary inductance, and the larger the current change slope, the larger the compensation current, which represents a higher line voltage;

[0050] The drive control module 14 is used to adjust the drive time cycle by cycle according to the change of the compensation current, and control the on and off of the power switch 15.

[0051] In a possible implementation, during the primary conduction phase of the transformer in each switching cycle, the sampling pulse generator module 11 generates two pulse signals, and during the generation phase of the two pulse signals, the primary inductor current is sampled by the current sampling module 12; the two pulse signals include a first pulse signal and a second pulse signal;

[0052] Furthermore, the load detection module 10 dynamically adjusts the generation time of the sampling second pulse signal according to the load state of the current cycle;

[0053] After completing the sampling of the primary inductor current, the compensation current generator module 13 processes the sampled primary inductor current to obtain the rising slope of the primary inductor current under the current line voltage, and outputs the compensation current according to the rising slope of the primary inductor current, so as to compensate the drive control module 14 according to the compensation current. Finally, the consistency of the primary peak current under different line voltages is achieved, thereby achieving the stability of the circuit overcurrent point.

[0054] In a possible implementation, the load detection module 10 obtains a reference voltage that changes with the load state through an auxiliary winding in a PSR power system and an optocoupler and a three-terminal adjustable shunt shunt regulator in an SSR power system.

[0055] In a possible implementation, the sampling pulse generator module 11 generates the first pulse signal after a preset fixed delay after the primary side of the transformer is turned on. The preset fixed delay is in the order of hundreds of nanoseconds and exceeds the leading edge blanking time to ensure that sampling will not occur during the ringing phase, thereby causing mis-sampling.

[0056] like Figure 5 As shown, the sampling pulse generating module 11 includes: a first current mirror I1, a first switch K1, a second switch K2, an amplifier CMP, a first resistor C1 and a pulse generator;

[0057] The positive input terminal of the amplifier CMP is connected to one end of the first switch K1 and one end of the first resistor C1; the other end of the first switch K1 is connected to the first current mirror I1; the second switch K2 is connected in parallel to both ends of the first resistor C1;

[0058] The inverting input terminal of the amplifier CMP is connected to the load detection module 10 ; the output terminal of the amplifier CMP is connected to one end of the pulse generator, and the other end of the pulse generator is connected to the current sampling module 12 .

[0059] In a possible implementation, during the primary conduction phase of any switching cycle, the compensation current generator module 13 dynamically adjusts the compensation current according to two pulse signals output by the sampling pulse generator module 11 and the sampled current value output by the current sampling module 12 .

[0060] In a possible implementation, the compensation current generator module 13 includes: a second current mirror I2, a plurality of switches, a plurality of capacitors, a plurality of PMOS transistors and a plurality of NMOS transistors;

[0061] The output end of the current sampling module 14 is respectively connected to one end of the fifth switch K5 and one end of the sixth switch K6; the other end of the fifth switch K5 is respectively connected to the gate of the second capacitor C2, the third switch K3 and the sixth PMOS tube P6; the gate of the sixth PMOS tube P6; the other end of the sixth switch K6 is respectively connected to the gate of the third capacitor C3, the fourth switch K4 and the seventh PMOS tube P7;

[0062] The drains of the first PMOS tube P1, the second PMOS tube P2, the third PMOS tube P3, the fourth PMOS tube P4, and the fifth PMOS tube P5 are connected respectively; the gates of the first PMOS tube P1, the second PMOS tube P2, and the third PMOS tube P3 are connected respectively; the gates of the fourth PMOS tube P4 and the fifth PMOS tube P5 are connected respectively; the source of the first PMOS tube P1 is connected to the second current mirror I2 and the gate of the first PMOS tube P1 respectively; the source of the second PMOS tube P2 is connected to the drain of the sixth PMOS tube P6 and one end of the first resistor R1 respectively; the source of the third PMOS tube P3 is connected to the drain of the seventh PMOS tube P7 and the other end of the first resistor R1; the drain of the fourth PMOS tube P4 is connected to the gate of the fourth PMOS tube P4 and the drain of the third NMOS tube N3 respectively; the drain of the fifth PMOS tube P5 is connected to the drain of the fourth NMOS tube N4 and the input end of the drive control module 14;

[0063] The sources of the first NMOS tube N1, the second NMOS tube N2, the third NMOS tube N3, and the fourth NMOS tube N4 are connected respectively; the gate of the first NMOS tube N1 is connected to the gate of the second NMOS tube N2; the gate of the third NMOS tube N3 is connected to the gate of the fourth NMOS tube N4; the drain of the first NMOS tube N1 is connected to the gate of the first NMOS tube N1 and the source of the sixth PMOS tube P6 respectively; the drain of the second NMOS tube N2 is connected to the gate of the second NMOS tube N2 and the source of the seventh PMOS tube P7 respectively.

[0064] Further, Figure 4 , Figure 5 Each switch in the Figure 3The signals in the figure are as follows: K1 is controlled by the primary conduction signal Φ1, K2, K3, and K4 are controlled by the initial state control signal Φ2, K5 is controlled by the sampling pulse signal Φ3, and K6 is controlled by the sampling pulse signal Φ4, and the primary conduction signal Φ1 and the initial state control signal Φ2 are signals with the same phase and opposite polarity. Figure 3 is a timing diagram of a current sampling signal provided by an embodiment of the present invention, Figure 4 is a schematic diagram of the structure of a sampling signal generator provided by an embodiment of the present invention, Figure 5 is a schematic structural diagram of a compensation current generator module provided in an embodiment of the present invention;

[0065] In the primary conduction phase of any switching cycle, the load detection module 10 provides a reference voltage Vload_sam that changes with the load state for the sampling pulse generator module 11. Vload_sam can be obtained in different ways, such as auxiliary winding sampling in the PSR power supply system and optocoupler and TL431 sampling in the SSR power supply system. On this basis, the sampling pulse generator module 11 generates two sampling pulse signals Φ3 and Φ4. The generation method of the sampling pulse signal Φ4 is as follows: Figure 4 As shown, first, the initial control signal Φ2 closes the switch K2 to discharge the capacitor C1 and set the voltage on the capacitor C1 to 0V; when the initial control signal Φ2 is 0 and the primary conduction signal Φ1 is 1, the switch K2 is opened and the switch K1 is closed. At this time, the constant current source I1 starts to charge the capacitor C1. When the voltage on the capacitor C1 reaches the reference voltage Vload_sam, the sampling pulse generator module 11 outputs the sampling pulse signal Φ4; when the primary conduction signal Φ1 is 0 and the initial control signal Φ2 is 1, the switch K1 is opened and the switch K2 is closed to discharge the capacitor C1 again.

[0066] In the primary conduction phase of any switching cycle, the compensation current generator module 13 dynamically adjusts the compensation current Icomp according to the sampling pulse signals Φ3 and Φ4 provided by the sampling pulse generator module 11 and the sampling current value Vcs provided by the current sampling module 12. The generation of the compensation current Icomp is as follows: Figure 5As shown, before the primary inductance of the transformer is turned on, the initial control signal Φ2 closes the switches K3 and K4, discharges the sampling capacitors C2 and C3, and sets the initial voltage of the sampling capacitors C2 and C3 to 0V; when the primary inductance of the transformer is turned on, the switches K3 and K4 are opened, and wait until the sampling pulse signals Φ3 and Φ4 arrive; after a fixed delay, the sampling pulse signal Φ3 closes the switch K5, and the sampling capacitor C2 records the primary inductance current provided by the current sampling module 12 at this time, and opens the switch K5 at the end of the sampling pulse signal Φ3, and stores the primary inductance current at this time in the sampling capacitor C2, which is recorded as Vcs1; similarly, in the sampling pulse signal Φ4 stage, the primary inductance current at this time is stored in the sampling capacitor C3, which is recorded as Vcs2; after the sampling pulse signal Φ4 ends, Figure 5 The transconductance amplifier in the circuit will process the voltage values ​​stored in the sampling capacitors C2 and C3.

[0067] The primary inductor peak current Icomp is calculated according to the following formula 4:

[0068] Icomp=k*(Vcs2-Vcs1) / R1 (Formula 4)

[0069] Wherein, k is the amplification factor of the current mirror, Vcs1 is the voltage of the primary inductor current stored in the second capacitor C2 when sampling the first pulse signal, Vcs2 is the voltage of the primary inductor current stored in the third capacitor when sampling the second pulse signal, and R1 is the resistance value of the first resistor of the sampling pulse generating module (11).

[0070] It can be seen from Formula 1 that, when Lp is known to be fixed, Ipk is only related to the line voltage Vac and the primary inductance conduction time Ton, and is a linear function with a slope of di / dt = √2*Vac / Lp. At the same time, according to the actual current rise curve in the primary inductance, we can also express the slope as di / dt = (Vcs2-Vcs1) / (T3-T2).

[0071] Combined with Formula 4, as long as k / R1 is fitted into T3-T2, Icomp can be strongly correlated with the line voltage Vac, and the change of Icomp can be used to characterize the change of the line voltage Vac to complete the control of the primary inductor peak current under different line voltages.

[0072] Figure 6 is a peak current curve diagram of the primary inductance after compensation provided by an embodiment of the present invention, such as Figure 6As shown, under different line voltages, according to the compensation current Icomp output by the compensation current generator module 13 in the current cycle, the reference current value Ipk for controlling the shutdown of the primary inductance in the drive control module 14 is dynamically adjusted to Ipk_comp, so as to avoid the influence of the system delay time Δt on the actual peak current in the primary inductance, thereby achieving consistency of the peak current in the primary inductance under different line voltages, thereby achieving stability of the circuit overcurrent point.

[0073] The line voltage sampling and compensation circuit for AC-DC provided by the present invention can achieve the consistency of primary peak current under different line voltages, thereby achieving the stability of the circuit overcurrent point.

[0074] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A line voltage sampling and compensation circuit for AC-DC, characterized in that: include: A load detection module (10), a sampling pulse generation module (11), a current sampling module (12), a compensation current generator module (13), a drive control module (14) and a power switch (15); Wherein, the load detection module (10) is used to detect the current load state; The sampling pulse generator module (11) is used to dynamically adjust the generation time of the sampling pulse signal according to the load state; The current sampling module (12) is used to sample the current change slope in the primary inductance; The compensation current generator module (13) is used to generate a compensation current according to the current change slope; The drive control module (14) is used to adjust the drive time cycle by cycle according to the change of the compensation current, and to control the on and off of the power switch (15).

2. The line voltage sampling and compensation circuit according to claim 1, characterized in that: One end of the load detection module (10) is connected to the load end of the whole machine, and the other end is connected to one end of the sampling pulse generator module (11); the other end of the sampling pulse generator module (11) is connected to the first end of the current sampling module (12); the second end of the current sampling module (12) is connected to the primary inductor, the third end of the current sampling module (12) is connected to one end of the compensation current generator module (13), the other end of the compensation current generator module (13) is connected to one end of the drive control module (14), and the other end of the drive control module (14) is connected to the power switch (15).

3. The line voltage sampling and compensation circuit according to claim 1, characterized in that: During the transformer primary conduction phase in each switching cycle, the sampling pulse generator module (11) generates two pulse signals, and during the generation phase of the two pulse signals, the primary inductor current is sampled through the current sampling module (12); the two pulse signals include a first pulse signal and a second pulse signal; Furthermore, the load detection module (10) dynamically adjusts the generation time of sampling the second pulse signal according to the load state of the current cycle; After completing the sampling of the primary inductor current, the compensation current generator module (13) processes the sampled primary inductor current to obtain the rising slope of the primary inductor current under the current line voltage, and outputs the compensation current according to the rising slope of the primary inductor current, so as to compensate the drive control module (14) according to the compensation current.

4. The line voltage sampling and compensation circuit according to claim 1, characterized in that: The load detection module (10) obtains a reference voltage that changes with the load state through an auxiliary winding in a PSR power supply system and an optocoupler and a three-terminal adjustable shunt shunt regulator in an SSR power supply system.

5. The line voltage sampling and compensation circuit according to claim 3, characterized in that: The sampling pulse generator module (11) generates the first pulse signal after a preset fixed delay after the primary side of the transformer is turned on.

6. The line voltage sampling and compensation circuit according to claim 5, characterized in that: The preset fixed delay is in the order of hundreds of nanoseconds and exceeds the leading edge blanking time.

7. The line voltage sampling and compensation circuit according to claim 1, characterized in that: The sampling pulse generating module (11) comprises: a first current mirror (I1), a first switch (K1), a second switch (K2), an amplifier (CMP), a first resistor (C1) and a pulse generator; The positive input end of the amplifier (CMP) is connected to one end of the first switch (K1) and one end of the first resistor (C1); the other end of the first switch (K1) is connected to the first current mirror (I1); the second switch (K2) is connected in parallel to both ends of the first resistor (C1); The reverse input end of the amplifier (CMP) is connected to the load detection module (10); the output end of the amplifier (CMP) is connected to one end of a pulse generator, and the other end of the pulse generator is connected to the current sampling module (12).

8. The line voltage sampling and compensation circuit according to claim 3, characterized in that: In the primary conduction phase of any switching cycle, the compensation current generator module (13) dynamically adjusts the compensation current according to the two pulse signals output by the sampling pulse generator module (11) and the sampled current value output by the current sampling module (12).

9. The line voltage sampling and compensation circuit according to claim 1, characterized in that: The compensation current generator module (13) comprises: a second current mirror (I2), a plurality of switches, a plurality of capacitors, a plurality of PMOS tubes and a plurality of NMOS tubes; The output end of the current sampling module (14) is respectively connected to one end of the fifth switch (K5) and one end of the sixth switch (K6); the other end of the fifth switch (K5) is respectively connected to the gate of the second capacitor (C2), the third switch (K3) and the sixth PMOS tube (P6); the gate of the sixth PMOS tube (P6); the other end of the sixth switch (K6) is respectively connected to the gate of the third capacitor (C3), the fourth switch (K4) and the seventh PMOS tube (P7); The drains of the first PMOS tube (P1), the second PMOS tube (P2), the third PMOS tube (P3), the fourth PMOS tube (P4) and the fifth PMOS tube (P5) are connected respectively; the gates of the first PMOS tube (P1), the second PMOS tube (P2) and the third PMOS tube (P3) are connected respectively; the gates of the fourth PMOS tube (P4) and the fifth PMOS tube (P5) are connected respectively; the source of the first PMOS tube (P1) is connected respectively to the second current mirror (I2) and the gate of the first PMOS tube (P1); The source of the PMOS tube (P2) is respectively connected to the drain of the sixth PMOS tube (P6) and one end of the first resistor (R1); the source of the third PMOS tube (P3) is connected to the drain of the seventh PMOS tube (P7) and the other end of the first resistor (R1); the drain of the fourth PMOS tube (P4) is respectively connected to the gate of the fourth PMOS tube (P4) and the drain of the third NMOS tube (N3); the drain of the fifth PMOS tube (P5) is connected to the drain of the fourth NMOS tube (N4) and the input end of the drive control module (14); The sources of the first NMOS tube (N1), the second NMOS tube (N2), the third NMOS tube (N3) and the fourth NMOS tube (N4) are connected respectively; the gate of the first NMOS tube (N1) is connected to the gate of the second NMOS tube (N2); the gate of the third NMOS tube (N3) is connected to the gate of the fourth NMOS tube (N4); the drain of the first NMOS tube (N1) is connected to the gate of the first NMOS tube (N1) and the source of the sixth PMOS tube (P6); and the drain of the second NMOS tube (N2) is connected to the gate of the second NMOS tube (N2) and the source of the seventh PMOS tube (P7).

10. The line voltage sampling and compensation circuit according to claim 1, characterized in that: The primary inductor peak current Icomp is calculated according to the following formula: Icomp=k*(Vcs2-Vcs1) / R1 Wherein, k is the amplification factor of the current mirror, Vcs1 is the voltage of the primary inductor current stored in the second capacitor C2 when sampling the first pulse signal, Vcs2 is the voltage of the primary inductor current stored in the third capacitor when sampling the second pulse signal, and R1 is the resistance value of the first resistor of the sampling pulse generating module (11).

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