Simulation IC test method and system based on load transient response

Abstract

The invention discloses a simulation IC test method and system based on load transient response, and aims to improve the performance evaluation precision of a simulation IC under a complex load condition. The method comprises the following steps: firstly, acquiring transient response waveforms and response delay characteristics of an analog IC (Integrated Circuit) in various load jump modes, and constructing a mapping matrix between a load current step change rate and response delay time; in the real-time test, response delay time in a future preset time period is predicted according to the step change rate of the current load current. When the steady-state time window exists, a fixed sampling time sequence is set based on the window to generate a first test waveform; and if the steady-state window does not exist, correcting the transient waveform, and generating a compensated second test waveform. And then time sequence decomposition is carried out on the test waveform, and a load transient stability evaluation matrix is constructed, so that the dynamic performance of the simulation IC is accurately evaluated, and a detailed performance test report is output.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing, and in particular to a load transient response-based analog IC testing method and system. Background Art

[0002] Analog integrated circuits (ICs) are widely used in key areas such as power management, signal processing, and communication interfaces. Their performance and stability are directly related to the reliability and power integrity of the entire system. In practical applications, analog ICs often face complex and variable load transitions, especially during rapid load steps. The chip's internal responsiveness becomes a key indicator for evaluating its dynamic performance.

[0003] The traditional load transient response test method of analog IC mainly adopts fixed sampling timing, that is, sampling and analyzing the output waveform at a preset trigger point to evaluate the device's overshoot suppression capability, steady-state voltage offset ( ), response recovery time, and other key parameters. However, this approach generally ignores the differences in activation levels of internal chip response paths caused by varying load current step change rates (di / dt). In particular, nonlinear factors such as transistor switching delays and layout parasitic capacitance can cause dynamic, nonlinear variations in chip response delay time.

[0004] The unpredictability of this response delay manifests itself as an obvious phase shift under a fixed sampling sequence, which directly causes the sampling point to miss the true peak of the output waveform, resulting in a serious distortion of the damping coefficient based on the high-frequency oscillation characteristic analysis (typical error exceeds 40%). At the same time, the voltage change that should belong to the delay stage is mistakenly counted into the steady-state interval, resulting in The voltage is artificially increased (error 10-30mV) and the recovery starting point timing is misjudged, thus affecting the true evaluation of the chip's overshoot regulation capability and response speed.

[0005] Furthermore, due to the lack of a compensation mechanism for response offsets caused by di / dt, traditional methods can easily lead to performance margin misjudgments in power integrity simulation and end-system design, which in turn poses the risk of system-level failure. Therefore, a test method and system that can dynamically track load transition behavior, correct sampling timing in real time, and restore true transient response characteristics is urgently needed to improve the accuracy and reliability of analog IC dynamic performance evaluation. Summary of the Invention

[0006] In order to solve at least one of the above technical problems, the present invention proposes an analog IC testing method and system based on load transient response.

[0007] A first aspect of the present invention provides an analog IC testing method based on load transient response, comprising: Acquire transient response waveform data and corresponding response delay characteristics of the analog IC under various load jump modes, and construct a mapping matrix between load current step change rate and delay time based on the response delay characteristics; Obtaining current load current step change rate data of the analog IC during real-time testing, and predicting a response delay time of the analog IC within a future preset time period based on the mapping matrix and the current load current step change rate data; According to the predicted response delay time, when a response steady-state time window exists within a future preset time period, a fixed sampling timing is set based on the steady-state time window for testing to generate a first transient response test waveform; When there is no response steady-state time window within a future preset time period, the transient response waveform obtained in real time is corrected to generate a compensated transient response waveform, which is calibrated as a second transient response test waveform; Perform timing decomposition according to the first transient response test waveform or the second transient response test waveform, construct a load transient stability evaluation matrix of the analog IC, determine the analog IC performance according to the stability evaluation matrix, and output an analog IC performance test report.

[0008] In this solution, the transient response waveform data and corresponding response delay characteristics of the analog IC under various load jump modes are obtained, and a mapping matrix between the load current step change rate and the delay time is constructed according to the response delay characteristics, specifically: Constructing a historical test record of the analog IC, and obtaining a load jump mode of the analog IC according to the historical test record, wherein the load jump mode includes a load current jump direction, a jump amplitude, a jump rate, and a jump frequency; Testing the analog IC under the multiple load jump modes, obtaining transient response waveform data of the analog IC under each load jump mode through the test, and identifying the corresponding transient start time and response stabilization time according to the transient response waveform data; Calculating the response delay time corresponding to each load jump mode according to the transient start time and the response stabilization time, and calculating the corresponding load current step change rate according to the load change amplitude and jump time under each load jump mode; The load current step change rate calculated in each load jump mode is paired with the corresponding response delay time to obtain a mapping matrix with the input variable being the load current step change rate and the output variable being the response delay time.

[0009] In this solution, the current load current step change rate data of the analog IC during real-time testing is obtained, and the response delay time of the analog IC within a future preset time period is predicted based on the mapping matrix and the current load current step change rate data. Specifically, Obtaining a load current change curve during multiple consecutive test cycles during the real-time test of the simulated IC, extracting a load current jump direction and jump rate according to the load current change curve, and calculating current load current step change rate data for each test cycle according to the load current jump direction and jump rate; A load change rate prediction model is constructed based on a long short-term memory network. The number of neurons in the input layer, hidden layer, and output layer is set, and the activation functions of the forget gate, input gate, and output gate are configured. The current load current step change rate data of each test cycle is converted into load change rate time series data according to the time series, and the load change rate time series data is divided into a training set and a prediction set. Importing the training set into the load change rate prediction model for model training, optimizing the network weights through a back propagation algorithm, and when the prediction error of the load change rate prediction model is lower than a preset threshold, importing the prediction set into the load change rate prediction model to predict the load current step change rate for multiple preset time periods within a future preset time period, thereby obtaining a predicted load current step change rate for each time period; The predicted load current step change rate is matched with the mapping matrix to predict the response delay time of the analog IC in each preset time period in the future preset time period.

[0010] In this solution, the predicted load current step change rate is matched with the mapping matrix to predict the response delay time of the analog IC in each preset time period in the future preset time period, specifically: querying, according to the mapping matrix, whether there is a load change rate record that matches the predicted load current step change rate, and when a matching record is found, directly extracting the corresponding response delay time from the mapping matrix as a prediction result; When no matching record is found, screening two load current step change rates and their response delay times adjacent to the predicted load current step change rate in the mapping matrix, and calculating a response delay time interpolation coefficient corresponding to the predicted load current step change rate based on a linear interpolation algorithm; Calculating an intermediate prediction delay time according to the interpolation coefficient and adjacent response delay times, and simultaneously obtaining a maximum response delay time and a minimum response delay time in the mapping matrix; determining whether the intermediate predicted delay time is within a threshold interval formed by a maximum response delay time and a minimum response delay time, and outputting the intermediate predicted delay time as a final response delay time when the intermediate predicted delay time is within the threshold interval; When the intermediate predicted delay time exceeds the threshold interval, the response delay time corresponding to the load change rate closest to the predicted load current step change rate is selected as the corrected prediction result, and the threshold interval judgment is repeated until the response delay time that meets the interval requirements is obtained, completing the response delay time prediction of the analog IC in each preset time period in the future preset time period.

[0011] In this solution, based on the predicted response delay time, when there is a response steady-state time window within a preset time period in the future, a fixed sampling timing is set based on the steady-state time window for testing to generate a first transient response test waveform, specifically: Based on the predicted response delay time, the response stable time point of each time period in the future preset time period is obtained, and the time length of each time period is analyzed in combination with the current system clock to obtain the stable response duration in each time period; Determine whether there is a response steady-state time window that meets the minimum test sampling time requirement based on the stable response duration; and when the stable response duration is greater than the minimum test sampling time, determine the center position of the stable window based on the time interval between the response delay time and the stabilization time; According to the center position of the stable window combined with the sampling period, a fixed sampling timing is planned, the sampling timing is aligned with the stable response time window in each time period, and a sampling time list is generated; The load transient response waveform during the real-time test of the analog IC is collected according to the sampling time list to obtain a first transient response test waveform.

[0012] In this solution, when there is no response steady-state time window within the preset time period in the future, the transient response waveform obtained in real time is corrected to generate a compensated transient response waveform, which is calibrated as the second transient response test waveform, specifically: When there is no response steady-state time window within the future preset time period, transient response waveform data of the simulated IC test is collected in real time during the test time of the future preset time period; Determining a delay compensation amount for each preset time period according to the predicted response delay time data for a plurality of preset time periods within a future preset time period; Extracting a time series response value based on the transient response waveform data collected in real time, and performing time axis displacement compensation on the time series response value based on the delay compensation amount to generate intermediate correction waveform data; Establishing a nonlinear response delay differential equation model based on the intermediate correction waveform data, wherein the model parameters are dynamically generated by fitting actual load step change characteristics and a history mapping matrix; An adaptive sliding time window is set along the load transition boundary. The time window width is adjusted in real time based on the solution of the differential equation model. When a high-frequency oscillation component is detected, a real-time reconstruction algorithm based on phase trajectory analysis is executed on the waveform data within the time window to generate an oscillation compensation waveform segment. In the transient recovery interval, an exponential decay envelope matching algorithm is used to correct the voltage offset. The oscillation compensation waveform fragment is fused with the corrected recovery interval waveform through time-series splicing to generate a compensated transient response waveform, which is calibrated as the second transient response test waveform.

[0013] In this solution, the timing decomposition is performed based on the first transient response test waveform or the second transient response test waveform, a load transient stability evaluation matrix of the analog IC is constructed, the analog IC performance is determined based on the stability evaluation matrix, and an analog IC performance test report is output, specifically: Performing time domain decomposition on the first transient response test waveform or the second transient response test waveform based on Fourier transform to extract a high-frequency oscillation component and a steady-state offset component; Extracting the amplitude attenuation sequence of each cycle based on the periodic envelope change curve of the high-frequency oscillation component, performing exponential fitting on the amplitude attenuation sequence to calculate the damping coefficient of the analog IC under the current load change; Establishing a transient stability vector for characterizing a transient response characteristic of a load according to the damping coefficient and the steady-state value change rate and the offset amplitude in the steady-state offset component; Constructing a load transient stability evaluation matrix based on the transient stability vector, and calculating the overshoot suppression capability and response recovery time of the analog IC under different load conditions based on the distribution of the damping coefficient and the steady-state offset change under load changes in the evaluation matrix; Generates an analog IC performance test report based on overshoot suppression capability and response recovery time, including stability level, response curve, and response recovery time.

[0014] A second aspect of the present invention further provides a load transient response-based analog IC test system, comprising: a memory and a processor, wherein the memory includes a load transient response-based analog IC test method program, and when the load transient response-based analog IC test method program is executed by the processor, the following steps are implemented: Acquire transient response waveform data and corresponding response delay characteristics of the analog IC under various load jump modes, and construct a mapping matrix between load current step change rate and delay time based on the response delay characteristics; Obtaining current load current step change rate data of the analog IC during real-time testing, and predicting a response delay time of the analog IC within a future preset time period based on the mapping matrix and the current load current step change rate data; According to the predicted response delay time, when a response steady-state time window exists within a future preset time period, a fixed sampling timing is set based on the steady-state time window for testing to generate a first transient response test waveform; When there is no response steady-state time window within a future preset time period, the transient response waveform obtained in real time is corrected to generate a compensated transient response waveform, which is calibrated as a second transient response test waveform; Perform timing decomposition according to the first transient response test waveform or the second transient response test waveform, construct a load transient stability evaluation matrix of the analog IC, determine the analog IC performance according to the stability evaluation matrix, and output an analog IC performance test report.

[0015] The present invention discloses an analog IC testing method and system based on load transient response, which aims to improve the performance evaluation accuracy of analog IC under complex load conditions. The method first obtains the transient response waveform and response delay characteristics of the analog IC under multiple load jump modes, and constructs a mapping matrix between the load current step change rate and the response delay time. In real-time testing, the response delay time within a preset time period in the future is predicted based on the step change rate of the current load current. When there is a steady-state time window, a fixed sampling timing is set based on the window to generate a first test waveform; if there is no steady-state window, the transient waveform is corrected to generate a compensated second test waveform. The above test waveform is then time-series decomposed to construct a load transient stability evaluation matrix, thereby accurately evaluating the dynamic performance of the analog IC and outputting a detailed performance test report. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A flow chart of a load transient response-based analog IC testing method according to the present invention is shown; Figure 2 A flow chart showing the construction of a mapping matrix between load current step change rate and delay time according to the present invention is shown; Figure 3 A flow chart of generating a first transient response test waveform according to the present invention is shown; Figure 4 A block diagram of an analog IC test system based on load transient response according to the present invention is shown. DETAILED DESCRIPTION

[0017] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that, in the absence of conflict, the embodiments of the present application and the features therein can be combined with each other.

[0018] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the scope of protection of the present invention is not limited to the specific embodiments disclosed below.

[0019] Figure 1 The flowchart of the present invention shows a method for analog IC testing based on load transient response.

[0020] like Figure 1 As shown, the first aspect of the present invention provides an analog IC testing method based on load transient response, comprising: S102, obtaining transient response waveform data and corresponding response delay characteristics of the analog IC under various load jump modes, and constructing a mapping matrix between load current step change rate and delay time according to the response delay characteristics; S104, obtaining current load current step change rate data of the analog IC during real-time testing, and predicting a response delay time of the analog IC within a future preset time period based on the mapping matrix and the current load current step change rate data; S106, based on the predicted response delay time, when a response steady-state time window exists within a preset time period in the future, setting a fixed sampling timing based on the steady-state time window for testing to generate a first transient response test waveform; S108, when there is no response steady-state time window within the future preset time period, correcting the transient response waveform obtained in real time to generate a compensated transient response waveform, and calibrating it as a second transient response test waveform; S110, performing timing decomposition according to the first transient response test waveform or the second transient response test waveform, constructing a load transient stability evaluation matrix of the analog IC, determining the analog IC performance according to the stability evaluation matrix, and outputting an analog IC performance test report.

[0021] It should be noted that the load transient response test measures the ability of analog ICs to quickly recover to a stable output voltage when the load current rapidly changes. During the load transient response test, a periodic load injection is performed on the analog IC. At the start of the test, varying load current step change rates (di / dt) trigger varying activation levels of parasitic parameters within the chip's internal transmission paths (such as transistor switching delay and layout capacitance). This can cause varying load transient response delays in the analog IC at the start of the test. These delays disappear only after the parasitic parameters are activated. Acquiring load transient response waveforms during this response delay can result in test errors. The response delay here refers to the delay in the analog IC's response to the load transient. By constructing a mapping matrix between load current step change rates and response delay times, the IC's dynamic response characteristics under varying di / dt conditions are accurately modeled, enabling delay prediction. During the test, the current load change rate is acquired in real time and used in conjunction with the mapping matrix to predict future response delays, enabling pre-planning of sampling timing. When a steady-state response window is predicted, fixed sampling points are set to generate a first transient response waveform, ensuring complete capture of key dynamic characteristics. If a steady-state window is not present, the real-time waveform is modified using delay compensation and phase correction techniques to generate a second compensated test waveform. Subsequently, the test waveform is decomposed in the time domain to extract high-frequency oscillation and steady-state offset components, and a transient stability evaluation matrix is constructed to assess the overshoot suppression and recovery performance of the analog IC. This method effectively eliminates the phase offset error caused by traditional fixed sampling, improving the test accuracy of key indicators such as the damping coefficient and steady-state recovery.

[0022] Figure 2 The flowchart of the present invention for constructing a mapping matrix between load current step change rate and delay time is shown.

[0023] According to an embodiment of the present invention, the transient response waveform data and corresponding response delay characteristics of the analog IC under multiple load jump modes are obtained, and a mapping matrix between the load current step change rate and the delay time is constructed according to the response delay characteristics, specifically: S202, constructing a historical test record of the analog IC, and obtaining a load jump pattern of the analog IC according to the historical test record, wherein the load jump pattern includes a load current jump direction, a jump amplitude, a jump rate, and a jump frequency; S204, testing the analog IC under the multiple load jump modes, obtaining transient response waveform data of the analog IC under each load jump mode through the test, and identifying the corresponding transient start time and response stabilization time based on the transient response waveform data; S206, calculating the response delay time corresponding to each load jump mode according to the transient start time and the response stabilization time, and calculating the corresponding load current step change rate according to the load change amplitude and jump time in each load jump mode; S208 , pairing the load current step change rate calculated in each load jump mode with the corresponding response delay time to obtain a mapping matrix with the input variable being the load current step change rate and the output variable being the response delay time.

[0024] It should be noted that the load current jump direction indicates the upward or downward trend of the current change, the jump amplitude indicates the magnitude of the current change, the jump rate indicates the speed of the current change per unit time, and the jump frequency indicates the number of jump events that occur within a certain period of time. Transient response waveform data refers to the transient response process of the output voltage generated by the output end of the analog IC under the action of the load jump over time. In short, it is the response waveform of the output voltage of the analog IC to the sudden change of the load current, usually manifested as voltage drop, recovery, oscillation and other characteristics. The load current step change rate refers to the rate at which the load current changes during the step change process per unit time, usually expressed as the ratio of the current change to the change time (di / dt). According to an embodiment of the present invention, the step of obtaining the current load current step change rate data of the analog IC during real-time testing and predicting the response delay time of the analog IC within a future preset time period based on the mapping matrix and the current load current step change rate data are specifically as follows: Obtaining a load current change curve during multiple consecutive test cycles during the real-time test of the simulated IC, extracting a load current jump direction and jump rate according to the load current change curve, and calculating current load current step change rate data for each test cycle according to the load current jump direction and jump rate; A load change rate prediction model is constructed based on a long short-term memory network. The number of neurons in the input layer, hidden layer, and output layer is set, and the activation functions of the forget gate, input gate, and output gate are configured. The current load current step change rate data of each test cycle is converted into load change rate time series data according to the time series, and the load change rate time series data is divided into a training set and a prediction set. Importing the training set into the load change rate prediction model for model training, optimizing the network weights through a back propagation algorithm, and when the prediction error of the load change rate prediction model is lower than a preset threshold, importing the prediction set into the load change rate prediction model to predict the load current step change rate for multiple preset time periods within a future preset time period, thereby obtaining a predicted load current step change rate for each time period; The predicted load current step change rate is matched with the mapping matrix to predict the response delay time of the analog IC in each preset time period in the future preset time period.

[0025] It should be noted that predicting the response delay for each preset time period in the future is intended to accurately determine the point in time when the analog IC enters a stable response state under rapid load changes, thereby guiding the dynamic adjustment of the subsequent test sampling strategy. Since load current jumps can trigger voltage perturbations and dynamic adjustments during the analog IC's response, failure to predict the time required for stabilization in advance can lead to incorrect sampling timing, thus affecting waveform quality and test accuracy. By constructing a load change rate prediction model based on a long short-term memory network and combining it with the established mapping matrix between load current step change rate and response delay time, the load change trend and corresponding response delay behavior for each future time period can be predicted in real time during the test process. This ensures that the test system performs fixed sampling within the stable time window or, if no stable window exists, activates compensation mechanisms to correct the waveform. This achieves forward-looking identification and time-domain control of the dynamic response characteristics of the analog IC.

[0026] According to an embodiment of the present invention, the predicted load current step change rate is matched with the mapping matrix to predict the response delay time of the analog IC in each preset time period in the future preset time period, specifically: querying, according to the mapping matrix, whether there is a load change rate record that matches the predicted load current step change rate, and when a matching record is found, directly extracting the corresponding response delay time from the mapping matrix as a prediction result; When no matching record is found, screening two load current step change rates and their response delay times adjacent to the predicted load current step change rate in the mapping matrix, and calculating a response delay time interpolation coefficient corresponding to the predicted load current step change rate based on a linear interpolation algorithm; Calculating an intermediate predicted delay time according to the interpolation coefficient and adjacent response delay times, and simultaneously obtaining a maximum response delay time and a minimum response delay time in the mapping matrix; determining whether the intermediate predicted delay time is within a threshold interval formed by a maximum response delay time and a minimum response delay time, and outputting the intermediate predicted delay time as a final response delay time when the intermediate predicted delay time is within the threshold interval; When the intermediate predicted delay time exceeds the threshold interval, the response delay time corresponding to the load change rate closest to the predicted load current step change rate is selected as the corrected prediction result, and the threshold interval judgment is repeated until the response delay time that meets the interval requirements is obtained, completing the response delay time prediction of the analog IC in each preset time period in the future preset time period.

[0027] It should be noted that when predicting the response delay for each preset time period within a preset future time period, the system first searches the mapping matrix for the corresponding record based on the predicted load current step rate. When a fully matching record is found, the corresponding response delay is directly extracted as the predicted value for that period, achieving fast and accurate prediction. However, in actual testing, the predicted load current step rate may not have occurred in historical tests, resulting in an inability to match the corresponding record. In this case, the system may encounter a situation where the predicted data is missing. To address this, the system further selects two recording points adjacent to the current rate and uses a linear interpolation algorithm to calculate the interpolation coefficient. This interpolation generates an intermediate predicted delay time, ensuring continuous and valid predictions even when samples are missing. The system then compares the intermediate predicted delay time with the maximum and minimum delay times in the mapping matrix, forming a threshold range. If the predicted value falls within the threshold range, the prediction is considered reasonable and directly output. However, if the intermediate predicted value exceeds the threshold range, it indicates that the delay time corresponding to the current predicted rate exhibits abnormal fluctuations or model inference errors, making it unacceptable. At this time, the system will automatically select the response delay time corresponding to the known rate closest to the predicted rate as the corrected predicted value, and re-judge whether it meets the threshold interval requirements until a result that meets the range is obtained.

[0028] Figure 3 A flow chart of generating a first transient response test waveform according to the present invention is shown.

[0029] According to an embodiment of the present invention, based on the predicted response delay time, when there is a response steady-state time window within a preset time period in the future, a fixed sampling timing is set based on the steady-state time window for testing to generate a first transient response test waveform, specifically: S302: Obtaining the response stable time points of each time period within a preset future time period based on the predicted response delay time, and analyzing the duration of each time period in combination with the current system clock to obtain the stable response duration within each time period; S304, determining whether there is a response steady-state time window that meets the minimum test sampling time requirement based on the stable response duration, and when the stable response duration is greater than the minimum test sampling time, determining the center position of the stable window based on the time interval between the response delay time and the stabilization time; S306, planning a fixed sampling sequence based on the center position of the stable window and the sampling period, aligning the sampling sequence with the stable response time window in each time period, and generating a sampling time list; S308 , collecting the load transient response waveform during the real-time test of the analog IC according to the sampling time list to obtain a first transient response test waveform.

[0030] It should be noted that when a response steady-state time window exists within a preset future time period, it indicates that the analog IC's load transient response within that time period has completed the transition from disturbance to steady state and entered a stable state after the predicted delay time, with a continuous stable response region that meets the minimum sampling time requirement. In this case, by analyzing the predicted response delay time and the system clock, the position and duration of the steady-state window can be accurately determined. A fixed sampling sequence aligned with this steady-state window can then be set to sample the analog IC's output waveform, thereby generating the first transient response test waveform. This effectively avoids fluctuation interference during the response transition phase, ensuring that the test waveform data is highly concentrated within the stable range, improving the stability and consistency of signal acquisition.

[0031] According to an embodiment of the present invention, when there is no response steady-state time window within the preset time period in the future, the transient response waveform acquired in real time is corrected to generate a compensated transient response waveform, which is calibrated as the second transient response test waveform, specifically: When there is no response steady-state time window within the future preset time period, transient response waveform data of the simulated IC test is collected in real time during the test time of the future preset time period; Determining a delay compensation amount for each preset time period according to the predicted response delay time data for a plurality of preset time periods within a future preset time period; Extracting a time series response value based on the transient response waveform data collected in real time, and performing time axis displacement compensation on the time series response value based on the delay compensation amount to generate intermediate correction waveform data; Establishing a nonlinear response delay differential equation model based on the intermediate correction waveform data, wherein the model parameters are dynamically generated by fitting actual load step change characteristics and a history mapping matrix; An adaptive sliding time window is set along the load transition boundary. The time window width is adjusted in real time based on the solution of the differential equation model. When a high-frequency oscillation component is detected, a real-time reconstruction algorithm based on phase trajectory analysis is executed on the waveform data within the time window to generate an oscillation compensation waveform segment. In the transient recovery interval, an exponential decay envelope matching algorithm is used to correct the voltage offset. The oscillation compensation waveform fragment is fused with the corrected recovery interval waveform through time-series splicing to generate a compensated transient response waveform, which is calibrated as the second transient response test waveform.

[0032] It should be noted that if the response steady-state time window does not exist within the preset future time period, it indicates that the analog IC is in a continuous dynamic adjustment or high-frequency perturbation process throughout the entire prediction period and has not entered the stable response phase. Conventional fixed sampling strategies will not be able to obtain representative steady-state response data, affecting test effectiveness. In this case, by real-time acquisition of the analog IC's transient response waveform and calculating compensation based on the predicted response delay time for each cycle, the waveform data is corrected for time axis shift, effectively eliminating waveform misalignment caused by delay differences. Furthermore, by constructing a nonlinear response delay differential equation model with dynamically generated parameters based on historical characteristics and setting an adaptive sliding time window along the load transition boundary, high-frequency oscillation regions are detected and located in real time, and phase trajectory analysis is performed to reconstruct oscillation waveform segments. Simultaneously, an exponentially decaying envelope matching algorithm is introduced in the transient recovery period to fine-tune voltage offset correction. Finally, multiple waveform segments are fused and spliced to generate a compensated transient response waveform that accurately reproduces the true response characteristics. This approach achieves waveform characteristics close to the true steady-state under dynamic conditions without a steady-state window, ensuring the integrity and usability of the test waveform and significantly improving the test adaptability and evaluation accuracy of analog ICs under complex dynamic conditions. The nonlinear response delay differential equation model is based on the dynamic response characteristics of analog ICs during load transitions. A time delay term is introduced to characterize the lag effect of input load changes on the output response. Specifically, a nonlinear differential equation is first constructed containing the time derivative of the output voltage. The output response Vout(t) is used as the state variable, and the predicted dynamic response delay time τ(t) is introduced as the input time delay term, forming a differential structure with a time delay. Subsequently, key model parameters are extracted by combining real-time transient response waveform data with the various load step change rates and delay characteristics recorded in a historical mapping matrix. The nonlinear terms are modeled using methods such as least squares fitting or neural network regression, enabling the differential equation to accurately describe the response evolution of the analog IC under different load transition conditions. The real-time reconstruction algorithm includes high-frequency oscillation detection, phase trajectory analysis, waveform fitting reconstruction, and dynamic splicing. The algorithm sets a sliding time window at the load transition boundary, detects high-frequency oscillation signals through frequency-domain analysis, extracts their phase variation characteristics, and reconstructs the waveform using a nonlinear response model. Fitting functions such as damped sine or exponential envelopes ensures a continuous transition between the waveform and the real data in terms of phase and amplitude. Finally, a compensation waveform is generated through boundary smoothing and splicing, effectively reducing sampling offset.

[0033] According to an embodiment of the present invention, performing timing decomposition based on the first transient response test waveform or the second transient response test waveform, constructing a load transient stability evaluation matrix of the analog IC, determining the analog IC performance based on the stability evaluation matrix, and outputting an analog IC performance test report are specifically as follows: Performing time domain decomposition on the first transient response test waveform or the second transient response test waveform based on Fourier transform to extract a high-frequency oscillation component and a steady-state offset component; Extracting the amplitude attenuation sequence of each cycle based on the periodic envelope change curve of the high-frequency oscillation component, performing exponential fitting on the amplitude attenuation sequence to calculate the damping coefficient of the analog IC under the current load change; Establishing a transient stability vector for characterizing a transient response characteristic of a load according to the damping coefficient and the steady-state value change rate and the offset amplitude in the steady-state offset component; Constructing a load transient stability evaluation matrix based on the transient stability vector, and calculating the overshoot suppression capability and response recovery time of the analog IC under different load conditions based on the distribution of the damping coefficient and the steady-state offset change under load changes in the evaluation matrix; Generates an analog IC performance test report based on overshoot suppression capability and response recovery time, including stability level, response curve, and response recovery time.

[0034] It should be noted that by performing time-series decomposition on the first or second transient response test waveforms and extracting the high-frequency oscillation component and steady-state offset component, the dynamic response behavior of the analog IC under different load transitions can be effectively captured, enabling precise quantification of its stability and regulation performance. Using Fourier transform to extract the oscillation period envelope and calculate the amplitude decay sequence followed by exponential fitting accurately determines the damping coefficient, which characterizes the response convergence rate. Furthermore, the rate of change and amplitude of the steady-state offset component reflect the system's ultimate steady-state control capability under load disturbances. The transient stability vector, constructed by integrating the damping coefficient and the steady-state offset variation, is a stability evaluation dimension used to quantify the IC's adaptability to different load conditions. The resulting stability evaluation matrix systematically characterizes performance under multi-dimensional load scenarios. By calculating overshoot suppression and response recovery time, a performance test report with engineering reference value is generated. The high-frequency oscillation component represents the voltage fluctuation signal during the transient process, while the steady-state offset component represents the final stable output level.

[0035] According to an embodiment of the present invention, the further embodiment includes: Calculate the real-time temperature rise gradient of the chip core according to the package thermal resistance parameters of the analog IC and the real-time test current value, establish a temperature-time mapping relationship based on the real-time temperature rise gradient, and generate a dynamic temperature feature vector; Obtaining correlation data between load current step change rates and response delay times at different temperature points in historical tests, performing three-dimensional expansion based on the mapping matrix of the dynamic temperature eigenvector, and constructing a load-temperature-delay mapping tensor including a temperature compensation dimension; During the real-time test, the temperature sensor is used to continuously collect the surface temperature of the analog IC package, the surface temperature of the package is input into the dynamic temperature feature vector to perform core temperature decoupling calculation, and a time-varying chip core temperature sequence is output; According to the current load current step change rate data and the time-varying chip core temperature sequence, the load-temperature-delay mapping tensor is queried to extract the basic response delay time. At the same time, the core temperature change rate is calculated by the temperature derivative to dynamically compensate for the basic response delay time and generate the corrected response delay time after temperature drift compensation.

[0036] It should be noted that during continuous high-load testing of analog ICs, the chip core temperature drifts significantly as the current increases, causing changes in transistor switching characteristics and distortion of response delay patterns. The mapping matrix, lacking a temperature dimension, produces systematic prediction deviations during continuous testing, leading to problems such as misjudgment of the steady-state window and distortion of the waveform compensation benchmark. A core temperature rise model is constructed based on package thermal resistance and real-time current, accurately decoupling the gradient difference between surface temperature and chip hotspots to generate a dynamic temperature feature vector. Secondly, historical multi-temperature point test data is integrated to perform a three-dimensional tensor expansion of the original mapping matrix, constructing a multi-dimensional compensation system for load, temperature, and delay. Finally, the basic response delay is dynamically corrected using the temperature change rate derivative, forming a full-link closed-loop compensation for temperature drift. By deeply embedding the temperature variable into the test process, the load transient response prediction maintains high accuracy even under high-temperature and high-current conditions.

[0037] Figure 4 A block diagram of an analog IC test system based on load transient response according to the present invention is shown.

[0038] A second aspect of the present invention further provides a load transient response-based simulated IC test system 4, comprising: a memory 41 and a processor 42. The memory includes a load transient response-based simulated IC test method program. When the load transient response-based simulated IC test method program is executed by the processor, the following steps are implemented: Acquire transient response waveform data and corresponding response delay characteristics of the analog IC under various load jump modes, and construct a mapping matrix between load current step change rate and delay time based on the response delay characteristics; Obtaining current load current step change rate data of the analog IC during real-time testing, and predicting a response delay time of the analog IC within a future preset time period based on the mapping matrix and the current load current step change rate data; According to the predicted response delay time, when a response steady-state time window exists within a future preset time period, a fixed sampling timing is set based on the steady-state time window for testing to generate a first transient response test waveform; When there is no response steady-state time window within a future preset time period, the transient response waveform obtained in real time is corrected to generate a compensated transient response waveform, which is calibrated as a second transient response test waveform; Perform timing decomposition according to the first transient response test waveform or the second transient response test waveform, construct a load transient stability evaluation matrix of the analog IC, determine the analog IC performance according to the stability evaluation matrix, and output an analog IC performance test report.

[0039] The present invention discloses an analog IC testing method and system based on load transient response, which aims to improve the performance evaluation accuracy of analog IC under complex load conditions. The method first obtains the transient response waveform and response delay characteristics of the analog IC under multiple load jump modes, and constructs a mapping matrix between the load current step change rate and the response delay time. In real-time testing, the response delay time within a preset time period in the future is predicted based on the step change rate of the current load current. When there is a steady-state time window, a fixed sampling timing is set based on the window to generate a first test waveform; if there is no steady-state window, the transient waveform is corrected to generate a compensated second test waveform. The above test waveform is then time-series decomposed to construct a load transient stability evaluation matrix, thereby accurately evaluating the dynamic performance of the analog IC and outputting a detailed performance test report.

[0040] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0041] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed across multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0042] In addition, all functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0043] Those skilled in the art will appreciate that all or part of the steps of the above-mentioned method embodiments may be implemented by hardware associated with program instructions, and the aforementioned program may be stored in a computer-readable storage medium. When the program is executed, the program executes the steps of the above-mentioned method embodiments. The aforementioned storage medium includes various media that can store program codes, such as mobile storage devices, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical disks.

[0044] Alternatively, if the integrated units described above are implemented as software modules and sold or used as standalone products, they can also be stored on a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present invention, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product, stored on a storage medium, includes instructions for enabling a computer device (such as a personal computer, server, or network device) to execute all or part of the methods described in various embodiments of the present invention. The aforementioned storage media include various media capable of storing program code, such as removable storage devices, ROM, RAM, magnetic disks, or optical disks.

[0045] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A method for analog IC testing based on load transient response, characterized in that: The following steps are involved: Acquire transient response waveform data and corresponding response delay characteristics of the analog IC under various load jump modes, and construct a mapping matrix between load current step change rate and delay time based on the response delay characteristics; Obtaining current load current step change rate data of the analog IC during real-time testing, and predicting a response delay time of the analog IC within a future preset time period based on the mapping matrix and the current load current step change rate data; According to the predicted response delay time, when a response steady-state time window exists within a future preset time period, a fixed sampling timing is set based on the steady-state time window for testing to generate a first transient response test waveform; When there is no response steady-state time window within a future preset time period, the transient response waveform obtained in real time is corrected to generate a compensated transient response waveform, which is calibrated as a second transient response test waveform; Perform timing decomposition according to the first transient response test waveform or the second transient response test waveform, construct a load transient stability evaluation matrix of the analog IC, determine the analog IC performance according to the stability evaluation matrix, and output an analog IC performance test report.

2. The analog IC testing method based on load transient response according to claim 1, characterized in that: The transient response waveform data and corresponding response delay characteristics of the analog IC under various load jump modes are obtained, and a mapping matrix between the load current step change rate and the delay time is constructed according to the response delay characteristics, specifically: Constructing a historical test record of the analog IC, and obtaining a load jump mode of the analog IC according to the historical test record, wherein the load jump mode includes a load current jump direction, a jump amplitude, a jump rate, and a jump frequency; Testing the analog IC under the multiple load jump modes, obtaining transient response waveform data of the analog IC under each load jump mode through the test, and identifying the corresponding transient start time and response stabilization time according to the transient response waveform data; Calculating the response delay time corresponding to each load jump mode according to the transient start time and the response stabilization time, and calculating the corresponding load current step change rate according to the load change amplitude and jump time under each load jump mode; The load current step change rate calculated in each load jump mode is paired with the corresponding response delay time to obtain a mapping matrix with the input variable being the load current step change rate and the output variable being the response delay time.

3. The analog IC testing method based on load transient response according to claim 1, characterized in that: The step-change rate data of the current load current of the analog IC during real-time testing is obtained, and the response delay time of the analog IC within a future preset time period is predicted based on the mapping matrix and the current load current step-change rate data, specifically: Obtaining a load current change curve during multiple consecutive test cycles during the real-time test of the simulated IC, extracting a load current jump direction and jump rate according to the load current change curve, and calculating current load current step change rate data for each test cycle according to the load current jump direction and jump rate; A load change rate prediction model is constructed based on a long short-term memory network. The number of neurons in the input layer, hidden layer, and output layer is set, and the activation functions of the forget gate, input gate, and output gate are configured. The current load current step change rate data of each test cycle is converted into load change rate time series data according to the time series, and the load change rate time series data is divided into a training set and a prediction set. Importing the training set into the load change rate prediction model for model training, optimizing the network weights through a back propagation algorithm, and when the prediction error of the load change rate prediction model is lower than a preset threshold, importing the prediction set into the load change rate prediction model to predict the load current step change rate for multiple preset time periods within a future preset time period, thereby obtaining a predicted load current step change rate for each time period; The predicted load current step change rate is matched with the mapping matrix to predict the response delay time of the analog IC in each preset time period in the future preset time period.

4. The analog IC testing method based on load transient response according to claim 3, characterized in that: The predicted load current step change rate is matched with the mapping matrix to predict the response delay time of the analog IC in each preset time period in the future preset time period, specifically: querying, according to the mapping matrix, whether there is a load change rate record that matches the predicted load current step change rate, and when a matching record is found, directly extracting the corresponding response delay time from the mapping matrix as a prediction result; When no matching record is found, screening two load current step change rates and their response delay times adjacent to the predicted load current step change rate in the mapping matrix, and calculating a response delay time interpolation coefficient corresponding to the predicted load current step change rate based on a linear interpolation algorithm; Calculating an intermediate predicted delay time according to the interpolation coefficient and adjacent response delay times, and simultaneously obtaining a maximum response delay time and a minimum response delay time in the mapping matrix; determining whether the intermediate predicted delay time is within a threshold interval formed by a maximum response delay time and a minimum response delay time, and outputting the intermediate predicted delay time as a final response delay time when the intermediate predicted delay time is within the threshold interval; When the intermediate predicted delay time exceeds the threshold interval, the response delay time corresponding to the load change rate closest to the predicted load current step change rate is selected as the corrected prediction result, and the threshold interval judgment is repeated until the response delay time that meets the interval requirements is obtained, completing the response delay time prediction of the analog IC in each preset time period in the future preset time period.

5. The analog IC testing method based on load transient response according to claim 1, characterized in that: According to the predicted response delay time, when there is a response steady-state time window within a preset time period in the future, a fixed sampling timing is set based on the steady-state time window to perform a test and generate a first transient response test waveform, specifically: Based on the predicted response delay time, the response stable time point of each time period in the future preset time period is obtained, and the time length of each time period is analyzed in combination with the current system clock to obtain the stable response duration in each time period; Determine whether there is a response steady-state time window that meets the minimum test sampling time requirement based on the stable response duration; and when the stable response duration is greater than the minimum test sampling time, determine the center position of the stable window based on the time interval between the response delay time and the stabilization time; According to the center position of the stable window combined with the sampling period, a fixed sampling timing is planned, the sampling timing is aligned with the stable response time window in each time period, and a sampling time list is generated; The load transient response waveform during the real-time test of the analog IC is collected according to the sampling time list to obtain a first transient response test waveform.

6. The analog IC testing method based on load transient response according to claim 1, characterized in that: When there is no response steady-state time window within the future preset time period, the transient response waveform acquired in real time is corrected to generate a compensated transient response waveform, which is calibrated as the second transient response test waveform, specifically: When there is no response steady-state time window within the future preset time period, transient response waveform data of the simulated IC test is collected in real time during the test time of the future preset time period; Determining a delay compensation amount for each preset time period according to the predicted response delay time data for a plurality of preset time periods within a future preset time period; Extracting a time series response value based on the transient response waveform data collected in real time, and performing time axis displacement compensation on the time series response value based on the delay compensation amount to generate intermediate correction waveform data; Establishing a nonlinear response delay differential equation model based on the intermediate correction waveform data, wherein the model parameters are dynamically generated by fitting actual load step change characteristics and a history mapping matrix; An adaptive sliding time window is set along the load transition boundary. The time window width is adjusted in real time based on the solution of the differential equation model. When a high-frequency oscillation component is detected, a real-time reconstruction algorithm based on phase trajectory analysis is executed on the waveform data within the time window to generate an oscillation compensation waveform segment. In the transient recovery interval, an exponential decay envelope matching algorithm is used to correct the voltage offset. The oscillation compensation waveform fragment is fused with the corrected recovery interval waveform through time-series splicing to generate a compensated transient response waveform, which is calibrated as the second transient response test waveform.

7. The analog IC testing method based on load transient response according to claim 1, characterized in that: The performing of timing decomposition according to the first transient response test waveform or the second transient response test waveform, constructing a load transient stability evaluation matrix of the analog IC, determining the analog IC performance according to the stability evaluation matrix, and outputting an analog IC performance test report, is specifically as follows: Performing time domain decomposition on the first transient response test waveform or the second transient response test waveform based on Fourier transform to extract a high-frequency oscillation component and a steady-state offset component; Extracting the amplitude attenuation sequence of each cycle based on the periodic envelope change curve of the high-frequency oscillation component, performing exponential fitting on the amplitude attenuation sequence to calculate the damping coefficient of the analog IC under the current load change; Establishing a transient stability vector for characterizing a transient response characteristic of a load according to the damping coefficient and the steady-state value change rate and the offset amplitude in the steady-state offset component; Constructing a load transient stability evaluation matrix based on the transient stability vector, and calculating the overshoot suppression capability and response recovery time of the analog IC under different load conditions based on the distribution of the damping coefficient and the steady-state offset change under load changes in the evaluation matrix; Generates an analog IC performance test report based on overshoot suppression capability and response recovery time, including stability level, response curve, and response recovery time.

8. An analog IC test system based on load transient response, characterized in that: The load transient response-based simulated IC test system includes a memory and a processor. The memory includes a load transient response-based simulated IC test method program. When the load transient response-based simulated IC test method program is executed by the processor, the following steps are implemented: Acquire transient response waveform data and corresponding response delay characteristics of the analog IC under various load jump modes, and construct a mapping matrix between load current step change rate and delay time based on the response delay characteristics; Obtaining current load current step change rate data of the analog IC during real-time testing, and predicting a response delay time of the analog IC within a future preset time period based on the mapping matrix and the current load current step change rate data; According to the predicted response delay time, when a response steady-state time window exists within a future preset time period, a fixed sampling timing is set based on the steady-state time window for testing to generate a first transient response test waveform; When there is no response steady-state time window within a future preset time period, the transient response waveform obtained in real time is corrected to generate a compensated transient response waveform, which is calibrated as a second transient response test waveform; Perform timing decomposition according to the first transient response test waveform or the second transient response test waveform, construct a load transient stability evaluation matrix of the analog IC, determine the analog IC performance according to the stability evaluation matrix, and output an analog IC performance test report.

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