Circuit and method for reducing offset voltage of amplifier

Abstract

The invention provides a circuit and a method for reducing offset voltage of an amplifier. The circuit comprises a chopper, a ripple detection circuit, a D trigger and a state machine, chopped wave processing is carried out at the input end and the output end of the amplifier, and if the amplifier is offset, ripples can be generated; a detected offset comparison result is input to a state machine through a D trigger by a ripple detection circuit; the state machine outputs a digital signal DTlt through some state conversion; n: 0gt; and Dlt; n: 0gt; according to the invention, the size of the small-size tube of the input geminate transistor of the operational amplifier is adjusted through the control signal of the switch tube, so that the size of the input geminate transistor is adjusted to be relatively balanced, and the offset voltage of the amplifier is reduced. Clock periods needing n-bit trimming form a large period, the offset voltage of the amplifier is rapidly adjusted back in a chip, the area of the chip is reduced, the chopping frequency is reduced, and the precision is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of amplifiers, and in particular to a circuit and a method for reducing amplifier offset voltage. Background Art

[0002] In electronic circuits, amplifiers are an indispensable and important component used to enhance the amplitude of signals for subsequent processing or transmission. However, in practical applications, amplifiers are often affected by offset voltage, which refers to the voltage offset that still exists at the output end when the input of the amplifier is zero. This offset will cause deviations in the output signal, affecting the overall performance and accuracy of the circuit. The offset voltage mainly comes from factors such as device mismatch, temperature changes, and external interference. Therefore, removing or reducing the offset voltage of the amplifier is one of the key technologies to improve circuit performance.

[0003] At present, the existing technology mainly adopts zero-drift operational amplifier and auto-zero technology to solve the above technical problems, wherein the zero-drift operational amplifier is an operational amplifier with a special calibration circuit integrated inside, which is used to reduce the offset voltage and temperature drift. It usually adopts chopping technology or auto-zero technology to realize the calibration of the offset voltage. Chopping technology periodically flips the polarity of the input signal and the offset voltage by adding a switch between the input stage and the amplifier stage, thereby eliminating the average value of the offset voltage. Chopping technology is a means of using the principles of modulation and demodulation to move low-frequency noise and offset to the high-frequency part, and then use a low-pass filter to filter it out. However, chopping technology will produce a large ripple that requires a large notch filter to remove it, and the chopping frequency needs to be very high.

[0004] Auto-zero technology is a time domain modulation method that mainly corrects the offset by sampling. It is often used in combination with switched capacitor circuits. The offset voltage is stored on the capacitor through sampling during the sampling phase, and the offset is eliminated during the signal operation phase. The offset voltage can exist at the input or output of the op amp. However, the in-band voltage noise of auto-zero technology is large. Since the noise is reflected back to the baseband, auto-zero technology may show large in-band voltage noise in some cases. Summary of the invention

[0005] In view of the deficiencies of the prior art, the present invention provides a circuit and method for reducing the offset voltage of an amplifier. The present invention can adjust and restore the offset voltage of the amplifier at any time.

[0006] The technical scheme of the present invention is: a circuit for reducing the offset voltage of an amplifier, comprising a chopper CH1, a chopper CH2, a ripple detection circuit, a D flip-flop DFF, and a state machine; the chopper CH1 and the chopper CH2 are respectively arranged at the input end and the output end of the amplifier A0; the output end of the chopper CH2 is also connected to the ripple detection circuit; the output end of the ripple detection circuit is connected to the D flip-flop DFF through a hysteresis inverter INV; the D flip-flop DFF is connected to the state machine; the output end of the state machine is connected to the amplifier A0 through a trimming circuit; and the output end of the state machine is also connected to the chopper CH1 and the chopper CH2;

[0007] By performing chopping processing at the input and output ends of the amplifier A0, ripples will be generated if the amplifier A0 is out of adjustment; the detected offset comparison result is input to the state machine through the D flip-flop DFF through the ripple detection circuit; the state machine outputs a digital signal DT after some state conversion <n:0>and D <n:0>To control the trim size of the amplifier A0 input to the tube, thereby reducing the amplifier offset voltage, and at the same time control the input of chopper CH1 and chopper CH2 through the state machine.

[0008] Preferably, the ripple detection circuit comprises three-stage auto-zero comparators A1-A3 and a hysteresis inverter INV, and the output end of the auto-zero comparator A3 is connected to the hysteresis inverter INV.

[0009] Preferably, the state machine includes several D flip-flops and an inverter INV1, and the several D flip-flops are arranged in three rows, namely the first row, the second row, and the third row from top to bottom, wherein the first row is provided with n+1 D flip-flops, the second row and the third row are both provided with n+2 D flip-flops, and the inverter INV1 is provided on the first row.

[0010] Preferably, the first row has D flip-flops DFF arranged in descending order from left to right. 3n+4 to DFF 2n+4 ; The leftmost D flip-flop DFF 3n+4 The set 1 terminal S is connected to the DFF of the second row n The output terminal Q of the D flip-flop DFF 3n+3 The set 1 terminal S is connected to the second row DFF n-1 The output terminal Q of the rightmost D flip-flop DFF 2n+4 The input terminal D is grounded, and the D flip-flop DFF 3n+4 To D flip-flop DFF 2n+5 The input terminals D of the n D flip-flops are all connected to the COMP signal through the inverted signal of the inverter INV1; the leftmost D flip-flop DFF 3n+4 The output Q signal is recorded as D <n-1>, D flip-flop DFF 3n+3 The output Q signal is recorded as D <n-2>, and is also connected to the previous D flip-flop DFF 3n+4 The clock input terminal CLK of the rightmost D flip-flop DFF 2n+4 The output Q is only used as the front DFF 2n+5 CLK signal, not recorded as other outputs; all D flip-flops DFF 3n+4 to DFF 2n+4 The inverting output terminal Q of all D flip-flops DFF is not left floating. 3n+4 to DFF 2n+4 The reset terminal R is connected to the RESET signal.

[0011] Preferably, the second row is arranged in descending order from left to right, with D flip-flops DFF n+1 to DFF 0 ; The leftmost D flip-flop DFF n+1 The set 1 terminal S is connected to the SET1 signal, and the D flip-flop DFF n to DFF 0 The n+1 D flip-flops have their set terminals S connected to the SET signal; the leftmost D flip-flop DFF n+1 The D input terminal D is grounded, and the D flip-flop DFF n The input terminal D is connected to the previous D flip-flop DFF n+1 The output terminal Q of the D flip-flop DFF n-1 The input terminal D is connected to the previous D flip-flop DFF n The output terminal Q, and so on; the D flip-flop DFF on the far right 0 The output terminal Q is connected to the last D flip-flop DFF in the first and third rows. 2n+4 and DFF n+2 The set-to-1 terminal S of all D flip-flops in the second row are connected to the clock signal CLK at the clock input terminal CLK; all D flip-flops DFF n+1 to DFF 0 The inverting output terminal Q of all D flip-flops DFF is not left floating. n+1 to DFF 0 The reset terminal R is connected to the RESET signal.

[0012] Preferably, the D flip-flops DFF are arranged in descending order from left to right in the third row. 2n+3 to DFF n+2 ; The leftmost D flip-flop DFF 2n+3 The set 1 terminal S is connected to the D flip-flop DFF of the second row n+1 The output terminal Q of the D flip-flop DFF 2n+2 The set 1 terminal S is connected to the second row DFF n The output terminal Q of the D flip-flop DFF 2n+1 The set 1 terminal S is connected to the second row DFF n-1 The output terminal Q of the rightmost DFF n+2 The input terminal D should be grounded, DFF 2n+3 to DFF n+3 The input terminals D of the n+1 D flip-flops are all connected to the COMP signal; the leftmost D flip-flop DFF 2n+3 The output Q signal is recorded as DT <n>, D flip-flop DFF 2n+2 The output Q signal is recorded as DT <n-1>, and is also connected to the previous D flip-flop DFF 2n+3 The clock input terminal CLK, D flip-flop DFF 2n+1 The output Q signal is recorded as DT <n-2>, and is also connected to the previous D flip-flop DFF 2n+2 The clock input terminal CLK, and the rest are similar, and the rightmost DFF n+2 The output Q is only used as the front DFF n+3 CLK signal, not recorded as other outputs; all D flip-flops DFF 2n+3 to DFF n+2 The inverting output terminal Q of all D flip-flops DFF is not left floating. 2n+3 to DFF n+2 The reset terminal R is connected to the RESET signal.

[0013] As a preferred embodiment, the trimming circuit includes switch tubes M1, M2, and a first trimming circuit and a second trimming circuit; the first trimming circuit and the second trimming circuit are respectively composed of DT <n>and D <n>Control; the source of the switch tubes M1 and M2 is connected to the source VC of the input pair of tubes on both sides of the amplifier A0; the gate of the switch tubes M1 and M2 is respectively connected by DT<n-1:0> and D<n-1:0> Control; the drains of the switch tubes M1 and M2 are connected to the first trimming circuit and the second trimming circuit respectively, and the input pairs of tubes MA and MB on both sides of the amplifier A0 are trimmed respectively.

[0014] Preferably, the first trimming circuit includes a plurality of PMOS switch tubes Msp1-Msp2 n -1 and several PMOS transistors Mp1-Mp2 n -1; the drain of the switch tube M1 and the PMOS switch tubes Msp1-Msp2 n -1's source is connected; the gate of the PMOS switch tube Msp1 is connected to DT <0> , the gates of the PMOS switches Msp2 and Msp3 are connected to DT <1> ;Msp2 n-1 -Msp2 n -1 of 2 n-1 The gate of each PMOS switch is connected to DT <n-1>; The PMOS switch tube Msp1-Msp2 n -1 and the drain of PMOS transistors Mp1-Mp2 n -1 is connected to the source; the PMOS transistors Mp1-Mp2 n The drains of the PMOS transistors Mp1-Mp2 are connected together and connected to the drain VA of the input pair tube MA on one side of the amplifier A0; n The gate of -1 is connected to the gate VI1 of the input pair tube MA on one side of the amplifier A0.

[0015] Preferably, the second trimming circuit includes a plurality of PMOS switch tubes Msn1-Msn2 n -1 and several PMOS transistors Mn1-Mn2 n -1; the drain of the switch tube M2 and the PMOS switch tubes Msn1-Msn2 n -1's source is connected, and Msn1's gate is connected to D <0> , the gates of Msn2 and Msn3 are connected to D <1> ; Msn2 n-1 -Msn2 n -1 of 2 n-1 The gate of the PMOS switch is connected to D <n-1>;

[0016] The PMOS switch tubes Msn1-Msn2 n -1 and the drain of PMOS transistors Mn1-Mn2 n -1 is connected to the source; the PMOS transistors Mn1-Mn2 n The drains of the PMOS transistors Mn1-Mn2 are connected together and connected to the drain VB of the input pair tube MB on the other side of the amplifier A0; n The gate of -1 is connected to the gate V12 of the input pair tube MB on the other side of the amplifier A0.

[0017] Preferably, the present invention also provides a method for reducing the offset voltage of an amplifier, comprising the following steps:

[0018] S1), performing chopping processing of a certain frequency at the input and output ends of the amplifier A0;

[0019] S2), when the amplifier A0 is out of adjustment; the ripple signal COMP is detected by the ripple detection circuit and output through the hysteresis inverter;

[0020] S3) Input the offset comparison result to the state machine through the D flip-flop DFF, and the state machine outputs the digital signal DT after some state transitions. <n:0>and D <n:0>The control trimming circuit trims the trimming size of the input pair tube of the amplifier A0, thereby achieving the result of reducing the offset voltage of the amplifier A0.

[0021] Preferably, in step S2), the ripple detection circuit includes three-stage auto-zero comparators A1-A3 and a hysteresis inverter INV.

[0022] As a preferred embodiment, in step S3), the source electrodes of the switch tubes M1 and M2 are connected to the source electrodes VC of the input pairs of tubes on both sides of the amplifier A0; the gate electrodes of the switch tubes M1 and M2 are connected to the source electrodes VC of the input pairs of tubes on both sides of the amplifier A0; <n>and D <n>Control; the drains of the switch tubes M1 and M2 are connected to the first trimming circuit and the second trimming circuit respectively, and the input pairs of tubes MA and MB on both sides of the amplifier A0 are trimmed respectively.

[0023] As a preferred embodiment, in step S3), the N-bit register is first set to the middle scale, the most significant bit MSB is set to 1, and the trimming circuit is turned off; the original size mismatch direction of the input pair tubes MA and MB on both sides of the comparison amplifier A0 is compared by the comparison value obtained by chopping switching; by judging the size of the gates VI1 and VI2 on both sides of the input pair tubes MA and MB, if VI1 is greater than VI2, the comparator outputs a logic high level 1, and the MSB of the N-bit register remains 1; if VI1 is less than VI2, the comparator outputs a logic low level 0, and the MSB of the N-bit register is cleared to 0; and then the input pair tubes that need to be increased in size are determined, and the control signal DT is determined by the corresponding state <n>and D <n>;

[0024] Then, the SAR control logic moves to the next bit and sets it high for the next comparison; until DT is obtained, <0> and D <0> ;

[0025] After the conversion is completed, the conversion result is stored in the register, and a signal is input through the state machine to turn off the chopping signal CH, and the chopping stops; while DT<n:0> and D<n:0> The result after comparison is maintained, and the offset voltage of the amplifier can be corrected within a certain range, thereby achieving the purpose of reducing the offset voltage of the amplifier.

[0026] As a preferred embodiment, in step S3), the control signals of the first trimming switch and the second trimming switch are DT<n-1:0> , D<n-1:0> ; and follow 1, 2, 4, ..., 2 n-1 ,2 n The quantitative relationship is controlled.

[0027] Preferably, in step S3), the SAR control logic is reset to zero through the RESET signal; then the register is set to the middle scale through the SET1 signal, during which the SW switch control of the dynamic zero comparator A1-A3 is closed through the SW signal for reset processing, and then the chopping signal CH starts to chop the input and output ends of the switching amplifier A0, and the obtained ripple comparison signal is passed through the ripple detection circuit to obtain a comparison signal, and the comparison signal is transmitted to the COMP end of the SAR control logic through a CLK_COM signal that is delayed by some time than CH through a D trigger, and then after some delay, COM is transmitted to the Q output end of the corresponding D trigger through the CLK clock signal on the rising edge.

[0028] The beneficial effects of the present invention are:

[0029] 1. The present invention realizes chopping processing and ripple detection by utilizing chopping and ripple detection of three auto-zero gain stage comparators, and converts the offset comparison result into an output digital control signal DT through a state machine. <n:0>and D <n:0>Control the trimming circuit to trim the size of the input pair tubes on both sides of the amplifier A0, thereby achieving the result of reducing the amplifier offset voltage;

[0030] 2. The present invention adjusts the size of the tube on the side of the relatively small size of the operational amplifier input pair tube through the switch tube control signal to adjust the input pair tube size to be relatively balanced, thereby achieving the effect of reducing the offset voltage of the operational amplifier;

[0031] 3. The present invention combines the required n-bit trimmed clock cycles into a large cycle to quickly adjust the amplifier offset voltage inside the chip, thereby reducing the chip area, lowering the chopping frequency, and improving the accuracy. Moreover, the amplifier offset voltage can be adjusted and restored at any time through system control. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic diagram of the framework of the circuit of the present invention;

[0033] Figure 2 A circuit framework diagram showing the connection between the trimming circuit and the amplifier of the present invention;

[0034] Figure 3 is a circuit diagram of a state machine of the present invention;

[0035] Figure 4 A circuit diagram of the trimming circuit of the present invention;

[0036] Figure 5 Schematic diagram of the main timing waveforms of the adjustment process of the present invention. DETAILED DESCRIPTION

[0037] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings:

[0038] Example 1

[0039] like Figure 1 and 2 As shown, this embodiment provides a circuit for reducing the offset voltage of an amplifier, including a chopper CH1, a chopper CH2, a ripple detection circuit, a D flip-flop DFF, and a state machine; the chopper CH1 and the chopper CH2 are respectively arranged at the input end and the output end of the amplifier A0; the output end of the chopper CH2 is also connected to the ripple detection circuit; the output end of the ripple detection circuit is connected to the D flip-flop DFF through a hysteresis inverter INV; the D flip-flop DFF is connected to the state machine; the output end of the state machine is connected to the amplifier A0 through the trimming circuit; and the output end of the state machine is also connected to the chopper CH1 and the chopper CH2.

[0040] In this embodiment, choppers CH1 and CH2 are used to perform chopping processing at the input and output of amplifier A0. If amplifier A0 is out of adjustment, ripples will be generated; then the detected offset comparison result is input to the state machine through the D flip-flop DFF through the ripple detection circuit; the state machine outputs a digital control signal DT after some state conversion. <n:0>and D <n:0>The control trimming circuit is used to trim the size of the input pair tubes on both sides of the amplifier A0, thereby achieving the result of reducing the amplifier offset voltage. At the same time, the inputs of the choppers CH1 and CH2 are controlled by the state machine.

[0041] As preferred in this embodiment, Figure 1 As shown, the ripple detection circuit includes three-stage auto-zero comparators A1-A3 and a hysteresis inverter INV, and capacitors C1, C2 and C3 are respectively arranged between the chopper CH2 and the auto-zero comparator A1, between the auto-zero comparator A1 and the auto-zero comparator A2, and between the auto-zero comparator A2 and the auto-zero comparator A3, and the output end of the auto-zero comparator A3 is connected to the hysteresis inverter INV; the capacitors C1, C2 and C3 are used to store the offset voltage of the operational amplifier when the three-stage auto-zero comparators A1-A3 are working.

[0042] And when the control voltage CH of the chopper CH2 is at a low level, the switch SW of the three-stage auto-zero comparator A1-A3 is closed, the three-stage auto-zero comparator A1-A3 is in a sampling state, and the operational amplifier is connected into a buffer structure. At this time, the input is equal to the output, and the offset voltage is added on both sides of the input capacitors C1, C2 and C3;

[0043] A short time before the control voltage CH of the chopper CH2 is at a high level, the switch SW of the three-level auto-zero comparator A1-A3 is turned on, the three-level auto-zero comparator A1-A3 is in an amplification state, and the ripple in the output voltage VOUT is amplified to a level that the three-level auto-zero comparator A1-A3 can detect. When the signal is amplified, the voltage on the capacitor is amplified together with the input signal.

[0044] As preferred in this embodiment, Figure 3 As shown, the state machine includes a plurality of D flip-flops and an inverter INV1, and the plurality of D flip-flops are arranged in three rows, namely the first row, the second row, and the third row from top to bottom, wherein the first row is provided with n+1 D flip-flops, the second row and the third row are both provided with n+2 D flip-flops, and the inverter INV1 is provided on the first row.

[0045] In this embodiment, the first row is arranged in descending order from left to right with D flip-flops DFF 3n+4 to DFF 2n+4 ; The leftmost D flip-flop DFF 3n+4 The set 1 terminal S is connected to the DFF of the second row n The output terminal Q of the D flip-flop DFF 3n+3 The set 1 terminal S is connected to the second row DFF n-1 The output terminal Q of the rightmost D flip-flop DFF 2n+4 The input terminal D of the D flip-flop DFF is grounded. 3n+4 To D flip-flop DFF 2n+5 The input terminals D of the n D flip-flops are all connected to the COMP signal through the inverted signal of the inverter INV1; the leftmost D flip-flop DFF 3n+4 The output Q signal is recorded as D <n-1>, D flip-flop DFF 3n+3 The output Q signal is recorded as D <n-2>, and is also connected to the previous D flip-flop DFF 3n+4 The clock input terminal CLK of the rightmost D flip-flop DFF 2n+4 The output Q is only used as the front DFF 2n+5 CLK signal, not recorded as other outputs; all D flip-flops DFF 3n+4 to DFF 2n+4 The inverting output terminal Q of all D flip-flops DFF is not left floating. 3n+4 to DFF 2n+4 The reset terminal R is connected to the RESET signal.

[0046] In this embodiment, the second row is arranged in descending order from left to right. n+1 to DFF 0 ; The leftmost D flip-flop DFF n+1 The set 1 terminal S is connected to the SET1 signal, and the D flip-flop DFF n to DFF 0 The n+1 D flip-flops have their set terminals S connected to the SET signal; the leftmost D flip-flop DFF n+1 The D input terminal D is grounded, and the D flip-flop DFF n The input terminal D is connected to the previous D flip-flop DFF n+1 The output terminal Q of the D flip-flop DFF n-1 The input terminal D is connected to the previous D flip-flop DFF n The output terminal Q, and so on; the D flip-flop DFF on the far right 0 The output terminal Q is connected to the last D flip-flop DFF in the first and third rows. 2n+4 and DFF n+2 The set-to-1 terminal S of all D flip-flops in the second row is connected to the clock signal CLK at the clock input terminal CLK; all D flip-flops DFF n+1 to DFF 0 The inverting output terminal Q of all D flip-flops DFF is not left floating. n+1 to DFF 0 The reset terminal R is connected to the RESET signal.

[0047] In this embodiment, the third row of D flip-flops DFF are arranged in descending order from left to right. 2n+3 to DFF n+2 ; The leftmost D flip-flop DFF 2n+3 The set 1 terminal S is connected to the D flip-flop DFF of the second row n+1 The output terminal Q of the D flip-flop DFF 2n+2 The set 1 terminal S is connected to the second row DFF n The output terminal Q of the D flip-flop DFF 2n+1 The set 1 terminal S is connected to the second row DFF n-1 The output terminal Q of the rightmost DFF n+2 The input terminal D should be grounded, DFF 2n+3 to DFF n+3 The input terminals D of the n+1 D flip-flops are all connected to the COMP signal; the leftmost D flip-flop DFF 2n+3 The output Q signal is recorded as DT <n>, D flip-flop DFF 2n+2 The output Q signal is recorded as DT <n-1>, and is also connected to the previous D flip-flop DFF 2n+3 The clock input terminal CLK, D flip-flop DFF 2n+1 The output Q signal is recorded as DT <n-2>, and is also connected to the previous D flip-flop DFF 2n+2 The clock input terminal CLK, and the rest are similar, and the rightmost DFF n+2 The output Q is only used as the front DFF n+3 CLK signal, not recorded as other outputs; all D flip-flops DFF 2n+3 to DFF n+2 The inverting output terminal Q of all D flip-flops DFF is not left floating. 2n+3 to DFF n+2 The reset terminal R is connected to the RESET signal.

[0048] In this embodiment, the signal of COMP is provided by the signal of the ripple detection circuit. First, the N-bit register is set to the middle scale, the most significant bit MSB is set to 1, and the trimming circuit is turned off; the comparison value obtained by chopping switching compares the original size mismatch direction of the input pair tubes MA and MB on both sides of the amplifier A0; by judging the size of the gates VI1 and VI2 on both sides of the input pair tubes MA and MB, if VI1 is greater than VI2, the comparator outputs a logic high level or 1, and the MSB of the N-bit register remains 1; if VI1 is less than VI2, the comparator outputs a logic low level, and the MSB of the N-bit register is cleared to 0; then the input pair tubes that need to be increased in size are determined, and the control signal DT is determined by the corresponding state <n>and D <n>;

[0049] Then, the SAR control logic moves to the next bit and sets it high for the next comparison; until DT is obtained, <0> and D <0> ;

[0050] After the conversion is completed, the conversion result is stored in the register, and a signal is input through the state machine to turn off the chopping signal CH, and the chopping stops; while DT<n:0> and D<n:0> The result after comparison is maintained, and the offset voltage of the amplifier can be corrected within a certain range, thereby achieving the purpose of reducing the offset voltage of the amplifier.

[0051] like Figure 5 As shown, the SAR control logic is reset to zero through the RESET signal; then the register is set at the middle scale through the SET1 signal, during which the SW switch control of the dynamic zero comparator A1-A3 is closed for reset processing through the SW signal, and then the chopping signal CH starts to chop the input and output ends of the switching amplifier A0, and the obtained ripple comparison signal is passed through the ripple detection circuit to obtain a comparison signal, and the comparison signal is transmitted to the COMP end of the SAR control logic through a CLK_COM signal that is delayed by some time than CH through the D trigger, and then after some delays, COM is transmitted to the Q output end of the corresponding D trigger through the CLK clock signal on the rising edge.

[0052] As preferred in this embodiment, Figure 4 As shown, the trimming circuit includes switch tubes M1, M2, and a first trimming circuit and a second trimming circuit; the first trimming circuit and the second trimming circuit are respectively composed of DT <n>and D <n>Control; the source of the switch tubes M1 and M2 is connected to the source VC of the input pair of tubes on both sides of the amplifier A0; the gate of the switch tubes M1 and M2 is respectively connected by DT <n>and D <n>Control; the drains of the switch tubes M1 and M2 are connected to the first trimming circuit and the second trimming circuit respectively, and the input pairs of tubes MA and MB on both sides of the amplifier A0 are trimmed respectively.

[0053] In this embodiment, the first trimming circuit includes a plurality of PMOS switch tubes Msp1-Msp2 n -1 and several PMOS transistors Mp1-Mp2 n -1; the drain of the switch tube M1 and the PMOS switch tubes Msp1-Msp2 n -1's source is connected; the gate of the PMOS switch tube Msp1 is connected to DT <0> , the gates of the PMOS switches Msp2 and Msp3 are connected to DT <1> ;Msp2 n-1 -Msp2 n -1 of 2 n-1 The gate of each PMOS switch is connected to DT <n-1>; The PMOS switch tube Msp1-Msp2 n -1 and the drain of PMOS transistors Mp1-Mp2 n -1 is connected to the source; the PMOS transistors Mp1-Mp2 n The drains of the PMOS transistors Mp1-Mp2 are connected together and connected to the drain VA of the input pair tube MA on one side of the amplifier A0; n The gate of -1 is connected to the gate VI1 of the input pair tube MA on one side of the amplifier A0.

[0054] In this embodiment, the second trimming circuit includes a plurality of PMOS switch tubes Msn1-Msn2 n -1 and several PMOS transistors Mn1-Mn2 n -1; the drain of the switch tube M2 and the PMOS switch tubes Msn1-Msn2 n -1's source is connected, and Msn1's gate is connected to D <0> , the gates of Msn2 and Msn3 are connected to D <1> ; Msn2 n-1 -Msn2 n -1 of 2 n-1 The gate of the PMOS switch is connected to D <n-1>; The PMOS switch tubes Msn1-Msn2 n -1 and the drain of PMOS transistors Mn1-Mn2 n -1 is connected to the source; the PMOS transistors Mn1-Mn2 n The drains of the PMOS transistors Mn1-Mn2 are connected together and connected to the drain VB of the input pair tube MB on the other side of the amplifier A0; n The gate of -1 is connected to the gate V12 of the input pair tube MB on the other side of the amplifier A0.

[0055] The control signals of the first trimming switch and the second trimming switch are DT<n-1:0> , D<n-1:0> ; and follow 1, 2, 4, ..., 2 n-1 ,2 n The quantity relationship is controlled. That is, the lowest DT <0> , or D <0> Control a tube, DT <1> , or D <1> Control 2 tubes, DT <2> , or D <2> Control 4 tubes, and so on, DT <n-1>, or D <n-1>Control 2 n-1 tubes, and the highest bit DT <n>, or D <n>Then control whether the corresponding first trimming circuit and second trimming circuit are turned on.

[0056] Example 2

[0057] This embodiment provides a method for reducing the offset voltage of an amplifier, comprising the following steps:

[0058] S1), performing chopping processing of a certain frequency at the input and output ends of the amplifier A0;

[0059] S2), when the amplifier A0 is out of adjustment; the ripple signal COMP is detected by the ripple detection circuit and output through the hysteresis inverter;

[0060] S3) Input the offset comparison result to the state machine through the D flip-flop DFF, and the state machine outputs the digital signal DT after some state transitions. <n:0>and D <n:0>The control trimming circuit trims the trimming size of the input pair tube of the amplifier A0, thereby achieving the result of reducing the offset voltage of the amplifier A0.

[0061] In this embodiment, in step S1), corresponding choppers are provided at the input and output ends of the amplifier A0.

[0062] In this embodiment, in step S2), the ripple detection circuit includes three-stage auto-zero comparators A1-A3 and a hysteresis inverter INV.

[0063] In this embodiment, in step S3), the source electrodes of the switch tubes M1 and M2 are connected to the source electrodes VC of the input pair tubes on both sides of the amplifier A0; the gate electrodes of the switch tubes M1 and M2 are connected to the source electrodes VC of the input pair tubes on both sides of the amplifier A0; <n>and D <n>Control; the drains of the switch tubes M1 and M2 are connected to the first trimming circuit and the second trimming circuit respectively, and the input pairs of tubes MA and MB on both sides of the amplifier A0 are trimmed respectively.

[0064] As preferred in this embodiment, Figure 3 As shown, the state machine includes a plurality of D flip-flops and an inverter INV1, and the plurality of D flip-flops are arranged in three rows, namely the first row, the second row, and the third row from top to bottom, wherein the first row is provided with n+1 D flip-flops, the second row and the third row are both provided with n+2 D flip-flops, and the inverter INV1 is provided on the first row.

[0065] In this embodiment, the first row is arranged in descending order from left to right with D flip-flops DFF 3n+4 to DFF 2n+4 ; The leftmost D flip-flop DFF 3n+4 The set 1 terminal S is connected to the DFF of the second row n The output terminal Q of the D flip-flop DFF 3n+3 The set 1 terminal S is connected to the second row DFF n-1 The output terminal Q of the rightmost D flip-flop DFF 2n+4 The input terminal D of the D flip-flop DFF should be grounded; 3n+4 To D flip-flop DFF 2n+5 The input terminals D of the n D flip-flops are all connected to the COMP signal through the inverted signal of the inverter INV1; the leftmost D flip-flop DFF 3n+4 The output Q signal is recorded as D <n-1>, D flip-flop DFF 3n+3 The output Q signal is recorded as D <n-2>, and is also connected to the previous D flip-flop DFF 3n+4 The clock input terminal CLK of the rightmost D flip-flop DFF 2n+4 The output Q is only used as the front DFF 2n+5 CLK signal, not recorded as other outputs; all D flip-flops DFF 3n+4 to DFF 2n+4 The inverting output terminal Q of all D flip-flops DFF is not floating. 3n+4 to DFF 2n+4 The reset terminal R is connected to the RESET signal.

[0066] In this embodiment, the second row of D flip-flops DFF are arranged in descending order from left to right. n+1 to DFF 0 ; The leftmost D flip-flop DFF n+1 The set 1 terminal S is connected to the SET1 signal, and the D flip-flop DFF n to DFF 0 The set 1 terminal S of the n+1 D flip-flops is connected to the SET signal; the D flip-flop DFF n+1 The D input terminal D is grounded; the D flip-flop DFF n The input terminal D is connected to the previous D flip-flop DFF n+1 The output terminal Q of the D flip-flop DFF n-1 The input terminal D is connected to the previous D flip-flop DFF n The output terminal Q, and so on; the D flip-flop DFF on the far right 0 The input terminal Q is connected to the last D flip-flop DFF in the first and third rows. 2n+4 and DFF n+2 and the clock input terminals CLK of all the D flip-flops in the second row are connected to the clock signal CLK.

[0067] In this embodiment, the third row of D flip-flops DFF are arranged in descending order from left to right. 2n+3 to DFF n+2 ; The leftmost D flip-flop DFF 2n+3 The set 1 terminal S is connected to the D flip-flop DFF of the second row n+1 The output terminal Q of the D flip-flop DFF 2n+2 The set 1 terminal S is connected to the second row DFF n The output terminal Q of the D flip-flop DFF 2n+1 The set 1 terminal S is connected to the second row DFF n-1 The output terminal Q of the rightmost DFF n+2 The input terminal D should be grounded, DFF 2n+3 to DFF n+3 The input terminals D of the n+1 D flip-flops are all connected to the COMP signal; the leftmost D flip-flop DFF 2n+3 The output Q signal is recorded as DT <n>, D flip-flop DFF 2n+2 The output Q signal is recorded as DT <n-1>, and is also connected to the previous D flip-flop DFF 2n+3 The clock input terminal CLK, D flip-flop DFF 2n+1 The output Q signal is recorded as DT <n-2>, and is also connected to the previous D flip-flop DFF 2n+2 The clock input terminal CLK, and the rest are similar, and the rightmost DFF n+2 The output Q is only used as the front DFF n+3 The CLK signal is not recorded as other outputs.

[0068] First, the N-bit register is set to the middle scale, the most significant bit MSB is set to 1, and the trimming circuit is turned off; the comparison value obtained by chopping switching compares the original size mismatch direction of the input pair tubes MA and MB on both sides of the amplifier A0; by judging the size of the gates VI1 and VI2 on both sides of the input pair tubes MA and MB, if VI1 is greater than VI2, the comparator outputs a logic high level or 1, and the MSB of the N-bit register remains 1; if VI1 is less than VI2, the comparator outputs a logic low level, and the MSB of the N-bit register is cleared to 0; then the input pair tube that needs to be increased in size is determined, and the control signal DT is determined by the corresponding state <n>and D <n>;

[0069] Then, the SAR control logic moves to the next bit and sets it high for the next comparison; until DT is obtained, <0> and D <0> ;

[0070] After the conversion is completed, the conversion result is stored in the register, and a signal is input through the state machine to turn off the chopping signal CH, and the chopping stops; while DT<n:0> and D<n:0> The result after comparison is maintained, and the offset voltage of the amplifier can be corrected within a certain range, thereby achieving the purpose of reducing the offset voltage of the amplifier.

[0071] like Figure 5 As shown, the SAR control logic is reset to zero through the RESET signal; then the register is set at the middle scale through the SET1 signal, and the SW switch control of the dynamic zero comparator A1-A3 is closed by the SW signal to reset the process, and then the chopping signal CH starts to chop the input and output ends of the switching amplifier A0, and the obtained ripple comparison signal is passed through the ripple detection circuit to obtain a comparison signal, which is transmitted to the COMP end of the SAR control logic through a CLK_COM signal that is delayed by some time than CH through the D trigger, and then after some delay, COM is transmitted to the Q output end of the corresponding D trigger through the CLK clock signal on the rising edge. In this embodiment, the clock cycles of CH, CLK_COM, CLK and SW are the same, but there is a sequence for the rising edge. The duty cycles of CH, CLK_COM and CLK are all 50%, and the duty cycle of SW can be set to 20%. The signals of RESET and SET1 are transmitted to the state machine through the system, which can control the adjustment and recovery of the offset voltage of the amplifier. Whether the clocks of CH, CLK_COM, CLK and SW are active is also controlled by the state machine.

[0072] As a preferred embodiment of this invention, in step S3), if Figure 4 As shown, the trimming circuit includes switch tubes M1, M2, and a first trimming circuit and a second trimming circuit; the first trimming circuit and the second trimming circuit are respectively composed of DT <n>and D <n>Control; the source of the switch tubes M1 and M2 is connected to the source VC of the input pair of tubes on both sides of the amplifier A0; the gate of the switch tubes M1 and M2 is respectively connected by DT <n>and D <n>Control; the drains of the switch tubes M1 and M2 are connected to the first trimming circuit and the second trimming circuit respectively, and the input pairs of tubes MA and MB on both sides of the amplifier A0 are trimmed respectively.

[0073] In this embodiment, the first trimming circuit includes a plurality of PMOS switch tubes Msp1-Msp2 n -1 and several PMOS transistors Mp1-Mp2 n -1; the drain of the switch tube M1 and the PMOS switch tubes Msp1-Msp2 n -1's source is connected; the gate of the PMOS switch tube Msp1 is connected to DT <0> , the gates of the PMOS switches Msp2 and Msp3 are connected to DT <1> ;Msp2 n-1 -Msp2 n -1 of 2 n-1 The gate of each PMOS switch is connected to DT <n-1>; The PMOS switch tube Msp1-Msp2 n -1 and the drain of PMOS transistors Mp1-Mp2 n -1 is connected to the source; the PMOS transistors Mp1-Mp2 n The drains of the PMOS transistors Mp1-Mp2 are connected together and connected to the drain VA of the input pair tube MA on one side of the amplifier A0; n The gate of -1 is connected to the gate VI1 of the input pair tube MA on one side of the amplifier A0.

[0074] In this embodiment, the second trimming circuit includes a plurality of PMOS switch tubes Msn1-Msn2 n -1 and several PMOS transistors Mn1-Mn2 n -1; the drain of the switch tube M2 and the PMOS switch tubes Msn1-Msn2 n -1's source is connected, and Msn1's gate is connected to D <0> , the gates of Msn2 and Msn3 are connected to D <1> ; Msn2 n-1 -Msn2 n -1 of 2 n-1 The gate of the PMOS switch is connected to D <n-1>; The PMOS switch tubes Msn1-Msn2 n -1 and the drain of PMOS transistors Mn1-Mn2 n -1 is connected to the source; the PMOS transistors Mn1-Mn2 n The drains of the PMOS transistors Mn1-Mn2 are connected together and connected to the drain VB of the input pair tube MB on the other side of the amplifier A0; n The gate of -1 is connected to the gate V12 of the input pair tube MB on the other side of the amplifier A0.

[0075] The control signals of the switch tubes M1 and M2 are DT<n:0> , D<n:0> ; and follow 1, 2, 4, ..., 2 n-1 ,2 n The quantity relationship is controlled. That is, the lowest DT <0> , or D <0> Control a tube, DT <1> , or D <1> Control 2 tubes, DT <2> , or D <2> Control 4 tubes, and so on, DT <n-1>, or D <n-1>Control 2 n-1 tubes, and the highest bit DT <n>, or D <n>Then control whether the corresponding first trimming circuit and second trimming circuit are turned on.

[0076] The above embodiments and descriptions are only for illustrating the principles and best embodiments of the present invention. Without departing from the spirit and scope of the present invention, the present invention may be subject to various changes and improvements, all of which fall within the scope of the present invention to be protected.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A circuit for reducing an amplifier offset voltage, characterized in that: It includes a chopper CH1, a chopper CH2, a ripple detection circuit, a D flip-flop DFF, and a state machine; the chopper CH1 and the chopper CH2 are respectively arranged at the input end and the output end of the amplifier A0; the output end of the chopper CH2 is also connected to the ripple detection circuit; the output end of the ripple detection circuit is connected to the D flip-flop DFF through a hysteresis inverter INV; the D flip-flop DFF is connected to the state machine; the output end of the state machine is connected to the amplifier A0 through a trimming circuit; and the output end of the state machine is also connected to the chopper CH1 and the chopper CH2.

2. A circuit for reducing amplifier offset voltage according to claim 1, characterized in that: The ripple detection circuit comprises three-stage auto-zero comparators A1-A3 and a hysteresis inverter INV, and the output end of the auto-zero comparator A3 is connected to the hysteresis inverter INV.

3. A circuit for reducing amplifier offset voltage according to claim 2, characterized in that: The state machine includes a plurality of D flip-flops and an inverter INV1. The plurality of D flip-flops are arranged in three rows, which are divided into the first row, the second row, and the third row from top to bottom. The first row is provided with n+1 D flip-flops, the second row and the third row are both provided with n+2 D flip-flops, and the inverter INV1 is provided on the first row.

4. A circuit for reducing amplifier offset voltage according to claim 3, characterized in that: The first row is arranged in descending order from left to right with D flip-flops DFF 3n+4 to DFF 2n+4 ; The leftmost D flip-flop DFF 3n+4 The set 1 terminal S is connected to the DFF of the second row n The output terminal Q of the D flip-flop DFF 3n+3 The set 1 terminal S is connected to the second row DFF n-1 The output terminal Q of the rightmost D flip-flop DFF 2n+4 The input terminal D of the D flip-flop DFF is grounded. 3n+4 To D flip-flop DFF 2n+5 The input terminals D of the n D flip-flops are all connected to the COMP signal through the inverted signal of the inverter INV1; the leftmost D flip-flop DFF 3n+4 The output Q signal is recorded as D <n-1>, D flip-flop DFF 3n+3 The output Q signal is recorded as D <n-2>, and is also connected to the previous D flip-flop DFF 3n+4 The clock input terminal CLK of the rightmost D flip-flop DFF 2n+4 The output Q is only used as the front DFF 2n+5 CLK signal, not recorded as other outputs; all D flip-flops DFF 3n+4 to DFF 2n+4 The inverting output terminal Q of all D flip-flops DFF is not left floating. 3n+4 to DFF 2n+4 The reset terminal R is connected to the RESET signal.

5. A circuit for reducing amplifier offset voltage according to claim 4, characterized in that: The second row is arranged in descending order from left to right, with D flip-flops DFF n+1 To DFF0; the leftmost D flip-flop DFF n+1 The set 1 terminal S is connected to the SET1 signal, and the D flip-flop DFF n The set 1 terminal S of the n+1 D flip-flops of DFF0 is connected to the SET signal; the D flip-flop DFF n+1 The D input terminal D is grounded, and the D flip-flop DFF n The input terminal D is connected to the previous D flip-flop DFF n+1 The output terminal Q of the D flip-flop DFF n-1 The input terminal D is connected to the previous D flip-flop DFF n The output terminal Q of the D flip-flop DFF0 on the right is connected to the last D flip-flop DFF in the first and third rows. 2n+4 and DFF n+2 and the clock input terminals CLK of all the D flip-flops in the second row are connected to the clock signal CLK.

6. The circuit for reducing amplifier offset voltage according to claim 5, characterized in that: The third row of D flip-flops DFF are arranged in descending order from left to right. 2n+3 to DFF n+2 ; The leftmost D flip-flop DFF 2n+3 The set 1 terminal S is connected to the D flip-flop DFF of the second row n+1 The output terminal Q of the D flip-flop DFF 2n+2 The set 1 terminal S is connected to the second row DFF n The output terminal Q of the D flip-flop DFF 2n+1 The set 1 terminal S is connected to the second row DFF n-1 The output terminal Q of the rightmost DFF n+2 The input terminal D of DFF should be grounded; 2n+3 to DFF n+3 The input terminals D of the n+1 D flip-flops are all connected to the COMP signal; the leftmost D flip-flop DFF 2n+3 The output Q signal is recorded as DT <n>, D flip-flop DFF 2n+2 The output Q signal is recorded as DT <n-1>, and is also connected to the previous D flip-flop DFF 2n+3 The clock input terminal CLK, D flip-flop DFF 2n+1 The output Q signal is recorded as DT <n-2>, and is also connected to the previous D flip-flop DFF 2n+2 The clock input terminal CLK, and the rest are similar, and the rightmost DFF n+2 The output Q is only used as the front DFF n+3 The CLK signal is not recorded as other outputs. < / n> 7. A circuit for reducing amplifier offset voltage according to claim 6, characterized in that: The trimming circuit includes switch tubes M1, M2, and a first trimming circuit and a second trimming circuit; the first trimming circuit and the second trimming circuit are respectively composed of DT<n-1:0> and D<n-1:0> Control; the source of the switch tubes M1 and M2 is connected to the source VC of the input pair of tubes on both sides of the amplifier A0; the gate of the switch tubes M1 and M2 is respectively connected by DT <n>and D <n> Control; the drains of the switch tubes M1 and M2 are connected to the first trimming circuit and the second trimming circuit respectively, and the input pairs of tubes MA and MB on both sides of the amplifier A0 are trimmed respectively.< / n> < / n> 8. The circuit for reducing amplifier offset voltage according to claim 7, characterized in that: The first trimming circuit includes a plurality of PMOS switch tubes Msp1-Msp2 n -1 and several PMOS transistors Mp1-Mp2 n -1; the drain of the switch tube M1 and the PMOS switch tubes Msp1-Msp2 n -1's source is connected; the gate of the PMOS switch tube Msp1 is connected to DT <0> , the gates of the PMOS switches Msp2 and Msp3 are connected to DT <1> ;Msp2 n-1 -Msp2 n -1 of 2 n-1 The gate of each PMOS switch is connected to DT <n-1>; The PMOS switch tube Msp1-Msp2 n -1 and the drain of PMOS transistors Mp1-Mp2 n -1 is connected to the source; the PMOS transistors Mp1-Mp2 n The drains of the PMOS transistors Mp1-Mp2 are connected together and connected to the drain VA of the input pair tube MA on one side of the amplifier A0; n The gate of -1 is connected to the gate VI1 of the input pair tube MA on one side of the amplifier A0.

9. The circuit for reducing amplifier offset voltage according to claim 7, characterized in that: The second trimming circuit includes a plurality of PMOS switch tubes Msn1-Msn2 n -1 and several PMOS transistors Mn1-Mn2 n -1; the drain of the switch tube M2 and the PMOS switch tubes Msn1-Msn2 n -1's source is connected, and Msn1's gate is connected to D <0> , the gates of Msn2 and Msn3 are connected to D <1> ; Msn2 n-1 -Msn2 n -1 of 2 n-1 The gate of the PMOS switch is connected to D <n-1>; The PMOS switch tubes Msn1-Msn2 n -1 and the drain of PMOS transistors Mn1-Mn2 n -1 is connected to the source; the PMOS transistors Mn1-Mn2 n The drains of the PMOS transistors Mn1-Mn2 are connected together and connected to the drain VB of the input pair tube MB on the other side of the amplifier A0; n The gate of -1 is connected to the gate V12 of the input pair tube MB on the other side of the amplifier A0.

10. A method for reducing amplifier offset voltage, characterized in that: The method uses the circuit according to any one of claims 1 to 9 to reduce the amplifier offset voltage, and the method comprises the following steps: S1), a chopping process of a certain frequency is performed at the input and output ends of the amplifier A0 through corresponding choppers; S2), when the amplifier A0 is out of adjustment; the ripple detection circuit detects the ripple signal COMP and outputs it through the hysteresis inverter; S3) Input the offset comparison result to the state machine through the D flip-flop DFF, and the state machine outputs the digital control signal DT after some state transitions. <n:0>and D <n:0>, through the digital control signal DT <n:0>and D <n:0> The control adjustment circuit adjusts the size of the input tube of the amplifier A0, thereby achieving the result of reducing the offset voltage of the amplifier A0.< / n:0>

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