FPGA (Field Programmable Gate Array) implementation method, system and equipment for multiphase filtering channelizer and medium

Abstract

The invention relates to an FPGA (Field Programmable Gate Array) implementation method, system, equipment and medium for a multiphase filtering channelizer, which comprises the following steps of: performing serial-parallel conversion and data shaping on serial data to obtain parallel shaping data, multiplying the parallel shaping data by a filter coefficient group, and performing summation and accumulation operation to obtain parallel data after multiphase filtering calculation; performing cache shaping and parallel-serial conversion on the parallel data by using an RAM (Random Access Memory) to obtain a serial multi-phase filtering data block, sending the serial multi-phase filtering data block into an IFFT (Inverse Fast Fourier Transform) module to obtain channelized data, and performing frequency offset compensation and cycle counting to obtain the parallel data; the FPGA implementation system of the multi-phase filtering channelizer comprises a data shaping module, a multi-phase filtering operation module, a parallel-serial conversion module, an inverse Fourier transform module, a frequency offset compensation module and a parallel data output module. The equipment and the medium are used for storing computer programs, and the FPGA implementation method is completed when the programs are executed; according to the method, the digital channelization function can be realized by using fewer FPGA resources.

Description

Technical Field

[0001] The present invention relates to the technical field of satellite communication digital signal processing, and in particular to an FPGA (Field-Programmable Gate Array) implementation method, system, device and medium of a polyphase filter channelizer. Background Art

[0002] With the rapid development of satellite communication technology and the popularization of the trend of massive intelligent terminals, various Internet of Things and Internet terminals have experienced explosive growth. These combined reasons have made the occupation of spectrum resources increasingly tight and the use conditions and environment have become complicated. In the field of wireless communications, the receiver will receive data signals with multiple channels at the same time. In order to distinguish these signals, the received broadband signal needs to be divided into sub-channels according to a certain bandwidth to meet the demodulation requirements of subsequent receivers. In addition, in electronic radar reconnaissance applications, there are multi-dimensional and multi-type communications, interference, radar reconnaissance and other frequency-using equipment emitting signals with different energies, modulation methods and bandwidths, making the competition for electromagnetic spectrum resources particularly fierce.

[0003] In order to meet the above needs, digital channelized receivers that integrate digital multiphase filter technology and channelized processing technology have been born. They have both the highly comprehensive capabilities of channelized receivers and the stability and flexibility of digital receivers, greatly reducing the power consumption, resource consumption, complexity, etc. of the receiver, outputting small bandwidth signals, and reducing the data processing rate of the back-end processing module; on the other hand, since the 1990s, with the rapid development of semiconductor digital chip design and manufacturing technology, digital receivers have replaced analog receivers and become the mainstream development trend of current receiving and demodulating equipment. They have good stability, can preserve the integrity of the signal as much as possible, and fully and flexibly use various digital signal demodulation technologies. Especially in the scenarios of massive satellite Internet of Things terminals and radar electronic reconnaissance, multi-channel digital channelized receivers can use large-scale parallel channels to process data, further increasing the ability to process multiple information at the same time, and ensuring the normal operation of the subsequent demodulation process of the receiver.

[0004] Digital channelization technology can be divided into single-channel digital channelizers according to the differences in core principles. The channelizer is constructed by performing parallel collective reception processing on multiple single channels; the digital channelizer based on FFT (Fast Fourier Transform) uses FFT or windowed STFT (Short-Time Fourier Transform) to achieve signal band division; the digital channelizer based on WOLA (Weighted OverLap-Add) and multi-phase filtering structure is mainly implemented by combining weighted digital filtering and multi-phase high-efficiency structure with IDFT (Inverse Discrete Fourier Transform).

[0005] Existing channelizers are mainly implemented using a multi-phase high-efficiency structure combined with DFT (Discrete Fourier Transform), but most of them are based on specific project requirements to establish an architecture with poor flexibility. Under harsh conditions, it is urgent to make digital receivers meet the requirements of large bandwidth, low latency, low complexity, high-precision and fast data processing capabilities.

[0006] In the prior art, the invention with the patent announcement number of "CN118353749B" and the name of "An Improved Digital Channelization FPGA Implementation Method" realizes multi-phase wave calculation through data weighting combined with array grouping and folding addition, and performs frequency correction and FFT calculation to realize channelization on this basis, which has good real-time performance and flexibility, and realizes the division of 16-way effective bandwidth 75M sub-bands; however, the multi-phase FPGA (Field-Programmable Gate Array) architecture consumes a lot of resources. If the structure is oriented to extremely high-order prototype filters, large-scale cluster sub-band division and non-critical extraction, the number of multipliers used is directly related to the length of the prototype filter. Considering the limited FPGA resources, it is difficult to implement in actual engineering. At the same time, the patent does not provide a specific and clear FPGA engineering implementation architecture.

[0007] In the prior art, a master's thesis entitled "Research on Digitalization of Wireless Receiver Channels and FPGA Implementation" (Li Chao. Research on Digitalization of Wireless Receiver Channels and FPGA Implementation [D]. University of Electronic Science and Technology of China, 2018.) completed the FPGA architecture design and verification of a 256-channel digital channelizer, which can correspond to a variety of application scenarios. At the same time, relevant research was conducted on the blind area coverage, channel ambiguity and signal cross-channel interference between adjacent sub-bands that may exist in the digital structure. In addition, the parallel DDC (Digital Down Converter) is combined to make the entire digital channelizer have better performance. The data extraction part is implemented using a register with a depth of 256 combined with a counter, which can save certain storage resources compared to using FIFO (First In First Out) or RAM. However, it is designed based on a theoretical multiphase structure, but the number of multiphase branches it uses is the same as the number of subband divisions. If a high-order prototype filter is used to perform convolution calculations on each branch, the multiplier resources consumed are large. At the same time, it has not conducted a more in-depth study on the implementation of the multiphase architecture. Summary of the invention

[0008] In order to overcome the shortcomings of the above-mentioned prior art, the purpose of the present invention is to propose an FPGA implementation method, system, device and medium of a multi-phase filter channelizer. The method establishes a multi-phase filter calculation architecture through the convolution law of the basic theory of multi-phase filtering. Combined with flexibly configurable parameters, it can realize multi-phase filtering operations with low resource consumption in non-critical extraction, that is, the extraction multiple is not equal to the number of channel divisions, and extremely high-order prototype filters. Under the premise that the signal has a large duty cycle and low rate, it can greatly reduce the DSP (Digital Signal Processor) resource consumption and realize signal frequency band division and variable rate processing in the scenario of burst signal demodulation of massive terminals of satellite Internet of Things.

[0009] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0010] In a first aspect, the present invention provides an FPGA implementation method of a polyphase filter channelizer, comprising the following steps:

[0011] S1: Set the N-order prototype filter coefficients of the channelizer, the number of sub-band channel divisions M, and the data extraction multiple D, and use FIFO and counter to complete the serial-to-parallel conversion and data shaping of the serial signal input to the channelizer to obtain I groups of parallel shaping data, where I = N / M;

[0012] S2: Evenly divide the N-order prototype filter coefficients in step S1 into I groups of branch filter coefficients, multiply the I groups of branch filter coefficients in reverse order with the I groups of parallel shaping data in step S1 to obtain convolution operation parallel data, and sum and accumulate the same channel data in the convolution operation parallel data to obtain parallel data after multi-phase filtering calculation;

[0013] S3: using RAM to perform cache shaping and parallel-to-serial conversion on the parallel data after the multi-phase filtering calculation in step S2 to obtain a serial multi-phase filtering data block;

[0014] S4: sending the serial multiphase filtered data block in step S3 to an IFFT module to complete an inverse Fourier transform, and obtaining M-point IFFT output data;

[0015] S5: Perform frequency offset compensation on the M-point IFFT output data in step S4 and then output serial data;

[0016] S6: Setting a loop counter to count the serial data in step S5 to obtain a loop counter value, selecting corresponding channel data according to the loop counter value and completing parallel data output.

[0017] Furthermore, the step S1 comprises the following steps:

[0018] S1.1: Set the N-order prototype filter coefficients, the number of sub-band channel divisions M, and the data extraction multiple D of the channelizer, and use FIFO to divide the serial signal input to the channelizer into I groups of single-channel data, where I = N / M, and each group of single-channel data differs by M clock delays;

[0019] S1.2: Set the value of the counter in step S1 to 0 to X, where X=M·(M / D-1). When the counter value is an integer multiple of D, assign values ​​to the second to M / D-th data according to the first data of each group of single-channel data. Similarly, I groups of parallel shaped data can be obtained, each of which contains M / D channels, and the serial signal completes the serial-to-parallel conversion.

[0020] Furthermore, step S2 comprises the following steps:

[0021] S2.1: performing phase division on the N-order prototype filter coefficients in step S1.1 according to the number of sub-band channel divisions M, into I groups of branch filter coefficients, where I = N / M, and reversing the order of the I groups of branch filter coefficients;

[0022] S2.2: For each data in the I group of parallel shaping data described in step S1.2, a counter with a value of 0 to M-1 is set, and the I group of branch filter coefficients after the reverse order described in step S2.1 is selected according to the principle of numerical correspondence for each group of branch filter coefficients, and each group of branch filter coefficients is sent to the multiplier together with the I group of parallel shaping data in step S1.2 to complete the corresponding multiplication operation to obtain the convolution operation parallel data;

[0023] S2.3: Sum and accumulate the same channel data in the parallel data of the convolution operation in step S2.2 respectively to obtain parallel data after multi-phase filtering calculation.

[0024] Furthermore, step S3 includes the following steps: setting p RAMs with a depth of M, where p = M / D, caching and shaping the parallel data after the multi-phase filtering calculation output in step S2, and after the parallel data after the multi-phase filtering calculation, i.e., the p-way parallel shaped data, in the corresponding channel of the RAM data is full, using an auxiliary counter to read the data in reverse order from the high address to the low address of the RAM, and finally converting the p-way parallel shaped data into serial multi-phase filtering data blocks, each of which contains M data units.

[0025] Further, step S5 comprises the following steps:

[0026] S5.1: setting the real part and imaginary part of the phase adjustment coefficient group in the frequency offset compensation operation to a total of two two-dimensional arrays, wherein each two-dimensional array contains M / D data elements, and the number of bits of the M / D data elements is M / D·16;

[0027] S5.2: Set a data block counter to complete the block counting of the M-point IFFT output data in step S4, set a compensation factor selection counter to complete the selection of the phase adjustment coefficient group data in step S5.1, send the M-point IFFT output data after block counting and the corresponding selected phase adjustment coefficient group data to the complex multiplier to complete the frequency offset compensation operation to obtain serial data. The frequency offset compensation formula is as follows:

[0028]

[0029] In formula (1), v k (n) is the data corresponding to the kth channel after frequency offset compensation, x k (n) is the serial data of the corresponding k-th channel after inverse Fourier transform, k is the channel number, M is the number of sub-band channel divisions, D is the data extraction multiple, j is the imaginary unit, and n is the subscript of the M-point IFFT output data sequence.

[0030] Furthermore, in step S6, the loop counter is set to a value from 0 to M.

[0031] In a second aspect, an FPGA implementation system of a multiphase filter channelizer is provided, and the FPGA implementation method of the multiphase filter channelizer is applied, and the FPGA implementation system includes a data shaping module, a multiphase filter operation module, a parallel-to-serial conversion module, an inverse Fourier transform module, a frequency offset compensation module, and a parallel data output module;

[0032] Data shaping module: sets the N-order prototype filter coefficients of the channelizer, the number of sub-band channel divisions M, and the data extraction multiple D, and uses FIFO and counter to complete serial-to-parallel conversion and data shaping of the serial signal input to the channelizer to obtain I groups of parallel shaping data, where I = N / M;

[0033] Polyphase filtering operation module: the N-order prototype filter coefficients are evenly divided into I groups of branch filter coefficients, the I groups of branch filter coefficients are reversed and multiplied with the I groups of parallel shaping data to obtain convolution operation parallel data, and the same channel data in the convolution operation parallel data are summed and accumulated to obtain parallel data after polyphase filtering calculation;

[0034] A parallel-to-serial conversion module: using RAM to cache and reshape the parallel data after the polyphase filtering calculation and perform parallel-to-serial conversion to obtain a serial polyphase filtering data block;

[0035] Inverse Fourier transform module: sending the serial multiphase filter data block to the IFFT module to complete the inverse Fourier transform, and obtain M-point IFFT output data;

[0036] Frequency offset compensation module: performs frequency offset compensation on the M-point IFFT output data and then outputs serial data;

[0037] Parallel data output module: set a loop counter to count the serial data to obtain a loop counter value, select corresponding channel data according to the loop counter value and complete parallel data output.

[0038] In a third aspect, an electronic device includes a memory and a processor:

[0039] Memory: used for storing a computer program for implementing the FPGA implementation method of the polyphase filter channelizer;

[0040] Processor: used to implement the FPGA implementation method of the polyphase filter channelizer when executing the computer program.

[0041] In a fourth aspect, a computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the FPGA implementation method of the multi-phase filter channelizer is implemented.

[0042] Compared with the prior art, the present invention has the following beneficial effects:

[0043] 1. In steps S1 to S2 of the present method, a multiphase filtering calculation architecture is established through the convolution law of the basic theory of multiphase filtering. Combined with the flexibly configurable parameters, namely the number of sub-band channel divisions M and the downsampling data decimation multiple D, it is possible to implement multiphase filtering operations with low resource consumption in the case of non-critical decimation, i.e., the decimation multiple is not equal to the number of channel divisions, and extremely high-order prototype filters.

[0044] 2. In the case of non-critical decimation, that is, the decimation multiple is not equal to the number of channel divisions, in steps S1 to S6 of the method, according to the convolution law of the basic theory of polyphase filtering, the serial data can be divided into N / M groups of parallel data by the prototype filter order N, the number of sub-band channel divisions M and the downsampling decimation multiple D (adjustable), and each group has M / D path data; when facing the processing of extremely low-rate signals, the front stage will sample and extract the ADC (Analog-to-Digital Convert) signal through multiple stages. Under the premise that the signal has a large duty cycle and a low rate, only N / D multipliers are used to complete the polyphase filtering calculation, which can greatly reduce the DSP resource consumption compared to directly using the polyphase theoretical structure for convolution operation and consuming the same multiplication resources as the prototype filter order; at the same time, combined with the IFFT channelization operation, it can realize the uniform division of broadband signals according to a certain sub-band channel bandwidth, which is suitable for the communication scenario of satellite Internet of Things massive terminals, and is conducive to engineering implementation, and has better engineering practicality and the ability to process low-rate signals at variable rates.

[0045] In summary, in the scenario of extremely narrowband and extremely low symbol rate sub-band channel division for demodulating massive terminal signals of satellite Internet of Things, and under the conditions of extremely high-order prototype filters, large-scale cluster sub-band low symbol rate signal division and non-critical extraction, the present invention can realize the digital channelization function with less FPGA resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a flow chart of an FPGA implementation method of a polyphase filter channelizer in the present invention.

[0047] Figure 2 The present invention discloses an algorithm flow chart of an FPGA implementation method of a polyphase filter channelizer.

[0048] Figure 3 It is an FPGA architecture flow chart of an FPGA implementation method of a polyphase filter channelizer in the present invention.

[0049] Figure 4It is a schematic diagram of sub-band distribution of an FPGA implementation method of a polyphase filter channelizer in the present invention.

[0050] Figure 5 It is a schematic diagram of FPGA multi-phase filtering convolution calculation waveform when the number of sub-band channel divisions M and the data extraction multiple D are both set to 512 provided by an embodiment of the present invention.

[0051] Figure 6 The input channelizer provided by the embodiment of the present invention includes a spectrum diagram of serial combined data with two different symbol rates.

[0052] Figure 7 It is a schematic diagram of the channelized spectrum of 350sps (symbol rate) data provided by an embodiment of the present invention.

[0053] Figure 8 It is a schematic diagram of a channelized spectrum of 500sps (symbol rate) data provided by an embodiment of the present invention.

[0054] Fig. 9 It is a schematic diagram of the quality of data constellation recovery after being processed by a digital channelizer provided by an embodiment of the present invention.

[0055] Fig.10 It is a schematic diagram of the data constellation recovery quality after low-pass filtering and extraction provided by the comparison structure. DETAILED DESCRIPTION

[0056] Combine the following Figures 1 to 10 The present invention is described in further detail:

[0057] In a first aspect, the present invention provides an FPGA implementation method of a polyphase filter channelizer, comprising the following steps: Figure 1 Shown is a schematic flow chart of the FPGA implementation method of the present invention:

[0058] S1: Set the N-order prototype filter coefficients, the number of sub-band channel divisions M, and the data extraction multiple D of the (digital) channelizer, and use the FIFO and counter to complete the serial-to-parallel conversion and data shaping of the serial signal input to the channelizer to obtain I groups of parallel shaping data, where I = N / M;

[0059] S2: Evenly divide the N-order prototype filter coefficients in step S1 into I groups of branch filter coefficients, multiply the I groups of branch filter coefficients in reverse order with the I groups of parallel shaping data in step S1 to obtain convolution operation parallel data, and sum and accumulate the same channel data in the convolution operation parallel data to obtain parallel data after multi-phase filtering calculation;

[0060] S3: using RAM to perform cache shaping and parallel-to-serial conversion on the parallel data after the multi-phase filtering calculation in step S2 to obtain a serial multi-phase filtering data block;

[0061] S4: sending the serial multiphase filtered data block in step S3 to an IFFT module to complete an inverse Fourier transform, and obtaining M-point IFFT output data;

[0062] S5: Perform frequency offset compensation on the M-point IFFT output data in step S4 and then output serial data;

[0063] S6: Setting a loop counter to count the serial data in step S5 to obtain a loop counter value, selecting corresponding channel data according to the loop counter value and completing parallel data output.

[0064] Furthermore, the step S1 comprises the following steps:

[0065] S1.1: First, set the floating-point N-order prototype filter coefficients of the channelizer, perform normalization and fixed-point operations on the floating-point N-order prototype filter coefficients, and generate the N-order prototype filter coefficients; set the N-order prototype filter coefficients of the (digital) channelizer, the number of sub-band channel divisions M, and the data extraction multiple D, use FIFO to divide the serial signal input to the channelizer into I groups of single-channel data, where I = N / M, and use I-1 FIFOs to delay the serial signal so that each group of single-channel data differs by M clock delays;

[0066] S1.2: Set the value of the counter in step S1 to 0 to X, where X=M·(M / D-1). When the counter value is an integer multiple of D, assign values ​​to the second to M / D-th data according to the first data of each group of single-channel data. Similarly, I groups of parallel shaped data can be obtained, each of which contains M / D channels, and the serial signal completes the serial-to-parallel conversion.

[0067] The step S2 mainly designs the corresponding FPGA hardware implementation architecture according to the software algorithm of the multi-phase channelizer, namely the multi-phase filter convolution calculation rule. In actual engineering, if the sub-band channel is directly subjected to a bandpass filter and digital frequency conversion to realize digital channelization, a large amount of hardware resources will be occupied. At the same time, the front-stage filter will have a large processing pressure due to the high data rate. Therefore, the multi-phase structure can be used for optimization. Compared with the order of filtering first and then extracting in ordinary filters, the multi-phase filter is calculated in the order of extraction and filtering. In this way, the extracted and discarded data will not be filtered again, which greatly reduces the calculation complexity and resource consumption.

[0068] Figure 2The flowchart of the algorithm for the FPGA implementation of the polyphase filter channelizer is shown in Figure 2. The core idea is to divide a broadband signal into multiple narrow sub-band signals. Let h(n) be the coefficient of the N-order filter bank. The bandwidth is evenly distributed in each sub-channel. The number of sub-channel divisions is M, and the decimation factor is D. M and D satisfy the integer multiple relationship, M = FD. Then the output formula (2) of the k-th sub-channel is as follows:

[0069]

[0070] In formula (2), y k (m) represents the output of the kth subchannel, x(n) is the input data, and h k (n) is the coefficient of the polyphase branch filter of k subchannels, ω k represents the center frequency of the kth subchannel, m represents the output data subscript, n represents the input data subscript, j represents the imaginary unit, and i represents the convolution calculation variable; Indicates that the sample data is moved to the frequency band of the low-pass filter, h(n) is the prototype filter coefficient; if i=rM+p, r∈(-∞,∞), p∈(0,M-1), where r is the data segment number, the subscript of the sample data point in this segment is set to p, l is a transient variable, which is specifically expressed as l=rF, F is the ratio between the number of sub-band channel divisions M and the data extraction multiple D F=M / D, at this time, x p (m) and h p (m) can be expressed as formula (3) and formula (4) respectively:

[0071] x p (m) = x(mD-p) (3)

[0072] h p (m) = h(mM+p) (4) y in formula (2) k (m) can be further expressed by formula (5):

[0073]

[0074] In formula (5), m is the output data subscript; h p (r) is the coefficient of each group of polyphase branch filters, that is, the prototype filter coefficient h lp (n) is obtained after M-fold decimation, p (l) Perform F times interpolation to obtain

[0075] As ordered Then we have formula (6):

[0076]

[0077] In formula (6), xp (m) is the new sequence after the input data x(m) is decimated by D times, m is the output data subscript, D is the data decimation multiple, g p (m), g p (l) are the coefficients of the polyphase branch filter after decimation and interpolation, j is the imaginary unit, ω k is the center frequency of the kth subchannel, S′ p (m) represents the extracted data and rotation factor The multiplication result is the spectrum shift to the baseband, S p (m) represents the result of the process of low-pass filtering after moving the extracted data spectrum to the baseband; then the output y of the kth subchannel divided in formula (5) k (m) As shown in formula (7):

[0078]

[0079] In formula (7), y k (m) represents the output of the kth subchannel, p∈(0,M-1) is the subscript of the segmented sample data, and M represents the number of subband channel divisions. Based on the derivation, it can be concluded that the multiphase filtering process of the digital channelization software algorithm is mainly to sample the data sample x(n) after D times sampling and then compare it with g p (m) performs convolution filtering. In addition, if the downsampling multiple D is inconsistent with the number of channel divisions M, that is, F is not equal to 0, the branch filter coefficients can be interpolated according to the value of F and then convolution filtering is performed with the parallel shaping data.

[0080] Derived from the formula of the above algorithm, combined with the convolution law of polyphase filtering, the corresponding FPGA polyphase convolution computing architecture can be designed; assuming the input signal x(n), the prototype filter coefficient is h(n), the polyphase filter coefficient length is N, the number of sub-band channel divisions is M, and the data extraction multiple is D, where M = FD, then there is formula (8):

[0081] m I′P′ (n) = x I′P′ (n+I′M+P′D)h(M(I′+1)-(nmodM)) (8)

[0082] Formula (8) is the multiplication result of the multiphase structure, where Indicates the number of single-channel data groups. Indicates the number of parallel shaping data paths in each group, n indicates the data index, x I′P′ (n) indicates the nth data of the P′th path of the I′th group of input, m IP′(n) represents the nth data of the P′th path of the I′th group of the calculated output, and mod represents the remainder operation; the convolution operation parallel data needs to be summed up subsequently to complete the multi-phase filtering calculation of the hardware architecture. The specific formula (9) is as follows:

[0083]

[0084] In formula (9), y P′ (n) represents the parallel data after multi-phase filtering calculation, n is the output data subscript, Indicates the number of single-channel data groups. Indicates the number of parallel shaping data paths for each group, m I′P′ (n) represents the nth data of the P′th path of the I′th group of calculated outputs; from formula (9), after the multiplication and summation calculations of the multiphase filtering hardware architecture, there are a total of M / D paths of data; Figure 5 It represents the multi-phase operation form of the first two groups of data when M=D=512. By completing the operation of 16 groups of data according to this rule, the multi-phase filtering with a downsampling multiple of 512 can be completed.

[0085] Further, the I groups of parallel shaped data in step S1 are multiplied and accumulated with the corresponding I groups of branch filter coefficients in reverse order to obtain parallel data after multi-phase filtering calculation, and the multi-phase filtering operation is completed. The step S2 specifically includes the following steps:

[0086] S2.1: Phase-dividing the N-order prototype filter coefficients in step S1.1 according to the number of sub-band channel divisions M, into I groups of branch filter coefficients, where I=N / M, and reversing the order of the I groups of branch filter coefficients; in FPGA, a two-dimensional array can be used to define the I groups of branch filter coefficients after the reversal, and the I groups of branch filter coefficients after the reversal correspond to the I groups of parallel shaping data in step S1.2 one by one;

[0087] S2.2: For each data in the I group of parallel shaping data described in step S1.2, a counter with a value of 0 to M-1 is set, and the I group of branch filter coefficients after the reverse order described in step S2.1 is selected according to the principle of numerical correspondence for each group of branch filter coefficients, and each group of branch filter coefficients is sent to the multiplier together with the I group of parallel shaping data in step S1.2 to complete the corresponding multiplication operation to obtain the convolution operation parallel data;

[0088] S2.3: Sum and accumulate the same channel data in the parallel data of the convolution operation in step S2.2 respectively to obtain parallel data after multi-phase filtering calculation.

[0089] Furthermore, step S3 includes the following steps: setting p RAMs with a depth of M (i.e., the RAM includes p IP cores with a depth of M), where p = M / D, and performing cache shaping on the parallel data calculated after the multi-phase filtering output in step S2. After the RAM data in the corresponding channel of the parallel data calculated after the multi-phase filtering, i.e., the p-way parallel shaped data, is full, an auxiliary counter is used to read the data in reverse order from the high address to the low address of the RAM, and finally the p-way parallel shaped data is converted into a serial multi-phase filtering data block, wherein each data block contains M data units.

[0090] Furthermore, the step S4 mainly uses the IFFT module to complete the M-point IFFT calculation of the serial polyphase filtering data block in step S3. Figure 4 is a schematic diagram of the distribution of sub-bands, where the center frequency of the kth sub-band channel is ω k =2πk / M, which means that the sampling rate f s Divided into M parts, M is the number of sub-band channel divisions. For the convenience of derivation, the number of sub-band channel divisions M is assumed to be the same as the data extraction multiple D, that is, F = 1, and ω k =2πk / M Substituting into formula (7), we can get formula (10):

[0091]

[0092] In formula (10), the e in the second row is -j2kπm =cos(2kπm)-jsin(2kπm)=1,y k (m) represents the output of the kth subchannel, p∈(0,M-1) is the subscript of the segmented sample data, M represents the number of subband channel divisions, x p (m) is the data after extraction and spectrum shifting, g p (m) is the coefficient of the polyphase branch filter, m represents the subscript of the output data, k represents the current subband channel number, j represents the imaginary unit, D is the data extraction multiple, and IDFT represents the inverse Fourier transform. Formula (10) shows that after completing the convolution operation of each group of data samples with the corresponding filter group coefficients, the IDFT (inverse Fourier transform) is calculated m times M points, and the obtained y k (m) is the mth output data of the kth subchannel.

[0093] Deduced from the formula of the above algorithm and combined with the convolution law of its multi-phase filtering, the corresponding FPGA multi-phase convolution computing architecture can be designed.

[0094] When the number of sub-band channel divisions M is 512, the data sample extraction multiple D is 64, and the polyphase filter length N is 8192, the overall digital channelization FPGA architecture is as follows Figure 3 shown.

[0095] Further, step S5 comprises the following steps:

[0096] S5.1: If each block of data (M / D blocks of data) in the M-point IFFT output data in step S4 is set as a group, the compensation factor of each group of data is exactly the same, and the compensation factor of each block of data changes cyclically with M / D data as a group. Based on this, a two-dimensional array can be set to define the compensation factor of each block of data; according to the above analysis, the real part and the imaginary part of the phase adjustment coefficient group in the frequency offset compensation operation are set to a total of 2 two-dimensional arrays, wherein each two-dimensional array contains M / D data elements, and the number of bits of the M / D data elements is M / D·16;

[0097] S5.2: Set a data block counter to complete the block counting of the M-point IFFT output data in step S4, set a compensation factor selection counter to complete the selection of the phase adjustment coefficient group data in step S5.1, and send the M-point IFFT output data after block counting and the corresponding selected phase adjustment coefficient group data to the complex multiplier to complete the frequency offset compensation operation to obtain serial data; because it involves signal rate change processing, it is necessary to multiply the channel data to be output in this step with the corresponding compensation factor, and then complete the corresponding frequency offset compensation. The frequency offset compensation formula (1) is as follows:

[0098]

[0099] In formula (1), v k (n) is the data corresponding to the kth channel after frequency offset compensation, x k (n) is the serial data of the corresponding k-th channel after inverse Fourier transform, k is the channel number, M is the number of sub-band channel divisions, D is the data extraction multiple, j is the imaginary unit, and n is the subscript of the M-point IFFT output data sequence.

[0100] Furthermore, in step S6, the loop counter is set to a value from 0 to M.

[0101] Embodiment 1

[0102] In this embodiment 1, a simulation experiment is used to illustrate the actual effect of a multi-phase filtering channelized processor FPGA implementation method in the present invention. The software simulation experiment is performed using MATLAB2023 software, and the hardware simulation experiment is performed under Vivado2020.2 software. The FPGA chip is selected as Vu13p. A channelizer (i.e., a digital channelized demodulator) with a sub-band channel number M of 512, a sub-band width of 750Hz, and a downsampling multiple D of 64 is taken as an example for detailed description.

[0103] Simulation content and result analysis:

[0104] A MATLAB simulation model and an FPGA engineering module were built for the algorithm theory and engineering implementation of the present invention. The FilterDesigner tool in MATLAB was used to design a prototype filter with an order of 8192 and a passband bandwidth of 375 Hz. The filter was divided into 16 groups to complete the multiphase components after 8 times interpolation. The sampling rate was 384 kHz and included two low symbol rates. The spectrum was as follows: Figure 6 The data shown in the figure is digitally channelized and the spectrum of the data with different symbol rates at a sampling rate of 6000 Hz after polyphase filtering extraction and channelization processing is shown in the figure. Figure 7 , Figure 8 As shown, the out-of-band suppression ratio is about 40dB.

[0105] Fig. 9 , Fig.10 The schematic diagrams show the quality recovery of data performance output by the post-stage demodulation module after the multi-phase digital channelization structure (i.e., the present invention) and the low-pass filtering extraction structure (i.e., the comparison structure) complete variable rate downsampling of data under noise-free conditions. Obviously, compared with the ordinary downsampling filtering structure, the performance of the multi-phase digital channelization structure of the present invention has no obvious difference; thus, it can be seen that after being processed by the multi-phase channelized FPGA architecture, the frequency band division and sampling rate conversion of the combined signal can be better completed.

[0106] After comprehensive implementation in Vivado2020.2, when the current-stage input sampling rate is 384kHz, the duty cycle is 1:191 for the combined data, and a 64-fold downsampling operation is performed, the resource occupancy of the present invention is as shown in Table 1. Because the optimized multi-phase convolution calculation structure is used, only 256 multipliers are used to complete the 64-fold downsampling 8192-order filtering of the real and imaginary data. Compared with the use of the multi-phase filtering theory algorithm divided into 512 multi-phase branches for calculation, the consumption is equal to the prototype filter order, that is, 8192 multiplier resources. The former can save a lot of FPGA resources, is suitable for variable sampling rate channelization operations of low-speed data, and has good practicality in engineering implementation; the specific implementation method of the overall FPGA hardware architecture is as follows: Figure 3 As shown, the present invention has good versatility and can adjust parameters and modify the architecture according to requirements to achieve corresponding functions.

[0107] Table 1 Resource occupancy table

[0108]

[0109] In a second aspect, an FPGA implementation system of a multiphase filter channelizer is provided, and the FPGA implementation method of the multiphase filter channelizer is applied, and the FPGA implementation system includes a data shaping module, a multiphase filter operation module, a parallel-to-serial conversion module, an inverse Fourier transform module, a frequency offset compensation module, and a parallel data output module;

[0110] Data shaping module: sets the N-order prototype filter coefficients of the channelizer, the number of sub-band channel divisions M, and the data extraction multiple D, and uses FIFO and counter to complete serial-to-parallel conversion and data shaping of the serial signal input to the channelizer to obtain I groups of parallel shaping data, where I = N / M;

[0111] Polyphase filtering operation module: the N-order prototype filter coefficients are evenly divided into I groups of branch filter coefficients, the I groups of branch filter coefficients are reversed and multiplied with the I groups of parallel shaping data to obtain convolution operation parallel data, and the same channel data in the convolution operation parallel data are summed and accumulated to obtain parallel data after polyphase filtering calculation;

[0112] A parallel-to-serial conversion module: using RAM to cache and reshape the parallel data after the polyphase filtering calculation and perform parallel-to-serial conversion to obtain a serial polyphase filtering data block;

[0113] Inverse Fourier transform module: sending the serial multiphase filter data block to the IFFT module to complete the inverse Fourier transform, and obtain M-point IFFT output data;

[0114] Frequency offset compensation module: performs frequency offset compensation on the M-point IFFT output data and then outputs serial data;

[0115] Parallel data output module: set a loop counter to count the serial data to obtain a loop counter value, select corresponding channel data according to the loop counter value and complete parallel data output.

[0116] In a third aspect, an electronic device includes a memory and a processor:

[0117] Memory: used for storing a computer program for implementing the FPGA implementation method of the polyphase filter channelizer;

[0118] Processor: used to implement the FPGA implementation method of the polyphase filter channelizer when executing the computer program.

[0119] In a fourth aspect, a computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the FPGA implementation method of the multi-phase filter channelizer is implemented; the computer-readable storage medium includes: a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store program codes.

[0120] The working principle of the present invention is:

[0121] In the present invention, necessary parameters of a digital channelizer are first set according to actual needs, such as N-order prototype filter coefficients, the number of sub-band channel divisions M and the data extraction multiple D. According to the convolution law of multi-phase theory, the large duty cycle serial data of the input channelizer is converted into a parallel shaped data group by using parallel-serial conversion and data shaping; the data is multiplied and accumulated with the multi-phase branch filter coefficients to complete the multi-phase filtering operation; subsequently, the parallel multi-phase filtering operation results are converted into serial multi-phase filtering data blocks using RAM, wherein the number of data units in each block is the same as the number of sub-band channel divisions M; the serial multi-phase filtering data blocks are subjected to M-point IFFT transformation and data is output; subsequently, a fixed phase adjustment coefficient group is combined with a counter to complete the frequency offset compensation of the IFFT calculation result (i.e., output data); finally, the corresponding channel data is selected according to the value of the cyclic counter from 0 to M-1 to complete the parallel data output.

Claims

1. A method for implementing a polyphase filter channelizer on FPGA, characterized in that: The following steps are involved: S1: Set the N-order prototype filter coefficients of the channelizer, the number of sub-band channel divisions M, and the data extraction multiple D, and use FIFO and counter to complete the serial-to-parallel conversion and data shaping of the serial signal input to the channelizer to obtain I groups of parallel shaping data, where I = N / M; S2: Evenly divide the N-order prototype filter coefficients in step S1 into I groups of branch filter coefficients, multiply the I groups of branch filter coefficients in reverse order with the I groups of parallel shaping data in step S1 to obtain convolution operation parallel data, and sum and accumulate the same channel data in the convolution operation parallel data to obtain parallel data after multi-phase filtering calculation; S3: using RAM to perform cache shaping and parallel-to-serial conversion on the parallel data after the multi-phase filtering calculation in step S2 to obtain a serial multi-phase filtering data block; S4: sending the serial polyphase filtering data block described in step S3 to an IFFT (Inverse Fast Fourier Transform) module to complete an inverse Fourier transform, and obtaining M-point IFFT output data; S5: Perform frequency offset compensation on the M-point IFFT output data in step S4 and then output serial data; S6: Setting a loop counter to count the serial data in step S5 to obtain a loop counter value, selecting corresponding channel data according to the loop counter value and completing parallel data output.

2. The FPGA implementation method of the polyphase filter channelizer as claimed in claim 1, characterized in that: Step S1 comprises the following steps: S1.1: Set the N-order prototype filter coefficients, the number of sub-band channel divisions M, and the data extraction multiple D of the channelizer, and use FIFO to divide the serial signal input to the channelizer into I groups of single-channel data, where I = N / M, and each group of single-channel data differs by M clock delays; S1.2: Set the value of the counter in step S1 to 0 to X, where X=M·(M / D-1). When the counter value is an integer multiple of D, assign values ​​to the second to M / D-th data according to the first data of each group of single-channel data. Similarly, I groups of parallel shaped data can be obtained, each of which contains M / D channels, and the serial signal completes the serial-to-parallel conversion.

3. The FPGA implementation method of the polyphase filter channelizer as claimed in claim 2, characterized in that: Step S2 comprises the following steps: S2.1: performing phase division on the N-order prototype filter coefficients in step S1.1 according to the number of sub-band channel divisions M, into I groups of branch filter coefficients, where I = N / M, and reversing the order of the I groups of branch filter coefficients; S2.2: For each data in the I group of parallel shaping data described in step S1.2, a counter with a value of 0 to M-1 is set, and the I group of branch filter coefficients after the reverse order described in step S2.1 is selected according to the principle of numerical correspondence for each group of branch filter coefficients, and each group of branch filter coefficients is sent to the multiplier together with the I group of parallel shaping data in step S1.2 to complete the corresponding multiplication operation to obtain the convolution operation parallel data; S2.3: Sum and accumulate the same channel data in the parallel data of the convolution operation in step S2.2 respectively to obtain parallel data after multi-phase filtering calculation.

4. The FPGA implementation method of the polyphase filter channelizer as claimed in claim 1, characterized in that: Step S3 includes the following steps: Set p RAMs with a depth of M, where p = M / D, and cache and reshape the parallel data after the multi-phase filtering calculation output in step S2. After the parallel data after the multi-phase filtering calculation, i.e., the p-way parallel reshaped data, in the corresponding channel of the RAM data is full, use an auxiliary counter to read the data in reverse order from the high address to the low address of the RAM, and finally convert the p-way parallel reshaped data into serial multi-phase filtering data blocks, each of which contains M data units.

5. The FPGA implementation method of the polyphase filter channelizer as claimed in claim 1, characterized in that: Step S5 comprises the following steps: S5.1: setting the real part and imaginary part of the phase adjustment coefficient group in the frequency offset compensation operation to a total of two two-dimensional arrays, wherein each two-dimensional array contains M / D data elements, and the number of bits of the M / D data elements is M / D·16; S5.2: Set a data block counter to complete the block counting of the M-point IFFT output data in step S4, set a compensation factor selection counter to complete the selection of the phase adjustment coefficient group data in step S5.1, send the M-point IFFT output data after block counting and the corresponding selected phase adjustment coefficient group data to the complex multiplier to complete the frequency offset compensation operation to obtain serial data. The frequency offset compensation formula is as follows: In formula (1), v k (n) is the data corresponding to the kth channel after frequency offset compensation, x k (n) is the serial data of the corresponding k-th channel after inverse Fourier transform, k is the channel number, M is the number of sub-band channel divisions, D is the data extraction multiple, j is the imaginary unit, and n is the subscript of the M-point IFFT output data sequence.

6. The FPGA implementation method of the polyphase filter channelizer as claimed in claim 1, characterized in that: In step S6, the loop counter is set to a value from 0 to M.

7. An FPGA implementation system of a multi-phase filter channelizer, using the FPGA implementation method of the multi-phase filter channelizer according to any one of claims 1 to 6, the FPGA implementation system comprising a data shaping module, a multi-phase filter operation module, a parallel-to-serial conversion module, an inverse Fourier transform module, a frequency offset compensation module, and a parallel data output module; Data shaping module: sets the N-order prototype filter coefficients of the channelizer, the number of sub-band channel divisions M, and the data extraction multiple D, and uses FIFO and counter to complete serial-to-parallel conversion and data shaping of the serial signal input to the channelizer to obtain I groups of parallel shaping data, where I = N / M; Polyphase filtering operation module: the N-order prototype filter coefficients are evenly divided into I groups of branch filter coefficients, the I groups of branch filter coefficients are reversed and multiplied with the I groups of parallel shaping data to obtain convolution operation parallel data, and the same channel data in the convolution operation parallel data are summed and accumulated to obtain parallel data after polyphase filtering calculation; A parallel-to-serial conversion module: using RAM to cache and reshape the parallel data after the polyphase filtering calculation and perform parallel-to-serial conversion to obtain a serial polyphase filtering data block; Inverse Fourier transform module: sending the serial multiphase filter data block to the IFFT module to complete the inverse Fourier transform, and obtain M-point IFFT output data; Frequency offset compensation module: performs frequency offset compensation on the M-point IFFT output data and then outputs serial data; Parallel data output module: set a loop counter to count the serial data to obtain a loop counter value, select corresponding channel data according to the loop counter value and complete parallel data output.

8. An electronic device, comprising a memory and a processor, characterized in that: Memory: used for storing a computer program for implementing the FPGA implementation method of the polyphase filter channelizer according to any one of claims 1 to 6; Processor: used to implement the FPGA implementation method of the polyphase filter channelizer according to any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the FPGA implementation method of the polyphase filter channelizer according to any one of claims 1 to 6.

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