Parallel error correction method based on FIR (Finite Impulse Response) parallel period time-varying filter

Abstract

The invention discloses a parallel error correction method based on an FIR (Finite Impulse Response) parallel period time-varying filter, which comprises the following steps that: a user can firstly select a sampling mode of a signal and then realize parallel error correction of an input signal through the FIR parallel period time-varying filter according to different sampling modes; in the error correction process, through normalization processing of filter coefficients and optimization multiplexing of an FIR operation structure, the operation speed is improved to the maximum extent, resources are saved, and meanwhile, high-precision and high-real-time correction of the frequency response mismatch error is met.

Description

Technical Field

[0001] The present invention belongs to the technical field of error correction, and more specifically, relates to a parallel error correction method based on a FIR parallel periodic time-varying filter. Background Art

[0002] The data acquisition system is a key module for realizing the digitization of analog signals. It has been widely used in the fields of communications, nuclear physics, deep space exploration, and measuring instruments. With the continuous advancement of technology, the signals in these fields are becoming more complex, with wider bandwidths and more obvious transient characteristics, which puts higher requirements on the performance of data acquisition systems. However, due to the limitations of existing integrated circuit processes, single-chip analog to digital converters (ADCs) are difficult to meet the various indicators of data acquisition systems, especially the sampling rate requirements.

[0003] Therefore, the acquisition system under the parallel architecture proposes a time-interleaved (TI) sampling architecture and a digital bandwidth interleaving (DBI) to achieve a sampling rate performance far exceeding that of a single-chip ADC, which has become the focus of current research.

[0004] However, in the actual acquisition system based on TI architecture, it is difficult to ensure that the parameters of the front-end circuits of each quantizer are completely consistent. Factors such as power dividers, circuit board layout and wiring, and mismatch of ADC internal parameters will lead to differences in the quantization signals of each sampling channel. These quantization differences will inevitably introduce errors when the final data is stitched together, which will appear as additional error spectra in the frequency domain. Fundamentally, these quantization differences are caused by the mismatch of frequency responses between sampling channels. In order to make the stitching result as close as possible to the ideal single ADC data acquisition system output, the frequency response mismatch error must be corrected.

[0005] Similar to the TI architecture, the actual acquisition system of the DBI architecture also faces the problem of inconsistent parameters between sub-band channels. Factors such as circuit layout, gain deviation, and characteristic differences of ADC sub-bands of different channels will lead to frequency response mismatch between sub-bands, resulting in phase inconsistency errors and amplitude distortion errors. These errors appear as additional noise and distortion in the frequency domain, affecting the accuracy of data after splicing. Especially under the requirements of high bandwidth and high sampling rate, the frequency overlap area between sub-bands has more stringent requirements for synchronization and matching. How to effectively correct the frequency response mismatch error has become a key technical challenge of the DBI architecture.

[0006] Among the existing error correction methods, patent CN110557122A uses multiple cascaded filter groups to correct the frequency response inconsistency error, but its resource consumption is large and it is difficult to apply to time-interleaved acquisition systems with more than 4 channels; at the same time, the implementation of IIR filters in FPGA cannot meet the real-time data processing requirements, which may lead to data accumulation problems during continuous sampling. Patent US7978104 uses frequency domain polynomials to approximate the frequency response of the sampling channel, but this method is only applicable to cases where the frequency response is relatively regular. Patent CN113114241B proposes a solution based on cascaded overlapping FFT, which can accurately correct the frequency response mismatch error under any number of channels and continuous data input. However, this method is first implemented serially, with low data throughput. Secondly, it processes data in the frequency domain, with high latency, which will greatly increase the dead time and reduce the waveform capture rate. At the same time, the frequency domain method will consume a lot of LUT resources in FPGA implementation. Finally, after IFFT, the method performs extraction, which consumes a lot of resources.

[0007] From the above analysis, it can be seen that there is currently a lack of a general error correction method that can effectively correct frequency response mismatch errors in parallel architecture acquisition systems while taking into account high throughput, low latency, low resource consumption, wide applicability and high real-time performance. Summary of the invention

[0008] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a parallel error correction method based on FIR parallel periodic time-varying filters, which realizes high-precision and high-real-time correction of frequency response mismatch errors based on the time domain FIR parallel filtering structure. The entire correction process relies entirely on hardware implementation, and maximizes the computing speed and saves resources.

[0009] To achieve the above-mentioned object of the invention, the present invention provides a parallel error correction method based on FIR parallel periodic time-varying filter, characterized in that it includes the following steps:

[0010] (1) Obtain normalized FIR filter coefficients;

[0011] (2) Power on the digital oscilloscope and then connect it to any input signal, such as a sine signal, a multi-tone signal, etc.

[0012] (3) The user selects an acquisition mode of the acquisition system in the digital oscilloscope, including: an interleaved sampling mode and a non-interleaved sampling mode; if the interleaved sampling mode is selected, proceed to step (4); otherwise, proceed to step (5);

[0013] (4) Implement parallel error correction of input signals through FIR parallel periodic time-varying filters in interleaved sampling mode;

[0014] (5) Parallel error correction of the input signal is achieved through FIR parallel periodic time-varying filters in non-interleaved sampling mode.

[0015] The object of the invention of the present invention is achieved in this way:

[0016] The present invention is based on a parallel error correction method of an FIR parallel periodic time-varying filter. The user can first select a sampling mode of a signal, and then implement parallel error correction of an input signal through an FIR parallel periodic time-varying filter according to different sampling modes. In the error correction process, the present invention normalizes the filter coefficients and optimizes and reuses the FIR operation structure to maximize the operation speed and save resources while meeting the requirements of high-precision and high-real-time correction of frequency response mismatch errors.

[0017] At the same time, the parallel error correction method based on the FIR parallel periodic time-varying filter of the present invention also has the following beneficial effects:

[0018] (1) The present invention proposes a general FIR parallel error correction architecture based on FPGA, which has high universality. It only needs to adjust the filter working mode and configuration parameters (such as interleaved / non-interleaved mode, normalized filter coefficients, etc.) according to the different requirements of the data acquisition system to achieve frequency response mismatch error correction under different acquisition architectures, thereby adapting to a variety of broadband data acquisition application scenarios.

[0019] (2) The present invention realizes efficient frequency response mismatch error correction based on FPGA, and has significant efficiency. Through the design of FIR parallel filtering module, the system realizes full parallel processing in hardware, avoiding the serial calculation bottleneck of time domain data. Compared with the serial method, the present invention significantly improves the operation speed and is very suitable for data acquisition scenarios with high real-time requirements.

[0020] (3) The hardware design of the present invention has good scalability and is applicable to a wide range of real-time data processing needs. The efficiency of time-domain filtering processing is improved by optimizing the associated structure of the shift register and the FIR filter group, parallelizing the time-domain filtering structure, and adjusting the point loss strategy. The coefficients are normalized and the DC bias is not amplified, which avoids the delay and pipeline interruption caused by the sampling signal averaging process, making the pipeline continuous and significantly improving the data throughput, so that parallel pipeline FIR can be realized. By adopting a multi-phase filter structure, half of the FIR resources are saved. The present invention provides a low-latency, high-throughput, high-stability, and resource-saving correction method. These design ideas can be used in data processing systems with other parallel filtering requirements, and provide reference and guidance for other high-performance data acquisition and error correction. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1It is a flow chart of a parallel error correction method based on FIR parallel periodic time-varying filter of the present invention;

[0022] Figure 2 It is a structural diagram of FIR parallel periodic time-varying filter in interleaved mode;

[0023] Figure 3 This is the structure diagram of the FIR parallel periodic time-varying filter in non-interleaved mode. DETAILED DESCRIPTION

[0024] The specific implementation of the present invention is described below in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when the detailed description of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.

[0025] Example

[0026] In this embodiment, if Figure 1 As shown, the present invention provides a parallel error correction method based on FIR parallel periodic time-varying filter, comprising the following steps:

[0027] (1) Obtain normalized FIR filter coefficients;

[0028] (1.1) Normalized filter coefficient acquisition in interleaved mode

[0029] (1.1.1) Use the point frequency method to perform equal-interval frequency sweeps on the K acquisition channels, and the sweep interval is [f0,f N-1 ], and obtain the frequency response H of the acquisition channel k [n],n=0,1,...,N-1;k=0,1,...,K-1;

[0030] (1.1.2) Calculate the ideal correction frequency response and use the fitting algorithm to obtain the frequency response H of the acquisition channel. k [n] curve fitting to obtain T k [n], to obtain the ideal corrected frequency response of the acquisition channel

[0031] (1.1.3), let the value of C[n] approaching 0 be λ, and normalize C[n] to get C τ [n]=C[n]-λ,n=0,1,...,N-1;

[0032] (1.1.4) The ideal corrected frequency response C after normalization τ [n] Perform IFFT operation to obtain the time domain filter coefficient c τ[n], and the filter coefficients are truncated to obtain the final FIR filter coefficients, assuming that the truncation length is 256, recorded as coe[n], n = 0, 1, ..., 255;

[0033] (1.2) Normalized filter coefficient acquisition in non-interlaced mode

[0034] (1.2.1) Use the point frequency method to perform equal-interval frequency sweeps on the K acquisition channels, and the sweep interval is [f0,f N-1 ], and obtain the frequency response H of the acquisition channel k [n],n=0,1,...,N-1;k=0,1,...,K-1;

[0035] (1.2.2) Calculate the ideal correction frequency response and use the fitting algorithm to obtain the frequency response H of the acquisition channel. k [n] curve fitting to obtain T k [n];

[0036] (1.2.3), record T k [n] tends to be close to 0 when the value is λ k , for T k [n] is normalized to get C τk [n] = T k [n]-λ k ,n=0,1,...,N-1;k=0,1,...,K-1;

[0037] (1.2.4) The ideal corrected frequency response C after normalization τk [n] Perform IFFT operation to obtain the time domain filter coefficient c of each acquisition channel τk [n], and the filter coefficients are truncated to obtain the final FIR filter coefficients, assuming that the truncation length is 256, recorded as coe k [n],n=0,1,...,255;k=0,1,...,K-1;

[0038] (2) Power on the digital oscilloscope and then connect it to any input signal, such as a sine signal, a multi-tone signal, etc.

[0039] (3) The user selects an acquisition mode of the acquisition system in the digital oscilloscope, including: an interleaved sampling mode and a non-interleaved sampling mode; if the interleaved sampling mode is selected, proceed to step (4); otherwise, proceed to step (5);

[0040] (4) Figure 2 As shown, in the interleaved sampling mode, the parallel error correction of the input signal is realized by the FIR parallel periodic time-varying filter;

[0041] (4.1) The FPGA in the digital oscilloscope configures the filter coefficients of the FIR parallel periodic time-varying filter in the interleaved sampling mode, and completes the initialization configuration of the FIR parallel periodic time-varying filter;

[0042] (4.2) The acquisition system in the digital oscilloscope acquires the input signal to obtain 8 parallel sampling data, and then inputs the 8 parallel sampling data into the FIR parallel periodic time-varying filter;

[0043] (4.3) In the FIR parallel periodic time-varying filter, let the storage depth of the shift register be N (N is greater than 263);

[0044] Starting from time t0, 8 parallel sampling data are sent to the FIR parallel periodic time-varying filter. At this time, the shift register is first right-shifted by 8 data bits, and then the 1 to 8 data sent at time t0 are sequentially loaded into the lower 8 data bits of the shift register, and the data bits above the upper 8 bits are filled with 0, and then the effective flag of the shift register is pulled high, and the output vector with a length of 263 is output;

[0045] At time t1, the data stored in the shift register is shifted right by 8 data bits, and then the 1-8 data sent at time t1 are sequentially loaded into the lower 8 data bits of the shift register, and the lower 16-bit data is formed with the 8 data bits loaded at time t0. The data bits above the upper 16 bits are filled with 0, and then the effective flag of the shift register is pulled high, and the output vector with a length of 263 is output;

[0046] Similarly, the same applies to subsequent moments;

[0047] (4.4) The output vector of the shift register at each moment is sent to 8 parallel FIR filter modules according to the corresponding relationship; wherein, the 0th to 255th elements x[0] to x

[255] in the output vector are input to the 0th FIR filter module FIR0, the 1st to 256th elements x[1] to x

[256] are input to the 1st FIR filter module FIR1, the 2nd to 257th elements x[2] to x

[257] are input to the 2nd FIR filter module FIR2, and so on, the 7th to 262nd elements x[7] to x

[262] are input to the 7th FIR filter module FIR7;

[0048] (4.5) Filtering the time domain data through each parallel FIR filter module;

[0049] (4.5.1) Assume that the filter coefficients of each FIR filter module are h[0] to h

[255] ;

[0050] (4.5.2) In each FIR filter module, the input data and the filter coefficients are sent to the multiplier in a corresponding relationship in reverse order. The outputs of each multiplier are then summed through an 8-stage adder. Then, it is detected whether the output data of the last stage adder overflows. That is, when the output data becomes negative, the output data is assigned a value of 0 as the output of the FIR filter module; when the output data is positive and exceeds the product of the maximum resolution and the coefficient magnification, the output data is assigned a value of the maximum ADC resolution as the output of the FIR filter module; otherwise, the output data is reduced by the coefficient magnification as the output of the FIR filter module;

[0051] Assume that the ADC resolution is 12 bits and the coefficient magnification is 2 16 , then when the output data is positive and exceeds the product of the maximum resolution and the coefficient magnification (2 12 -1)*2 16 When the output data is assigned the maximum value of ADC resolution 2 12 -1, as the output of the FIR filter module; otherwise, the output data is reduced by a factor of 2 16 As the output of the FIR filter module;

[0052] (4.5.3) The outputs of the eight FIR filter modules are concatenated in order, and then the first 128 points of the concatenated vector are discarded to obtain the final correction output.

[0053] (5) Figure 3 As shown, parallel error correction of the input signal is implemented by a FIR parallel periodic time-varying filter in a non-interleaved sampling mode;

[0054] (5.1) The FPGA in the digital oscilloscope configures the filter coefficients of the FIR parallel periodic time-varying filter in the non-interleaved sampling mode, and completes the initialization configuration of the FIR periodic time-varying filter;

[0055] (5.2) The acquisition system in the digital oscilloscope acquires input signals, obtains two sets of non-interleaved 4-way parallel sampling data of two acquisition channels ch1 and ch2, and then inputs the 8-way parallel sampling data into the FIR parallel periodic time-varying filter;

[0056] (5.3) In the FIR parallel periodic time-varying filter, assume that the storage depths of the two shift registers SR1 and SR2 are both M (M is greater than 259);

[0057] Starting from time t0, two groups of 4-channel parallel sampling data are fed into the FIR parallel periodic time-varying filter. At this time, both shift registers are first right-shifted by 4 data bits, and then the 1-4-channel sampling data collected by channel ch1 fed at time t0 are loaded into the lower 4 data bits of shift register SR1, and the data bits above the upper 4 bits are filled with 0, and then the valid flag of shift register SR1 is pulled high, and an output vector with a length of 259 is output; at the same time, the 1-4-channel sampling data collected by channel ch2 fed at time t0 are loaded into the lower 4 data bits of shift register SR2, and the data bits above the upper 4 bits are filled with 0, and then the valid flag of shift register SR2 is pulled high, and an output vector with a length of 259 is output;

[0058] At time t1, the data stored in shift registers SR1 and SR2 are right-shifted by 4 data bits, and then the 1-4 sampling data collected by channel ch1 sent at time t1 are loaded into the lower 4 data bits of shift register SR1, and together with the 4 data bits loaded at time t0, they form lower 8-bit data, and the data bits above the upper 8 bits are filled with 0, and then the valid flag of shift register SR1 is pulled high, and an output vector with a length of 259 is output; at the same time, the 1-4 sampling data collected by channel ch2 sent at time t1 are loaded into the lower 4 data bits of shift register SR2, and together with the 4 data bits loaded at time t0, they form lower 8-bit data, and the data bits above the upper 8 bits are filled with 0, and then the valid flag of shift register SR2 is pulled high, and an output vector with a length of 259 is output;

[0059] Similarly, the subsequent moments are deduced in the same way;

[0060] (5.4) The output vectors of the two shift registers at each moment are sent to four parallel FIR filter modules according to the corresponding relationship; wherein the corresponding relationship of each shift register is as follows: the 0th to 255th elements x[0]~x

[255] in the output vector of shift register SR1 are input to the 0th FIR filter module Filter0, the 1st to 256th elements x[1]~x

[256] are input to the 1st FIR filter module Filter2, the 2nd to 257th elements x[2]~x

[257] are input to the 2nd FIR filter module Filter4, and the 3rd to 258th elements x[0]~x

[255] are input to the 0th FIR filter module Filter0. [3]~x

[258] are input to the third FIR filter module Filter6; the 0th to 255th elements x[0]~x

[255] in the output vector of the shift register SR2 are input to the 0th FIR filter module Filter1, the 1st to 256th elements x[1]~x

[256] are input to the 1st FIR filter module Filter3, the 2nd to 257th elements x[2]~x

[257] are input to the 2nd FIR filter module Filter5, and the 3rd to 258th elements x[3]~x

[258] are input to the 3rd FIR filter module Filter7;

[0061] (5.5) Filter the time domain data through two sets of parallel FIR filter modules;

[0062] (5.5.1) Assume that each of the two parallel FIR filter modules contains 4 parallel FIR filter modules, and the filter coefficient of each FIR filter module is h[0] to h

[255] ;

[0063] (5.5.2) In each FIR filter module, the input data and the filter coefficient are sent to the multiplier in a corresponding relationship in reverse order. The outputs of each multiplier are then summed through an 8-stage adder. Then, it is detected whether the output data of the last stage adder overflows. That is, when the output data becomes negative, the output data is assigned a value of 0 as the output of the FIR filter module; when the output data is positive and exceeds the product of the maximum resolution and the coefficient magnification, the output data is assigned a value of the maximum ADC resolution as the output of the FIR filter module; otherwise, the output data is reduced by the coefficient magnification as the output of the FIR filter module;

[0064] Assume that the ADC resolution is 12 bits and the coefficient magnification is 2 16 , then when the output data is positive and exceeds the product of the maximum resolution and the coefficient magnification (2 12 -1)*2 16 When the output data is assigned the maximum value of ADC resolution 2 12 -1, as the output of the FIR filter module; otherwise, the output data is reduced by a factor of 2 16As the output of the FIR filter module;

[0065] (5.5.3) The outputs of the four FIR filter modules in each group are concatenated in sequence, and then the first 128 points of the concatenated vector are discarded, thereby obtaining the corrected output of the FIR parallel periodic time-varying filter in channels ch1 and ch2.

[0066] Although the above describes the illustrative specific embodiments of the present invention to facilitate those skilled in the art to understand the present invention, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations using the concept of the present invention are protected.

Claims

1. A parallel error correction method based on FIR parallel periodic time-varying filter, characterized in that: The following steps are involved: (1) Obtaining the filter coefficients of the normalized FIR parallel periodic time-varying filter; (2) Power on the digital oscilloscope and then connect it to any input signal, such as a sine signal, a multi-tone signal, etc. (3) The user selects an acquisition mode of the acquisition system in the digital oscilloscope, including: an interleaved sampling mode and a non-interleaved sampling mode; if the interleaved sampling mode is selected, proceed to step (4); otherwise, proceed to step (5); (4) Implement parallel error correction of input signals through FIR parallel periodic time-varying filters in interleaved sampling mode; (5) Parallel error correction of the input signal is achieved through FIR parallel periodic time-varying filters in non-interleaved sampling mode.

2. The parallel error correction method based on FIR parallel periodic time-varying filter according to claim 1 is characterized in that: The method for implementing parallel error correction of input signals by using FIR parallel periodic time-varying filters in the interleaved sampling mode is: (2.1) The FPGA in the digital oscilloscope configures the filter coefficients of the FIR parallel periodic time-varying filter in the interleaved sampling mode, and completes the initialization configuration of the FIR parallel periodic time-varying filter; (2.2) The acquisition system in the digital oscilloscope acquires the input signal to obtain 8 parallel sampling data, and then inputs the 8 parallel sampling data into the FIR parallel periodic time-varying filter; (2.3) In the FIR parallel periodic time-varying filter, the storage depth of the shift register is set to 263; Starting from time t0, 8 parallel sampling data are sent to the FIR parallel periodic time-varying filter. At this time, the shift register is first right-shifted by 8 data bits, and then the 1 to 8 data sent at time t0 are sequentially loaded into the lower 8 data bits of the shift register, and the data bits above the upper 8 bits are filled with 0, and then the effective flag of the shift register is pulled high, and the output vector with a length of 263 is output; At time t1, the data stored in the shift register is shifted right by 8 data bits, and then the 1-8 data sent at time t1 are sequentially loaded into the lower 8 data bits of the shift register, and the lower 16-bit data is formed with the 8 data bits loaded at time t0. The data bits above the upper 16 bits are filled with 0, and then the effective flag of the shift register is pulled high, and the output vector with a length of 263 is output; Similarly, the same applies to subsequent moments; (2.4) The output vector of the shift register at each moment is sent to 8 parallel FIR filter modules according to the corresponding relationship; wherein, the 0th to 255th elements x[0] to x[255] in the output vector are input to the 0th FIR filter module FIR0, the 1st to 256th elements x[1] to x[256] are input to the 1st FIR filter module FIR1, the 2nd to 257th elements x[2] to x[257] are input to the 2nd FIR filter module FIR2, and so on, the 7th to 262nd elements x[7] to x[262] are input to the 7th FIR filter module FIR7; (2.5) Filtering the time domain data through each parallel FIR filter module; (2.5.1) Assume that the filter coefficients of each FIR filter module are h[0] to h[255]; (2.5.2) In each FIR filter module, the input data and the filter coefficient are sent to the multiplier in a corresponding relationship in reverse order. The outputs of each multiplier are then summed through an 8-stage adder. Then, it is detected whether the output data of the last stage adder overflows. That is, when the output data becomes negative, the output data is assigned a value of 0 as the output of the FIR filter module; when the output data is positive and exceeds the product of the maximum resolution and the coefficient magnification, the output data is assigned a value of the maximum ADC resolution as the output of the FIR filter module; otherwise, the output data is reduced by the coefficient magnification as the output of the FIR filter module; (2.5.3) The outputs of the eight FIR filter modules are concatenated in order, and then the first 128 points of the concatenated vector are discarded to obtain the final correction output.

3. The parallel error correction method based on FIR parallel periodic time-varying filter according to claim 1, characterized in that: The method for implementing parallel error correction of input signals by using FIR parallel periodic time-varying filters in the non-interleaved sampling mode is as follows: (3.1) The FPGA in the digital oscilloscope configures the filter coefficients of the FIR parallel periodic time-varying filter in the non-interleaved sampling mode, and completes the initialization configuration of the FIR periodic time-varying filter; (3.2) The acquisition system in the digital oscilloscope acquires input signals, obtains two sets of non-interleaved 4-way parallel sampling data of two acquisition channels ch1 and ch2, and then inputs the 8-way parallel sampling data into the FIR parallel periodic time-varying filter; (3.3) In the FIR parallel periodic time-varying filter, assume that the storage depths of the two shift registers SR1 and SR2 are both 259; Starting from time t0, two groups of 4-channel parallel sampling data are fed into the FIR parallel periodic time-varying filter. At this time, both shift registers are first right-shifted by 4 data bits, and then the 1-4-channel sampling data collected by channel ch1 fed at time t0 are loaded into the lower 4 data bits of shift register SR1, and the data bits above the upper 4 bits are filled with 0, and then the valid flag of shift register SR1 is pulled high, and an output vector with a length of 259 is output; at the same time, the 1-4-channel sampling data collected by channel ch2 fed at time t0 are loaded into the lower 4 data bits of shift register SR2, and the data bits above the upper 4 bits are filled with 0, and then the valid flag of shift register SR2 is pulled high, and an output vector with a length of 259 is output; At time t1, the data stored in shift registers SR1 and SR2 are right-shifted by 4 data bits, and then the 1-4 sampling data collected by channel ch1 sent at time t1 are loaded into the lower 4 data bits of shift register SR1, and together with the 4 data bits loaded at time t0, they form lower 8-bit data, and the data bits above the upper 8 bits are filled with 0, and then the valid flag of shift register SR1 is pulled high, and an output vector with a length of 259 is output; at the same time, the 1-4 sampling data collected by channel ch2 sent at time t1 are loaded into the lower 4 data bits of shift register SR2, and together with the 4 data bits loaded at time t0, they form lower 8-bit data, and the data bits above the upper 8 bits are filled with 0, and then the valid flag of shift register SR2 is pulled high, and an output vector with a length of 259 is output; Similarly, the subsequent moments are deduced in the same way; (3.4) The output vectors of the two shift registers at each moment are sent to four parallel FIR filter modules according to the corresponding relationship; wherein the corresponding relationship of each shift register is as follows: the 0th to 255th elements x[0] to x[255] in the output vector are input to the 0th FIR filter module FIR0, the 1st to 256th elements x[1] to x[256] are input to the 1st FIR filter module FIR1, the 2nd to 257th elements x[2] to x[257] are input to the 2nd FIR filter module FIR2, and the 3rd to 258th elements x[3] to x[258] are input to the 3rd FIR filter module FIR3; (3.5) Filter the time domain data through two sets of parallel FIR filter modules; (3.5.1) Assume that each of the two parallel FIR filter modules contains 4 parallel FIR filter modules, and the filter coefficient of each FIR filter module is h[0] to h[255]; (3.5.2) In each FIR filter module, the input data and the filter coefficients are sent to the multiplier in a corresponding relationship in reverse order. The outputs of each multiplier are then summed through an 8-stage adder. Then, it is detected whether the output data of the last stage adder overflows. That is, when the output data becomes negative, the output data is assigned a value of 0 as the output of the FIR filter module; when the output data is positive and exceeds the product of the maximum resolution and the coefficient magnification, the output data is assigned a value of the maximum ADC resolution as the output of the FIR filter module; Otherwise, the output data is reduced by the factor magnification as the output of the FIR filter module; (3.5.3) The outputs of the four FIR filter modules in each group are concatenated in sequence, and then the first 128 points of the concatenated vector are discarded, thereby obtaining the corrected output of the FIR parallel periodic time-varying filter in channels ch1 and ch2.

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