A circuit device of a digital filter

Abstract

The present application provides a digital filter circuit device, which includes at least one storage circuit, at least one multiply-accumulate circuit, at least one addition circuit, a first data selection circuit, a second data selection circuit, and a third data selection circuit; the first data selection circuit inputs discrete digital signals; the storage circuit stores discrete digital signals and filter coefficients; the multiply-accumulate circuit performs multiplication and addition operations on the discrete digital signals and the filter coefficients according to a preset correspondence relationship, determines the multiply-accumulate result and inputs it to the second data selection circuit; the second data selection circuit and the third data selection circuit select corresponding data paths according to the configuration mode and perform input and output, and the addition circuit is used to add the output signal of the second data selection circuit and the output signal of the third data selection circuit to output the filtering result corresponding to the configuration mode. Through the present application, different filter functions can be realized, and the flexibility of the application of the digital filter can be improved.

Description

Technical Field

[0001] This application belongs to the technical field of digital signal processing, and particularly relates to a circuit device for a digital filter. Background Art

[0002] Since the 21st century, the information and communication industry has entered a new stage of development. Signal processing technology has become an important part of the communication field, and digital filtering technology, as an indispensable key technology among them, has been widely studied. A digital filter is a device that applies digital filtering technology. It processes signals through mathematical operations to attenuate or amplify them, and is mainly applied to the processing of digital signals. According to the characteristics of the impulse response of a digital filter in the time domain, it can be divided into two categories, namely, the Finite Impulse Response (FIR) filter and the Infinite Impulse Response (IIR) filter.

[0003] The FIR digital filter is a basic filter element in the field of digital signal processing. Its characteristic is that after inputting a digital signal with an arbitrary amplitude-frequency characteristic, it can ensure that the phase-frequency characteristic of the output digital signal still maintains a strict linear relationship. The FIR digital filter is a filter with strong stability, no feedback structure and easy hardware implementation. At the same time, it satisfies coefficient symmetry, and the filtered signal is not prone to phase distortion. Therefore, it has been widely used in the fields of information transmission and digital image processing. However, the filtering process of the FIR digital filter requires a long operation time, and only when the order of the FIR digital filter reaches several times to more than a dozen times that of the IIR digital filter, its amplitude response characteristic can be comparable to that of the IIR digital filter.

[0004] The IIR digital filter is characterized in that the impulse response of the system is infinite. Its output depends not only on the current and past signal input values, but also on the past signal output values. According to the mathematical expression of the IIR digital filter, it can be known that the IIR digital filter has a feedback structure, and the filtered signal will have the problem of phase distortion. However, the IIR digital filter has a high filtering efficiency and can achieve a similar frequency response effect with a smaller order compared to the FIR digital filter. The IIR digital filter is characterized by good amplitude-frequency characteristics, but the output signal is not strictly linear. Therefore, the IIR digital filter is suitable for occasions where strict requirements for signal phase are not required, such as voice calls, low-end video signal processing and other fields.

[0005] Therefore, it is extremely important to provide a circuit device that can simultaneously satisfy the functions of the FIR digital filter and the IIR digital filter to meet the development of digital filters in different application scenarios. Summary of the Invention

[0006] The present application discloses a circuit device for a digital filter, which can configure different filter types and select the data path corresponding to the filter to implement the corresponding filter function and improve the flexibility of the application of the digital filter.

[0007] Other objects and advantages of the present application can be further understood from the technical features disclosed in the present application.

[0008] To achieve one or part or all of the above objects or other objects, the present application provides a digital filter circuit device, which includes at least one storage circuit, at least one multiply-accumulate circuit, at least one addition circuit, a first data selection circuit, a second data selection circuit, and a third data selection circuit; the first data selection circuit is connected to the storage circuit and is used for inputting discrete digital signals; the storage circuit is used for storing the discrete digital signals and filter coefficients; the multiply-accumulate circuit is connected between the storage circuit and the second data selection circuit, and the multiply-accumulate circuit is used for multiplying and adding the discrete digital signals and the filter coefficients according to a preset corresponding relationship, determining the multiply-accumulate result and inputting it into the second data selection circuit;

[0009] The addition circuit is respectively connected to the second data selection circuit and the third data selection circuit. The second data selection circuit and the third data selection circuit are used for selecting the corresponding data path according to the configuration mode and performing input and output. The addition circuit is used for adding the output signal of the second data selection circuit and the output signal of the third data selection circuit and outputting the filtering result corresponding to the configuration mode.

[0010] In one implementation, each of the three data selection circuits includes an A terminal and a B terminal for inputting signals and a Z terminal for outputting signals. When the configuration mode is the FIR mode, each of the three data selection circuits selects the A terminal signal;

[0011] The signal input to the A terminal of the first data selection circuit is a discrete digital signal, the signal input to the A terminal of the second data selection circuit is the multiply-accumulate result, and the signal input to the A terminal of the third data selection circuit is 0.

[0012] In one implementation, the expression of the filtering result in the FIR mode is:

[0013] ;

[0014] where x(n - i) is the discrete digital signal sequence of the sampled input, h(i) is the FIR filter coefficient, y(n) is the filter output signal sequence, L is the filter order, MUX2 Z is the output signal of the Z terminal of the second data selection circuit, MUX3Z The output signal of the Z terminal of the third data selection circuit.

[0015] In one implementation, the three data selection circuits each include an A terminal and a B terminal for input signals, and a Z terminal for output signals. When the configuration mode is the IIR mode, the circuit device is composed of a first circuit device and a second circuit device. For the three data selection circuits of the first circuit device, the A terminal signals are selected, and for the three data selection circuits of the second circuit device, the B terminal signals are selected.

[0016] In one implementation, the filtering result of the first circuit device serves as the input signal of the B terminal of the third data selection circuit of the second circuit device, and the filtering result of the second circuit device serves as the input signal of the B terminal of the first data selection circuit of the second circuit device.

[0017] In one implementation, the first circuit device loads first filter coefficients, and the second circuit device loads second filter coefficients. The number of the second filter coefficients is one less than that of the first filter coefficients.

[0018] In one implementation, the signal value of the B terminal of the second data selection circuit of the second circuit device is the opposite of the signal value of the A terminal of the second data selection circuit of the second circuit device. The expression of the filtering result in the IIR mode is:

[0019] ;

[0020] where x(n) is the discrete digital signal sequence of the sampled input, y(n) is the filter output signal sequence, a(i) is the filter coefficient related to the input signal sequence, b(i) is the filter coefficient related to the filtering result, L is the filter order, y nume(n) is the filtering result of the first circuit device, and DENO MUX2B is the signal value of the B terminal of the second data selection circuit of the second circuit device.

[0021] In one implementation, the circuit device switches different configuration modes through registers to achieve different filtering effects; in different configuration modes, the corresponding number of storage circuits, multiply-accumulate circuits, and addition circuits are set according to the filter order corresponding to the configuration mode.

[0022] In one implementation, the storage circuit includes a signal storage circuit for storing the discrete digital signal and a coefficient storage circuit for storing the filter coefficients.

[0023] In one implementation, the multiply-accumulate circuit includes a multiplier and an adder. The multiplier is connected to the signal storage circuit and the coefficient storage circuit. The multiplier performs a multiplication operation on the discrete digital signal and the filter coefficient according to a preset correspondence relationship to obtain a multiplication result. The adder adds the multiplication results to obtain a multiply-accumulate result.

[0024] The above digital filter circuit device can, by switching different configuration modes, select and enable the data path of the corresponding filter, load the corresponding filter coefficients, and can switch different filter types to implement the corresponding filtering functions, thereby meeting different application scenarios and enhancing the flexibility of digital filter applications.

[0025] To make the above and other purposes, features, and advantages of the present application more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes a detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] To more clearly illustrate the technical solutions in the specific embodiments of the present application, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the following described drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0027] Figure 1 It is a schematic structural diagram of a digital filter circuit device provided by the present application.

[0028] Figure 2 It is a schematic circuit diagram of a digital filter provided by the present application.

[0029] Figure 3 It is a schematic diagram of the data path of a FIR digital filter circuit device provided by the present application.

[0030] Figure 4 It is a schematic diagram of the data path of an IIR digital filter circuit device provided by the present application.

[0031] Figure 5 It is a schematic diagram of the calculation of a 12th-order FIR digital filter provided by the present application diagram.

[0032] Figure 6 It is a schematic diagram of the calculation of a 12th-order FIR digital filter provided by the present application diagram.

[0033] Figure 7 It is a schematic diagram of the calculation of a 12th-order IIR digital filter provided by the present application diagram.

[0034] Figure 8 Calculation of a 12th-order IIR digital filter provided for this application Schematic diagram. Specific implementation manner

[0035] Regarding the foregoing and other technical contents, features and effects of this application, they will be clearly presented in the following detailed description of a preferred embodiment in conjunction with the reference drawings. Terms such as "first" and "second" in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances, which is only a way of distinguishing objects with the same attributes when describing the embodiments of this application.

[0036] A digital filter is a component used to process digital signals. It attenuates interference signals by performing multiplication and accumulation operations on the input digital signals, and it filters the signals by changing the frequency characteristics of the signals. According to the time-domain characteristics of the impulse response of the digital filter, the digital filter can be divided into a finite impulse response filter (FIR) and an infinite impulse response filter (IIR). The FIR digital filter is a filter with strong stability, no feedback structure and easy hardware implementation. At the same time, it satisfies coefficient symmetry, and the filtered signal is not prone to phase distortion, but the operation time is relatively long and the amplitude response characteristic is not as good as that of the IIR digital filter. The characteristic of the IIR digital filter is that the impulse response of the system is infinite. Its output depends not only on the current and past signal input values, but also on the past signal output values. Therefore, there is a feedback loop in its circuit structure, and the filtered signal will have a problem of phase distortion. However, the IIR digital filter has high filtering efficiency and good amplitude-frequency characteristics. According to the above characteristics, the FIR digital filter is suitable for occasions with high requirements for filtering accuracy such as the information transmission field and the digital image processing field, and the IIR digital filter is suitable for occasions with low requirements for signal phase such as voice calls and low-end video signal processing.

[0037] To enhance the versatility of the filter application scenario, this application proposes a digital filter circuit device, as Figure 1As shown in the figure, the circuit device includes at least one storage circuit, at least one multiply-accumulate circuit, at least one addition circuit, a first data selection circuit, a second data selection circuit, and a third data selection circuit; the first data selection circuit is connected to the storage circuit and is used for inputting discrete digital signals; the storage circuit is used for storing discrete digital signals and filter coefficients; the multiply-accumulate circuit is connected between the storage circuit and the second data selection circuit, and the multiply-accumulate circuit is used for multiplying and adding the discrete digital signals and the filter coefficients according to a preset corresponding relationship, determining the multiply-accumulate result and inputting it into the second data selection circuit; the addition circuit is respectively connected to the second data selection circuit and the third data selection circuit, and the second data selection circuit and the third data selection circuit are used for selecting and enabling corresponding data paths according to the configuration mode for input and output, and the addition circuit is used for adding the output signal of the second data selection circuit and the output signal of the third data selection circuit to output the filtering result corresponding to the configuration mode.

[0038] The circuit device is a circuit device that can simultaneously satisfy the functions of FIR digital filters and IIR digital filters. According to different application scenarios, different filter types can be switched. The user configures the type of digital filter (FIR or IIR) through a register and loads the corresponding filter coefficients. According to the filter type configured by the user, the circuit device selects and enables the data path of the corresponding filter to implement the function of the corresponding filter. When the user configures the circuit device as an FIR digital filter, the circuit device selects and enables a specific data path, and the discrete digital signal enters the circuit device through the input end, and the filtering result is output at the output end to achieve the filtering effect of the FIR digital filter; when the user configures the circuit device as an IIR digital filter, two circuit devices of the present application are connected according to a specific data path, the discrete digital signal is input in the first circuit device, and the filtering result is output in the second circuit device to achieve the filtering effect of the IIR digital filter.

[0039] The present application will be described in detail below with reference to the accompanying drawings.

[0040] Figure 2 It is a circuit schematic diagram of a digital filter provided by the present application. The circuit device is composed of several storage circuits, several multiply-accumulate circuits, several adder circuits, and three data selection circuits. Hereinafter, the data selection circuit will be simply referred to as the MUX circuit (Multiplexer, data selector), the first data selection circuit will be simply referred to as MUX1, the second data selection circuit will be simply referred to as MUX2, and the third data selection circuit will be simply referred to as MUX3.

[0041] Among them, the storage circuit is a digital circuit that can store data. The storage circuit includes a signal storage circuit and a coefficient storage circuit. The signal storage circuit is responsible for storing the input discrete digital signal Z -1, the coefficient storage circuit is responsible for storing the filter coefficient coeff, and the storage circuit includes but is not limited to single-port and dual-port RAM, FIFO, and shift register.

[0042] The multiply-accumulate circuit includes a multiplier and an adder. The multiplier is an electronic device circuit that performs the multiplication of two independent digital signals and is composed of a basic adder circuit; the adder is a digital circuit that can perform digital addition to produce the sum of numbers. The multiply-accumulate circuit is responsible for performing multiply-accumulate operations on discrete digital signals and filter coefficients according to a specific correspondence. The multiply-accumulate circuit includes but is not limited to serial multiply-accumulate units, fully parallel multiply-accumulate units, and other forms of multiply-accumulate unit structures.

[0043] The MUX circuit is a digital logic circuit that selects one of multiple input signals and outputs it. The MUX circuit is responsible for gating a specific data path. The A and B terminals are input signals, and the Z terminal is the output signal. According to the selection signal value SEL, the MUX circuit selects and outputs the A-terminal signal or the B-terminal signal. The A-terminal signal of MUX1 is the discrete digital signal, and the B-terminal signal of MUX1 is the filtering result of the circuit device; the A-terminal signal of MUX2 is the operation result of the multiply-accumulate unit, and the B-terminal signal of MUX2 is the negative result of the A-terminal signal; the A-terminal signal of MUX3 is 0, and the B-terminal signal of MUX3 can be connected to other signals.

[0044] In some embodiments, when the configuration mode is the FIR mode, all three data selection circuits select the A-terminal signal to achieve the filtering effect of the FIR digital filter. Specifically, the mathematical expression of the FIR digital filter is:

[0045] (Expression 1);

[0046] where x(n - i) is the discrete digital signal sequence of the sampled input, h(i) is the FIR filter coefficient, y(n) is the filter output signal sequence, is the filter order (length). It can be seen from Expression 1 that the FIR filter has no feedback structure, and the current filter result does not need to participate in subsequent filtering operations. The filtering result is only related to the filter coefficient and the input signal value.

[0047] When the user configures the circuit device as an FIR digital filter through the register, the data path of the circuit device is as Figure 3 shown. MUX1, MUX2, and MUX3 all select the A-terminal signal, load the FIR filter coefficient h(i) into the coefficient storage circuit, and load the sampled input signal sequence into the signal storage circuit. After the circuit device runs, according to a specific correspondence, perform a multiplication operation on h(i) and x(n - i), and then perform an addition operation on the product. The multiply-accumulate result is , which is the signal at the A terminal of MUX2. As can be seen from the circuit device structure diagram of the present application, the filtering result y(n) is obtained by adding the signals at the Z terminals of MUX2. In the FIR filter, both MUX2 and MUX3 select the signal at the A terminal, and the signal value at the Z terminal of MUX2 can be obtained as , the signal value at the Z terminal of MUX3 is 0. Therefore, the expression of the filtering result y(n) is:

[0048]

[0049] (Expression 2);

[0050] It can be seen that Expression 1 is consistent with Expression 2. Therefore, Figure 3 the circuit device shown can implement the function of the FIR digital filter.

[0051] In some embodiments, when the configuration mode is the IIR mode, the circuit device is composed of a first circuit device and a second circuit device. All three data selection circuits of the first circuit device select the signal at the A terminal, and all three data selection circuits of the second circuit device select the signal at the B terminal to achieve the filtering effect of the IIR digital filter. Specifically, the implementation form of the IIR digital filter is:

[0052] (Expression 3);

[0053] Among them, x(n) is the sampled input signal sequence, y(n) is the filter output signal sequence, a(i) is the filter coefficient related to the input signal sequence, b(i) is the filter coefficient related to the filtering result, and L is the filter order (length). It can be seen from Expression 2 that the IIR filter has a feedback structure. The current filtering result y(n) is not only related to the input signal value, but also related to the previous filtering results, and the current filtering result will also participate in subsequent filtering calculations.

[0054] When the user configures the circuit device as an IIR digital filter through the register, the data path of the circuit device is as Figure 4 shown. The circuit device is composed of two circuit devices of the present application combined according to a specific signal connection relationship. The circuit device is divided into upper and lower parts. The first circuit device is the upper half part, that is, the NUME part, and the second circuit device is the lower half part, that is, the DENO part. Specifically, the output result y of the NUME part nume(n)Connect to the signal at the B terminal of DENO_MUX3, and the current output result y(n) of the entire IIR filter circuit device is fed back to the signal at the B terminal of DENO_MUX1 as the input for the next cycle of the DENO part. NUME_MUX1, NUME_MUX2, and NUME_MUX3 all select the signal at the A terminal, and DENO_MUX1, DENO_MUX2, and DENO_MUX3 all select the signal at the B terminal. The circuit device of the NUME part loads the first filter coefficient a(i), and the circuit device of the DENO part loads the second filter coefficient b(i). From Expression 3, it can be seen that the number of b(i) is 1 less than that of a(i). Therefore, after the coefficient storage circuit of the DENO part finishes loading b(L - 1), it needs to fill in 1 more 0. From Figure 4 it can be known that the NUME part of the IIR filter circuit device has the same circuit structure as the FIR filter circuit. Therefore, we get:

[0055] (Expression 4);

[0056] From the data path of the IIR filter circuit device, it can be seen that the input signal of the DENO part is the filtering result y(n) of the IIR filter in the previous cycle. Therefore, the value of the signal at the A terminal of DENO_MUX2 is:

[0057] (Expression 5);

[0058] The value of the signal at the B terminal of DENO_MUX2 is the negative form of the value of the signal at the A terminal. Therefore,

[0059] (Expression 6);

[0060] Therefore, we obtain:

[0061] (Expression 7);

[0062] It can be seen that Expression 7 is consistent with Expression 3. Therefore, Figure 4 the circuit device shown can implement the IIR digital filter function.

[0063] In a specific embodiment, the circuit device of the present application is configured as a 12th-order FIR digital filter, and the data path of the circuit device is as Figure 5As shown, the first filtering result y(0) of the FIR digital filter is calculated. The sampled input signal sequence x(0) enters the circuit device. According to the FIR mathematical expression, it is multiplied by the corresponding coefficient h(0) to obtain y(0)=h(0)x(0). Then, x(1) enters the circuit device to calculate y(1), x(2) enters the circuit device to calculate y(2), and so on. For each input of a sampled input signal sequence, a filtering result is obtained. To save space, the calculation processes of y(1) to y(10) are omitted. The calculation process of y(11) is as Figure 6 shown. The sampled input signal sequence and the filter coefficients perform multiplication operations according to the corresponding relationship shown in the figure. Then, the circuit device adds the multiplication results to obtain:

[0064]

[0065] (Expression 8);

[0066] As can be seen from Expression 8, the filtering operation process of this circuit device conforms to the FIR filter mathematical expression.

[0067] In another specific embodiment, the circuit device of the present application is configured as a 12th-order IIR digital filter. The data path of the circuit device is as Figure 7 shown. The first filtering result y(0) of the IIR digital filter is calculated. The sampled input signal sequence x(0) enters the NUME part of the circuit device. According to the IIR mathematical expression, y(0)=a(0)x(0) is obtained. After obtaining the value of y(0), it is fed back to the input end of the DENO part of the circuit device. The sampled input signal sequence x(1) enters the NUME part of the circuit device. According to x(0), x(1), and y(0), y(1)=a(0)x(1)+a(1)x(0)+b(1)y(0) is calculated and y(1) is fed back to the input end of the DENO part of the circuit device. And so on. For each feedback of a current filtering result and input of a sampled input signal sequence, the next filtering result is calculated. To save space, the specific calculation processes of y(1) to y(10) are omitted. The calculation process of y(11) is as Figure 8 shown. y(11) is obtained by adding two parts: y_nume(11) and the opposite of y_deno(10):

[0068]

[0069] (Expression 9);

[0070] As can be seen from Expression 9, the filtering operation process of this circuit device conforms to the IIR filter mathematical expression.

[0071] In summary, for the digital filter circuit device of the present application, the filter type of the circuit device is configured through a register, the data path of the corresponding filter is gated by the circuit device, and the corresponding filter coefficients are loaded to implement the corresponding filter function. The circuit device of the present application can be compatible with implementing the functions of FIR digital filters and IIR digital filters, and has the advantages of high flexibility and wide application scenarios.

[0072] It should be noted that for those of ordinary skill in the art of the present technology, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application. It should be understood that certain features of the present disclosure described in the context of separate embodiments for clarity can also be provided in a single embodiment by combination. Conversely, the various features of the present disclosure described in the context of a single embodiment for clarity can also be provided separately or in any suitable combination or as any other described embodiment of the present disclosure.

Claims

1. A digital filter circuit device, characterized in that: The circuit device comprises at least one storage circuit, at least one multiplication and addition circuit, at least one addition circuit, and a first data selection circuit, a second data selection circuit, and a third data selection circuit; the first data selection circuit is connected to the storage circuit and is used to input a discrete digital signal; the storage circuit is used to store the discrete digital signal and the filter coefficient; the multiplication and addition circuit is connected between the storage circuit and the second data selection circuit, and the multiplication and addition circuit is used to perform multiplication and addition operations on the discrete digital signal and the filter coefficient according to a preset corresponding relationship, determine the multiplication and addition result, and input it into the second data selection circuit; The adding circuit is connected to the second data selection circuit and the third data selection circuit respectively. The second data selection circuit and the third data selection circuit are used to select corresponding data paths and perform input and output according to the configuration mode. The adding circuit is used to add the output signal of the second data selection circuit and the output signal of the third data selection circuit, and output the filtering result corresponding to the configuration mode; wherein the three data selection circuits all include an A terminal and a B terminal for inputting signals and a Z terminal for outputting signals. When the configuration mode is the FIR mode, the three data selection circuits all select the A terminal signal; when the configuration mode is the IIR mode, the circuit device is composed of a first circuit device and a second circuit device. The three data selection circuits of the first circuit device all select the A terminal signal, and the three data selection circuits of the second circuit device all select the B terminal signal. The filtering result of the first circuit device is used as the B terminal input signal of the third data selection circuit of the second circuit device, and the filtering result of the second circuit device is used as the B terminal input signal of the first data selection circuit of the second circuit device.

2. A digital filter circuit device according to claim 1, characterized in that: When the configuration mode is FIR mode, the input signal of the A terminal of the first data selection circuit is a discrete digital signal, the input signal of the A terminal of the second data selection circuit is a multiplication and addition result, and the input signal of the A terminal of the third data selection circuit is 0.

3. A digital filter circuit device according to claim 2, characterized in that: The expression of the filtering result in the FIR mode is: ； in, x(ni) is the discrete digital signal sequence of the sampled input, h(i) are the FIR filter coefficients, y(n) is the filter output signal sequence, L is the filter order, MUX2 Z The Z terminal output signal of the second data selection circuit, MUX3 Z The Z terminal of the third data selection circuit outputs a signal.

4. A digital filter circuit device according to claim 1, characterized in that: The first circuit device is loaded with a first filter coefficient, and the second circuit device is loaded with a second filter coefficient, the number of the second filter coefficient being one less than the number of the first filter coefficient.

5. A digital filter circuit device according to claim 4, characterized in that: The signal value at the B terminal of the second data selection circuit of the second circuit device is the inverse of the signal value at the A terminal of the second data selection circuit of the second circuit device, and the expression of the filtering result in the IIR mode is: ； in, x(n) is the discrete digital signal sequence of the sampled input, y(n) is the filter output signal sequence, a(i) is the filter coefficient related to the input signal sequence, b(i) is the filter coefficient related to the filtering result, L is the filter order, y nume(n) is the filtering result of the first circuit device, DENO MUX2B It is the signal value of the B terminal of the second data selection circuit of the second circuit device.

6. A digital filter circuit device according to claim 1, characterized in that: The circuit device switches different configuration modes through registers to achieve different filtering effects; in different configuration modes, corresponding numbers of storage circuits, multiplication and addition circuits and addition circuits are set according to the filter order corresponding to the configuration mode.

7. A digital filter circuit device according to claim 1, characterized in that: The storage circuit includes a signal storage circuit for storing the discrete digital signal and a coefficient storage circuit for storing the filter coefficient.

8. A digital filter circuit device according to claim 7, characterized in that: The multiplication and addition circuit includes a multiplier and an adder, the multiplier is connected to the signal storage circuit and the coefficient storage circuit, the multiplier performs multiplication operation on the discrete digital signal and the filter coefficient according to a preset corresponding relationship to obtain a multiplication result, and the adder adds the multiplication results to obtain a multiplication and addition result.

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