Automatic start-stop burst mode clock and data recovery circuit with temperature compensation

Abstract

The invention relates to an automatic start-stop burst mode clock and data recovery circuit with temperature compensation, and the circuit comprises an edge detection circuit which is used for detecting the edge of an input signal and generating a delay signal and an enable signal; the digital control circuit is used for controlling the working state of the whole circuit according to the enable signal and the pulse signal and outputting a gating signal and a control signal; the CTAT reference current source is used for generating bias current with a negative temperature coefficient when being started; the ring oscillator is used for generating a clock signal insensitive to power supply voltage and temperature; the first D trigger is used for sampling the delay signal according to the clock signal to obtain recovery data; and the digital correlator is used for outputting a high-level pulse signal when the recovery data is judged to be consistent with the preset comparison signal. According to the circuit, wakeup and dormancy of the clock and data recovery circuit are automatically realized, long-time working of the circuit is avoided, and thus the overall power consumption is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of digital-analog mixed signal integrated circuit design, and in particular relates to a self-start-stop burst mode clock and data recovery circuit with temperature compensation. Background Art

[0002] With the development of 5G communication technology, the number of wireless communication devices has exploded, driving the rapid development of the Internet of Things technology. Against the backdrop of massive application demands, low-cost, low-power, and low-latency wireless communications have become a research hotspot. The wake-up receiver technology was proposed in 2007 to reduce the meaningless waste of power consumption in wireless device information transmission. Its working principle is: the main receiver is usually off and the wake-up receiver is in working state; when the wake-up receiver receives a communication request, it wakes up the main receiver to start working, and then turns off the main receiver after the communication is completed. The advantage of this communication method is that it can not only ensure the real-time communication, but also meet the low power consumption requirements of the Internet of Things.

[0003] The wake-up receiver needs to accurately recover the received wake-up pattern, which often requires a local clock. The stability of the clock will directly affect the performance of the entire receiver. At the same time, in most traditional wake-up receivers, the clock is not turned off when the wake-up is successful, resulting in huge power consumption. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a temperature-compensated self-start-stop burst mode clock and data recovery circuit. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] The embodiment of the present invention provides a temperature-compensated self-start-stop burst mode clock and data recovery circuit, comprising: an edge detection circuit, a digital control circuit, a CTAT reference current source, a ring oscillator, a first D flip-flop and a digital correlator, wherein:

[0006] The edge detection circuit is used to detect the edge of the input signal and generate a delay signal and an enable signal;

[0007] The digital control circuit is used to control the working state of the clock and data recovery circuit according to the enable signal and the pulse signal, and output the gating signal and the control signal;

[0008] The CTAT reference current source is used to be turned on or off according to the control signal, and to generate a bias current with a negative temperature coefficient when turned on;

[0009] The ring oscillator is used to generate a clock signal that is insensitive to power supply voltage and temperature according to the gating signal, the bias current and the voltage signal;

[0010] The first D flip-flop is used to sample the delayed signal according to the clock signal to obtain recovered data;

[0011] The digital correlator is used to output the pulse signal as a high level when it is determined that the restored data is consistent with a preset comparison signal.

[0012] In one embodiment of the present invention, the edge detection circuit comprises: a variable delay unit and an XOR gate, wherein:

[0013] The input end of the variable delay unit is used to input the input signal, the first control end, the second control end, the third control end, and the fourth control end are used to input the digital control signal, and the output end is connected to the first input end of the XOR gate and outputs the delay signal;

[0014] The second input terminal of the XOR gate inputs the input signal, and the output terminal outputs the enable signal.

[0015] In one embodiment of the present invention, the delay width of the delayed signal is half of a bit width of the input signal;

[0016] The pulse width of the enable signal is half of a bit width of the input signal.

[0017] In one embodiment of the present invention, the digital control circuit includes a three-bit counter, an OR gate, a threshold detector, a second D flip-flop, an inverter, a first data selector, a second data selector and a third data selector, wherein:

[0018] The input trigger terminal of the three-bit counter inputs the enable signal, the reset terminal is connected to the output terminal of the OR gate, and the first output terminal, the first output terminal, and the third output terminal are correspondingly connected to the first input terminal, the second input terminal, and the third input terminal of the threshold detector;

[0019] The fourth input terminal, the fifth input terminal and the sixth input terminal of the threshold detector input the threshold control signal, and the output terminal is connected to the clock trigger terminal of the second D flip-flop;

[0020] The data input terminal of the second D flip-flop is connected to the power supply, the reset terminal is connected to the output terminal of the OR gate, and the output terminal is connected to the input terminal of the inverter;

[0021] The output end of the inverter is connected to the data selection end of the first data selector and the first data input end of the third data selector;

[0022] The first input terminal of the OR gate inputs a reset signal, and the second input terminal inputs the pulse signal;

[0023] The first data input terminal of the first data selector is connected to a power supply, the second data input terminal inputs the enable signal, and the data output terminal is connected to the first data input terminal of the second data selector;

[0024] The second data input terminal of the second data selector inputs the enable signal, the data selection terminal inputs the mode control signal, and the data output terminal outputs the gating signal;

[0025] The second data input terminal of the third data selector is connected to the ground terminal, the data selection terminal is connected to the input mode control signal, and the data output terminal outputs the control signal.

[0026] In one embodiment of the present invention, the CTAT reference current source includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a resistor and an operational amplifier, wherein:

[0027] The source of the first transistor, the source of the second transistor, the source of the third transistor, the source of the fourth transistor, the source of the fifth transistor, the source of the sixth transistor, the source of the seventh transistor, the source of the eighth transistor and the drain of the ninth transistor are connected; the gate of the ninth transistor inputs the control signal, and the source of the ninth transistor is connected to the power supply voltage; the gate of the first transistor, the source of the tenth transistor, and one end of the resistor are connected to the ground terminal;

[0028] The drain of the first transistor is connected to the gate of the second transistor; the drain of the second transistor, the drain of the third transistor, the positive input terminal of the operational amplifier, the gate of the tenth transistor, and the drain of the tenth transistor are connected; the gate of the third transistor, the gate of the fourth transistor, the gate of the fifth transistor, the gate of the sixth transistor, the gate of the seventh transistor, the gate of the eighth transistor, and the output terminal of the operational amplifier are connected; the drain of the fourth transistor, the reverse input terminal of the operational amplifier, and the other end of the resistor are connected; the drain of the fifth transistor, the drain of the sixth transistor, the drain of the seventh transistor, and the drain of the eighth transistor output the bias current and are respectively connected to the first current input terminal, the second current input terminal, the third current input terminal, and the fourth current input terminal of the ring oscillator.

[0029] In one embodiment of the present invention, the bias current is expressed as:

[0030]

[0031] Among them, I S0 is the bias current of the fifth transistor output, I S1is the bias current output by the sixth transistor, I S2 is the bias current of the seventh transistor output, I S3 is the bias current output by the eighth transistor, I ref (T) is the current output by the fourth transistor, V GS1 (T) is the gate-source voltage of the tenth transistor, and R1 is the resistance value of the resistor.

[0032] In one embodiment of the present invention, the ring oscillator includes a first differential delay unit, a second differential delay unit, a first variable capacitor, a second variable capacitor, a third variable capacitor, a fourth variable capacitor and an eleventh transistor, wherein:

[0033] The non-inverting input terminal of the first differential delay unit, the inverting output terminal of the second differential delay unit, the PLUS terminal of the first variable capacitor, and the drain of the eleventh transistor are connected to the first current input terminal of the ring oscillator and output the clock signal;

[0034] The inverting input terminal of the first differential delay unit, the non-inverting output terminal of the second differential delay unit, and the PLUS terminal of the second variable capacitor are connected to the fourth current input terminal of the ring oscillator;

[0035] The positive phase output terminal of the first differential delay unit, the positive phase input terminal of the second differential delay unit, and the PLUS terminal of the third variable capacitor are connected to the third current input terminal of the ring oscillator;

[0036] The inverting output terminal of the first differential delay unit, the inverting input terminal of the second differential delay unit, and the PLUS terminal of the fourth variable capacitor are connected to the second current input terminal of the ring oscillator;

[0037] The MINUS end of the first variable capacitor and the MINUS end of the second variable capacitor are connected and input with a voltage signal; the MINUS end of the third variable capacitor and the MINUS end of the fourth variable capacitor are connected and input with a voltage signal;

[0038] The gate of the eleventh transistor inputs the gate control signal, and the source is connected to the ground terminal.

[0039] In one embodiment of the present invention, the first differential delay unit and the second differential delay unit have the same structure.

[0040] In one embodiment of the present invention, the first differential delay unit and the second differential delay unit each include a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor and a twenty-fifth transistor, wherein:

[0041] The source of the twelfth transistor, the source of the sixteenth transistor, the source of the seventeenth transistor, the source and drain of the eighteenth transistor, the source and drain of the nineteenth transistor, the source of the twenty-fourth transistor, and the source of the twenty-fifth transistor are all connected to the ground terminal, the drain of the twelfth transistor, the drain and gate of the thirteenth transistor, the gate of the fourteenth transistor, the gate of the fifteenth transistor, the gate of the sixteenth transistor, the drain of the seventeenth transistor, the gate of the nineteenth transistor, and the gate of the twentieth transistor are connected to the inverting output terminal of the differential delay unit, and the drain of the twenty-fifth transistor, the drain and gate of the twenty-first transistor, the gate of the twenty-second transistor, the gate of the twenty-third transistor, The gate of the twenty-fourth transistor, the drain of the twentieth transistor, the gate of the eighteenth transistor, and the gate of the seventeenth transistor are connected to the positive phase output terminal of the differential delay unit, the source of the thirteenth transistor is connected to the drain of the fourteenth transistor, the source of the fourteenth transistor is connected to the drain of the fifteenth transistor, the source of the fifteenth transistor is connected to the drain of the sixteenth transistor, the source of the twenty-first transistor is connected to the drain of the twenty-second transistor, the source of the twenty-second transistor is connected to the drain of the twenty-third transistor, the source of the twenty-third transistor is connected to the drain of the twenty-fourth transistor, the gate of the twelfth transistor is connected to the positive phase input terminal of the differential delay unit, and the gate of the twenty-fifth transistor is connected to the negative phase input terminal of the differential delay unit.

[0042] Compared with the prior art, the present invention has the following beneficial effects:

[0043] 1. The temperature-compensated self-start-stop burst mode clock and data recovery circuit of this embodiment automatically turns on the CTAT reference current source and the ring oscillator through a digital control circuit, so that the entire circuit starts to work, and automatically turns off the subsequent circuit after the recovery work is completed, thereby controlling the working state of the clock and data recovery circuit, automatically realizing the wake-up and sleep of the clock and data recovery circuit, avoiding the circuit from working for a long time, thereby reducing the overall power consumption;

[0044] 2. The temperature-compensated self-start-stop burst mode clock and data recovery circuit of this embodiment obtains a clock that is insensitive to temperature and power supply voltage through temperature compensation, improves circuit robustness, reduces circuit complexity and power consumption, and is suitable for wake-up receiver applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A schematic structural diagram of a self-start-stop burst mode clock and data recovery circuit with temperature compensation provided by an embodiment of the present invention;

[0046] Figure 2 A schematic diagram of the structure of an edge detection circuit provided by an embodiment of the present invention;

[0047] Figure 3 A timing diagram of an edge detection circuit provided by an embodiment of the present invention;

[0048] Figure 4 A schematic diagram of the structure of a digital control circuit provided by an embodiment of the present invention;

[0049] Figure 5 A schematic diagram of the structure of a CTAT reference current source provided by an embodiment of the present invention;

[0050] Figure 6 A schematic diagram of the structure of a ring oscillator provided in an embodiment of the present invention;

[0051] Figure 7 A schematic diagram of the structure of a differential delay unit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0052] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0053] Embodiment 1

[0054] This embodiment provides a temperature-compensated self-start-stop burst mode clock and data recovery circuit, which realizes automatic wake-up and sleep through a digital control circuit, thereby reducing circuit power consumption; the circuit realizes a stable clock through a temperature-compensated ring oscillator, thereby improving clock performance and circuit robustness; the clock and data recovery circuit is suitable for wake-up receiver applications, and improves the stability and energy efficiency of the wake-up receiver.

[0055] See also Figure 1 , Figure 1A structural schematic diagram of a self-start-stop burst mode clock and data recovery circuit with temperature compensation provided in an embodiment of the present invention, the self-start-stop burst mode clock and data recovery circuit with temperature compensation includes an edge detection circuit, a digital control circuit, a CTAT reference current source, a ring oscillator, a first D flip-flop and a digital correlator.

[0056] The edge detection circuit is used to detect the edge of the input signal DATA and generate a delayed signal DATA DELAY and enable signal EN.

[0057] Specifically, the edge detection circuit is composed of four digital control signals DS 0～3 Control the delay size of the internal delay unit, thereby controlling the pulse width of the output enable signal EN and outputting the delayed signal DATA with different delays DELAY .

[0058] The digital control circuit is used to control the operation of the entire clock and data recovery circuit according to the enable signal EN and the wake-up signal WAKE_UP, and output the gating signal (GT EN ) and control signal (T OFF ). When the digital control circuit is in the first working state, the enable signal EN is used as the gate control signal GT EN , and output control signal T OFF is low level; when in the second working state, the number of enable signals EN is recorded, and when the number of enable signals EN is equal to the threshold control signal EDGE_THRESHOLD 0～2 When the threshold is equal to the output control signal T OFF is low level, and the enable signal EN is used as the gate signal GT EN , and outputs the control signal T according to the high level pulse signal WAKE_UP OFF is high level.

[0059] Specifically, the digital control circuit is controlled by the enable signal EN, the high level pulse signal WAKE_UP, the reset RSTP, the mode control signal MDSW and the threshold control signal EDGE_THRESHOLD0~2, which are used to control the working state of the entire circuit. Among them, the enable signal EN is used to generate the gate signal GT EN , controls the entire BMCDR to start normal operation, generates a recovered clock and retimes the data; the WAKE_UP signal is used to control the digital control circuit output signal T OFF The CTAT reference current source is turned off to stop the ring oscillator. The reset signal RSTP is used to reset the circuit when it starts working. The threshold control signal EDGE_THRESHOLD 0～2It is used to control the threshold for edge counting of the enable signal, and the mode control signal MDSW is used to control the working state of the digital control circuit.

[0060] CTAT reference current source, controlled by the control signal T OFF Controls whether it works or not. It is used when the control signal T OFF When the control signal T OFF When it is high, it turns off and when it is turned on, it generates a bias current I with a negative temperature coefficient S0～3 , temperature compensate the ring oscillator and control its output frequency.

[0061] Ring oscillator, used to generate a gate signal GT EN , bias current I S0～3 And the voltage signal V CT Generates a broadband clock signal CK that is insensitive to power supply voltage and temperature, wherein the gate signal GT EN Used to gate the ring oscillator for burst mode applications. The bias current IS 0～3 Used to perform temperature compensation on the ring oscillator. The voltage signal V CT Used for frequency tuning of ring oscillators.

[0062] The first D flip-flop is used to delay the signal DATA according to the clock signal CK. DELAY Sampling is performed to obtain the recovered data DATA REC .

[0063] A digital correlator is used to generate a digital signal based on a clock signal CK and a bit signal B. 0～5 , determine the recovery data DATA REC Compare with preset signal WUCODE 0～15 When determining the consistency of the restored data DATA REC Compare with preset signal WUCODE 0～15 When they are consistent, the output pulse signal WAKE_UP is high, indicating that the wake-up is successful.

[0064] The temperature-compensated self-start-stop burst mode clock and data recovery circuit of this embodiment realizes the sleep and wake-up of the clock and data recovery circuit through the digital control circuit. Specifically, the digital control circuit is reset by the external reset signal RSTP when the circuit starts working. When the external input is detected, the edge detector generates a pulse signal EN at each input data edge. The digital control circuit records the number of pulse signals and compares it with the preset threshold EDGE_THRESHOLD. 0～2 When the threshold is reached, T OFFThe signal is set to a low level, the CTAT reference current source and the ring oscillator are started, and the clock and data recovery function begins. When BMCDR performs the data recovery function, the digital correlator continuously compares the recovered data DATA REC Compare with preset signal WUCODE 0～15 When the two are detected to be consistent, a high-level pulse signal WAKE_UP is output to clear the state in the digital control circuit and turn T OFF The signal becomes high level, turning off the CTAT reference current source and the ring oscillator, and the circuit enters sleep mode, thereby greatly reducing the power consumption of the circuit when it is in sleep mode.

[0065] See also Figure 2 , Figure 2 A schematic diagram of the structure of an edge detection circuit provided by an embodiment of the present invention.

[0066] The edge detection circuit includes: a variable delay unit and an XOR gate, wherein the input end of the variable delay unit Variable Delay is used to input the input signal DATA, and the first control end, the second control end, the third control end, and the fourth control end are used to input the digital control signal DS 0～3 The output end is connected to the first input end of the XOR gate XOR and outputs the delayed signal DATA DELAY The second input terminal of the XOR gate XOR inputs the input signal DATA, and the output terminal outputs the enable signal EN. Among them, the delay signal DATA DELAY The delay width is half of the one-bit width of the input signal DATA; the pulse width of the enable signal EN is half of the one-bit width of the input signal DATA.

[0067] Specifically, when the input signal DATA arrives, the digital control signal DS 0～3 Adjust the delay of the variable delay unit to UI / 2, where UI represents one bit width of the input signal, and then DELAY The XOR operation is performed with the input signal DATA, thereby generating a pulse signal EN at each data edge, whose width is UI / 2, such as Figure 3 As shown, Figure 3 This is a timing diagram of the edge detection circuit provided by an embodiment of the present invention. The pulse signal EN is used for the subsequent enabling operation of the ring oscillator.

[0068] See also Figure 4 , Figure 4 A schematic diagram of the structure of a digital control circuit provided by an embodiment of the present invention.

[0069] The digital control circuit includes a three-bit counter, an OR gate, a threshold detector, a second D flip-flop, an inverter, a first data selector MUX1, a second data selector MUX2, and a third data selector MUX3.

[0070] Among them, the input trigger end of the three-bit counter inputs an enable signal EN, which is used as a trigger signal of the three-bit counter; the reset end of the three-bit counter is connected to the output end of the OR gate, which is used to clear the state of the three-bit counter; the first output end, the first output end, and the third output end of the three-bit counter are correspondingly connected to the first input end, the second input end, and the third input end of the threshold detector.

[0071] The threshold detector has six input terminals and one output terminal. The first to third input terminals are connected to the output terminal Q of the three-bit counter. 0～2 , used to detect the number of edges that appear; the fourth input terminal, the fifth input terminal, and the sixth input terminal of the threshold detector input the threshold control signal EDGE_THRESHOLD 0～2 , used to control the detection threshold; the output end is connected to the clock trigger end of the second D flip-flop.

[0072] The second D flip-flop has three input terminals and one output terminal, wherein the data input terminal D is connected to the power supply VDD, and is used to convert the short pulse signal output by the threshold detector into a long 1 signal; the reset terminal R is connected to the output terminal of the OR gate, and the output terminal Q is connected to the input terminal of the inverter.

[0073] The output terminal of the inverter is connected to the data selection terminal of the first data selector MUX1 and the first data input terminal of the third data selector MUX3.

[0074] The first input terminal of the OR gate is input with the reset signal RSTP, and the second input terminal is input with the pulse signal WAKE_UP.

[0075] The first data input terminal of the first data selector MUX1 is connected to the power supply VDD, the second data input terminal is input with the enable signal EN, and the data output terminal is connected to the first data input terminal of the second data selector MUX2; the second data input terminal of the second data selector MUX2 is input with the enable signal EN, the data selection terminal is input with the mode control signal MDSW, and the data output terminal outputs the gating signal GT EN The second data input terminal of the third data selector MUX3 is connected to the ground terminal GND, the data selection terminal is connected to the input mode control signal MDSW, and the data output terminal outputs the control signal T OFF .

[0076] Specifically, when the mode control signal MDSW=0, the digital control circuit is in a transparent state, and the enable signal EN output by the edge detector is directly used as the gate control signal GT output by the digital control circuit. EN, control signal T OFF is selected as GND (i.e. low level), turning on the CTAT reference current source and the ring oscillator, and the gate signal GT EN Injected into the ring oscillator to adjust the clock phase.

[0077] When the mode control signal MDSW = 1, the digital control circuit works normally. At the beginning, GT EN =VDD,T OFF =1, the CTAT current source and the ring oscillator are in the off state. When the input data arrives, the three-bit counter records the number of pulse signals EN, and the threshold detector compares the counter output with the preset threshold. When the counter output reaches the threshold, the threshold detector outputs a high-level pulse, and the output of the second D flip-flop becomes high, turning T OFF The value of becomes 0, waking up the subsequent CTAT reference current source and ring oscillator, and controlling the data selector MUX1 to pass the enable signal EN to the output. At this time, GT EN =EN, BMCDR starts to work normally.

[0078] See also Figure 5 , Figure 5 A schematic diagram of the structure of a CTAT reference current source provided by an embodiment of the present invention.

[0079] The CTAT reference current source includes a first transistor MP1, a second transistor MP2, a third transistor MP3, a fourth transistor MP4, a fifth transistor MP5, a sixth transistor MP6, a seventh transistor MP7, an eighth transistor MP8, a ninth transistor MP9, a tenth transistor MN1, a resistor R1 and an operational amplifier, wherein:

[0080] The source of the first transistor MP1, the source of the second transistor MP2, the source of the third transistor MP3, the source of the fourth transistor MP4, the source of the fifth transistor MP5, the source of the sixth transistor MP6, the source of the seventh transistor MP7, the source of the eighth transistor MP8 are connected to the drain of the ninth transistor MP9; the gate of the ninth transistor MP9 is input with a control signal T OFF, the source of the ninth transistor MP9 is connected to the power supply voltage VDD; the gate of the first transistor MP1, the source of the tenth transistor MN1, and one end of the resistor R1 are connected to the ground terminal GND; the drain of the first transistor MP1 is connected to the gate of the second transistor MP2; the drain of the second transistor MP2, the drain of the third transistor MP3, the positive input terminal of the operational amplifier, the gate of the tenth transistor MN1, and the drain of the tenth transistor MN1 are connected, the gate of the third transistor MP3, the gate of the fourth transistor MP4, the gate of the fifth transistor MP5, the gate of the sixth transistor MP6, the gate of the seventh transistor MP7, the gate of the eighth transistor MP8, and the output terminal of the operational amplifier are connected, the drain of the fourth transistor MP4, the reverse input terminal of the operational amplifier, and the other end of the resistor R1 are connected, and the drain of the fifth transistor MP5, the drain of the sixth transistor MP6, the drain of the seventh transistor MP7, and the drain of the eighth transistor MP8 output the bias current I S0～3 And they are respectively connected to the first current input terminal, the second current input terminal, the third current input terminal and the fourth current input terminal of the ring oscillator.

[0081] Specifically, in order to obtain the CTAT current, the tenth transistor MN1 in the CTAT reference current source is required to be in the subthreshold region. The source-drain current expression of the MOS transistor in the subthreshold region is:

[0082]

[0083] Where, I is the source-drain current of the subthreshold MOS tube, Figure 4 I S0 ~I S3 Both are subthreshold currents obtained by mirroring. Formula 1 is applicable to both PMOS and NMOS tubes. I0 is the unit saturation current. V T ≈26mV; ξ is the subthreshold slope factor, ξ=2, and its value is related to process parameters and tube size; V GS is the difference between the gate voltage and the source voltage of the MOS tube in the subthreshold region; V DS is the difference between the drain voltage and the source voltage of the MOS tube in the subthreshold region, W is the gate width of the transistor, and L is the gate length of the transistor.

[0084] Since the channel length of the transistor in this embodiment is long enough and there is no substrate bias effect, |V DS | Much larger than V T Therefore, the source-drain current expression of the subthreshold MOS tube can be simplified as:

[0085]

[0086] The gate-source voltage V of the NMOS tube working in the subthreshold region GSWith the threshold voltage V TH Satisfies the temperature-dependent function:

[0087]

[0088] Where T0 is room temperature = 300K, threshold voltage V TH T can be written as:

[0089] V TH (T) = V TH (T0)+K T (T / T0-1) (4)

[0090] Among them, K T Typical values ​​are negative.

[0091] Using equations (3) and (4), V GS It can be expressed as:

[0092]

[0093] Due to K T +V GS (T0)-V TH (T0) is usually negative, so V GS T decreases with increasing temperature, showing CTAT characteristics.

[0094] Due to the virtual short characteristic of the op amp, the voltages at its positive input and reverse input are basically the same, and the gate-source voltage of MN1 is recorded as V GS1 , resistor R1 is a ZTAT resistor, so I ref It can be written as:

[0095]

[0096] From formula (6), we can see that when the temperature rises, V GS1 T decreases, I ref T also decreases, thus obtaining the CTAT current.

[0097] Through the mirror tube M P5 、M P6 、M P7 、M P8 Copy I ref ,Right now Used to connect subsequent ring oscillators.

[0098] It can be seen that the CTAT reference current source in this embodiment can generate a bias current with a negative temperature coefficient.

[0099] See also Figure 6 , Figure 6A schematic diagram of the structure of a ring oscillator provided in an embodiment of the present invention.

[0100] The ring oscillator includes a first differential delay unit DLY1 , ​​a second differential delay unit DLY2 , a first variable capacitor C1 , a second variable capacitor C2 , a third variable capacitor C3 , a fourth variable capacitor C4 and an eleventh transistor MN2 .

[0101] Among them, the positive phase input terminal VP of the first differential delay unit DLY1, the inverting output terminal VON of the second differential delay unit DLY2, the PLUS terminal of the first variable capacitor C1, and the drain of the eleventh transistor MN2 are connected to the first current input terminal of the ring oscillator and output the clock signal CK; the inverting input terminal VN of the first differential delay unit DLY1, the positive phase output terminal VOP of the second differential delay unit DLY2, and the PLUS terminal of the second variable capacitor C2 are connected to the fourth current input terminal of the ring oscillator; the positive phase output terminal VOP of the first differential delay unit DLY1, the positive phase input terminal VP of the second differential delay unit DLY2, and the PLUS terminal of the third variable capacitor C3 are connected to the third current input terminal of the ring oscillator; the inverting output terminal VON of the first differential delay unit DLY1, the inverting input terminal VN of the second differential delay unit DLY2, and the PLUS terminal of the fourth variable capacitor C4 are connected to the second current input terminal of the ring oscillator; the MINUS terminal of the first variable capacitor C1 and the MINUS terminal of the second variable capacitor C2 are connected and the input voltage signal V CT The MINUS terminal of the third variable capacitor C3 and the MINUS terminal of the fourth variable capacitor C4 are connected and the input voltage signal V CT ; The gate of the eleventh transistor MN2 inputs the gate control signal GT EN , the source is connected to the ground terminal.

[0102] Specifically, the ring oscillator of this embodiment adopts a two-stage differential delay unit structure, and each stage provides a 90° phase shift. In order to ensure that the ring oscillator can oscillate stably, the output end of the first differential delay unit DLY1 is connected in phase with the input end of the second differential delay unit DLY2, and the output end of the second differential delay unit DLY2 is connected in reverse phase with the input end of the first differential delay unit DLY1, so that the two-stage differential delay unit generates a total of 180° phase shift.

[0103] Specifically, the first differential delay unit DLY1 and the second differential delay unit DLY2 have the same structure.

[0104] See also Figure 7 , Figure 7 A schematic diagram of the structure of a differential delay unit provided by an embodiment of the present invention.

[0105] The first differential delay unit DLY1 and the second differential delay unit DLY2 each include a twelfth transistor MN3, a thirteenth transistor MN4, a fourteenth transistor MN5, a fifteenth transistor MN6, a sixteenth transistor MN7, a seventeenth transistor MN8, an eighteenth transistor MN9, a nineteenth transistor MN10, a twentieth transistor MN11, a twenty-first transistor MN12, a twenty-second transistor MN13, a twenty-third transistor MN14, a twenty-fourth transistor MN15 and a twenty-fifth transistor MN16.

[0106] Among them, the source of the twelfth transistor MN3, the source of the sixteenth transistor MN7, the source of the seventeenth transistor MN8, the source and drain of the eighteenth transistor MN9, the source and drain of the nineteenth transistor MN10, the source of the twenty-fourth transistor MN15, and the source of the twenty-fifth transistor MN16 are all connected to the ground terminal, the drain of the twelfth transistor MN3, the drain and gate of the thirteenth transistor MN4, the gate of the fourteenth transistor MN5, the gate of the fifteenth transistor MN6, the gate of the sixteenth transistor MN7, the drain of the seventeenth transistor MN8, the gate of the nineteenth transistor MN10, and the gate of the twentieth transistor MN11 are connected to the inverting output terminal VON of the differential delay unit, the drain of the twenty-fifth transistor MN16, the drain and gate of the twenty-first transistor MN12, the gate of the twenty-second transistor MN13, the gate of the twenty-third transistor MN14, and the gate of the twenty-third transistor MN15 are connected to the inverting output terminal VON of the differential delay unit. The gate of the fourteenth transistor MN15, the drain of the twentieth transistor MN11, the gate of the eighteenth transistor MN9, and the gate of the seventeenth transistor MN8 are connected to the positive phase output terminal VOP of the differential delay unit, the source of the thirteenth transistor MN4 is connected to the drain of the fourteenth transistor MN5, the source of the fourteenth transistor MN5 is connected to the drain of the fifteenth transistor MN6, the source of the fifteenth transistor MN6 is connected to the drain of the sixteenth transistor MN7, the source of the twenty-first transistor MN12 is connected to the drain of the twenty-second transistor MN13, the source of the twenty-second transistor MN13 is connected to the drain of the twenty-third transistor MN14, the source of the twenty-third transistor MN14 is connected to the drain of the twenty-fourth transistor MN15, the gate of the twelfth transistor MN3 is connected to the positive phase input terminal VP of the differential delay unit, and the gate of the twenty-fifth transistor MN16 is connected to the negative phase input terminal VN of the differential delay unit.

[0107] In this embodiment, the CTAT reference current source realizes the CTAT current at low voltage through the CTAT characteristic of the gate-source voltage of the NMOS tube working in the subthreshold region and the clamping operational amplifier, compensating for the PTAT characteristic of the output clock frequency of the ring oscillator, thereby obtaining a clock that is insensitive to temperature; at the same time, the ring oscillator adopts a full NMOS structure and has the characteristic of being insensitive to the power supply voltage. The clock that is insensitive to power supply and temperature avoids the use of a phase-locked loop in a traditional CDR, reduces power consumption and design complexity, and does not require an additional reference clock, making the BMCDR suitable for wake-up receiver applications.

[0108] As an optional implementation, the first D flip-flop and the digital correlator may be implemented using an existing conventional circuit framework, which will not be described in detail in this embodiment.

[0109] The temperature-compensated self-start-stop ultra-low power clock and data recovery circuit of this embodiment automatically turns on the CTAT reference current source and the ring oscillator through a digital control circuit, and the entire circuit starts working. After the recovery work is completed, the subsequent circuit is automatically turned off, thereby realizing the wake-up and sleep of the BMCDR, avoiding the circuit from working for a long time, improving the working efficiency of the BMCDR, and greatly reducing the power consumption of the BMCDR; the positive temperature coefficient of the ring oscillator is compensated by the negative temperature coefficient of the CTAT reference current source, so that the ring oscillator is insensitive to temperature changes, and a clock that is insensitive to temperature and power supply voltage is obtained, thereby avoiding the overhead of an additional reference clock, improving the circuit robustness, and reducing the circuit complexity and power consumption; the burst mode BMCDR is suitable for waking up the receiver architecture, which can effectively reduce the overall power consumption of the receiver and improve the robustness of the receiver.

[0110] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A temperature-compensated self-start-stop burst mode clock and data recovery circuit, characterized in that: include: An edge detection circuit, a digital control circuit, a CTAT reference current source, a ring oscillator, a first D flip-flop and a digital correlator, wherein: The edge detection circuit is used to detect the edge of the input signal (DATA) and generate a delay signal (DATA DELAY ) and enable signal (EN); The digital control circuit is used to control the working state of the clock and data recovery circuit according to the enable signal (EN) and the pulse signal (WAKE_UP), and output a gating signal (GT EN ) and control signal (T OFF ); The CTAT reference current source is used to adjust the current according to the control signal (T OFF ) to turn it on or off, and when turned on, it generates a bias current (I S0～3 ); The ring oscillator is used to generate a gate signal (GT) according to the gate signal EN ), the bias current (I S0～3 ) and voltage signal (V CT ) generates a clock signal (CK) that is insensitive to power supply voltage and temperature; The first D flip-flop is used to trigger the delay signal (DATA) according to the clock signal (CK). DELAY ) to obtain the recovered data (DATA REC ); The digital correlator is used to determine the recovery data (DATA REC ) and the preset comparison signal (WUCODE 0～15 ) are consistent with each other, the pulse signal (WAKE_UP) is output as a high level.

2. The temperature-compensated self-start-stop burst mode clock and data recovery circuit according to claim 1, characterized in that: The edge detection circuit includes: a variable delay unit (Variable Delay) and an exclusive OR gate (XOR), wherein: The input end of the variable delay unit (Variable Delay) is used to input the input signal (DATA), and the first control end, the second control end, the third control end, and the fourth control end are used to input the digital control signal (DS 0～3 ), the output end is connected to the first input end of the XOR gate (XOR) and outputs the delayed signal (DATA DELAY ); The input signal (DATA) is input at the second input terminal of the XOR gate (XOR), and the enable signal (EN) is output at the output terminal.

3. The self-start-stop burst mode clock and data recovery circuit with temperature compensation according to claim 2, characterized in that: The delayed signal (DATA DELAY ) has a delay width of half a bit width of the input signal (DATA); The pulse width of the enable signal (EN) is half of a bit width of the input signal (DATA).

4. The self-start-stop burst mode clock and data recovery circuit with temperature compensation according to claim 1, characterized in that: The digital control circuit includes a three-bit counter, an OR gate, a threshold detector, a second D flip-flop, an inverter, a first data selector (MUX1), a second data selector (MUX2) and a third data selector (MUX3), wherein: The input trigger terminal of the three-bit counter inputs the enable signal (EN), the reset terminal is connected to the output terminal of the OR gate, and the first output terminal, the first output terminal, and the third output terminal are correspondingly connected to the first input terminal, the second input terminal, and the third input terminal of the threshold detector; The fourth input terminal, the fifth input terminal, and the sixth input terminal of the threshold detector input a threshold control signal (EDGE_THRESHOLD 0～2 ), the output end of which is connected to the clock trigger end of the second D flip-flop; The data input terminal of the second D flip-flop is connected to the power supply (VDD), the reset terminal is connected to the output terminal of the OR gate, and the output terminal is connected to the input terminal of the inverter; The output end of the inverter is connected to the data selection end of the first data selector (MUX1) and the first data input end of the third data selector (MUX3); The first input terminal of the OR gate inputs the reset signal (RSTP), and the second input terminal inputs the pulse signal (WAKE_UP); The first data input terminal of the first data selector (MUX1) is connected to a power supply (VDD), the second data input terminal inputs the enable signal (EN), and the data output terminal is connected to the first data input terminal of the second data selector (MUX2); The second data input terminal of the second data selector (MUX2) inputs the enable signal (EN), the data selection terminal inputs the mode control signal (MDSW), and the data output terminal outputs the gating signal (GT EN ); The second data input terminal of the third data selector (MUX3) is connected to the ground terminal (GND), the data selection terminal is connected to the input mode control signal (MDSW), and the data output terminal outputs the control signal (T OFF ).

5. The self-start-stop burst mode clock and data recovery circuit with temperature compensation according to claim 1, characterized in that: The CTAT reference current source includes a first transistor (MP1), a second transistor (MP2), a third transistor (MP3), a fourth transistor (MP4), a fifth transistor (MP5), a sixth transistor (MP6), a seventh transistor (MP7), an eighth transistor (MP8), a ninth transistor (MP9), a tenth transistor (MN1), a resistor (R1) and an operational amplifier, wherein: The source of the first transistor (MP1), the source of the second transistor (MP2), the source of the third transistor (MP3), the source of the fourth transistor (MP4), the source of the fifth transistor (MP5), the source of the sixth transistor (MP6), the source of the seventh transistor (MP7), the source of the eighth transistor (MP8) and the drain of the ninth transistor (MP9) are connected; the gate of the ninth transistor (MP9) inputs the control signal (T OFF ), the source of the ninth transistor (MP9) is connected to a power supply voltage (VDD); the gate of the first transistor (MP1), the source of the tenth transistor (MN1), and one end of the resistor (R1) are connected to a ground terminal (GND); The drain of the first transistor (MP1) is connected to the gate of the second transistor (MP2); the drain of the second transistor (MP2), the drain of the third transistor (MP3), the positive input terminal of the operational amplifier, the gate of the tenth transistor (MN1), and the drain of the tenth transistor (MN1) are connected; the gate of the third transistor (MP3), the gate of the fourth transistor (MP4), the gate of the fifth transistor (MP5), the gate of the sixth transistor (MP6), the gate of the seventh transistor (MP7), the gate of the eighth transistor (MP8), and the output terminal of the operational amplifier are connected; the drain of the fourth transistor (MP4), the reverse input terminal of the operational amplifier, and the other end of the resistor (R1) are connected; the drain of the fifth transistor (MP5), the drain of the sixth transistor (MP6), the drain of the seventh transistor (MP7), and the drain of the eighth transistor (MP8) output the bias current (I S0～3 ) and are respectively connected to the first current input terminal, the second current input terminal, the third current input terminal, and the fourth current input terminal of the ring oscillator.

6. The temperature-compensated self-start-stop burst mode clock and data recovery circuit according to claim 5, characterized in that: The bias current (I S0～3 ) is: Among them, I S0 is the bias current output by the fifth transistor (MP5), I S1 is the bias current output by the sixth transistor (MP6), I S2 is the bias current output by the seventh transistor (MP7), I S3 is the bias current output by the eighth transistor (MP8), I ref (T) is the current output by the fourth transistor (MP4), V GS1 (T) is the gate-source voltage of the tenth transistor (MN1), and R1 is the resistance value of the resistor (R1).

7. The self-start-stop burst mode clock and data recovery circuit with temperature compensation according to claim 1, characterized in that: The ring oscillator comprises a first differential delay unit (DLY1), a second differential delay unit (DLY2), a first variable capacitor (C1), a second variable capacitor (C2), a third variable capacitor (C3), a fourth variable capacitor (C4) and an eleventh transistor (MN2), wherein: The positive phase input terminal (VP) of the first differential delay unit (DLY1), the negative phase output terminal (VON) of the second differential delay unit (DLY2), the PLUS terminal of the first variable capacitor (C1), and the drain of the eleventh transistor (MN2) are connected to the first current input terminal of the ring oscillator and output the clock signal (CK); The inverting input terminal (VN) of the first differential delay unit (DLY1), the positive output terminal (VOP) of the second differential delay unit (DLY2), and the PLUS terminal of the second variable capacitor (C2) are connected to the fourth current input terminal of the ring oscillator; The positive phase output terminal (VOP) of the first differential delay unit (DLY1), the positive phase input terminal (VP) of the second differential delay unit (DLY2), and the PLUS terminal of the third variable capacitor (C3) are connected to the third current input terminal of the ring oscillator; The inverting output terminal (VON) of the first differential delay unit (DLY1), the inverting input terminal (VN) of the second differential delay unit (DLY2), and the PLUS terminal of the fourth variable capacitor (C4) are connected to the second current input terminal of the ring oscillator; The MINUS end of the first variable capacitor (C1) and the MINUS end of the second variable capacitor (C2) are connected and an input voltage signal (V CT ); the MINUS end of the third variable capacitor (C3) and the MINUS end of the fourth variable capacitor (C4) are connected and the input voltage signal (V CT ); The gate of the eleventh transistor (MN2) inputs the gate control signal (GT EN ), the source is connected to the ground terminal.

8. The temperature-compensated self-start-stop burst mode clock and data recovery circuit according to claim 7, characterized in that: The first differential delay unit (DLY1) and the second differential delay unit (DLY2) have the same structure.

9. The self-start-stop burst mode clock and data recovery circuit with temperature compensation according to claim 8, characterized in that: The first differential delay unit (DLY1) and the second differential delay unit (DLY2) each include a twelfth transistor (MN3), a thirteenth transistor (MN4), a fourteenth transistor (MN5), a fifteenth transistor (MN6), a sixteenth transistor (MN7), a seventeenth transistor (MN8), an eighteenth transistor (MN9), a nineteenth transistor (MN10), a twentieth transistor (MN11), a twenty-first transistor (MN12), a twenty-second transistor (MN13), a twenty-third transistor (MN14), a twenty-fourth transistor (MN15) and a twenty-fifth transistor (MN16), wherein: The source of the twelfth transistor (MN3), the source of the sixteenth transistor (MN7), the source of the seventeenth transistor (MN8), the source and drain of the eighteenth transistor (MN9), the source and drain of the nineteenth transistor (MN10), the source of the twenty-fourth transistor (MN15), and the source of the twenty-fifth transistor (MN16) are all connected to the ground terminal, and the drain of the twelfth transistor (MN3), the drain and gate of the thirteenth transistor (MN4), and the gate of the fourteenth transistor (MN5) are connected to the ground terminal. , the gate of the fifteenth transistor (MN6), the gate of the sixteenth transistor (MN7), the drain of the seventeenth transistor (MN8), the gate of the nineteenth transistor (MN10), and the gate of the twentieth transistor (MN11) are connected to the inverting output terminal (VON) of the differential delay unit, the drain of the twenty-fifth transistor (MN16), the drain and gate of the twenty-first transistor (MN12), the gate of the twenty-second transistor (MN13), the gate of the twenty-third transistor (MN14), the second The gate of the fourteenth transistor (MN15), the drain of the twentieth transistor (MN11), the gate of the eighteenth transistor (MN9), and the gate of the seventeenth transistor (MN8) are connected to the positive phase output terminal (VOP) of the differential delay unit, the source of the thirteenth transistor (MN4) is connected to the drain of the fourteenth transistor (MN5), the source of the fourteenth transistor (MN5) is connected to the drain of the fifteenth transistor (MN6), and the source of the fifteenth transistor (MN6) is connected to the drain of the sixteenth transistor (MN7). , the source of the twenty-first transistor (MN12) is connected to the drain of the twenty-second transistor (MN13), the source of the twenty-second transistor (MN13) is connected to the drain of the twenty-third transistor (MN14), the source of the twenty-third transistor (MN14) is connected to the drain of the twenty-fourth transistor (MN15), the gate of the twelfth transistor (MN3) is connected to the positive phase input terminal (VP) of the differential delay unit, and the gate of the twenty-fifth transistor (MN16) is connected to the negative phase input terminal (VN) of the differential delay unit.

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