A self-starting stop-and-go burst mode clock and data recovery circuit with temperature compensation

Abstract

The application relates to a self-start-stop burst mode clock and data recovery circuit with temperature compensation, which comprises an edge detection circuit for detecting the edge of an input signal and generating a delay signal and an enable signal; a digital control circuit for controlling the working state of the whole circuit according to the enable signal and a pulse signal, outputting a gate signal and a control signal; a CTAT reference current source for generating a bias current with a negative temperature coefficient when starting; a ring oscillator for generating a clock signal insensitive to power supply voltage and temperature; a first D flip-flop for sampling the delay signal according to the clock signal to obtain recovered data; and a digital correlator for outputting the pulse signal as a high level when judging that the recovered data is consistent with a preset comparison signal. The circuit automatically realizes the wake-up and sleep of the clock and data recovery circuit, avoids long-time work of the circuit, and thus reduces the overall power consumption.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of digital-analog hybrid signal integrated circuit design, and particularly relates to a self-start-stop burst mode clock and data recovery circuit with temperature compensation. BACKGROUND

[0002] With the development of 5G communication technology, the number of wireless communication devices has increased explosively, which has promoted the rapid development of Internet of Things technology. Under the background of massive application demand, low-cost, low-power and low-delay wireless communication has become a research hotspot. The wake-up receiver technology was proposed in 2007, aiming to reduce the meaningless power waste in wireless device information transmission. Its working principle is that the main receiver is in an off state, and the wake-up receiver is in a working state. When the wake-up receiver receives a communication request, the main receiver is woken up to start working, and the main receiver is turned off after the communication is completed. The advantage of this communication mode is that it can guarantee the real-time performance of communication and meet the low-power requirement of Internet of Things.

[0003] The wake-up receiver needs to accurately recover the received wake-up code shape, which often requires a local clock. The stability of the clock directly affects the performance of the overall receiver, and in most traditional wake-up receivers, the clock does not shut down with the success of the wake-up, causing huge power consumption. SUMMARY

[0004] In order to solve the above problems existing in the prior art, the application provides a self-start-stop burst mode clock and data recovery circuit with temperature compensation. The technical problem to be solved by the application is solved through the following technical scheme:

[0005] The application provides a self-start-stop burst mode clock and data recovery circuit with temperature compensation, which comprises an edge detection circuit, a digital control circuit, a CTAT reference current source, a ring oscillator, a first D flip-flop and a digital correlator, wherein,

[0006] The edge detection circuit is used for detecting the edge of an input signal and generating a delay signal and an enable signal.

[0007] The digital control circuit is used for controlling the working state of the clock and data recovery circuit according to the enable signal and a pulse signal, and outputting a gate signal and a control signal.

[0008] The CTAT reference current source is used for being turned on or turned off according to the control signal, and generating a bias current with a negative temperature coefficient when being turned on.

[0009] The ring oscillator is used for generating a clock signal insensitive to power supply voltage and temperature according to the gate signal, the bias current and a voltage signal.

[0010] the first D flip-flop is configured to sample the delay signal according to the clock signal to obtain recovered data;

[0011] the digital correlator is configured to output the pulse signal as a high level when judging that the recovered data is consistent with a preset comparison signal.

[0012] In an embodiment of the present application, the edge detection circuit comprises a variable delay unit and an XOR gate, wherein,

[0013] an input end of the variable delay unit is configured to input the input signal, first, second, third and fourth control ends are configured to input a digital control signal, and an output end is connected to a first input end of the XOR gate and outputs the delay signal;

[0014] a second input end of the XOR gate is configured to input the input signal, and an output end outputs the enable signal.

[0015] In an embodiment of the present application, a delay width of the delay signal is half of a bit width of the input signal.

[0016] a pulse width of the enable signal is half of a bit width of the input signal.

[0017] In an embodiment of the present application, the digital control circuit comprises a three-bit counter, an OR gate, a threshold detector, a second D flip-flop, an inverter, a first data selector, a second data selector and a third data selector, wherein,

[0018] an input trigger end of the three-bit counter is configured to input the enable signal, a reset end is connected to an output end of the OR gate, and first, second and third output ends are connected to first, second and third input ends of the threshold detector, respectively;

[0019] fourth, fifth and sixth input ends of the threshold detector are configured to input a threshold control signal, and an output end is connected to a clock trigger end of the second D flip-flop;

[0020] a data input end of the second D flip-flop is connected to a power supply, a reset end is connected to the output end of the OR gate, and an output end is connected to an input end of the inverter;

[0021] an output end of the inverter is connected to a data selection end of the first data selector and a first data input end of the third data selector;

[0022] a first input end of the OR gate is configured to input a reset signal, and a second input end is configured to input the pulse signal;

[0023] The first data input of the first data selector is connected to a power supply, the second data input inputs the enable signal, and the data output is connected to the first data input of the second data selector;

[0024] The second data input of the second data selector inputs the enable signal, the data selection input inputs a mode control signal, and the data output outputs the gate signal;

[0025] The second data input of the third data selector is connected to a ground terminal, the data selection input inputs an input mode control signal, and the data output outputs the control signal.

[0026] In an embodiment of the present application, the CTAT reference current source comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a resistor, and an operational amplifier, wherein,

[0027] The source of the first transistor, the source of the second transistor, the source of the third transistor, the source of the fourth transistor, the source of the fifth transistor, the source of the sixth transistor, the source of the seventh transistor, the source of the eighth transistor, and the drain of the ninth transistor are connected; the gate of the ninth transistor inputs the control signal, and the source of the ninth transistor is connected to a power supply voltage; the gate of the first transistor and the source of the tenth transistor are connected to a ground terminal, and one end of the resistor is connected to the ground terminal;

[0028] The drain of the first transistor is connected to the gate of the second transistor; the drain of the second transistor, the drain of the third transistor, the positive input of the operational amplifier, the gate of the tenth transistor, and the drain of the tenth transistor are connected, the gate of the third transistor, the gate of the fourth transistor, the gate of the fifth transistor, the gate of the sixth transistor, the gate of the seventh transistor, the gate of the eighth transistor, and the output of the operational amplifier are connected, the drain of the fourth transistor, the negative input of the operational amplifier, and the other end of the resistor are connected, and the drain of the fifth transistor, the drain of the sixth transistor, the drain of the seventh transistor, and the drain of the eighth transistor output the bias current and are respectively connected to the first current input, the second current input, the third current input, and the fourth current input of the ring oscillator.

[0029] In an embodiment of the present application, the expression of the bias current is:

[0030]

[0031] wherein, I S0 is the bias current output by the fifth transistor, I S1I is a bias current output by the sixth transistor S2 I is a bias current output by the seventh transistor S3 I is a bias current output by the eighth transistor ref V is a current output by the fourth transistor GS1 R1 is a resistance value of a resistance.

[0032] In one embodiment of the present application, the ring oscillator comprises a first differential delay unit, a second differential delay unit, a first variable capacitor, a second variable capacitor, a third variable capacitor, a fourth variable capacitor and an eleventh transistor, wherein,

[0033] a non-inverting input terminal of the first differential delay unit, an inverting output terminal of the second differential delay unit, a PLUS terminal of the first variable capacitor, a drain of the eleventh transistor are connected with a first current input terminal of the ring oscillator and output the clock signal;

[0034] an inverting input terminal of the first differential delay unit, a non-inverting output terminal of the second differential delay unit, a PLUS terminal of the second variable capacitor are connected with a fourth current input terminal of the ring oscillator;

[0035] a non-inverting output terminal of the first differential delay unit, a non-inverting input terminal of the second differential delay unit, a PLUS terminal of the third variable capacitor are connected with a third current input terminal of the ring oscillator;

[0036] an inverting output terminal of the first differential delay unit, an inverting input terminal of the second differential delay unit, a PLUS terminal of the fourth variable capacitor are connected with a second current input terminal of the ring oscillator;

[0037] a MINUS terminal of the first variable capacitor, a MINUS terminal of the second variable capacitor are connected and input a voltage signal; a MINUS terminal of the third variable capacitor, a MINUS terminal of the fourth variable capacitor are connected and input a voltage signal;

[0038] a gate of the eleventh transistor inputs the gate signal, a source is connected with a ground terminal.

[0039] In one embodiment of the present application, the first differential delay unit and the second differential delay unit are of the same structure.

[0040] In one embodiment of the present application, the first differential delay unit and the second differential delay unit each comprise a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor and a twenty-fifth transistor, wherein,

[0041] The source of the twelfth transistor, the source of the sixteenth transistor, the source of the seventeenth transistor, the source and the drain of the eighteenth transistor, the source and the drain of the nineteenth transistor, the source of the twenty-fourth transistor, and the source of the twenty-fifth transistor are connected to a ground terminal, the drain of the twelfth transistor, the drain and the gate of the thirteenth transistor, the gate of the fourteenth transistor, the gate of the fifteenth transistor, the gate of the sixteenth transistor, the drain of the seventeenth transistor, the gate of the nineteenth transistor, and the gate of the twentieth transistor are connected to an inverting output terminal of the differential delay unit, the drain of the twenty-fifth transistor, the drain and the gate of the twenty-first transistor, the gate of the twenty-second transistor, the gate of the twenty-third transistor, the gate of the twenty-fourth transistor, the drain of the twentieth transistor, the gate of the eighteenth transistor, and the gate of the seventeenth transistor are connected to a non-inverting output terminal of the differential delay unit, the source of the thirteenth transistor is connected to the drain of the fourteenth transistor, the source of the fourteenth transistor is connected to the drain of the fifteenth transistor, the source of the fifteenth transistor is connected to the drain of the sixteenth transistor, the source of the twenty-first transistor is connected to the drain of the twenty-second transistor, the source of the twenty-second transistor is connected to the drain of the twenty-third transistor, the source of the twenty-third transistor is connected to the drain of the twenty-fourth transistor, the gate of the twelfth transistor is connected to a non-inverting input terminal of the differential delay unit, and the gate of the twenty-fifth transistor is connected to an inverting input terminal of the differential delay unit.

[0042] Compared with the prior art, the present application has the following beneficial effects:

[0043] 1. The self-starting and stopping burst mode clock and data recovery circuit with temperature compensation of the embodiment can automatically start the CTAT reference current source and the ring oscillator through the digital control circuit, so that the whole circuit starts to work, and the subsequent circuit is automatically turned off after the recovery work is completed, thereby controlling the working state of the clock and data recovery circuit, automatically realizing the wake-up and sleep of the clock and data recovery circuit, avoiding long-time work of the circuit, and reducing the overall power consumption.

[0044] 2. The self-starting stop-burst mode clock and data recovery circuit with temperature compensation according to the embodiment has a clock which is not sensitive to temperature and power voltage through temperature compensation, improves the circuit robustness, reduces the circuit complexity and power consumption, and is suitable for wake-up receiver application. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1 A structure schematic diagram of the self-starting stop-burst mode clock and data recovery circuit with temperature compensation according to the embodiment is provided.

[0046] Figure 2 A structure schematic diagram of the edge detection circuit according to the embodiment is provided.

[0047] Figure 3 A timing diagram of the edge detection circuit according to the embodiment is provided.

[0048] Figure 4 A structure schematic diagram of the digital control circuit according to the embodiment is provided.

[0049] Figure 5 A structure schematic diagram of the CTAT reference current source according to the embodiment is provided.

[0050] Figure 6 A structure schematic diagram of the ring oscillator according to the embodiment is provided.

[0051] Figure 7 A structure schematic diagram of the differential delay unit according to the embodiment is provided. DETAILED DESCRIPTION

[0052] The application will be further described in detail below with specific embodiments, but the embodiments of the application are not limited thereto.

[0053] Embodiment one

[0054] The embodiment provides a self-starting stop-burst mode clock and data recovery circuit with temperature compensation, which realizes automatic wake-up and sleep through a digital control circuit, thereby reducing the circuit power consumption; the circuit realizes stable clock through a temperature-compensated ring oscillator, thereby improving the clock performance and circuit robustness; the clock and data recovery circuit is suitable for wake-up receiver application, thereby improving the stability and energy efficiency of the wake-up receiver.

[0055] Please refer to Figure 1 Figure 1 ​The structure diagram of the self-starting and stopping burst mode clock and data recovery circuit with temperature compensation provided by the embodiment of the application comprises an edge detection circuit, a digital control circuit, a CTAT reference current source, a ring oscillator, a first D flip-flop and a digital correlator.

[0056] The edge detection circuit is used for detecting the edge of the input signal DATA and generating the delay signal DATA DELAY and the enable signal EN.

[0057] Specifically, the edge detection circuit is controlled by four digital signals DS 0～3 , which controls the delay size of the internal delay unit, thereby controlling the pulse width of the output enable signal EN and outputting delay signals DATA with different delays DELAY .

[0058] The digital control circuit is used for controlling the working or not of the whole clock and data recovery circuit according to the enable signal EN and the wake-up signal WAKE_UP and outputting the gate signal (GT EN ) and the control signal (T OFF ). When the digital control circuit is in the first working state, the enable signal EN is taken as the gate signal GT EN , and the control signal T OFF is output as low level; when the digital control circuit is in the second working state, the number of the enable signal EN is recorded, and when the number of the enable signal EN is equal to the threshold of the threshold control signal EDGE_THRESHOLD 0～2 , the control signal T OFF is output as low level, the enable signal EN is taken as the gate signal GT EN , and the control signal T OFF is output as high level according to the high level pulse signal WAKE_UP.

[0059] Specifically, the digital control circuit is controlled by the enable signal EN, the high level pulse signal WAKE_UP, the reset signal RSTP, the mode control signal MDSW and the threshold control signal EDGE_THRESHOLD 0-2, and is used for controlling the working state of the whole circuit. The enable signal EN is used for generating the gate signal GT EN , controlling the whole BMCDR to start normal working, generating the recovered clock and re-timing the data; the WAKE_UP signal is used for controlling the digital control circuit to output the control signal T OFF as high level and thereby shutting down the CTAT reference current source, so as to stop the working of the ring oscillator; the reset signal RSTP is used for resetting the circuit when the circuit starts working; and the threshold control signal EDGE_THRESHOLD 0～2It is used to control the threshold for edge counting of the enable signal, and the mode control signal MDSW is used to control the working state of the digital control circuit.

[0060] CTAT reference current source, controlled by the control signal T OFF Controls whether it works or not. It is used when the control signal T OFF When the control signal T OFF It is turned off when it is high and generates a bias current I with a negative temperature coefficient when it is turned on. S0～3 , temperature compensation of the ring oscillator and control of its output frequency.

[0061] Ring oscillator, used to generate a gate signal GT EN , bias current I S0～3 And the voltage signal V CT Generates a wideband clock signal CK that is insensitive to power supply voltage and temperature, wherein the gate signal GT EN Used to gate the ring oscillator to adapt to burst mode applications, bias current IS 0～3 Used to perform temperature compensation on the ring oscillator, the voltage signal V CT Used for frequency tuning of ring oscillators.

[0062] The first D flip-flop is used to delay the signal DATA according to the clock signal CK. DELAY Sampling is performed to obtain the recovered data DATA REC .

[0063] Digital correlator for clock signal CK and bit signal B 0～5 , determine the recovery data DATA REC Compare with the preset signal WUCODE 0～15 When determining the consistency of the recovery data DATA REC Compare with the preset signal WUCODE 0～15 When they are consistent, the output pulse signal WAKE_UP is high, indicating that the wake-up is successful.

[0064] The temperature-compensated self-start-stop burst mode clock and data recovery circuit of this embodiment realizes the sleep and wake-up of the clock and data recovery circuit through the digital control circuit. Specifically, the digital control circuit is reset by the external reset signal RSTP when the circuit starts working. When the external input is detected, the edge detector generates a pulse signal EN at each input data edge. The digital control circuit records the number of pulse signals and compares it with the preset threshold EDGE_THRESHOLD. 0～2 Compare, when the threshold is reached, T OFFThe signal is set to low level, the CTAT reference current source and ring oscillator are started to work, and the clock and data recovery function is started to be realized. REC The preset comparison signal WUCODE is compared with the recovered data DATA 0～15 When the two are detected to be consistent, a high level pulse signal WAKE_UP is output, the state in the digital control circuit is cleared, and the T OFF The signal becomes high level, the CTAT reference current source and ring oscillator are turned off, and the circuit enters the sleep mode, so that the power consumption of the circuit in the sleep mode is greatly reduced.

[0065] Please refer to Figure 2 , Figure 2 The structure schematic diagram of the edge detection circuit provided by the embodiment of the application is shown.

[0066] The edge detection circuit comprises a variable delay unit and an XOR gate, wherein the input end of the variable delay unit Variable Delay is used for inputting an input signal DATA, the first control end, the second control end, the third control end and the fourth control end are used for inputting a digital control signal DS 0～3 , the output end is connected to the first input end of the XOR gate and outputs a delay signal DATA DELAY ; the second input end of the XOR gate inputs the input signal DATA, and the output end outputs an enable signal EN. Wherein, the delay width of the delay signal DATA DELAY is half of the bit width of the input signal DATA; the pulse width of the enable signal EN is half of the bit width of the input signal DATA.

[0067] Specifically, when the input signal DATA arrives, the delay of the variable delay unit is adjusted through the digital control signal DS 0～3 , so that the delay is UI / 2, and UI represents the bit width of the input signal, then the delay signal DATA DELAY is XOR operated with the input signal DATA, so that a pulse signal EN with a width of UI / 2 is generated at each data edge, as shown in Figure 3 , Figure 3 The timing diagram of the edge detection circuit provided by the embodiment of the application is shown, and the pulse signal EN is used for subsequent enable operation of the ring oscillator.

[0068] Please refer to Figure 4 , Figure 4 The structure schematic diagram of the digital control circuit provided by the embodiment of the application is shown.

[0069] The digital control circuit comprises a three-bit counter, an OR gate, a threshold detector, a second D flip-flop, an inverter, a first data selector MUX1, a second data selector MUX2 and a third data selector MUX3.

[0070] The input trigger end of the three-bit counter is connected with an enable signal EN, which is used as a trigger signal of the three-bit counter; the reset end of the three-bit counter is connected with the output end of the OR gate, which is used for clearing the state of the three-bit counter; the first output end, the second output end and the third output end of the three-bit counter are connected with the first input end, the second input end and the third input end of the threshold detector respectively.

[0071] The threshold detector has six input ends and one output end. The first to third input ends are connected with the output ends Q 0～2 of the three-bit counter, which are used for detecting the number of edges; the fourth input end, the fifth input end and the sixth input end of the threshold detector are connected with the threshold control signal EDGE_THRESHOLD 0～2 , which is used for controlling the detection threshold; and the output end is connected with the clock trigger end of the second D flip-flop.

[0072] The second D flip-flop has three input ends and one output end. The data input end D is connected with the power supply VDD, which is used for converting the short pulse signal output by the threshold detector into a long 1 signal; the reset end R is connected with the output end of the OR gate; and the output end Q is connected with the input end of the inverter.

[0073] The output end of the inverter is connected with the data selection end of the first data selector MUX1 and the first data input end of the third data selector MUX3.

[0074] The first input end of the OR gate is connected with the reset signal RSTP, and the second input end is connected with the pulse signal WAKE_UP.

[0075] The first data input end of the first data selector MUX1 is connected with the power supply VDD, the second data input end is connected with the enable signal EN, and the data output end is connected with the first data input end of the second data selector MUX2; the second data input end of the second data selector MUX2 is connected with the enable signal EN, the data selection end is connected with the mode control signal MDSW, and the data output end outputs the gate signal GT EN ; the second data input end of the third data selector MUX3 is connected with the ground end GND, the data selection end is connected with the mode control signal MDSW, and the data output end outputs the control signal T OFF .

[0076] Specifically, when the mode control signal MDSW=0, the digital control circuit is in a transparent state, and the enable signal EN output by the edge detector is directly used as the gate signal GT EN, control signal T OFF is selected as GND (i.e. low level), turning on the CTAT reference current source and ring oscillator, and the gate signal GT EN Injected into the ring oscillator to adjust the clock phase.

[0077] When the mode control signal MDSW=1, the digital control circuit works normally. At the beginning, GT EN =VDD, T OFF =1, the CTAT current source and the ring oscillator are in the off state. When the input data arrives, the three-bit counter records the number of pulse signals EN, and the threshold detector compares the counter output with the preset threshold. When the counter output reaches the threshold, the threshold detector outputs a high-level pulse, and the output of the second D flip-flop becomes high, which turns T OFF The value of becomes 0, waking up the subsequent CTAT reference current source and ring oscillator, and at the same time controlling the data selector MUX1 to pass the enable signal EN to the output. At this time, GT EN =EN, BMCDR starts to work normally.

[0078] See Figure 5 , Figure 5 A schematic diagram of the structure of a CTAT reference current source provided by an embodiment of the present invention.

[0079] The CTAT reference current source includes a first transistor MP1, a second transistor MP2, a third transistor MP3, a fourth transistor MP4, a fifth transistor MP5, a sixth transistor MP6, a seventh transistor MP7, an eighth transistor MP8, a ninth transistor MP9, a tenth transistor MN1, a resistor R1 and an operational amplifier, wherein:

[0080] The source of the first transistor MP1, the source of the second transistor MP2, the source of the third transistor MP3, the source of the fourth transistor MP4, the source of the fifth transistor MP5, the source of the sixth transistor MP6, the source of the seventh transistor MP7, the source of the eighth transistor MP8 and the drain of the ninth transistor MP9 are connected; the gate of the ninth transistor MP9 is input with the control signal T OFFThe source of the ninth transistor MP9 is connected with the power voltage VDD; the gate of the first transistor MP1, the source of the tenth transistor MN1 and one end of the resistor R1 are connected with the ground terminal GND; the drain of the first transistor MP1 is connected with the gate of the second transistor MP2; the drain of the second transistor MP2, the drain of the third transistor MP3, the positive input terminal of the operational amplifier, the gate of the tenth transistor MN1 and the drain of the tenth transistor MN1 are connected, the gate of the third transistor MP3, the gate of the fourth transistor MP4, the gate of the fifth transistor MP5, the gate of the sixth transistor MP6, the gate of the seventh transistor MP7, the gate of the eighth transistor MP8 and the output terminal of the operational amplifier are connected, the drain of the fourth transistor MP4, the reverse input terminal of the operational amplifier and the other end of the resistor R1 are connected, the drain of the fifth transistor MP5, the drain of the sixth transistor MP6, the drain of the seventh transistor MP7 and the drain of the eighth transistor MP8 output the bias current I S0～3 and are connected with the first current input terminal, the second current input terminal, the third current input terminal and the fourth current input terminal of the ring oscillator respectively.

[0081] Specifically, in order to obtain the CTAT current, it is required that the tenth transistor MN1 in the CTAT reference current source is in the sub-threshold region. The source-drain current expression of the MOS transistor in the sub-threshold region is:

[0082]

[0083] wherein I is the source-drain current of the MOS transistor in the sub-threshold region, Figure 4 I S0 ~I S3 are the sub-threshold region currents obtained by mirroring, formula 1 is applicable to both PMOS type and NMOS type transistors; I0 is the unit saturation current; V T ≈26mV at normal temperature; ξ is the sub-threshold slope factor, ξ=2, which is related to the process parameters and the size of the transistor; V GS is the difference between the gate voltage and the source voltage of the MOS transistor in the sub-threshold region; V DS is the difference between the drain voltage and the source voltage of the MOS transistor in the sub-threshold region, W is the gate width of the transistor, and L is the gate length of the transistor.

[0084] Since the channel length of the transistor in the embodiment is long enough, there is no substrate bias effect, and |V DS | is much larger than V T Therefore, the source-drain current expression of the MOS transistor in the sub-threshold region can be simplified as:

[0085]

[0086] The gate-source voltage V GSVth TH satisfies a temperature-dependent function:

[0087]

[0088] wherein T0 is room temperature = 300K, threshold voltage V TH T can be written as:

[0089] V TH (T) = V TH (T0) + K T (T / T0-1) (4)

[0090] wherein K T is a negative number.

[0091] Using equations (3) and (4), V GS can be expressed as:

[0092]

[0093] Since K T +V GS (T0) - V TH (T0) is usually negative, V GS T decreases with the increase of temperature, having a CTAT characteristic.

[0094] Due to the virtual short characteristic of the operational amplifier, the voltage at the positive input terminal is basically the same as that at the negative input terminal, and the gate-source voltage of MN1 is denoted as V GS1 , and the resistance R1 is a ZTAT resistance, so that I ref can be written as:

[0095]

[0096] As can be seen from equation (6), when the temperature rises, V GS1 T decreases, and I ref T also decreases, thereby obtaining a CTAT current.

[0097] Through the mirror tubes M P5 , M P6 , M P7 , M P8 , I ref is copied, that is used to connect a subsequent ring oscillator.

[0098] It can be seen that the CTAT reference current source in the embodiment can generate a bias current with a negative temperature coefficient.

[0099] Please refer to Figure 6 , Figure 6A structure schematic diagram of the ring oscillator provided by the embodiment of the present application is shown.

[0100] The ring oscillator comprises a first differential delay unit DLY1, a second differential delay unit DLY2, a first variable capacitor C1, a second variable capacitor C2, a third variable capacitor C3, a fourth variable capacitor C4 and an eleventh transistor MN2.

[0101] The positive phase input end VP of the first differential delay unit DLY1, the inverting output end VON of the second differential delay unit DLY2, the PLUS end of the first variable capacitor C1 and the drain of the eleventh transistor MN2 are connected with the first current input end of the ring oscillator and output a clock signal CK; the inverting input end VN of the first differential delay unit DLY1, the positive output end VOP of the second differential delay unit DLY2 and the PLUS end of the second variable capacitor C2 are connected with the fourth current input end of the ring oscillator; the positive output end VOP of the first differential delay unit DLY1, the positive input end VP of the second differential delay unit DLY2 and the PLUS end of the third variable capacitor C3 are connected with the third current input end of the ring oscillator; the inverting output end VON of the first differential delay unit DLY1, the inverting input end VN of the second differential delay unit DLY2 and the PLUS end of the fourth variable capacitor C4 are connected with the second current input end of the ring oscillator; the MINUS end of the first variable capacitor C1 and the MINUS end of the second variable capacitor C2 are connected and input a voltage signal V CT ; the MINUS end of the third variable capacitor C3 and the MINUS end of the fourth variable capacitor C4 are connected and input a voltage signal V CT ; the gate of the eleventh transistor MN2 inputs a gate signal GT EN , and the source is connected with the ground end.

[0102] Specifically, the ring oscillator of the embodiment adopts a two-stage differential delay unit structure, and each stage provides a phase shift of 90°. In order to ensure that the ring oscillator can oscillate stably, the output end of the first differential delay unit DLY1 is connected in phase with the input end of the second differential delay unit DLY2, and the output end of the second differential delay unit DLY2 is connected reversely with the input end of the first differential delay unit DLY1, so that the two-stage differential delay units generate a phase shift of 180° together.

[0103] Specifically, the first differential delay unit DLY1 and the second differential delay unit DLY2 have the same structure.

[0104] Please refer to Figure 7 , Figure 7 A structure schematic diagram of the differential delay unit provided by the embodiment of the present application is shown.

[0105] The first differential delay unit DLY1 and the second differential delay unit DLY2 each include a twelfth transistor MN3, a thirteenth transistor MN4, a fourteenth transistor MN5, a fifteenth transistor MN6, a sixteenth transistor MN7, a seventeenth transistor MN8, an eighteenth transistor MN9, a nineteenth transistor MN10, a twentieth transistor MN11, a twenty-first transistor MN12, a twenty-second transistor MN13, a twenty-third transistor MN14, a twenty-fourth transistor MN15, and a twenty-fifth transistor MN16.

[0106] The source of the twelfth transistor MN3, the source of the sixteenth transistor MN7, the source of the seventeenth transistor MN8, the source and the drain of the eighteenth transistor MN9, the source and the drain of the nineteenth transistor MN10, the source of the twenty-fourth transistor MN15, and the source of the twenty-fifth transistor MN16 are connected to a ground terminal. The drain of the twelfth transistor MN3, the drain and the gate of the thirteenth transistor MN4, the gate of the fourteenth transistor MN5, the gate of the fifteenth transistor MN6, the gate of the sixteenth transistor MN7, the drain of the seventeenth transistor MN8, the gate of the nineteenth transistor MN10, and the gate of the twentieth transistor MN11 are connected to an inverting output terminal VON of the differential delay unit. The drain of the twenty-fifth transistor MN16, the drain and the gate of the twenty-first transistor MN12, the gate of the twenty-second transistor MN13, the gate of the twenty-third transistor MN14, the gate of the twenty-fourth transistor MN15, the drain of the twentieth transistor MN11, the gate of the eighteenth transistor MN9, and the gate of the seventeenth transistor MN8 are connected to a non-inverting output terminal VOP of the differential delay unit. The source of the thirteenth transistor MN4 is connected to the drain of the fourteenth transistor MN5. The source of the fourteenth transistor MN5 is connected to the drain of the fifteenth transistor MN6. The source of the fifteenth transistor MN6 is connected to the drain of the sixteenth transistor MN7. The source of the twenty-first transistor MN12 is connected to the drain of the twenty-second transistor MN13. The source of the twenty-second transistor MN13 is connected to the drain of the twenty-third transistor MN14. The source of the twenty-third transistor MN14 is connected to the drain of the twenty-fourth transistor MN15. The gate of the twelfth transistor MN3 is connected to a non-inverting input terminal VP of the differential delay unit. The gate of the twenty-fifth transistor MN16 is connected to an inverting input terminal VN of the differential delay unit.

[0107] In this embodiment, the CTAT reference current source realizes the CTAT current at low voltage through the CTAT characteristic of the gate-source voltage of the NMOS tube when it operates in the subthreshold region and the clamping operational amplifier, thereby compensating for the PTAT characteristic of the output clock frequency of the ring oscillator, thereby obtaining a clock that is insensitive to temperature. At the same time, the ring oscillator adopts an all-NMOS structure and has the characteristic of being insensitive to the power supply voltage. The clock that is insensitive to power supply and temperature avoids the use of a phase-locked loop in a traditional CDR, reduces power consumption and design complexity, and does not require an additional reference clock, making the BMCDR suitable for wake-up receiver applications.

[0108] As an optional implementation, the first D flip-flop and the digital correlator may be implemented using an existing conventional circuit framework, which will not be described in detail in this embodiment.

[0109] The temperature-compensated, self-start / stop, ultra-low-power clock and data recovery circuit of this embodiment automatically starts the CTAT reference current source and ring oscillator through a digital control circuit, and the entire circuit starts working. After the recovery work is completed, the subsequent circuits are automatically shut down, realizing the wake-up and sleep of the BMCDR, avoiding long-term operation of the circuit, improving the working efficiency of the BMCDR, and significantly reducing the power consumption of the BMCDR; the positive temperature coefficient of the ring oscillator is compensated by the negative temperature coefficient of the CTAT reference current source, making the ring oscillator insensitive to temperature changes, and obtaining a clock that is insensitive to temperature and power supply voltage, avoiding the overhead of an additional reference clock, improving circuit robustness, and reducing circuit complexity and power consumption; this burst mode BMCDR is suitable for wake-up receiver architecture, which can effectively reduce the overall power consumption of the receiver and improve the robustness of the receiver.

[0110] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A self-starting stop-and-go burst mode clock and data recovery circuit with temperature compensation, comprising: Comprising: an edge detection circuit, a digital control circuit, a CTAT reference current source, a ring oscillator, a first D flip-flop and a digital correlator, wherein, The edge detection circuit is used for detecting the edge of the input signal (DATA) and generating a delay signal (DATA DELAY ) and an enable signal (EN). The digital control circuit is used to control the working state of the clock and data recovery circuit according to the enable signal (EN) and the pulse signal (WAKE_UP), and output the gating signal (GT EN ) and control signal (T OFF ); The CTAT reference current source is used to start or stop according to the control signal (T OFF ) and generate a bias current (I S0～3 ) with negative temperature coefficient when starting. the ring oscillator is configured to generate a clock signal (CK) that is insensitive to power supply voltage and temperature from the gate signal (GT EN ), the bias current (I S0～3 ), and the voltage signal (V CT ). The first D flip-flop is used for sampling the delay signal (DATA DELAY ) according to the clock signal (CK) to obtain recovered data (DATA REC ); The digital correlator is configured to output the pulse signal (WAKE_UP) as a high level when it is judged that the recovered data (DATA REC ) is consistent with a preset comparison signal (WUCODE 0～15 ). The digital control circuit comprises a three-bit counter, an OR gate, a threshold detector, a second D flip-flop, an inverter, a first data selector (MUX1), a second data selector (MUX2) and a third data selector (MUX3), wherein an input trigger end of the three-bit counter inputs the enable signal (EN), a reset end is connected to an output end of the OR gate, a first output end, a second output end and a third output end are correspondingly connected to a first input end, a second input end and a third input end of the threshold detector; a fourth input end, a fifth input end and a sixth input end of the threshold detector input a threshold control signal (EDGE_THRESHOLD 0～2 ), and an output end is connected to a clock trigger end of the second D flip-flop; a data input end of the second D flip-flop is connected to a power supply (VDD), a reset end is connected to an output end of the OR gate, and an output end is connected to an input end of the inverter; an output end of the inverter is connected to a data selection end of the first data selector (MUX1) and a first data input end of the third data selector (MUX3); a first input end of the OR gate inputs a reset signal (RSTP), and a second input end inputs the pulse signal (WAKE_UP); a first data input end of the first data selector (MUX1) is connected to the power supply (VDD), a second data input end inputs the enable signal (EN), and a data output end is connected to a first data input end of the second data selector (MUX2); a second data input end of the second data selector (MUX2) inputs the enable signal (EN), a data selection end inputs a mode control signal (MDSW), and a data output end outputs the gate signal (GT EN ); a second data input end of the third data selector (MUX3) is connected to a ground end (GND), a data selection end inputs the mode control signal (MDSW), and a data output end outputs the control signal (T OFF ); When the mode control signal (MDSW) is 0, the enable signal EN output by the edge detector is the gate signal (GT EN ) output by the digital control circuit, the control signal (T OFF ) is low, the CTAT reference current source is turned on and the ring oscillator is turned on, the gate signal (GT EN ) is injected into the ring oscillator, and the adjustment of the clock phase is realized. When the mode control signal MDSW = 1, the digital control circuit works normally, at the beginning GT EN = VDD, T OFF = 1, the CTAT reference current source and the ring oscillator are in the off state, when the input data comes, the three-bit counter records the number of pulse signals (EN), the threshold detector compares the output of the counter with the pre-set threshold, when the output of the counter reaches the threshold, the threshold detector outputs a high level pulse, the output of the second D flip-flop becomes high, the value of the control signal (T OFF ) becomes 0, and the subsequent CTAT reference current source and the ring oscillator are awakened, at the same time, the first data selector (MUX1) is controlled to transmit the enable signal (EN) to the output, at this time, the gate signal (GT EN ) is equal to the enable signal (EN), and the burst mode clock and data recovery circuit starts to work normally.

2. The self-starting stop-and-go burst mode clock and data recovery circuit with temperature compensation of claim 1, wherein, the edge detection circuit comprises: a variable delay unit (Variable Delay) and an XOR gate (XOR), wherein, The input end of the variable delay unit is used for inputting the input signal (DATA), the first control end, the second control end, the third control end and the fourth control end are used for inputting a digital control signal (DS 0～3 ), and the output end is connected with the first input end of the XOR gate and outputs the delay signal (DATA DELAY ). the second input terminal of the XOR gate (XOR) inputs the input signal (DATA), and the output terminal outputs the enable signal (EN).

3. The self-starting stop-and-go burst mode clock and data recovery circuit with temperature compensation of claim 2, wherein, the delay width of the delay signal (DATA DELAY ) is half of one bit width of the input signal (DATA) The pulse width of the enable signal (EN) is half of the bit width of the input signal (DATA).

4. The self-starting stop-and-go burst mode clock and data recovery circuit with temperature compensation of claim 1, wherein, The CTAT reference current source comprises a first transistor (MP1), a second transistor (MP2), a third transistor (MP3), a fourth transistor (MP4), a fifth transistor (MP5), a sixth transistor (MP6), a seventh transistor (MP7), an eighth transistor (MP8), a ninth transistor (MP9), a tenth transistor (MN1), a resistor (R1) and an operational amplifier, wherein, The source of the first transistor (MP1), the source of the second transistor (MP2), the source of the third transistor (MP3), the source of the fourth transistor (MP4), the source of the fifth transistor (MP5), the source of the sixth transistor (MP6), the source of the seventh transistor (MP7), the source of the eighth transistor (MP8) and the drain of the ninth transistor (MP9) are connected; the gate of the ninth transistor (MP9) inputs the control signal (T OFF ), the source of the ninth transistor (MP9) is connected with the power supply voltage (VDD); the gate of the first transistor (MP1), the source of the tenth transistor (MN1) and one end of the resistor (R1) are connected with the ground terminal (GND); The drain of the first transistor (MP1) is connected to the gate of the second transistor (MP2); the drain of the second transistor (MP2), the drain of the third transistor (MP3), the positive input of the operational amplifier, the gate of the tenth transistor (MN1), the drain of the tenth transistor (MN1) are connected, the gate of the third transistor (MP3), the gate of the fourth transistor (MP4), the gate of the fifth transistor (MP5), the gate of the sixth transistor (MP6), the gate of the seventh transistor (MP7), the gate of the eighth transistor (MP8), the output of the operational amplifier are connected, the drain of the fourth transistor (MP4), the negative input of the operational amplifier, the other end of the resistor (R1) are connected, the drain of the fifth transistor (MP5), the drain of the sixth transistor (MP6), the drain of the seventh transistor (MP7), the drain of the eighth transistor (MP8) output the bias current (I S0～3 ) and are connected to the first current input, the second current input, the third current input, the fourth current input of the ring oscillator respectively.

5. The self-starting stop-and-go burst mode clock and data recovery circuit with temperature compensation of claim 4, wherein, The expression of the bias current (I S0～3 ) is: where I S0 is a bias current output from the fifth transistor (MP5), I S1 is a bias current output from the sixth transistor (MP6), I S2 is a bias current output from the seventh transistor (MP7), I S3 is a bias current output from the eighth transistor (MP8), I ref (T) is a current output from the fourth transistor (MP4), V GS1 (T) is a gate-source voltage of the tenth transistor (MN1), and R1 is a resistance value of the resistor (R1).

6. The self-starting stop-and-go burst mode clock and data recovery circuit with temperature compensation of claim 1, wherein, The ring oscillator comprises a first differential delay unit (DLY1), a second differential delay unit (DLY2), a first variable capacitor (C1), a second variable capacitor (C2), a third variable capacitor (C3), a fourth variable capacitor (C4) and an eleventh transistor (MN2), wherein, the non-inverting input terminal (VP) of the first differential delay unit (DLY1), the inverting output terminal (VON) of the second differential delay unit (DLY2), the PLUS terminal of the first variable capacitor (C1), and the drain of the eleventh transistor (MN2) are connected to the first current input terminal of the ring oscillator and output the clock signal (CK); the inverting input terminal (VN) of the first differential delay unit (DLY1), the non-inverting output terminal (VOP) of the second differential delay unit (DLY2), and the PLUS terminal of the second variable capacitor (C2) are connected to the fourth current input terminal of the ring oscillator; the non-inverting output terminal (VOP) of the first differential delay unit (DLY1), the non-inverting input terminal (VP) of the second differential delay unit (DLY2), and the PLUS terminal of the third variable capacitor (C3) are connected to the third current input terminal of the ring oscillator; the inverting output terminal (VON) of the first differential delay unit (DLY1), the inverting input terminal (VN) of the second differential delay unit (DLY2), and the PLUS terminal of the fourth variable capacitor (C4) are connected to the second current input terminal of the ring oscillator; the MINUS terminal of said first variable capacitor (C1), the MINUS terminal of said second variable capacitor (C2) are connected and input a voltage signal (V CT ); the MINUS terminal of said third variable capacitor (C3), the MINUS terminal of said fourth variable capacitor (C4) are connected and input a voltage signal (V CT ); The gate of the eleventh transistor (MN2) inputs the gate signal (GT EN ), and the source is connected to a ground terminal.

7. The self-starting stop-and-go burst mode clock and data recovery circuit with temperature compensation of claim 6, wherein, The first differential delay unit (DLY1) and the second differential delay unit (DLY2) have the same structure.

8. The self-starting stop-and-go burst mode clock and data recovery circuit with temperature compensation of claim 7, wherein, The first differential delay unit (DLY1) and the second differential delay unit (DLY2) each comprise a twelfth transistor (MN3), a thirteenth transistor (MN4), a fourteenth transistor (MN5), a fifteenth transistor (MN6), a sixteenth transistor (MN7), a seventeenth transistor (MN8), an eighteenth transistor (MN9), a nineteenth transistor (MN10), a twentieth transistor (MN11), a twenty-first transistor (MN12), a twenty-second transistor (MN13), a twenty-third transistor (MN14), a twenty-fourth transistor (MN15) and a twenty-fifth transistor (MN16), wherein, The source of the twelfth transistor (MN3), the source of the sixteenth transistor (MN7), the source of the seventeenth transistor (MN8), the source and the drain of the eighteenth transistor (MN9), the source and the drain of the nineteenth transistor (MN10), the source of the twenty-fourth transistor (MN15), the source of the twenty-fifth transistor (MN16) are connected to a ground terminal, the drain of the twelfth transistor (MN3), the drain and the gate of the thirteenth transistor (MN4), the gate of the fourteenth transistor (MN5), the gate of the fifteenth transistor (MN6), the gate of the sixteenth transistor (MN7), the drain of the seventeenth transistor (MN8), the gate of the nineteenth transistor (MN10), the gate of the twentieth transistor (MN11) are connected to an inverting output terminal (VON) of the differential delay unit, the drain of the twenty-fifth transistor (MN16), the drain and the gate of the twenty-first transistor (MN12), the gate of the twenty-second transistor (MN13), the gate of the twenty-third transistor (MN14), the gate of the twenty-fourth transistor (MN15), the drain of the twentieth transistor (MN11), the gate of the eighteenth transistor (MN9), the gate of the seventeenth transistor (MN8) are connected to a non-inverting output terminal (VOP) of the differential delay unit, the source of the thirteenth transistor (MN4) is connected to the drain of the fourteenth transistor (MN5), the source of the fourteenth transistor (MN5) is connected to the drain of the fifteenth transistor (MN6), the source of the fifteenth transistor (MN6) is connected to the drain of the sixteenth transistor (MN7), the source of the twenty-first transistor (MN12) is connected to the drain of the twenty-second transistor (MN13), the source of the twenty-second transistor (MN13) is connected to the drain of the twenty-third transistor (MN14), the source of the twenty-third transistor (MN14) is connected to the drain of the twenty-fourth transistor (MN15), the gate of the twelfth transistor (MN3) is connected to a non-inverting input terminal (VP) of the differential delay unit, the gate of the twenty-fifth transistor (MN16) is connected to an inverting input terminal (VN) of the differential delay unit.

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