A mutual calibration method applied to an ADC differential capacitor array

Abstract

The application belongs to the technical field of integrated circuit design, and discloses a mutual calibration method applied to an ADC differential capacitor array, which comprises the following steps: step 1, extraction and quantification of error voltage of each capacitor in the CDAC capacitor array; and step 2, addition of corresponding error code value in the output code value of the ADC. The calibration method disclosed by the application removes the additional calibration CDAC in the traditional analog calibration method, significantly reduces the capacitor area, combines the error code value and the normal quantization code value of the ADC to obtain the final output code value, and the operation process can be operated on-chip or off-chip, thereby reducing the complexity of circuit design and significantly reducing the loss of ADC conversion precision caused by the mismatch of the capacitor array.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuit design, and particularly relates to a mutual calibration method applied to an ADC differential capacitor array. BACKGROUND

[0002] Generally, a CDAC (capacitor digital-to-analog converter) composed of a capacitor array is required to be very high in a design of a high-precision ADC (analog-to-digital converter) with more than 12 bits, and a capacitor manufactured by a current integrated circuit process is difficult to meet the stringent mismatch requirement. Traditionally, a method of increasing a capacitor area to reduce a relative mismatch of the capacitor is very inefficient and cannot be applied to the design of the high-precision ADC. Therefore, in order to solve the mismatch problem of the capacitor in the high-precision ADC, many calibration methods of the ADC have been proposed by predecessors. Current ADC calibration methods mainly include an analog domain calibration algorithm and a digital domain calibration algorithm. The analog domain calibration algorithm is mainly a self-calibration algorithm, which adds a calibration CDAC capacitor array to a main CDAC capacitor array. The working principle is that an error voltage caused by a mismatch of each capacitor in the main CDAC is quantized into a digital code value through the calibration CDAC by a specific capacitor flipping sequence, and a mismatch code value of each capacitor is stored in a RAM. In an ADC normal conversion process, the mismatch code value of each capacitor is read from the RAM, and the error voltage is re-compensated into the main CDAC capacitor array through the calibration CDAC capacitor array to complete the calibration. The digital domain calibration algorithm mainly adjusts a weight of each capacitor in the main CDAC to complete the calibration process, and mainly includes a "perturbation" algorithm and a "split" ADC algorithm. The "perturbation" algorithm adds a "positive" perturbation signal and a "negative" perturbation signal to an input signal of the ADC respectively to obtain an output code value of the ADC, and then adjusts a weight of the ADC code value in a digital domain through an LMS (least mean square algorithm) algorithm to complete the calibration process. The "split" ADC is to quantize an input signal through two ADCs respectively, and adjusts a weight of the ADC code value in the digital domain through an LMS algorithm to complete the calibration process.

[0003] Although the calibration method described above can improve the accuracy of the ADC, its disadvantages are also very obvious, for example, the analog self-calibration technology needs to add a calibration CDAC capacitor array, which occupies a very large layout area in the integrated circuit manufacturing process, and the error code value of the capacitor array needs to be frequently read from the RAM during the normal conversion process of the ADC, which requires a large number of adder resources and the algorithm can only run on the chip and cannot be moved off the chip, which increases the cost of the chip in manufacturing and use. The calibration algorithm in the digital domain mainly uses the LMS algorithm, and the calibration algorithm in the digital domain usually increases the hardware overhead, such as the "split" algorithm which needs two ADCs to quantize the input signal, and the LMS algorithm parameters are not designed properly, which can cause the algorithm to not converge and cause calibration failure, which needs to be carefully adjusted, and the LMS algorithm needs a long correction time to complete the calibration, which limits the application field of the algorithm. SUMMARY

[0004] The present application aims to provide a mutual calibration method applied to the differential capacitor array of an ADC to solve the above technical problems.

[0005] To solve the above technical problems, the specific technical scheme of the mutual calibration method applied to the differential capacitor array of an ADC is as follows:

[0006] A mutual calibration method applied to the differential capacitor array of an ADC, the differential capacitor array of the ADC includes two capacitors Cu, one capacitor Cu is connected in parallel with capacitors C1, P~C13, P at both ends, the other capacitor Cu is connected in parallel with capacitors C1, N~C13, N at both ends, the two capacitors Cu are connected through switches S5 and S6 to connect capacitors Cal, C8, P~C13, P, one end of the capacitors C8, P~C13, P is connected to the positive end of a comparator through a switch S1, and the other end is connected to Vip, Vrefp, Vrefn, and Vcm through switches, respectively; one end of the capacitors C1, P~C7, P is connected to Cu, and the other end is connected to Vip, Vrefp, Vrefn, and Vcm through switches, respectively; one end of the capacitors C8, N~C13, N is connected to the negative end of a comparator through a switch S2, and the other end is connected to Vin, Vrefp, Vrefn, and Vcm through switches, respectively; one end of the capacitors C1, N~C7, N is connected to Cu, and the other end is connected to Vin, Vrefp, Vrefn, and Vcm through switches, respectively; the positive and negative ends of the comparator are connected to Vcm through switches S3 and S4, respectively; the method comprises the following steps:

[0007] Step 1: Extraction and quantization of error voltage of each capacitor in the CDAC capacitor array; after power-on, the calibration process of the CDAC is performed first, and then the normal quantization process of the ADC is performed;

[0008] Step 2: Adding the corresponding error code value to the output code value of the ADC.

[0009] Further, the step 1 comprises the following steps:

[0010] Step 1.1: First, calibrate the highest bit capacitor C13,P of the positive capacitor array of the comparator: switches S1, S3, S4, S5, S6 are closed, S2 is disconnected, at this time the negative terminal of the comparator is connected to Vcm and the positive terminal of the comparator is connected to the capacitor array, at the same time the lower plate of the highest bit capacitor C13,P of the positive capacitor array of the comparator is connected to Vrefn, and the lower plate of other bit capacitors C1,P~C12,P is connected to Vrefp.

[0011] Step 1.2: Switch S3 is disconnected, and the states of switches S1, S2, S4, S5, S6 remain unchanged, at the same time the lower plate of the highest bit capacitor C13,P of the positive capacitor array of the comparator is connected to Vrefp, and the lower plate of other bit capacitors C1,P~C12,P is connected to Vrefn; this process completes the error voltage extraction of the highest bit capacitor C13,P of the positive terminal of the comparator.

[0012] Step 1.3: The error voltage is quantized by switching the lower plate of the negative capacitor C1,N~C13,N of the comparator, and the quantized code value is stored in the RAM. After the error voltage of the highest bit capacitor C13,P of the positive terminal of the comparator is quantized, the lower plate of the capacitor C13,P is connected to Vrefn and remains unchanged in the subsequent process.

[0013] Further, the step 1 comprises step 1.4: quantize the error voltage of other bit capacitors C1,P~C12,P in the same way as steps 1.1-1.3 and store them in the RAM.

[0014] Further, the step 1 comprises step 1.5: after the positive terminal capacitor is quantized, the negative terminal capacitor is quantized in the same way as steps 1.1-1.4.

[0015] Further, the step 2 comprises: after the calibration process is completed and the normal conversion process of the ADC is started to obtain the output code, if the code value of the bit capacitor is 1, the error code value of the bit is added, and if it is 0, the error code value of the bit capacitor is not added, and the ADC output code value added with the error code value is taken as the final conversion output code value.

[0016] The mutual calibration method applied to the ADC differential capacitor array has the following advantages: the calibration method provided by the application removes the extra calibration CDAC in the traditional analog calibration method, significantly reduces the capacitor area, and combines the error code value and the normal quantization code value of the ADC to obtain the final output code value. The operation process can be run on-chip or operated on the off-chip software, so that the calibration method provided by the application reduces the complexity of circuit design and significantly reduces the loss of ADC conversion precision caused by capacitor array mismatch. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 It is a schematic diagram of a 14-bit ADC differential capacitor array structure;

[0018] Figure 2 It is a flowchart of the calibration method provided by the application;

[0019] Figure 3 It is a comparison diagram of the results before and after calibration of a 14-bit ADC under the condition that the relative mismatch error of the capacitor is 1%. DETAILED DESCRIPTION

[0020] In order to better understand the purpose, structure and function of the application, the mutual calibration method applied to the ADC differential capacitor array will be further described in detail below in combination with the drawings.

[0021] This embodiment takes the calibration process of a 14-bit ADC differential capacitor array as an example for illustration. As shown in the figure, Figure 1 a 14-bit ADC differential capacitor array includes two capacitors Cu, one capacitor Cu is connected in parallel with capacitors C1, P~C13, P at both ends, and the other capacitor Cu is connected in parallel with capacitors C1, N~C13, N at both ends. The capacitors Cu are connected through switches S5 and S6 to connect capacitors Cal, C8, P~C13, P at one end, and the other end is connected to the positive terminal of the comparator through the switch S1, and the other end is connected to the Vip, Vrefp, Vrefn, Vcm terminal through the switch, respectively. The capacitors C1, P~C7, P are connected to Cu at one end, and the other end is connected to the Vin, Vrefp, Vrefn, Vcm terminal through the switch, respectively. The capacitors C8, N-C13, N are connected to the negative terminal of the comparator through the switch S2 at one end, and the other end is connected to the Vin, Vrefp, Vrefn, Vcm terminal through the switch, respectively. The capacitors C1, N-C7, N are connected to Cu at one end, and the other end is connected to the Vin, Vrefp, Vrefn, Vcm terminal through the switch, respectively. The positive and negative terminals of the comparator are connected to Vcm through switches S3 and S4, respectively.

[0022] As shown in the figure, Figure 2 The mutual calibration method applied to the ADC differential capacitor array includes the following steps:

[0023] Step 1: Extraction and quantization of error voltage of each capacitor in CDAC capacitor array;

[0024] After power-up, the calibration process of CDAC is performed first, and then the normal quantization process of ADC is performed.

[0025] Step 1.1: First, calibrate the highest bit capacitor (C13, P) of the positive terminal capacitor array of the comparator: switches S1, S3, S4, S5, S6 are closed, S2 is disconnected, at this time the negative terminal of the comparator is connected to Vcm and the positive terminal of the comparator is connected to the capacitor array, at the same time the lower plate of the highest bit capacitor (C13, P) in the positive terminal capacitor array of the comparator is connected to Vrefn, and the lower plate of other bit capacitors (C1, P~C12, P) is connected to Vrefp.

[0026] Step 1.2: Switch S3 is disconnected, and the states of switches S1, S2, S4, S5, S6 remain unchanged, at the same time the lower plate of the highest bit capacitor (C13, P) in the positive terminal capacitor array of the comparator is connected to Vrefp, and the lower plate of other bit capacitors (C1, P~C12, P) is connected to Vrefn; this process completes the extraction of error voltage of the highest bit capacitor (C13, P) in the positive terminal of the comparator.

[0027] Step 1.3: Quantize the error voltage by switching the lower plate of the negative terminal capacitor (C1, N~C13, N) of the comparator, and store the quantized code value in the RAM, after the error voltage quantization of the highest bit capacitor (C13, P) in the positive terminal of the comparator is completed, the lower plate of C13, P is connected to Vrefn and remains unchanged in the subsequent process,

[0028] Step 1.4: Complete the error voltage quantization of other bits (C1, P~C12, P) and store them in the RAM in the same way as steps 1.1-1.3.

[0029] Step 1.5: After the quantization of the positive terminal capacitor is completed, complete the quantization process of the negative terminal capacitor in the same way as steps 1.1-1.4.

[0030] Step 2: Add the corresponding error code value to the output code value of the ADC.

[0031] After the calibration process is completed, the normal conversion process of the ADC is started to obtain the output code, if the code value of the bit capacitor is 1, the error code value of the bit capacitor is added, and if the code value is 0, the error code value of the bit capacitor is not added, and the ADC output code value added with the error code value is taken as the final conversion output code value.

[0032] The above process completes the ADC calibration process and conversion process. The extraction principle of the capacitor error voltage can refer to the prior art method.

[0033] As shown in Figure 3 The calibration method proposed in the application removes the additional calibration CDAC in the conventional analog calibration method, significantly reduces the capacitor area, and combines the error code value and the normal quantization code value of the ADC to obtain the final output code value. The operation process can be run on-chip or operated on the software off-chip, so that the proposed calibration method reduces the complexity of circuit design and significantly reduces the loss of ADC conversion precision caused by capacitor array mismatch.

[0034] It can be understood that the application is described by some embodiments, and those skilled in the art know that various changes or equivalent replacements can be made to the features and embodiments without departing from the spirit and scope of the application. In addition, under the guidance of the application, the features and embodiments can be modified to adapt to specific conditions and materials without departing from the spirit and scope of the application. Therefore, the application is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of the application are within the scope of the application.

Claims

1. A mutual calibration method for an ADC differential capacitor array, wherein the ADC differential capacitor array includes two capacitors Cu, one capacitor Cu is connected in parallel with capacitors C1, P~C13, P, and the other capacitor Cu is connected in parallel with capacitors C1, N~C13, N. The two capacitors Cu are connected to capacitor Cal, capacitors C8, P~C13, P at one end through switch S1, and capacitors C1, P~C7, P at the other end through switch S1, which can be connected to Vip, Vrefp, Vrefn, and Vcm respectively. One end of capacitor C8 is connected to Cu, and the other end can be connected to Vip, Vrefp, Vrefn, and Vcm respectively via switches; one end of capacitor C8 (N-C13) is connected to the negative terminal of the comparator via switch S2, and the other end can be connected to Vin, Vrefp, Vrefn, and Vcm respectively via switches; one end of capacitor C1 (N-C7) is connected to Cu, and the other end can be connected to Vin, Vrefp, Vrefn, and Vcm respectively via switches; the positive and negative terminals of the comparator are connected to Vcm respectively via switches S3 and S4; Its characteristic is that... The method includes the following steps: Step 1: Extraction and quantization of the error voltage of each capacitor in the CDAC capacitor array; after power-on, the CDAC calibration process is performed first, and then the normal quantization process of the ADC is performed. Step 1.1: First, calibrate the highest-order capacitor C13,P in the comparator's positive terminal capacitor array: close switches S1, S3, S4, S5, and S6, and open switch S2. At this time, the negative terminal of the comparator is connected to Vcm, and the positive terminal of the comparator is connected to the capacitor array. At the same time, the lower plates of the capacitor array C1,N to C13,N in the negative terminal of the comparator are all connected to Vcm. The lower plate of the highest-order capacitor C13,P in the capacitor array of the positive terminal of the comparator is connected to Vrefn, while the lower plates of the other capacitors C1,P to C12,P are connected to Vrefp. Step 1.2: Switch S3 is open, while the states of switches S1, S2, S4, S5, and S6 remain unchanged. At the same time, the lower plate of the highest-order capacitor C13,P in the comparator's positive terminal capacitor array is connected to Vrefp, while the lower plates of the other capacitors C1,P to C12,P are connected to Vrefn. This process completes the extraction of the error voltage of the highest-order capacitor C13,P at the positive terminal of the comparator. Step 1.3: The error voltage is quantized by switching the lower plate of capacitors C1,N~C13,N at the negative terminal of the comparator, and the quantized code value is stored in RAM. After the error voltage of the highest bit capacitor C13,P at the positive terminal of the comparator is quantized, the lower plate of capacitor C13,P is connected to Vrefn and remains unchanged in the subsequent process. Step 1.4: Perform the error voltage quantization of other bit capacitors C1,P~C12,P in the same way as steps 1.1-1.3 and store them in RAM; Step 1.5: After the positive terminal capacitor of the comparator is quantized, the quantization process of the negative terminal capacitor is completed in the same way as in steps 1.1-1.4; Step 2: Add the corresponding error code value to the ADC output code value; After the calibration process is completed, the normal conversion process of the ADC begins and the output code is obtained. If the code value of the capacitor bit is 1, the error code value of the corresponding bit is added. If it is 0, the error code value of the capacitor bit is not added. The ADC output code value with the added error code value is used as the final conversion output code value.

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