Transceiving multiplexing circuit device for transceiver and control method thereof

Abstract

The invention provides a transceiver multiplexing circuit apparatus for a transceiver and a control method thereof. The transmit-receive multiplexing circuit device comprises: a multiplexing module which is provided with a first state and a second state and comprises a first multiplexing end, a second multiplexing end, a third multiplexing end, a fourth multiplexing end, a fifth multiplexing end and a sixth multiplexing end; the multiplexing module is provided with a transceiving multiplexing mixer, and the transmitting module end comprises a first transmitting input end, a second transmitting input end, a third transmitting input end, a fourth transmitting input end, a first transmitting output end and a second transmitting output end; the receiving module end comprises a first receiving input end, a second receiving input end, a first receiving output end, a second receiving output end, a third receiving output end and a fourth receiving output end. The invention further provides a corresponding control method. According to the transceiving multiplexing circuit device provided by the embodiment of the invention, the circuit area can be effectively reduced, so that the manufacturing cost of a chip is reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of radio frequency receivers, and in particular to a transceiver multiplexing circuit device for a transceiver and a control method thereof. Background Art

[0002] In today's information age, people have regarded the transmission and interaction of information as an essential part of social life. Among them, wireless communication is the most active part in the communication field and has been widely used in various aspects.

[0003] With the development of communication technology, there are more and more communication signals, communication systems are becoming more and more complex, and the application cost is getting higher and higher. Under the condition of achieving the same functions and performance indicators, it is becoming more and more important to simplify and miniaturize the circuit. However, with the continuous increase in frequency bands and the increasing complexity of communication systems, traditional independent transceiver solutions have become increasingly unable to meet the requirements of multiple communication systems. Usually, the transceiver circuits are implemented using different circuits, which brings about the problem of complex circuits, increased chip area, and increased costs. Therefore, how to simplify the circuit, reduce the chip area, and reduce costs has become one of the problems that technicians in this field need to solve urgently.

[0004] Therefore, the prior art still needs to be improved and enhanced.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0006] In order to solve at least one of the above problems and one or more of other potential problems, the present disclosure proposes a transceiver multiplexing circuit device for a transceiver, which can effectively simplify the circuit, reduce the chip area, and thus reduce the cost.

[0007] In a first aspect of the present disclosure, a transceiver multiplexing circuit device is provided, which includes: a multiplexing module, which is configured to be connected to a transmitting module end and a receiving module end of the transceiver, the multiplexing module is configured with a first state and a second state, the multiplexing module includes a first multiplexing end, a second multiplexing end, a third multiplexing end, a fourth multiplexing end, a fifth multiplexing end and a sixth multiplexing end; the multiplexing module is configured with a transceiver multiplexing mixer, the transmitting module end includes a first transmitting input end, a second transmitting input end, a third transmitting input end and a fourth transmitting input end, and a first transmitting output end and a second transmitting output end; the receiving module end includes a first receiving input end and a second receiving input end, and a first transmitting output end and a second transmitting output end; a receiving output terminal, a second receiving output terminal, a third receiving output terminal and a fourth receiving output terminal; when the multiplexing module is set to the first state, the multiplexing module transmits the signals from the first transmitting input terminal, the second transmitting input terminal, the third transmitting input terminal and the fourth transmitting input terminal to the first transmitting output terminal and the second transmitting output terminal via the multiplexing module; when the multiplexing module is set to the second state, the multiplexing module transmits the signals from the first receiving input terminal and the second receiving input terminal to the first receiving output terminal, the second receiving output terminal, the third receiving output terminal and the fourth receiving output terminal via the multiplexing module.

[0008] Further, in some embodiments, the multiplexing module further includes: a first transmitting end TX_IF_IP, a first receiving end RX_IF_IP, a second transmitting end TX_IF_IN, a second receiving end RX_IF_IN, a third transmitting end TX_IF_QP, a third receiving end RX_IF_QP, a fourth transmitting end TX_IF_QN, and a fourth receiving end RX_IF_QN; wherein the source end of the transistors where the first transmitting end TX_IF_IP, the second transmitting end TX_IF_IN, the third transmitting end TX_IF_QP, and the fourth transmitting end TX_IF_QN are located is set A transistor anti-leakage structure is provided; wherein, the source terminals of the transistors at the first transmitting terminal TX_IF_IP, the second transmitting terminal TX_IF_IN, the third transmitting terminal TX_IF_QP, and the fourth transmitting terminal TX_IF_QN are provided with a transistor anti-leakage structure; the transistor anti-leakage structure is configured as follows: when the multiplexing module is set to the second state, an anti-leakage bias voltage is applied to the source terminals of the transistors at the first transmitting terminal TX_IF_IP, the second transmitting terminal TX_IF_IN, the third transmitting terminal TX_IF_QP, and the fourth transmitting terminal TX_IF_QN.

[0009] Further, in some embodiments, when the multiplexing module is set to the first state, the first transmitting terminal TX_IF_IP is set to be connected to the first multiplexing terminal and the first receiving terminal RX_IF_IP is set to be disconnected from the first multiplexing terminal; the second transmitting terminal TX_IF_IN is set to be connected to the first multiplexing terminal and the second receiving terminal RX_IF_IN is set to be disconnected from the second multiplexing terminal; the third transmitting terminal TX_IF_QP is set to be connected to the first multiplexing terminal and the third receiving terminal RX_IF_QP is set to be disconnected from the third multiplexing terminal; the fourth transmitting terminal TX_IF_QN is set to be connected to the first multiplexing terminal and the fourth receiving terminal RX_IF_QN is set to be disconnected from the above-mentioned fourth multiplexing end; when the above-mentioned multiplexing module is set to the above-mentioned second state, the above-mentioned first receiving end RX_IF_IP is set to be connected to the above-mentioned first multiplexing end and the above-mentioned first transmitting end TX_IF_IP is set to be grounded; the above-mentioned second receiving end RX_IF_IN is set to be connected to the above-mentioned first multiplexing end and the above-mentioned second transmitting end TX_IF_IN is set to be grounded; the above-mentioned third receiving end RX_IF_QP is set to be connected to the above-mentioned first multiplexing end and the above-mentioned third transmitting end TX_IF_QP is set to be grounded; the above-mentioned fourth receiving end RX_IF_QN is set to be connected to the above-mentioned first multiplexing end and the above-mentioned fourth transmitting end TX_IF_QN is set to be grounded.

[0010] Further, in some embodiments, when the multiplexing module is in the first state, the multiplexing module is configured to connect the first transmission input terminal to the first multiplexing terminal, the second transmission input terminal to the second multiplexing terminal, the third transmission input terminal to the third multiplexing terminal, the fourth transmission input terminal to the fourth multiplexing terminal, the fifth multiplexing terminal to the first transmission output terminal, and the sixth multiplexing terminal to the second transmission output terminal; when the multiplexing module is in the second state, the multiplexing module is configured to connect the first reception output terminal to the first multiplexing terminal, the second reception output terminal to the second multiplexing terminal, the third reception output terminal to the third multiplexing terminal, the fourth reception output terminal to the fourth multiplexing terminal, the fifth multiplexing terminal to the first reception input terminal, and the sixth multiplexing terminal to the second reception input terminal.

[0011] Furthermore, in some embodiments, the multiplexing module is provided with a transceiver multiplexing local oscillator, the transceiver multiplexing local oscillator includes a first local oscillator signal output terminal LO_1, a second local oscillator signal output terminal LO_2, a third local oscillator signal output terminal LO_3 and a fourth local oscillator signal output terminal LO_4; the transceiver multiplexing mixer includes a first transceiver multiplexing mixer and a second transceiver multiplexing mixer, the first transceiver multiplexing mixer includes a first local oscillator signal receiving terminal and a second local oscillator signal receiving terminal, the second transceiver multiplexing mixer includes a third local oscillator signal receiving terminal and a fourth local oscillator signal receiving terminal; when the multiplexing module is set to the first state, the first local oscillator signal receiving terminal is connected to the first local oscillator signal receiving terminal. The output terminal LO_1 is connected, the second local oscillator signal receiving terminal is connected to the second local oscillator signal output terminal LO_2, the third local oscillator signal receiving terminal is connected to the third local oscillator signal output terminal LO_3, and the fourth local oscillator signal receiving terminal is connected to the fourth local oscillator signal output terminal LO_4; when the multiplexing module is set to the second state, the first local oscillator signal receiving terminal is connected to the fourth local oscillator signal output terminal LO_4, the second local oscillator signal receiving terminal is connected to the third local oscillator signal output terminal LO_3, the third local oscillator signal receiving terminal is connected to the second local oscillator signal output terminal LO_2, and the fourth local oscillator signal receiving terminal is connected to the first local oscillator signal output terminal LO_1.

[0012] Further, in some embodiments, the multiplexing module is provided with a transceiver multiplexing balun, and when the multiplexing module is set to a first state, the transceiver multiplexing balun is configured to transmit the signal from the low noise amplifier of the transceiver to the transceiver multiplexing mixer; when the multiplexing module is set to a second state, the signal from the transceiver multiplexing mixer is transmitted to the power amplifier of the transceiver.

[0013] Further, in some embodiments, the multiplexing module includes a transceiver multiplexing filter, and the transceiver multiplexing filter includes a first multiplexing filter end, a second multiplexing filter end, a third multiplexing filter end, a fourth multiplexing filter end, a fifth multiplexing filter end, a sixth multiplexing filter end, a seventh multiplexing filter end and an eighth multiplexing filter end; when the multiplexing module is set to the first state, the transceiver multiplexing filter is configured to receive the signal from the digital-to-analog conversion module by the first multiplexing filter end, the second multiplexing filter end, the third multiplexing filter end and the fourth multiplexing filter end, and the signal is filtered after filtering. The signal is output by the fifth multiplexing filter terminal, the sixth multiplexing filter terminal, the seventh multiplexing filter terminal and the eighth multiplexing filter terminal; when the multiplexing module is set to the second state, the transceiver multiplexing filter is set to receive the signal by the fifth multiplexing filter terminal, the sixth multiplexing filter terminal, the seventh multiplexing filter terminal and the eighth multiplexing filter terminal, and the filtered signal after filtering is output by the first multiplexing filter terminal, the second multiplexing filter terminal, the third multiplexing filter terminal and the fourth multiplexing filter terminal, and the output signal is transmitted to the analog-to-digital conversion module.

[0014] Further, in some embodiments, when the multiplexing module is set to the first state, the multiplexing module is set to be disconnected from the low noise amplifier of the transceiver, and the antenna of the transceiver is set to be connected to the output of the power amplifier of the transceiver but disconnected from the input of the low noise amplifier of the transceiver; when the multiplexing module is set to the second state, the multiplexing module is set to be connected to the low noise amplifier of the transceiver, and the antenna of the transceiver is set to be connected to the input of the low noise amplifier of the transceiver but disconnected from the output of the power amplifier of the transceiver.

[0015] Further, in some embodiments, the transceiver multiplexing mixer is provided with a first transistor M0, a second transistor M1, a third transistor M2, a fourth transistor M3, a fifth transistor M4, a sixth transistor M5, a seventh transistor M6, an eighth transistor M7, a ninth transistor M8, a tenth transistor M9, an eleventh transistor M10, a twelfth transistor M11, a thirteenth transistor M12, and a fourteenth transistor M13; the gate of the first transistor M0 is configured to be connected to the first transmitting terminal TX_IF_IP, the drain of the first transistor M0 is configured to be connected to the first receiving terminal RX_IF_IP, and the gate of the second transistor M1 is configured to be connected to the second transmitting terminal TX_IF_ IN is connected, the drain of the second transistor M1 is configured to be connected to the second receiving terminal RX_IF_IN, the gate of the third transistor M2 is configured to be connected to the third transmitting terminal TX_IF_QP, the drain of the third transistor M2 is configured to be connected to the third receiving terminal RX_IF_QP, the gate of the fourth transistor M3 is configured to be connected to the fourth transmitting terminal TX_IF_QN, and the drain of the fourth transistor M3 is configured to be connected to the fourth receiving terminal RX_IF_QN; the gate of the fifth transistor M4 and the gate of the eighth transistor M7 are configured to be connected to the first local oscillation signal output terminal LO_1, the gate of the sixth transistor M5 and the gate of the seventh transistor M6 are configured to be connected to the first local oscillation signal output terminal LO_1, and the gate of the sixth transistor M5 is configured to be connected to the seventh transistor M6. The gate of the ninth transistor M8 and the gate of the twelfth transistor M11 are arranged to be connected to the second local oscillation signal output terminal LO_2, and the gate of the tenth transistor M9 and the gate of the eleventh transistor M10 are arranged to be connected to the fourth local oscillation signal output terminal LO_4; the drain of the first transistor M0 is arranged to be connected to the source of the fifth transistor M4 and the source of the sixth transistor M5; the drain of the second transistor M1 is arranged to be connected to the source of the seventh transistor M6 and the source of the eighth transistor M7; the drain of the third transistor M2 is arranged to be connected to the ninth transistor The source of the first transistor M0 and the source of the second transistor M1 are connected to the drain of the thirteenth transistor M12, and the source of the third transistor M2 and the source of the fourth transistor M3 are connected to the drain of the fourteenth transistor M13; the drain of the thirteenth transistor M12 is connected to the anti-leakage bias voltage via the first resistor R1, and the drain of the fourteenth transistor M13 is connected to the anti-leakage bias voltage via the second resistor R2;The source of the thirteenth transistor M12 is grounded, and the gate of the thirteenth transistor M12 is connected to a bias voltage; the source of the fourteenth transistor M13 is grounded, and the gate of the fourteenth transistor M13 is connected to a bias voltage. ;

[0016] Further, in some embodiments, the drain of the fifth transistor M4, the drain of the seventh transistor M6, the drain of the ninth transistor M8 and the drain of the eleventh transistor M10 are configured to be connected to the third end of the transceiver multiplexing balun, and the drain of the sixth transistor M5, the drain of the eighth transistor M7, the drain of the tenth transistor M9 and the drain of the twelfth transistor M11 are configured to be connected to the fourth end of the transceiver multiplexing balun.

[0017] In the second aspect of the present disclosure, a control method for a transceiver multiplexing circuit device is also provided, which includes: judging and obtaining the state of the transceiver; when the transceiver is in a transmitting state, setting the multiplexing module to a first state so that the signal from the digital-to-analog converter is passed to the power amplifier via the multiplexing module; when the transceiver is in a receiving state, setting the multiplexing module to a second state so that the signal from the low-noise amplifier is passed to the analog-to-digital converter via the multiplexing module.

[0018] In a third aspect of the present disclosure, a transceiver is further provided, comprising: the transceiver multiplexing circuit device as described above.

[0019] Compared with the prior art, the present disclosure has the following beneficial effects: By setting up a multiplexing module, the entire transceiver can simplify the original circuit scale, especially save chip area, thereby reducing costs. In particular, in some embodiments, a transceiver multiplexing balun is used to reduce the overall chip area of ​​the transceiver; further, a transceiver multiplexing mixer and a corresponding transceiver multiplexing local oscillator are used, rather than using independent mixers and local oscillators in the receiver and transmitter, respectively, which can effectively reduce the chip area; further, the use of a transceiver multiplexing filter can further simplify the circuit and reduce the chip area compared to using independent filters in the receiver and transmitter, respectively. In addition, in some embodiments, in order to solve the problem of transistor leakage corresponding to the port serving the transmitter when the transceiver multiplexing mixer is in receiver mode, an anti-leakage structure is also used at the source of the corresponding transistor, thereby improving the overall performance of the transceiver multiplexing mixer. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings, in which:

[0021] Figure 1 A schematic diagram showing a transceiver multiplexing circuit device according to an embodiment of the present disclosure is shown; Figure 2 A diagram showing a transceiver multiplexing mixer according to an embodiment of the present disclosure is shown; Figure 3 A diagram showing a transceiver multiplexing local oscillator according to an embodiment of the present disclosure is shown; Figure 4 A flow chart showing a method for controlling a transceiver multiplexing local oscillator according to an embodiment of the present disclosure; and In the various drawings, the same or corresponding reference numerals denote the same or corresponding parts. DETAILED DESCRIPTION

[0022] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0023] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0024] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first state may also be referred to as the second state, and similarly, the second state may also be referred to as the first state. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0025] Generally, the transceiver circuits are implemented using different circuits, which brings about the problem of complex circuits, increased chip area, and increased cost. Therefore, how to simplify the circuit, reduce the chip area, and reduce the cost has become one of the problems that the technicians in this field need to solve urgently. Furthermore, it is conceivable to reuse the corresponding devices / modules / units, so as to effectively simplify the circuit, reduce the chip area, and reduce the cost; however, the reuse of the corresponding devices / modules / units cannot be based on simple reuse, but will face various technical problems, which will be discussed below in conjunction with the accompanying drawings and specific embodiments.

[0026] Figure 1A diagram of a transceiver multiplexing circuit device according to an embodiment of the present disclosure is shown. In the illustrated embodiment, the transceiver multiplexing circuit device includes a multiplexing module, which is configured to be connected to the transmitting module end and the receiving module end of the transceiver, wherein the multiplexing module is configured to have a first state (e.g., a transmitting state) and a second state (e.g., a receiving state). For example, in the illustrated embodiment, the multiplexing module can be configured as a module portion between the circuit nodes 1-6 in the diagram, correspondingly having a first multiplexing end corresponding to node 1, a second multiplexing end corresponding to node 2, a third multiplexing end corresponding to node 3, a fourth multiplexing end corresponding to node 4, a fifth multiplexing end corresponding to node 5, and a sixth multiplexing end corresponding to node 6; accordingly, the multiplexing module is configured with a transceiver multiplexing mixer, as shown in the figure, including a transceiver multiplexing mixer I for the upper path and a transceiver multiplexing mixer Q for the lower path. Furthermore, the corresponding transmitting module end, for example, includes a first transmitting input end (for example, corresponding to the DAC_out1 port of the illustrated digital-to-analog converter I), a second transmitting input end (for example, corresponding to the DAC_out2 port of the illustrated digital-to-analog converter I), a third transmitting input end (for example, corresponding to the DAC_out3 port of the illustrated digital-to-analog converter Q) and a fourth transmitting input end (for example, corresponding to the DAC_out4 port of the illustrated digital-to-analog converter Q), as well as a first transmitting output end (for example, corresponding to the port connected to the power amplifier and the node 5) and a second transmitting output end (for example, corresponding to the port connected to the power amplifier and the node 6).Correspondingly, the receiving module end includes, for example, a first receiving input terminal (for example, a port corresponding to the low noise amplifier connected to the switch K1) and a second receiving input terminal (for example, a port corresponding to the low noise amplifier connected to the switch K2), as well as a first receiving output terminal (for example, corresponding to the ADC_in1 port of the analog-to-digital converter I shown in the figure), a second receiving output terminal (for example, corresponding to the ADC_in2 port of the analog-to-digital converter I shown in the figure), a third receiving output terminal (for example, corresponding to the ADC_in3 port of the analog-to-digital converter Q shown in the figure) and a fourth receiving output terminal (for example, corresponding to the ADC_in4 port of the analog-to-digital converter Q shown in the figure); accordingly, when the multiplexing module is set to the first state (for example, the transmitting state), the multiplexing module transmits the first transmitting input terminal (DAC_out1), the second transmitting input terminal (DAC_out2), the third transmitting output terminal (DAC_out3), and the fourth transmitting output terminal (DAC_in4). The multiplexing module transmits the signals from the first receiving input terminal (DAC_out3) and the fourth transmitting input terminal (DAC_out4) (for example, a complex signal composed of the I path and the Q path, and the I path and the Q path each have two differential signals) to the first transmitting output terminal (for example, the upper port on the right side of the power amplifier) ​​and the second transmitting output terminal (for example, the lower port on the right side of the power amplifier) ​​via the multiplexing module; when the multiplexing module is set to the second state (for example, the receiving state), the multiplexing module transmits the signals from the first receiving input terminal (for example, the upper port on the right side of the low noise amplifier) ​​and the second receiving input terminal (for example, the lower port on the right side of the low noise amplifier) ​​to the first receiving output terminal (ADC_in1), the second receiving output terminal (ADC_in2), the third receiving output terminal (ADC_in3) and the fourth receiving output terminal (ADC_in4) via the multiplexing module. In particular, in some embodiments, when the multiplexing module is set to the first state (transmitting state), the multiplexing module is set to be disconnected from the low noise amplifier of the transceiver (for example, implemented by the switch K1 and the switch K2 as shown in the figure), and the antenna of the transceiver is set to be connected to the output end of the power amplifier of the transceiver but disconnected from the input end of the low noise amplifier of the transceiver (for example, implemented by the transceiver switch shown in the figure); thereby preventing interference in the receiver part; when the multiplexing module is set to the second state (receiving state), the multiplexing module is set to be connected to the low noise amplifier of the transceiver (for example, implemented by the switch K1 and the switch K2 as shown in the figure), and the antenna of the transceiver is set to be connected to the input end of the low noise amplifier of the transceiver but disconnected from the output end of the power amplifier of the transceiver (for example, implemented by the transceiver switch shown in the figure); thereby preventing interference in the transmitter part. It should be understood that in other embodiments, switches can also be respectively set between the nodes 5 and 6 connected to the power amplifier in the figure to implement functions similar to the switches K1 and K2.

[0027] It should be understood that Figure 1In the exemplary embodiment, the multiplexing module is a "transceiver multiplexing module", which may include a transceiver multiplexing balun, which is respectively connected to the four circuits (i.e., nodes 5-8) shown in the figure. Two baluns (i.e., one balun for the transmitter and one balun for the receiver) are saved by using one transceiver multiplexing balun. In particular, the transceiver multiplexing balun has a switch K3 at the center tap part on the right side thereof as shown in the figure, and the other end of the switch K3 is connected to the power supply voltage; when the multiplexing module is set to the first state (transmitting state), the signal from the transceiver multiplexing mixer is transmitted to the power amplifier of the transceiver. At this time, the switch K3 is disconnected, so that the center tap part on the right side of the transceiver multiplexing balun is disconnected from the power supply voltage via the switch K3; when the multiplexing module is set to the second state (receiving state), the transceiver multiplexing balun is set to transmit the signal from the low noise amplifier of the transceiver to the transceiver multiplexing mixer. At this time, the switch K3 is closed, so that the center tap part on the right side of the transceiver multiplexing balun is connected to the power supply voltage via the switch K3.

[0028] Further, in Figure 1 In the exemplary embodiment, when the multiplexing module is in the first state (transmitting state), the multiplexing module is configured to connect the first transmitting input terminal (DAC_out1) to the first multiplexing terminal (node ​​1), the second transmitting input terminal (DAC_out2) to the second multiplexing terminal (node ​​2), the third transmitting input terminal (DAC_out3) to the third multiplexing terminal (node ​​3), the fourth transmitting input terminal (DAC_out4) to the fourth multiplexing terminal (node ​​4), the fifth multiplexing terminal (node ​​5) to the first transmitting output terminal (the right end upper path of the power amplifier), and the sixth multiplexing terminal (node ​​6) to the second transmitting output terminal (the right end lower path of the power amplifier); thereby the entire transceiver is in the transmitter state, that is, the multiplexing module is in the transmitting state, and the transmitter function of the transceiver based on the multiplexing module is realized.

[0029] Further, in Figure 1In the exemplary embodiment, when the multiplexing module is in the second state (receiving state), the multiplexing module is configured to connect the first receiving output terminal (ADC_in1) to the first multiplexing terminal (node ​​1), connect the second receiving output terminal (ADC_in2) to the second multiplexing terminal (node ​​2), connect the third receiving output terminal (ADC_in3) to the third multiplexing terminal (node ​​3), connect the fourth receiving output terminal (ADC_in4) to the fourth multiplexing terminal (node ​​4), connect the fifth multiplexing terminal (node ​​5) to the first receiving input terminal (for example, the upper path on the right side of the low noise amplifier, or the right end of the switch K1), and connect the sixth multiplexing terminal (node ​​6) to the second receiving input terminal (for example, the lower path on the right side of the low noise amplifier, or the right end of the switch K2); thereby, the entire transceiver is in the receiver state, that is, the multiplexing module is in the receiving state, and the receiver function of the transceiver based on the multiplexing module is realized.

[0030] It should also be understood that Figure 1 In the exemplary embodiment, the multiplexing module may include a transceiver multiplexing filter (for example, a transceiver multiplexing filter I and a transceiver multiplexing filter Q), the transceiver multiplexing filter includes a first multiplexing filter end (for example, a right upper path of the transceiver multiplexing filter I connected to node 1), a second multiplexing filter end (for example, a right lower path of the transceiver multiplexing filter I connected to node 2), a third multiplexing filter end (for example, a right upper path of the transceiver multiplexing filter Q connected to node 3), a fourth multiplexing filter end (for example, a right lower path of the transceiver multiplexing filter Q connected to node 4), a fifth multiplexing filter end (the right upper path of the transceiver multiplexing filter I), a sixth multiplexing filter end (the right lower path of the transceiver multiplexing filter I), a seventh multiplexing filter end (the right upper path of the transceiver multiplexing filter Q) and an eighth multiplexing filter end (the right lower path of the transceiver multiplexing filter Q); when the multiplexing module is set to the first state (transmitting state), the transceiver multiplexing filter is set to be composed of the first multiplexing filter end and the eighth multiplexing filter end. The first multiplexing filter terminal, the second multiplexing filter terminal, the third multiplexing filter terminal and the fourth multiplexing filter terminal receive signals from the digital-to-analog conversion module (for example, the digital-to-analog converter I and the digital-to-analog converter Q), and the signals to be filtered after filtering are output by the fifth multiplexing filter terminal, the sixth multiplexing filter terminal, the seventh multiplexing filter terminal and the eighth multiplexing filter terminal; accordingly, when the multiplexing module is set to the second state (receiving state), the transceiver multiplexing filter is set to receive signals by the fifth multiplexing filter terminal, the sixth multiplexing filter terminal, the seventh multiplexing filter terminal and the eighth multiplexing filter terminal, and the signals to be filtered after filtering are output by the first multiplexing filter terminal, the second multiplexing filter terminal, the third multiplexing filter terminal and the fourth multiplexing filter terminal, and the output signals are transmitted to the analog-to-digital conversion module (for example, the analog-to-digital converter I and the analog-to-digital converter Q); thereby, the transceiver multiplexing filter is implemented to simultaneously assume the filter function of the transmitter and the filter function of the receiver, thereby realizing multiplexing. It should be understood that in some embodiments, Figure 1 The transceiver multiplexing filter part can be replaced by four filters, that is, instead of using the transceiver multiplexing filter, two filters are provided to the I and Q paths of the transmitter, and the other two paths are provided to the I and Q paths of the receiver. Figure 1 The transceiver multiplexing mixer part can also be replaced by four mixers, that is, instead of using the transceiver multiplexing mixer, two mixers are provided to the I and Q paths of the transmitter, and the other two are provided to the I and Q paths of the receiver. Figure 1 The transceiver multiplexing balun part can also be replaced by two dedicated baluns, that is, instead of using the transceiver multiplexing balun, one balun is provided to the transmitter and the other balun is provided to the receiver.

[0031] Further refinement Figure 1 The multiplexing module, especially the transceiver multiplexing mixer part, and the corresponding transceiver multiplexing balun part, are described in detail below with reference to the accompanying drawings.

[0032] Figure 2A diagram of a transceiver multiplexing mixer according to an embodiment of the present disclosure is shown. In the illustrated embodiment, the transceiver multiplexing mixer is provided with a first transistor M0, a second transistor M1, a third transistor M2, a fourth transistor M3, a fifth transistor M4, a sixth transistor M5, a seventh transistor M6, an eighth transistor M7, a ninth transistor M8, a tenth transistor M9, an eleventh transistor M10, a twelfth transistor M11, a thirteenth transistor M12, and a fourteenth transistor M13; in particular, the gate of the first transistor M0 is arranged to be connected to the first transmitting terminal TX_IF_IP, the drain of the first transistor M0 is arranged to be connected to the first receiving terminal RX_IF_IP, the gate of the second transistor M1 is arranged to be connected to the second transmitting terminal TX_IF_IN, and the second transistor M The drain of the third transistor M1 is configured to be connected to the second receiving terminal RX_IF_IN, the gate of the third transistor M2 is configured to be connected to the third transmitting terminal TX_IF_QP, the drain of the third transistor M2 is configured to be connected to the third receiving terminal RX_IF_QP, the gate of the fourth transistor M3 is configured to be connected to the fourth transmitting terminal TX_IF_QN, and the drain of the fourth transistor M3 is configured to be connected to the fourth receiving terminal RX_IF_QN; the gate of the fifth transistor M4 and the gate of the eighth transistor M7 are configured to be connected to the first local oscillation signal output terminal LO_1, the gate of the sixth transistor M5 and the gate of the seventh transistor M6 are configured to be connected to the third local oscillation signal output terminal LO_3, and the gate of the ninth transistor M8 is configured to be connected to the third local oscillation signal output terminal LO_4. The gate of the twelfth transistor M11 is configured to be connected to the second local oscillation signal output terminal LO_2, the gate of the tenth transistor M9 and the gate of the eleventh transistor M10 are configured to be connected to the fourth local oscillation signal output terminal LO_4; the drain of the first transistor M0 is configured to be connected to the source of the fifth transistor M4 and the source of the sixth transistor M5; the drain of the second transistor M1 is configured to be connected to the source of the seventh transistor M6 and the source of the eighth transistor M7; the drain of the third transistor M2 is configured to be connected to the source of the ninth transistor M8 and the source of the tenth transistor M9; the drain of the fourth transistor M3 is configured to be connected to the source of the eleventh transistor M10 and the source of the twelfth transistor M11; the first transistor The source of M0 and the source of the second transistor M1 are arranged to be connected to the drain of the thirteenth transistor M12, and the source of the third transistor M2 and the source of the fourth transistor M3 are arranged to be connected to the drain of the fourteenth transistor M13; the drain of the thirteenth transistor M12 is arranged to be connected to the anti-leakage bias voltage via the first resistor R1, and the drain of the fourteenth transistor M13 is arranged to be connected to the anti-leakage bias voltage via the second resistor R2; the source of the thirteenth transistor M12 is arranged to be grounded, and the gate of the thirteenth transistor M12 is arranged to be connected to the bias voltage connection terminal VB; the source of the fourteenth transistor M13 is arranged to be grounded, and the gate of the fourteenth transistor M13 is arranged to be connected to the bias voltage connection terminal VB.The drain of the fifth transistor M4, the drain of the seventh transistor M6, the drain of the ninth transistor M8 and the drain of the eleventh transistor M10 are arranged to be connected to the third end (node ​​7) of the transceiver multiplexing balun, and the drain of the sixth transistor M5, the drain of the eighth transistor M7, the drain of the tenth transistor M9 and the drain of the twelfth transistor M11 are arranged to be connected to the fourth end (node ​​8) of the transceiver multiplexing balun.

[0033] It should be understood that in this illustrated embodiment, when the multiplexing module is set to the first state, the first transmitting end TX_IF_IP is set to be connected to the first multiplexing end and the first receiving end RX_IF_IP is set to be disconnected from the first multiplexing end; the second transmitting end TX_IF_IN is set to be connected to the first multiplexing end and the second receiving end RX_IF_IN is set to be disconnected from the second multiplexing end; the third transmitting end TX_IF_QP is set to be connected to the first multiplexing end and the third receiving end RX_IF_QP is set to be disconnected from the third multiplexing end; the fourth transmitting end TX_IF_QN is set to be connected to the first multiplexing end and the fourth receiving end RX_IF_QN is set to be disconnected from the fourth multiplexing end; when the multiplexing module is set to the second state, the first receiving end RX_IF_IP is set to be connected to the first multiplexing end and the second receiving end RX_IF_IN is set to be disconnected from the second multiplexing end; A multiplexing end is connected and the first transmitting end TX_IF_IP is set to be disconnected from the first multiplexing end; the second receiving end RX_IF_IN is set to be connected to the first multiplexing end and the second transmitting end TX_IF_IN is set to be disconnected from the second multiplexing end; the third receiving end RX_IF_QP is set to be connected to the first multiplexing end and the third transmitting end TX_IF_QP is set to be disconnected from the third multiplexing end; the fourth receiving end RX_IF_QN is set to be connected to the first multiplexing end and the fourth transmitting end TX_IF_QN is set to be disconnected from the fourth multiplexing end; wherein the source ends of the transistors where the first transmitting end TX_IF_IP, the second transmitting end TX_IF_IN, the third transmitting end TX_IF_QP and the fourth transmitting end TX_IF_QN are located are provided with transistor anti-leakage structures. Specifically, the transistor anti-leakage structure includes the drain of the thirteenth transistor M12 (also the source of the first transistor M0 and the source of the second transistor M1) being set to be connected to the anti-leakage bias voltage via the first resistor R1, the drain of the fourteenth transistor M13 (also the source of the third transistor M2 and the source of the fourth transistor M3) being set to be connected to the anti-leakage bias voltage via the second resistor R2, the source of the thirteenth transistor M12 being set to be grounded, and the gate of the thirteenth transistor M12 being set to be connected to the bias voltage terminal (shown as VB); the source of the fourteenth transistor M13 being set to be grounded, and the gate of the fourteenth transistor M13 being set to be connected to the bias voltage terminal (shown as VB). Thus, when the multiplexing module is in the second state (receiving state), the leakage of transistors M0, M1, M2, and M3 can be effectively prevented, thereby affecting the performance of the entire multiplexing module (especially the transceiver multiplexing mixer) in the overall receiving state.

[0034] It should be understood that Figure 2In the figure, when the multiplexing module is in the first state (transmitting state), all transistors (MOS tubes) and current sources in the figure are working (especially the gate input bias voltage VB of transistors M12 and M13, but the connection with the leakage protection bias voltage VB_leakgae is disconnected in the figure, that is, the leakage protection bias voltage VB_leakgae is not input; and the switch K3 is closed, so that the center tap part of the lower side of the transceiver multiplexing balun is connected to the power supply voltage), wherein the four orthogonal signals of the first transmitting terminal TX_IF_IP, the second transmitting terminal TX_IF_IN, the third transmitting terminal TX_IF_QP, and the fourth transmitting terminal TX_IF_QN come from the filter, as the intermediate frequency input signal of the mixer in the transmitting state, through the active orthogonal mixer composed of transistors M0-M11, converted into a differential signal, and then output to the power amplifier through the first terminal RF_P and the second terminal RF_N of the upper transceiver multiplexing balun. Further, when the multiplexing module is in the second state (receiving state), in particular, the gates of transistors M12 and M13 in the figure shut off the input bias voltage VB (generally, the corresponding bias voltage VB terminal is grounded, so that the input voltage is zero), and the input leakage protection bias voltage VB_leakgae is shown in the figure (for example, 0.5 times the power supply voltage is input), and the transistors M0-M3 are shut off to ensure that they are turned off, and the mixer becomes a passive mixer (by turning off switch K3). The first end RF_P (for example, node 5) and the second end RF_N (for example, node 6) of the transceiver multiplexing balun are switched to the output of the low noise amplifier LNA through the switch, and then given to the input end of the orthogonal passive mixer composed of transistors M4-M11 (i.e., the drain of transistors M4-M11 in the figure) through the transceiver multiplexing balun. And output four orthogonal signals of the first receiving terminal RX_IF_IP, the second receiving terminal RX_IF_IN, the third receiving terminal RX_IF_QP, and the fourth receiving terminal RX_IF_QN, and then pass through the signal selection switch to the input terminal of the filter. It should be understood that the working principle of the transistor anti-leakage structure is that if there is no transistor anti-leakage structure, when the multiplexing module is in the second state (receiving state), the drain and gate of the transistors M0-M3 may generate a weak current (leakage) flowing to its source, thereby affecting the performance of the multiplexing module in the second state.Therefore, in order to prevent the occurrence of leakage, a leakage prevention bias voltage VB_leakgae is set for reverse charging. When the multiplexing module is in the second state (receiving state), the gate VB of the transistors M12 and M13 is grounded, and a power supply voltage of 0.5 is set as the leakage prevention bias voltage VB_leakgae for input as shown in the figure. Although a weak voltage drop is generated through the resistor R1 or R2, the voltage at the drain of the transistors M12 and M13 is high enough, so that the drain and gate of the transistors M0-M3 cannot generate a weak current (leakage) flowing to their sources, and the drain of the transistors M12 and M13 will be grounded through the source of the transistors M12 and M13 to achieve leakage. Thereby ensuring the performance of the multiplexing module in the second state.

[0035] Figure 3 A schematic diagram of a transceiver multiplexing local oscillator according to an embodiment of the present disclosure is shown. It should be understood that in a wireless communication transceiver, a local oscillator signal, especially an orthogonal four-phase local oscillator signal, is usually generated by a divide-by-2 circuit. In the illustrated embodiment, the four output terminals of the transceiver multiplexing local oscillator (two-frequency division circuit) sequentially output signal phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees from top to bottom; through the illustrated selector, when the multiplexing module is in the first state, it sequentially outputs four local oscillator signals of 0 degrees, 90 degrees, 180 degrees, and 270 degrees, and when the multiplexing module is in the second state, it needs to output the external change order equivalent to sequentially outputting 270 degrees, 180 degrees, 90 degrees, and 0 degrees; thereby meeting the local oscillator signal requirements of the transceiver multiplexing mixer. It should be understood that the four output ends of the transceiver multiplexing local oscillator (two-way frequency division circuit) always maintain the output of the four phases as shown in the figure. However, through the selector shown in the figure and the mode control, the final four output ends (for example, the first local oscillator signal output end LO_1; the second local oscillator signal output end LO_2; the third local oscillator signal output end LO_3; the fourth local oscillator signal output end LO_4 in the figure) realize different outputs in the first state or the second state to ensure the multiplexing module's demand for the local oscillator signal in different states.

[0036] Figure 4 A flow chart of a control method of a transceiver multiplexing local oscillator according to an embodiment of the present disclosure is shown. In this embodiment, the process shown is a control method 100 based on the above-mentioned transceiver multiplexing circuit device, and the control method 100 includes: step 110, judging and obtaining the state of the transceiver; step 130, when the transceiver is in the transmitting state, setting the multiplexing module to the first state, so that the signal from the digital-to-analog converter is passed to the power amplifier via the multiplexing module; when the transceiver is in the receiving state, setting the multiplexing module to the second state, so that the signal from the low noise amplifier is passed to the analog-to-digital converter via the multiplexing module.

[0037] Furthermore, in some embodiments, a transceiver is proposed, which includes: the above-mentioned transceiver multiplexing circuit device.

[0038] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

[0039] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A transceiver multiplexing circuit device for a transceiver, characterized in that: include: A multiplexing module is configured to be connected to the transmitting module end and the receiving module end of the transceiver, the multiplexing module is configured with a first state and a second state, the multiplexing module includes a first multiplexing end, a second multiplexing end, a third multiplexing end, a fourth multiplexing end, a fifth multiplexing end and a sixth multiplexing end; the multiplexing module is configured with a transceiver multiplexing mixer, The transmitting module end includes a first transmitting input end, a second transmitting input end, a third transmitting input end and a fourth transmitting input end, and a first transmitting output end and a second transmitting output end; The receiving module end includes a first receiving input end and a second receiving input end, and a first receiving output end, a second receiving output end, a third receiving output end and a fourth receiving output end; When the multiplexing module is set to the first state, the multiplexing module transmits the signals from the first transmit input terminal, the second transmit input terminal, the third transmit input terminal and the fourth transmit input terminal to the first transmit output terminal and the second transmit output terminal via the multiplexing module; When the multiplexing module is set to the second state, the multiplexing module transmits the signals from the first receiving input terminal and the second receiving input terminal to the first receiving output terminal, the second receiving output terminal, the third receiving output terminal and the fourth receiving output terminal via the multiplexing module.

2. The transceiver multiplexing circuit device according to claim 1, characterized in that: The multiplexing module also includes: a first transmitting end (TX_IF_IP), a first receiving end (RX_IF_IP), a second transmitting end (TX_IF_IN), a second receiving end (RX_IF_IN), a third transmitting end (TX_IF_QP), a third receiving end (RX_IF_QP), a fourth transmitting end (TX_IF_QN), and a fourth receiving end (RX_IF_QN); wherein the source ends of the transistors at which the first transmitting end (TX_IF_IP), the second transmitting end (TX_IF_IN), the third transmitting end (TX_IF_QP), and the fourth transmitting end (TX_IF_QN) are located are provided with a transistor anti-leakage structure; wherein the source ends of the transistors at which the first transmitting end (TX_IF_IP), the second transmitting end (TX_IF_IN), the third transmitting end (TX_IF_QP), and the fourth transmitting end (TX_IF_QN) are located are provided with a transistor anti-leakage structure; The transistor anti-leakage structure is configured as follows: When the multiplexing module is set to the second state, an anti-leakage bias voltage is applied to the source terminals of the transistors at the first transmitting terminal (TX_IF_IP), the second transmitting terminal (TX_IF_IN), the third transmitting terminal (TX_IF_QP), and the fourth transmitting terminal (TX_IF_QN).

3. The transceiver multiplexing circuit device according to claim 2, characterized in that: When the multiplexing module is set to the first state, the first transmitting end (TX_IF_IP) is set to be connected to the first multiplexing end and the first receiving end (RX_IF_IP) is set to be disconnected from the first multiplexing end; the second transmitting end (TX_IF_IN) is set to be connected to the first multiplexing end and the second receiving end (RX_IF_IN) is set to be disconnected from the second multiplexing end; the third transmitting end (TX_IF_QP) is set to be connected to the first multiplexing end and the third receiving end (RX_IF_QP) is set to be disconnected from the third multiplexing end; the fourth transmitting end (TX_IF_QN) is set to be connected to the first multiplexing end and the fourth receiving end (RX_IF_QN) is set to be disconnected from the fourth multiplexing end; When the multiplexing module is set to the second state, the first receiving end (RX_IF_IP) is set to be connected to the first multiplexing end and the first transmitting end (TX_IF_IP) is set to be grounded; the second receiving end (RX_IF_IN) is set to be connected to the first multiplexing end and the second transmitting end (TX_IF_IN) is set to be grounded; the third receiving end (RX_IF_QP) is set to be connected to the first multiplexing end and the third transmitting end (TX_IF_QP) is set to be grounded; the fourth receiving end (RX_IF_QN) is set to be connected to the first multiplexing end and the fourth transmitting end (TX_IF_QN) is set to be grounded.

4. The transceiver multiplexing circuit device according to claim 2, characterized in that: When the multiplexing module is in the first state, the multiplexing module is configured to connect the first transmission input terminal to the first multiplexing terminal, connect the second transmission input terminal to the second multiplexing terminal, connect the third transmission input terminal to the third multiplexing terminal, connect the fourth transmission input terminal to the fourth multiplexing terminal, connect the fifth multiplexing terminal to the first transmission output terminal, and connect the sixth multiplexing terminal to the second transmission output terminal; When the multiplexing module is in the second state, the multiplexing module is configured to connect the first receiving output end to the first multiplexing end, connect the second receiving output end to the second multiplexing end, connect the third receiving output end to the third multiplexing end, connect the fourth receiving output end to the fourth multiplexing end, connect the fifth multiplexing end to the first receiving input end, and connect the sixth multiplexing end to the second receiving input end.

5. The transceiver multiplexing circuit device according to claim 4, characterized in that: The multiplexing module is provided with a transceiver multiplexing local oscillator, The transceiver multiplexing local oscillator comprises a first local oscillator signal output terminal (LO_1), a second local oscillator signal output terminal (LO_2), a third local oscillator signal output terminal (LO_3) and a fourth local oscillator signal output terminal (LO_4); The transceiver multiplexing mixer includes a first transceiver multiplexing mixer and a second transceiver multiplexing mixer, the first transceiver multiplexing mixer includes a first local oscillator signal receiving end and a second local oscillator signal receiving end, and the second transceiver multiplexing mixer includes a third local oscillator signal receiving end and a fourth local oscillator signal receiving end; When the multiplexing module is set to the first state, the first local oscillator signal receiving end is connected to the first local oscillator signal output end (LO_1), the second local oscillator signal receiving end is connected to the second local oscillator signal output end (LO_2), the third local oscillator signal receiving end is connected to the third local oscillator signal output end (LO_3), and the fourth local oscillator signal receiving end is connected to the fourth local oscillator signal output end (LO_4); When the multiplexing module is set to the second state, the first local oscillator signal receiving end is connected to the fourth local oscillator signal output end (LO_4), the second local oscillator signal receiving end is connected to the third local oscillator signal output end (LO_3), the third local oscillator signal receiving end is connected to the second local oscillator signal output end (LO_2), and the fourth local oscillator signal receiving end is connected to the first local oscillator signal output end (LO_1).

6. The transceiver multiplexing circuit device according to claim 5, characterized in that: The multiplexing module is provided with a transceiver multiplexing balun, When the multiplexing module is set to the first state, the transceiver multiplexing balun is configured to transmit a signal from the low noise amplifier of the transceiver to the transceiver multiplexing mixer; When the multiplexing module is set to the second state, the signal from the transceiver multiplexing mixer is transmitted to the power amplifier of the transceiver.

7. The transceiver multiplexing circuit device according to claim 6, characterized in that: The multiplexing module includes a transceiver multiplexing filter, and the transceiver multiplexing filter includes a first multiplexing filter end, a second multiplexing filter end, a third multiplexing filter end, a fourth multiplexing filter end, a fifth multiplexing filter end, a sixth multiplexing filter end, a seventh multiplexing filter end and an eighth multiplexing filter end; When the multiplexing module is set to the first state, the transceiver multiplexing filter is configured to receive the signal from the digital-to-analog conversion module by the first multiplexing filter end, the second multiplexing filter end, the third multiplexing filter end and the fourth multiplexing filter end, and the filtered signal after filtering is output by the fifth multiplexing filter end, the sixth multiplexing filter end, the seventh multiplexing filter end and the eighth multiplexing filter end; When the multiplexing module is set to the second state, the transceiver multiplexing filter is set to receive signals from the fifth multiplexing filter end, the sixth multiplexing filter end, the seventh multiplexing filter end and the eighth multiplexing filter end, and the filtered signal after filtering is output by the first multiplexing filter end, the second multiplexing filter end, the third multiplexing filter end and the fourth multiplexing filter end, and the output signal is transmitted to the analog-to-digital conversion module.

8. The transceiver multiplexing circuit device according to claim 6, characterized in that: When the multiplexing module is set to the first state, the multiplexing module is set to be disconnected from the low noise amplifier of the transceiver, and the antenna of the transceiver is set to be connected to the output end of the power amplifier of the transceiver but disconnected from the input end of the low noise amplifier of the transceiver; When the multiplexing module is set to the second state, the multiplexing module is set to be connected to the low noise amplifier of the transceiver, and the antenna of the transceiver is set to be connected to the input end of the low noise amplifier of the transceiver but disconnected from the output end of the power amplifier of the transceiver.

9. The transceiver multiplexing circuit device according to claim 8, characterized in that: The transceiver multiplexing mixer is provided with a first transistor (M0), a second transistor (M1), a third transistor (M2), a fourth transistor (M3), a fifth transistor (M4), a sixth transistor (M5), a seventh transistor (M6), an eighth transistor (M7), a ninth transistor (M8), a tenth transistor (M9), an eleventh transistor (M10), a twelfth transistor (M11), a thirteenth transistor (M12), and a fourteenth transistor (M13); The gate of the first transistor (M0) is configured to be connected to the first transmitting terminal (TX_IF_IP), the drain of the first transistor (M0) is configured to be connected to the first receiving terminal (RX_IF_IP), the gate of the second transistor (M1) is configured to be connected to the second transmitting terminal (TX_IF_IN), the drain of the second transistor (M1) is configured to be connected to the second receiving terminal (RX_IF_IN), the gate of the third transistor (M2) is configured to be connected to the third transmitting terminal (TX_IF_QP), the drain of the third transistor (M2) is configured to be connected to the third receiving terminal (RX_IF_QP), the gate of the fourth transistor (M3) is configured to be connected to the fourth transmitting terminal (TX_IF_QN), and the drain of the fourth transistor (M3) is configured to be connected to the fourth receiving terminal (RX_IF_QN); The gate of the fifth transistor (M4) and the gate of the eighth transistor (M7) are arranged to be connected to the first local oscillation signal output terminal (LO_1), the gate of the sixth transistor (M5) and the gate of the seventh transistor (M6) are arranged to be connected to the third local oscillation signal output terminal (LO_3), the gate of the ninth transistor (M8) and the gate of the twelfth transistor (M11) are arranged to be connected to the second local oscillation signal output terminal (LO_2), and the gate of the tenth transistor (M9) and the gate of the eleventh transistor (M10) are arranged to be connected to the fourth local oscillation signal output terminal (LO_4); The drain of the first transistor (M0) is arranged to be connected to the source of the fifth transistor (M4) and the source of the sixth transistor (M5); the drain of the second transistor (M1) is arranged to be connected to the source of the seventh transistor (M6) and the source of the eighth transistor (M7); the drain of the third transistor (M2) is arranged to be connected to the source of the ninth transistor (M8) and the source of the tenth transistor (M9); the drain of the fourth transistor (M3) is arranged to be connected to the source of the eleventh transistor (M10) and the source of the twelfth transistor (M11); The source of the first transistor (M0) and the source of the second transistor (M1) are arranged to be connected to the drain of the thirteenth transistor (M12), and the source of the third transistor (M2) and the source of the fourth transistor (M3) are arranged to be connected to the drain of the fourteenth transistor (M13); the drain of the thirteenth transistor (M12) is arranged to be connected to via a first resistor (R1), and the drain of the fourteenth transistor (M13) is arranged to be connected to the anti-leakage bias voltage via a second resistor (R2); The source of the thirteenth transistor (M12) is set to be grounded, and the gate of the thirteenth transistor (M12) is set to be connected to a bias voltage; the source of the fourteenth transistor (M13) is set to be grounded, and the gate of the fourteenth transistor (M13) is set to be connected to a bias voltage.

10. The transceiver multiplexing circuit device according to claim 9, characterized in that: The drain of the fifth transistor (M4), the drain of the seventh transistor (M6), the drain of the ninth transistor (M8) and the drain of the eleventh transistor (M10) are arranged to be connected to the third end of the transceiver multiplexing balun, and the drain of the sixth transistor (M5), the drain of the eighth transistor (M7), the drain of the tenth transistor (M9) and the drain of the twelfth transistor (M11) are arranged to be connected to the fourth end of the transceiver multiplexing balun.

11. A control method for a transceiver multiplexing circuit device according to any one of claims 1 to 10, characterized in that: include: Determine and obtain the state of the transceiver; When the transceiver is in a transmitting state, the multiplexing module is set to a first state so that the signal from the digital-to-analog converter is transmitted to the power amplifier via the multiplexing module; When the transceiver is in a receiving state, the multiplexing module is set to a second state so that the signal from the low noise amplifier is transmitted to the analog-to-digital converter via the multiplexing module.

12. A transceiver, characterized in that: include: A transceiver multiplexing circuit device as claimed in any one of claims 1 to 10.

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