1T1R array encryption method based on Benes network

Abstract

The invention discloses a 1T1R array encryption method based on a Benes network, and belongs to the technical field of semiconductor memories. A plurality of Benes networks 1 are connected to rows of a 1T1R array, a plurality of Benes networks 2 are connected to columns of the 1T1R array, control signals of the Benes networks 1 and the Benes networks 2 are secret keys and are independently stored and transmitted, and the method comprises the following specific steps of: firstly, performing any row and column conversion on the 1T1R array so as to disorganize internal data of a storage and calculation integrated chip; and then the Benes network 1 and the Benes network 2 are used for replacing the input and the output. According to the encryption method, weight distribution is not changed, and compared with a traditional encryption replacement mode, the encryption method has the advantages of being small in occupied area and low in power consumption. In addition, introduction of new calculation errors is avoided by adopting the Benes network, and accuracy and integrity can be kept in the encryption process.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor memory, and in particular relates to an encryption method of a 1T1R array. Background Art

[0002] Storage and computing technology is seen as an important way to transform the traditional von Neumann computing architecture and break through the bottlenecks of chip computing power and energy efficiency. Resistive memory (ReRAM, MRAM, FeRAM, PCRAM, etc.) is a device with memory and resistance characteristics that can maintain its resistance state without the need for power and can change its resistance level by applying voltage. Resistive memory can store neural network weights and realize in-memory computing. A common storage array of resistive memory is the 1T1R type, which is an array composed of units consisting of a transistor connected to a resistive device.

[0003] In the resistive memory based on 1T1R array, voltage is used as input and current is used as output. The input voltage is multiplied by the conductance between the fixed resistors to generate current, thereby realizing the multiplication and accumulation operation of the neural network. In this architecture, the resistance value of each storage unit corresponds to a specific weight in the neural network. However, since these weights usually exist in physical form, that is, in the form of resistance values, they may be at risk of being read and copied by physical or other means.

[0004] Permuting the neural network weights stored in the 1T1R array is an effective way to achieve encryption. This permutation operation is designed to encrypt the weight data, prevent potential theft, and ensure the security of stored information. However, simply permuting the weights in the memory will change the order of input and output, resulting in incorrect calculation results after permutation. Therefore, special read-in and read-out circuits are required to adjust them to ensure that the correct calculation results in the memory are read out. Summary of the invention

[0005] The object of the present invention is to provide an encryption method for a 1T1R array based on a Benes network, which can effectively encrypt the internal data of an in-memory computing chip.

[0006] The technical solution provided by the present invention is as follows:

[0007] A 1T1R array encryption method based on Benes network, characterized in that a plurality of Benes networks 1 are added to the rows of the 1T1R array, and a plurality of Benes networks 2 are added to the columns of the 1T1R array, and the control signals of the Benes networks 1 and 2 are secret keys, which are stored and transmitted separately, and the specific steps include the following:

[0008] 1) Performing a permutation operation on the neural network weights stored in the 1T1R array, and performing a column transformation on the basis of the row transformation of the 1T1R array to achieve encryption;

[0009] 2) The original input sequence is replaced by the Benes network 1 into a row sequence of a 1T1R array for input;

[0010] 3) The 1T1R array completes the matrix-vector multiplication operation and outputs the calculation result sequence;

[0011] 4) Benes network 2 replaces the calculation result sequence of the output of the 1T1R array with the calculation result sequence of the original input, thereby obtaining the correct calculation result of the original input and completing the decryption.

[0012] Furthermore, every 8 rows and every 8 columns of the 1T1R array are equipped with an 8-bit Benes network.

[0013] Furthermore, every three adjacent Benes networks use the same control signal.

[0014] The beneficial effects of the present invention are as follows:

[0015] The encryption method designed by the Benes network in the present invention does not change the weight distribution, but can effectively realize information encryption. Compared with the traditional encryption replacement method, the encryption circuit designed by the Benes network has the advantages of small footprint and low power consumption. In addition, the encryption circuit designed by the Benes network avoids the introduction of new calculation errors, which means that the data can maintain accuracy and integrity during the encryption process. These advantages not only ensure the privacy of the data, but also have important significance for the development of current and future information security technologies, and bring new exploration directions to the field of information security. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of 1T1R array;

[0017] Figure 2 A schematic diagram of the circuit structure for completing multiplication and addition operations for a 1T1R array;

[0018] Figure 3 A schematic diagram of the internal circuit structure of a chip that has not yet been replaced;

[0019] Figure 4 The schematic diagram of the internal circuit structure of the chip for replacement by row;

[0020] Figure 5 A schematic diagram of the internal circuit structure of a chip that performs permutations by row and column;

[0021] Figure 6 This is a schematic diagram of the Benes network structure;

[0022] Figure 7 The schematic diagram of the Benes network structure with 8-bit input;

[0023] Figure 8 It is a schematic diagram of the encryption method of the present invention. DETAILED DESCRIPTION

[0024] like Figure 1 As shown, the 1T1R array is used to complete matrix-vector multiplication, that is, after the values ​​of the resistors in the array have been set, this circuit structure can be used to perform multiplication and addition operations, such as Figure 2 As shown. Take BL1 as an example to illustrate this operation. First, ground BL1. For BL1, its output current is equal to the sum of the currents in each branch. According to the relationship between current and voltage and the concept of conductance, current equals voltage multiplied by conductance. Suppose the input voltages are V1, V2, V3…Vn, and the conductances between BL1 and WL1, WL2, WL3…WLn are G1, G2, G3…Gn, respectively. Therefore, the output current I1 at the BL1 end is equal to V1*G1+V2*G2+V3*G3+…+Vn*Gn, which means that a multiplication and addition operation is realized.

[0025] The internal data of the 1T1R-based integrated storage and computing chip is at risk of unauthorized access or theft. The neural network weights stored in the chip are easy to read, so a method is needed to encrypt and protect this data. However, simply permuting the internal weights of the chip for encryption will cause confusion in input and output, which will lead to errors in the results of in-memory calculations. Therefore, the way to encrypt the 1T1R array is to perform arbitrary row and column transformations on it to disrupt the internal data of the integrated storage and computing chip. Figure 3 This is a schematic diagram of the 1T1R array structure before replacement. It can be seen that when the input is abcd, the output is 1*a+1*b+1*c+1*d, 1*a+1*b+1*c+0*d, 0*a+1*b+0*c+0*d and 1*a+0*b+0*c+0*d, which correspond to a+b+c+d, a+b+c, b and a respectively. Figure 4 Figure 1 is a schematic diagram of a 1T1R array structure that performs row permutation. It can be seen that row permutation is performed, and the input signal is transformed from the order of abcd to the order of cdba. Figure 5 The schematic diagram of the 1T1R array structure is a row-column permutation. On the basis of the row transformation, the column transformation is performed, and the order of the output signal is changed from a+b+c+d, a+b+c, b and a to b, a+b+c+d, a+b+c and a. Obviously, through these row and column transformations, the internal weights have been completely changed compared to the original array. Due to the comprehensive rearrangement of the 1T1R array, the order of the chip input and output has become chaotic.

[0026] The present invention adds several Benes networks 1 on the rows of the 1T1R array, adds several Benes networks 2 on the columns of the 1T1R array, and uses the above two Benes networks to permute them. The Benes network is a rearrangeable network based on the Banyan network, which is linked by the Butterfly and InverseButterfly structures. Its structure enables it to complete various permutation operations from the input end to the output end, and has flexibility and efficiency. Figure 6 Schematic diagram of the Benes network structure (8bit). In the Benes network, completing an n-bit permutation operation requires log2n levels of Butterfly transformation and log2n levels of InverseButterfly transformation. This means that for a 64-bit permutation operation, 12 levels of transformation are required to implement. In this transformation, the amount of configuration information required at each level is This design enables the Benes network to efficiently perform data routing and transformation. Usually, performing a permutation operation in a processor requires a Butterfly instruction and an InverseButterfly instruction, as well as log2n n-bit configuration information. These instructions and information work together to complete the entire permutation operation.

[0027] In realizing the replacement function of the Benes network, MUX (data selector) is a logic element. Its main function is to select a specific signal from multiple input signals and direct it to a single output port. It is a multi-input, single-output combinational logic circuit. For the Butterfly structure in the Benes network, when the control signal is 0, the MUX will perform a replacement operation; when the control signal is 1, the MUX directly conducts the input signal to the output port. In the InverseButterfly, the corresponding logic is exactly the opposite. When the control signal is 1, the MUX performs a replacement operation; when the control signal is 0, the MUX directly passes the input signal. The MUX in the Benes network correctly transmits the input signal to the specified output port through configuration instructions, thereby realizing the replacement of input and output. As one of the key components of the Benes network, the MUX provides the necessary support and guarantee for the effective transmission of data in complex network structures. The Benes network can realize arbitrary order exchange of signals. Taking 8-bit data input and 8bit Benes network as an example, Figure 7 The figure is a schematic diagram of an 8-bit Benes network circuit structure. Under the action of specific control signals 11010010, 01100010, 01000010, the input signal can be replaced from the order of ABCDEFGH to CFGHBDEA. The control signals of the Benes network 1 and the Benes network 2 are secret keys, which are stored and transmitted separately.

[0028] The present invention provides a specific embodiment, such as Figure 8 As shown, the specific steps include the following:

[0029] 1) Performing a permutation operation on the neural network weights stored in the 1T1R array, and performing a column transformation on the basis of the row transformation of the 1T1R array to achieve encryption;

[0030] 2) The original input sequence abcd is permuted through the Benes network 1. In this example, the input sequence is permuted to cdba. Through the Benes network 1, the input signal can be corresponded to the row sequence of the encrypted 1T1R array one by one, and the row transformation can be achieved.

[0031] 3) The 1T1R array completes the corresponding matrix-vector multiplication operation and obtains the corresponding output result.

[0032] 4) Benes network 2 is used to process the calculation result sequence of the 1T1R array output, which replaces the calculation result sequence of the original input to complete the decryption. That is, the chaotic calculation result sequence c'a'b'd' is restored to the correct calculation result sequence of the original input a'b'c'd', and the results a+b+c+d, a+b+c, b and a are obtained.

[0033] The present invention utilizes Benes network 1 and Benes network 2 for auxiliary encryption, which not only ensures that the order of input and output remains unchanged, but also effectively encrypts the data of the internal circuit of the chip.

[0034] The present invention can use an 8-bit Benes network for 1T1R arrays to encrypt every 8 rows and 8 columns in the array, respectively, thereby further improving data security. That is, an 8-bit Benes network is added to every 8 rows and every 8 columns of the 1T1R array, and every three adjacent benes networks use the same encryption method (i.e., have the same control signal), so that the storage and bandwidth requirements of the control signal are greatly reduced. Only under the action of the corresponding control signal (i.e., the key) can the correct in-memory calculation result be read, thereby realizing data encryption of the in-memory computing chip. The present invention ensures that the order of the data stream is not affected by the encryption operation, while ensuring the security and confidentiality of the weight data inside the chip. Since the power consumption and area of ​​the Benes network itself are very small, this method can achieve more efficient and flexible data encryption and replacement protection at the chip level.

[0035] The above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit the same. A person skilled in the art may modify or make equivalent substitutions for the technical solutions of the present invention without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to the claims.

Claims

1. A 1T1R array encryption method based on Benes network, characterized in that: Several Benes networks 1 are connected to the rows of the 1T1R array, and several Benes networks 2 are connected to the columns of the 1T1R array. The control signals of the Benes networks 1 and 2 are secret keys, which are stored and transmitted separately. The specific steps include the following: 1) Performing a permutation operation on the neural network weights stored in the 1T1R array, and performing a column transformation on the basis of the row transformation of the 1T1R array to achieve encryption; 2) The original input sequence is replaced by the Benes network 1 into a row sequence of a 1T1R array for input; 3) The 1T1R array completes the matrix-vector multiplication operation and outputs the calculation result sequence; 4) Benes network 2 replaces the calculation result sequence of the output of the 1T1R array with the calculation result sequence of the original input, thereby obtaining the correct calculation result of the original input and completing the decryption.

2. The 1T1R array encryption method based on Benes network as claimed in claim 1, characterized in that: Every 8 rows in the 1T1R array are connected to an 8-bit Benes network 1.

3. The 1T1R array encryption method based on Benes network as claimed in claim 1, characterized in that: Every 8 columns in the 1T1R array are connected to an 8-bit Benes network2.

4. The 1T1R array encryption method based on Benes network as claimed in claim 1, characterized in that: Every three adjacent Benes networks 1 or Benes networks 2 use the same control signal.

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