Nonvolatile memory device and memory system including same

Abstract

A nonvolatile memory device includes: a peripheral circuit structure including a peripheral circuit and a lower insulating structure on the peripheral circuit; a cell array structure having a cell region and a peripheral connection region and including: an upper insulating structure in contact with the lower insulating structure; a cell stack in the cell region on the upper insulating structure; a common source line layer on the cell stack and having a common source opening; a plurality of cell channel structures extending in a vertical direction in the cell stack and extending into the common source line layer; and a support structure extending in a vertical direction in the cell stack and into the common source opening; and a pad pattern extending from the peripheral connection region to the cell region on the cell array structure and overlapping the support structure in the vertical direction.

Description

Technical Field

[0001] The present inventive concept generally relates to a nonvolatile memory device, a method of manufacturing the nonvolatile memory device, and a memory system including the nonvolatile memory device. More specifically, the present inventive concept relates to a three-dimensional nonvolatile memory device and a memory system including the three-dimensional nonvolatile memory device. Background Art

[0002] Consumers demand nonvolatile memory devices with high performance, small size, and low price. Therefore, in order to realize nonvolatile memory devices with high integration, three-dimensional nonvolatile memory devices including a plurality of memory cells arranged in a vertical direction have been proposed. Summary of the invention

[0003] The inventive concept provides a nonvolatile memory device having structural reliability and a memory system including the nonvolatile memory device.

[0004] According to aspects of the inventive concept, a nonvolatile memory device is provided, which includes a peripheral circuit structure and a cell array structure, the peripheral circuit structure including a peripheral circuit, a lower insulating structure covering the peripheral circuit, and a plurality of lower bonding pads on an upper surface of the lower insulating structure and electrically connected to the peripheral circuit, the cell array structure having a cell region and a peripheral connection region and including: an upper insulating structure in contact with the lower insulating structure; an upper bonding pad on a lower surface of the upper insulating structure and bonded to the plurality of lower bonding pads; a cell stack arranged on the upper insulating structure in the cell region; a common source line layer on the cell stack and having a common source opening; a plurality of cell channel structures penetrating (i.e., at least partially extending to) the cell stack and extending into the common source line layer; and a support structure penetrating the cell stack and extending into the common source opening; and a pad pattern extending from the peripheral connection region to the cell region on the cell array structure and overlapping with the support structure in a vertical direction.

[0005] According to another aspect of the inventive concept, a nonvolatile memory device is provided, including a peripheral circuit structure, the peripheral circuit structure including a peripheral circuit, a lower insulating structure covering the peripheral circuit (i.e., on or above the peripheral circuit), and a plurality of lower bonding pads on an upper surface of the lower insulating structure and electrically connected to the peripheral circuit; a cell array structure having a cell region and a peripheral connection region, and including: an upper insulating structure in contact with the lower insulating structure; a common source line layer arranged on the upper insulating structure in the cell region and having a common source opening; a filling insulating layer covering the cell stack on the upper insulating structure; a base insulating layer filling the common source opening and covering the common source line layer and the filling insulating layer; a base insulating layer penetrating the cell stack and extending to the common source line layer; and a base insulating layer extending from the base insulating layer to the common source line layer. A plurality of cell channel structures in a layer; a support structure that penetrates the cell stack, extends into a base insulating layer filling a common source opening, and is not electrically connected to a plurality of upper bonding pads; and a through contact plug that penetrates the filling insulating layer in a peripheral connection area, extends into the base insulating layer, and is connected to one of a plurality of upper bonding pads; a pad pattern that extends from the peripheral connection area to the cell area on the cell array structure, overlaps with the support structure and the through contact plug in a vertical direction, and is electrically connected to the through contact plug; and a pad connection path and a pad support path that penetrate the base insulating layer and are connected between the through contact plug and the pad pattern and between the support structure and the pad pattern, the pad connection path and the pad support path comprising the same material.

[0006] According to another aspect of the inventive concept, a memory system is provided, comprising: a nonvolatile memory device, the nonvolatile memory device comprising a peripheral circuit structure, a cell array structure bonded to the peripheral circuit structure and having a cell region and a peripheral connection region, and a pad pattern extending from the peripheral connection region to the cell region on the cell array structure, the peripheral circuit structure comprising a peripheral circuit, a lower insulating structure covering the peripheral circuit, and a plurality of lower bonding pads on an upper surface of the lower insulating structure and electrically connected to the peripheral circuit; and a memory controller electrically connected to the nonvolatile memory device through bonding wires connected to the pad pattern and configured to control the nonvolatile memory device, wherein the cell array structure comprises: an upper insulating structure contacting the lower insulating structure; an upper bonding pad on a lower surface of the upper insulating structure and bonded to the plurality of lower bonding pads; and a storage controller electrically connected to the nonvolatile memory device through bonding wires connected to the pad pattern. A cell stack in a cell area on the structure; a common source line layer arranged on the cell stack in the cell area and having a common source opening; a filling insulation layer covering the cell stack on the upper insulation structure; a base insulation layer filling the common source opening and covering the common source line layer and the filling insulation layer; a plurality of cell channel structures penetrating the cell stack and extending into the common source line layer; a support structure penetrating the cell stack, extending into the base insulation layer filling the common source opening, and not electrically connected to a plurality of upper bonding pads; a through contact plug penetrating the filling insulation layer in the peripheral connection area, extending into the base insulation layer, and electrically connecting a pad pattern to one of a plurality of upper bonding pads; and a pad connection path and a pad support path, each of which penetrates the base insulation layer and is connected between the through contact plug and the pad pattern and between the support structure and the pad pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which like reference numerals (when used) indicate corresponding elements throughout the several views, and in which:

[0008] Figure 1 is a schematic block diagram of an example non-volatile memory device according to one or more embodiments;

[0009] Figure 2 is a schematic perspective view of an example non-volatile memory device according to one or more embodiments;

[0010] Figure 3 is an equivalent circuit diagram of a memory cell array of a nonvolatile memory device according to one or more embodiments;

[0011] Figure 4A and 4B is a schematic layout (ie, plan view) diagram of an example nonvolatile memory device according to one or more embodiments;

[0012] FIG. 5A to FIG. 5C is a schematic plan view of a nonvolatile memory device according to an embodiment;

[0013] FIG. 6A to FIG. 6D is a schematic cross-sectional view of an example nonvolatile memory device according to an embodiment;

[0014] Fig. 7A and 7B is a schematic cross-sectional view of an example nonvolatile memory device according to an embodiment;

[0015] Fig. 8A and 8B is a schematic layout diagram of a nonvolatile memory device according to an embodiment;

[0016] 9A to 9C is a schematic cross-sectional view of a nonvolatile memory device according to an embodiment;

[0017] Fig. 10A and Fig. 10B is a schematic cross-sectional view of a nonvolatile memory device according to an embodiment;

[0018] Fig.11 is a schematic cross-sectional view of an example nonvolatile memory device according to one or more embodiments;

[0019] FIG. 12A to FIG. 12C is a schematic cross-sectional view of an example nonvolatile memory device according to an embodiment;

[0020] Fig.13 is a diagram schematically illustrating an example memory system including a nonvolatile memory device according to one or more embodiments;

[0021] Fig.14 is a perspective view schematically illustrating an example memory system including a nonvolatile memory device according to one or more embodiments; and

[0022] Fig.15 is a cross-sectional view schematically illustrating an example semiconductor package according to one or more embodiments. DETAILED DESCRIPTION

[0023] Figure 1 is a schematic block diagram depicting at least a portion of an example non-volatile memory device 10 according to one or more embodiments.

[0024] Reference Figure 1, the nonvolatile memory device 10 may include a memory cell array 20 and a peripheral circuit 30. The memory cell array 20 may include a plurality of memory cell blocks BLK1, BLK2, ..., BLKn, where n is an integer greater than 1. Each of the memory cell blocks BLK1, BLK2, ..., BLKn may include a plurality of memory cells. The memory cell blocks BLK1, BLK2, ..., BLKn may be connected to the peripheral circuit 30 through one or more corresponding bit lines BL, one or more corresponding word lines WL, one or more corresponding string selection lines SSL, and one or more ground selection lines GSL.

[0025] The peripheral circuit 30 may include a row decoder 32, a page buffer 34, a data input / output (I / O) circuit 36, and a control logic 38. In some embodiments, the peripheral circuit 30 may also include an I / O interface, column logic, a voltage generator, a pre-decoder, a temperature sensor, a command decoder, an address decoder, an amplification circuit, etc. (not explicitly shown).

[0026] The memory cell array 20 may be connected to the page buffer 34 through the bit line BL, and may be connected to the row decoder 32 through the word line WL, the string selection line SSL and the ground selection line GSL. In the memory cell array 20, each of the memory cells included in the memory cell blocks BLK1, BLK2, ..., BLKn may be a flash memory cell. The memory cell array 20 may include a three-dimensional memory cell array. The three-dimensional memory cell array may include a plurality of NAND strings extending in a vertical direction. Each of the NAND strings may include a plurality of memory cells connected to a plurality of word lines WL vertically stacked on a substrate.

[0027] The peripheral circuit 30 may receive an external address ADDR, a command signal CMD, and a control signal CTRL from outside the nonvolatile memory device 10 , and may transmit and receive data DATA to and from a device existing outside the nonvolatile memory device 10 .

[0028] The row decoder 32 may select at least one of the memory cell blocks BLK1, BLK2, ..., BLKn in response to the external address ADDR, and may select the word line WL, the string selection line SSL, and the ground selection line GSL of the selected memory cell block. The row decoder 32 may transmit a voltage for performing a storage operation to the word line WL of the selected memory cell block.

[0029] The page buffer 34 may be connected to the memory cell array 20 through the bit line BL. The page buffer 34 may operate as a write driver during a program operation and may apply a voltage to the bit line BL according to the data DATA to be stored in the memory cell array 20. The page buffer 34 may operate as a sense amplifier during a read operation and may detect the data DATA stored in the memory cell array 20. The page buffer 34 may operate in response to a control signal PCTL provided from the control logic 38.

[0030] The data I / O circuit 36 ​​may be connected to the page buffer 34 through the data line DL. The data I / O circuit 36 ​​may receive data DATA from a memory controller (not shown) during a program operation and may provide the program data DATA to the page buffer 34 based on the column address C_ADDR provided from the control logic 38. The data I / O circuit 36 ​​may provide read data DATA stored in the page buffer 34 to the memory controller based on the column address C_ADDR provided from the control logic 38 during a read operation.

[0031] The data I / O circuit 36 ​​may transmit an input address or command to the control logic 38 or the row decoder 32. The peripheral circuit 30 may also include an electrostatic discharge (ESD) circuit and a pull-up / pull-down driver.

[0032] The control logic 38 may receive a command CMD and a control signal CTRL from a memory controller. The control logic 38 may provide a row address R_ADDR to the row decoder 32 and may provide a column address C_ADDR to the data I / O circuit 36. The control logic 38 may generate various internal control signals used in the nonvolatile memory device 10 in response to the control signal CTRL. For example, the control logic 38 may control the voltage levels provided to the word lines WL and the bit lines BL during a memory operation such as a program operation or an erase operation.

[0033] Figure 2 is a schematic perspective view of an example nonvolatile memory device 10 according to one or more embodiments.

[0034] Reference Figure 2 , the nonvolatile memory device 10 may include a cell array structure CS and a peripheral circuit structure PS that overlap each other in a vertical direction (Z direction). As may be used herein, the term "overlap" (or "overlapping" or similar terms) is intended to broadly refer to a first element that intersects at least a portion of a second element in a vertical direction (i.e., Z direction), but does not require that the first element and the second element be completely aligned with each other in a horizontal plane (i.e., in the X direction and / or Y direction). The cell array structure CS may include reference Figure 1 The memory cell array 20 described herein. The peripheral circuit structure PS may include reference Figure 1 The peripheral circuit 30 is described.

[0035] The cell array structure CS may include a plurality of memory cell blocks BLK1 , BLK2 , . . . , BLKn. Each of the memory cell blocks BLK1 , BLK2 , . . . , BLKn may include memory cells that are three-dimensionally arranged (eg, in a stacked configuration).

[0036] Figure 3 is an equivalent circuit diagram of at least a portion of an example memory cell array MCA of a nonvolatile memory device according to one or more embodiments.

[0037] refer to Figure 3 , the memory cell array MCA may include a plurality of memory cell strings MS. The memory cell array MCA may include a reference Figure 1 At least a portion of the memory cell array 20 described. In some embodiments, the memory cell array MCA may include reference Figure 1 At least a portion of one of the memory cell blocks BLK1, BLK2, . . . , BLKn included in the described memory cell array 20.

[0038] Each of the memory cell strings MS may extend in a vertical direction (Z direction). The memory cell array MCA may include a plurality of word lines WL (WL1, WL2, ..., WLn-1, WLn, where n is an integer greater than 1), a plurality of bit lines BL (BL1, BL2, ..., BLm, where m is an integer greater than 1, which may be equal to or not equal to n), at least one string selection line SSL, at least one ground selection line GSL, and a common source line CSL. Each of the word lines WL (WL1, WL2, ..., WLn-1, WLn) may extend in a first horizontal direction (e.g., X direction), and each of the bit lines BL (BL1, BL2, ..., BLm) may extend in a second horizontal direction (e.g., Y direction) perpendicular to the first horizontal direction (X direction). At least one string selection line SSL and at least one ground selection line GSL may each extend in the same direction as the word lines WL (WL1, WL2, . . . , WLn-1, WLn), for example, in a first horizontal direction (X direction). The memory cell string MS may be formed between the bit lines BL (BL1, BL2, . . . , BLm) and the common source line CSL. Although Figure 3 A case where each memory cell string MS includes two string selection lines SSL is illustrated, but the technical concept of the inventive concept is not limited thereto. For example, each of the memory cell strings MS may include one string selection line SSL.

[0039] Each of the memory cell strings MS may include a string selection transistor SST, a ground selection transistor GST, and a plurality of memory cell transistors MC1, MC2, ..., MCn-1, and MCn. The drain region of the string selection transistor SST may be connected to a bit line BL (BL1, BL2, ..., BLm), and the source region of the ground selection transistor GST may be connected to a common source line CSL. The common source line CSL may be a region where the source regions of the ground selection transistors GST are commonly connected.

[0040] The string selection transistor SST may be connected to a string selection line SSL, and the ground selection transistor GST may be connected to a ground selection line GSL. The memory cell transistors MC1, MC2, ..., MCn-1, and MCn may be connected to word lines WL (WL1, WL2, ..., WLn-1, WLn), respectively.

[0041] Figure 4A and 4B is a schematic layout diagram of a nonvolatile memory device 1 according to one or more embodiments.

[0042] Reference Figure 4A , the nonvolatile memory device 1 may include a cell region CELL and an edge region ER surrounding the cell region CELL in a plan view (e.g., the periphery of the memory device 1). The term "surrounding" (or "enclosing" or similar terms) as may be used herein is intended to broadly refer to an element, structure or layer that extends around, encapsulates, surrounds or surrounds another element, structure or layer on all sides, although there may also be a break or gap. Thus, for example, a material layer having a void or gap therein may still "surround" another layer that surrounds it. The peripheral connection area PA may be between the cell region CELL and the edge region ER. In some embodiments, the peripheral connection area PA may be between the cell region CELL and the edge region ER in the second horizontal direction (Y direction) and extend in the first horizontal direction (X direction). In some embodiments, the peripheral connection area PA may not be between the cell region CELL and the edge region ER in the second horizontal direction (Y direction).

[0043] The nonvolatile memory device 1 may include a plurality of pad patterns PAD. In some embodiments, the pad patterns PAD may be arranged on two sides of the edge region ER that are opposite to each other in the second horizontal direction (Y direction). The pad patterns PAD may be arranged to form rows along the peripheral connection region PA. In some embodiments, the pad patterns PAD may be arranged to form rows in the first horizontal direction (X direction), but the embodiment is not limited thereto. Each of the pad patterns PAD may be positioned across the peripheral connection region PA and the cell region CELL. For example, a portion of each pad pattern PAD may be located in the peripheral connection region PA, and another portion thereof may be located in the cell region CELL.

[0044] Also refer to Figure 4A and Figure 4B , the nonvolatile memory device 1 may include a cell array structure CS. The nonvolatile memory device 1 may be Figure 1 The nonvolatile memory device 10 shown in FIG. 1 may include a cell array structure CS. Figure 2 The cell array structure CS is shown.

[0045] The cell array structure CS may include a plurality of memory cell blocks BLK1, BLK2, BLK3, and BLK4. The memory cell blocks BLK1, BLK2, BLK3, and BLK4 may be arranged to form rows and columns in a first horizontal direction (X direction) and a second horizontal direction (Y direction). The first horizontal direction (X direction) may be Figure 3 The extending direction of each of the word lines WL (WL1, WL2, . . . , WLn-1, WLn) shown, and the second horizontal direction (Y direction) may be Figure 3 An extending direction of each of the bit lines BL (BL1, BL2, . . . , BLm) is shown. Each of the memory cell blocks BLK1, BLK2, BLK3, and BLK4 may include a plurality of memory cells.

[0046] Each of the memory cell blocks BLK1, BLK2, BLK3, and BLK4 may include a cell region CELL and a cell connection region EXT. In some embodiments, each of the memory cell blocks BLK1, BLK2, BLK3, and BLK4 may include one cell region CELL and a pair of cell connection regions EXT arranged on two (e.g., opposite) sides of one cell region CELL. The pair of cell connection regions EXT may extend in the second horizontal direction (Y direction) on both sides of one cell region CELL in the first horizontal direction (X direction). In other embodiments, each of the memory cell blocks BLK1, BLK2, BLK3, and BLK4 may include one cell region CELL and one cell connection region EXT arranged on one side of one cell region CELL. In other embodiments, each of the memory cell blocks BLK1, BLK2, BLK3, and BLK4 may include one cell region CELL and two pairs of cell connection regions EXT, which are arranged on two (opposite) sides of one cell region CELL in the first horizontal direction (X direction) and on both sides of one cell region CELL in the second horizontal direction (Y direction).

[0047] In some embodiments, each of the memory cell blocks BLK1, BLK2, BLK3, and BLK4 may further include a peripheral connection region PA. The peripheral connection region PA may be arranged on at least one of both sides of the cell region CELL in the second horizontal direction (Y direction). Figure 2 The components of the peripheral circuit structure PS described above connected to the cell region CELL and / or the cell connection region EXT may be arranged in the peripheral connection region PA. Alternatively, for example, the peripheral connection region PA may also include reference Figure 1 At least a portion of the peripheral circuit 30 is described.

[0048] Figure 4A The peripheral connection area PA shown in FIG. 1 may only show Figure 4B The peripheral connection area PA shown in FIG. 1 is a portion of the peripheral connection area PA adjacent to the edge area ER of the nonvolatile memory device 1. For example, Figure 4A The cell region CELL shown may include Figure 4B The cell region CELL and the cell connection region EXT of each of the memory cell blocks BLK1, BLK2, BLK3, and BLK4 are shown as well as Figure 4B At least a portion of the peripheral connection area PA of each of the memory cell blocks BLK1, BLK2, BLK3, and BLK4 is shown.

[0049] FIG. 5A to FIG. 5C is a schematic plan view of a nonvolatile memory device according to an embodiment.

[0050] Reference Figure 5A , the nonvolatile memory device 1 - 1 may include a cell region CELL and a peripheral connection region PA adjacent to the cell region CELL in a plan view. Figure 5A The peripheral connection area PA shown can be connected with Figure 4A The cell region CELL may include a real cell region RCR and a dummy cell region DCR adjacent to the real cell region RCR. The dummy cell region DCR may be arranged along the edge of the cell region CELL so as to surround the real cell region RCR in a plan view. For example, the dummy cell region DCR may be between the real cell region RCR and the peripheral connection region PA.

[0051] The pad pattern PAD may extend from the peripheral connection area PA to the cell area CELL in a second horizontal direction (Y direction) so as to be positioned across the peripheral connection area PA and the cell area CELL. For example, a portion of the pad pattern PAD may be located in the peripheral connection area PA, and another portion of the pad pattern PAD may be located in the cell area CELL. In the cell area CELL, the pad pattern PAD may extend across the dummy cell area DCR and the real cell area RCR. For example, the pad pattern PAD may extend across the peripheral connection area PA, the dummy cell area DCR, and the real cell area RCR in the second horizontal direction. The edge portion of the pad pattern PAD may be covered with a protective layer (not shown) (e.g., see Fig. 10A 350). As may be used herein, the term "covering" (or "covering" or similar terms) is intended to broadly refer to an element, structure or layer that is on or over another element, structure or layer, directly or with one or more other intervening elements, structures or layers therebetween. Protective layer (see Fig. 10A 350) may have a pad opening POP (see Fig. 10A At least a portion of the pad pattern PAD may be exposed to the outside of the nonvolatile memory device 1-1 through the pad opening POP. The term "exposed" (or "exposed" or similar terms) may be used herein to describe the relationship between elements and / or refer to an intermediate process in manufacturing a semiconductor device, but may not require that a particular element be exposed in a completed device. Similarly, the term "unexposed" may be used to describe the relationship between elements and / or refer to an intermediate process in manufacturing a semiconductor device, but may not require that a particular element be unexposed in a completed device.

[0052] The common source line layer CSL may be disposed in at least a portion of the cell region CELL. The common source line layer CSL may be Figure 3The common source line CSL shown. In a plan view, a portion of the pad pattern PAD may overlap vertically with the common source line layer CSL. The common source line layer CSL may have a common source opening CSLO. The common source opening CSLO may be formed by removing a portion of the common source line layer CSL from a portion of the cell area CELL adjacent to the peripheral connection area PA. For example, the common source line layer CSL may not be located in the peripheral connection area PA, and may be located only in the cell area CELL. The common source opening CSLO may be located in the cell area CELL adjacent to the peripheral connection area PA. In a plan view, the common source opening CSLO may be located at the edge of the common source line layer CSL. In some embodiments, the common source opening CSLO may be located in the dummy cell area DCR, and may not be located in the real cell area RCR. At least a portion of the common source opening CSLO may overlap with the pad pattern PAD in the vertical direction (Z direction).

[0053] In the peripheral connection area PA, at least one through contact plug IOMC may be disposed under the pad pattern PAD. In the cell area CELL, at least one support structure SPS may be disposed under the pad pattern PAD. At least one support structure SPS may overlap with the common source opening CSLO in the vertical direction (Z direction). In a plan view, the support structure SPS may be located in the dummy cell area DCR and may not be located in the real cell area RCR. Although Figure 5A It is shown that a plurality of support structures SPS overlap with one common source opening CSLO in the vertical direction (Z direction), but this is only an example, and the inventive concept is not limited thereto. For example, the common source line layer CSL may have a plurality of common source openings CSLO. Each of the common source openings CSLO may overlap with at least one support structure SPS in the vertical direction (Z direction).

[0054] although Figure 5A It is shown that the through contact plugs IOMC are all arranged in the peripheral connection area PA and the support structures SPS are all arranged in the dummy cell area DCR, but the inventive concept is not limited thereto. For example, some through contact plugs IOMC may be arranged in the peripheral connection area PA, and at least one other through contact plug IOMC may be arranged in the dummy cell area DCR. For example, some support structures SPS may be arranged in the dummy cell area DCR, and at least one other support structure SPS may be arranged in the peripheral connection area PA.

[0055] In some embodiments, Figure 5A Unlike the embodiment shown in , the pad pattern PAD may be located only in the dummy cell region DCR in the cell region CELL. Fig. 7AAs shown, the pad pattern PAD may be positioned across the peripheral connection region PA and the dummy cell region DCR. In some embodiments, the pad pattern PAD may not overlap the common source line layer CSL in a plan view.

[0056] Reference Figure 5B , the nonvolatile memory device 1-2 may include a cell region CELL and a peripheral connection region PA adjacent to the cell region CELL in a plan view. The cell region CELL may include a real cell region RCR and a dummy cell region DCR adjacent to the real cell region RCR. The pad pattern PAD may extend from the peripheral connection region PA to the cell region CELL in a second horizontal direction (Y direction) so as to be positioned across the peripheral connection region PA and the cell region CELL. In the cell region CELL, the pad pattern PAD may be positioned across the dummy cell region DCR and the real cell region RCR. The common source line layer CSL may be arranged in the cell region CELL. In a plan view, a portion of the pad pattern PAD may overlap with the common source line layer CSL.

[0057] The common source line layer CSL may have a plurality of common source openings CSLO spaced apart from each other in a first horizontal direction (X direction) and / or a second horizontal direction (Y direction). A plurality of common source openings CSLO may be formed by removing a portion of the common source line CSL from a portion of the cell region CELL adjacent to the peripheral connection region PA. In some embodiments, some of the common source openings CSLO may be located in a dummy cell region DCR, and other common source openings therein may be located in a real cell region RCR. For example, in a plan view, some of the plurality of support structures SPS may be located in a dummy cell region DCR, and other support structures therein may be located in a real cell region RCR. At least some of the common source openings CSLO may be spaced apart from the edge of the common source line layer CSL.

[0058] In the cell region CELL, the support structure SPS may be disposed under the pad pattern PAD. Each of the support structures SPS may overlap one of the common source openings CSLO in the vertical direction (Z direction). For example, each of the common source openings CSLO may overlap at least one support structure SPS in the vertical direction (Z direction).

[0059] Reference Figure 5C, the non-volatile memory device 1-3 may include a cell area CELL and a peripheral connection area PA adjacent to the cell area CELL in a plan view. The pad pattern PAD may extend from the peripheral connection area PA to the cell area CELL in a second horizontal direction (Y direction) so as to be positioned across the peripheral connection area PA and the cell area CELL. In the cell area CELL, the pad pattern PAD may be positioned across the dummy cell area DCR and the real cell area RCR. The common source line layer CSL may be arranged in the cell area CELL. In a plan view, the pad pattern PAD may not overlap with the common source line layer CSL in a vertical direction. The common source line layer CSL may have a common source opening CSLO. The common source opening CSLO may be formed by removing a portion of the common source line CSL from a portion of the cell area CELL adjacent to the peripheral connection area PA. The common source opening CSLO may be located in the cell area CELL adjacent to the peripheral connection area PA. In a plan view, the common source opening CSLO may be located at the edge of the common source line layer CSL. The common source opening CSLO may extend across the dummy cell region DCR and the real cell region RCR in the second horizontal direction (Y direction).

[0060] In the cell region CELL, the support structure SPS may be disposed under the pad pattern PAD. The support structure SPS may overlap with the common source opening CSLO in the vertical direction (Z direction). Some of the support structures SPS may be arranged in the dummy cell region DCR, and other support structures therein may be arranged in the real cell region RCR.

[0061] FIG. 6A to FIG. 6D is a schematic cross-sectional view of an example nonvolatile memory device according to some embodiments.

[0062] Reference Fig. 6A , the nonvolatile memory device 1 a may include a cell region CELL and a peripheral connection region PA adjacent to the cell region CELL. Fig. 6A The peripheral connection area PA shown can be connected with Figure 4A The edge region ER shown is adjacent. In some embodiments, the cell region CELL may include FIG. 5A to FIG. 5C The real cell area RCR shown in .

[0063] The pad pattern PAD may extend from the peripheral connection area PA to the cell area CELL in a second horizontal direction (Y direction) so as to be positioned across the peripheral connection area PA and the cell area CELL. The pad pattern PAD may be exposed to the outside of the nonvolatile memory device 1a through a pad opening POP vertically overlapping at least a portion of the pad pattern PAD. The stacked mold SMLD and the common source line layer CSL disposed on the stacked mold SMLD may be arranged in the cell area CELL. The stacked mold SMLD and the common source line layer CSL may be arranged in the cell area CELL and may not be arranged in the peripheral connection area PA. A plurality of cell channel structures CHS may penetrate (i.e., at least partially extend to) the stacked mold SMLD and extend in a vertical direction (Z direction) so as to be connected to the common source line layer CSL. As may be used herein, the term "connected" (or "connected" or similar terms, such as "contact" or "contacting") is intended to refer to a physical and / or electrical connection between two or more elements, and may include other intermediate elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0064] The common source line layer CSL may have at least one common source opening CSLO. The at least one common source opening CSLO may extend from the upper surface of the common source line layer CSL to the lower surface. At least one support structure SPS may penetrate (i.e., at least partially extend to) the stacked mold SMLD and extend into the at least one common source opening CSLO. At least one support structure SPS may overlap with the pad pattern PAD in the vertical direction (Z direction). In some embodiments, the common source line layer CSL may have a plurality of common source openings CSLO spaced apart from each other in a first horizontal direction (X direction) and / or a second horizontal direction (Y direction). Although Fig. 6A It is shown that one support structure SPS penetrates the stack mold SMLD and extends into the common source opening CSLO, but the inventive concept is not limited thereto. For example, two or more support structures SPS may penetrate the stack mold SMLD and extend into the common source opening CSLO.

[0065] In the peripheral connection area PA, at least one through contact plug IOMC may be disposed under the pad pattern PAD. The pad pattern PAD may overlap with at least one through contact plug IOMC and at least one support structure SPS in the vertical direction (Z direction). In some embodiments, the pad pattern PAD may overlap with some unit channel structures CHS in the vertical direction (Z direction) and may not overlap with other unit channel structures CHS. In some embodiments, the pad pattern PAD may not overlap with all unit channel structures CHS in the vertical direction (Z direction).

[0066] The pad connection path PCOT may be between the pad pattern PAD and the through contact plug IOMC. The upper surface and the lower surface of the pad connection path PCOT may contact the lower surface of the pad pattern PAD and the upper surface of the through contact plug IOMC, respectively. The pad support path SCOT may be between the pad pattern PAD and the support structure SPS. The upper surface and the lower surface of the pad support path SCOT may contact the lower surface of the pad pattern PAD and the upper surface of the support structure SPS, respectively.

[0067] The cell channel structure CHS and at least one through contact plug IOMC may be electrically connected to the upper bonding pad BPD. The cell channel structure CHS and at least one through contact plug IOMC may be electrically connected to the upper bonding pad BPD. Figure 2 The peripheral circuit structure PS shown. The unit channel structure CHS and at least one through contact plug IOMC may be electrically connected to the bit line BL. The unit channel structure CHS and at least one through contact plug IOMC may be electrically connected to the bit line BL through the bit line contact BLC. The bit line BL may be electrically connected to the upper bonding pad BPD through the upper interconnect structure ITCS. For example, the bit line contact BLC, the bit line BL, and the upper interconnect structure ITCS may be sequentially arranged between each unit channel structure CHS and at least one through contact plug IOMC and the upper bonding pad BPD.

[0068] although Fig. 6A It is shown that the upper interconnect structure ITCS is a contact, but this is only an example, and the inventive concept is not limited thereto. For example, the upper interconnect structure ITCS may include one or more contacts and one or more wiring layers. In some embodiments, the contact plug, the bit line contact BLC, and the through contact plug IOMC included in the upper interconnect structure ITCS may each have a tapered shape, wherein when extending vertically from the lower side to the upper side, its horizontal width decreases. In some embodiments, the pad connection path PCOT and the pad support path SCOT may each have a tapered shape, wherein when extending vertically from the lower side to the upper side, its horizontal width increases.

[0069] The support structure SPS may not be electrically connected to the upper bonding pad BPD. The support structure SPS may not be electrically connected to the bit line BL. For example, the bit line contact BLC may be connected to the lower surface of each cell channel structure CHS and at least one through contact IOMC, but the bit line contact BLC may not be connected to the lower surface of the support structure SPS.

[0070] In some embodiments, at least a portion of the unit channel structure CHS and at least a portion of the support structure SPS may be formed together by the same manufacturing process. For example, the support structure SPS may have a structure that is the same as or substantially similar to that of the unit channel structure CHS. Fig. 10A and 10B The unit channel structure CHS is described in detail. The pad connection path PCOT and the pad support path SCOT can be formed together by the same manufacturing process. For example, the pad connection path PCOT and the pad support path SCOT may include the same material and have the same structure. In some embodiments, the pad connection path PCOT and the pad support path SCOT may include metal.

[0071] The nonvolatile memory device 1a according to the present invention may include a support structure SPS disposed below a pad pattern PAD, and a pad support path SCOT between the support structure SPS and the pad pattern PAD. Therefore, even when a load is applied to the pad pattern PAD during a wire bonding process of connecting a bonding wire to the upper surface of the pad pattern PAD exposed through a pad opening POP, the pad pattern PAD may be supported by the support structure SPS and the pad support path SCOT. Therefore, the nonvolatile memory device 1a according to the present invention may have structural reliability to prevent damage to the pad pattern PAD, the common source line layer CSL, the stack mold SMLD, and / or the cell channel structure CHS due to a load applied to the pad pattern PAD during the wire bonding process even when the pad pattern PAD is located on the cell region CELL.

[0072] Reference Figure 6B , the nonvolatile memory device 1b may include a support structure SPSa instead of Fig. 6A The support structure SPSa may include a material different from that of the unit channel structure CHS and may have a structure different from that of the unit channel structure CHS. For example, the support structure SPSa may include polysilicon or a carbon-containing material. In forming a plurality of channel holes (see Fig. 10A and Fig. 10B CHH), multiple sacrificial layers filling the channel holes CHH may be formed. The term "filled" (or "fill" or similar terms) as may be used herein is intended to broadly refer to completely filling a defined space (e.g., a channel hole CHH) or partially filling a defined space; that is, the defined space does not need to be completely filled, but may, for example, be partially filled or always have a void or other space. The support structure SPSA may be formed by leaving the sacrificial layer filling some of the channel holes CHH without being removed. After removing the sacrificial layer filling some of the channel holes CHH, a unit channel structure CHS may be formed by filling other channel holes CHH.

[0073] refer to Figure 6C , the nonvolatile memory device 1c may include a support structure SPSb instead of Fig. 6A The support structure SPSb may include a material different from that of the unit channel structure CHS and may have a structure different from that of the unit channel structure CHS. The support structure SPSb may include a metal-based material. For example, the support structure SPSb may include a metal (such as tungsten, nickel, cobalt, and tantalum), a conductive metal nitride (such as titanium nitride, tantalum nitride, and tungsten nitride), a metal silicide (such as tungsten silicide, nickel silicide, cobalt silicide, and tantalum silicide), or any combination thereof, but the embodiment is not limited thereto.

[0074] In some embodiments, the support structure SPSb may be electrically connected to the upper bonding pad BPD to electrically connect the pad pattern PAD together with the through contact IOMC to the upper bonding pad BPD. Figure 2 The peripheral circuit structure PS shown. For example, the bit line contact BLC, the bit line BL and the upper interconnect structure ITCS may be sequentially located between the support structure SPSb and the upper bonding pad BPD. In other embodiments, similar to Fig. 6A The support structure SPS shown in Figure 6B , the support structure SPSb may not be electrically connected to the upper bonding pad BPD, and the bit line contact BLC may not be connected to the lower surface of the support structure SPSb.

[0075] Reference Fig.6D , the nonvolatile memory device 1d may include a support structure SPSc instead of Figure 6C The support structure SPSc may include a material different from that of the cell channel structure CHS and may have a structure different from that of the cell channel structure CHS. The support structure SPSc may include a support core layer SPC and a support spacer layer SSP surrounding the support core layer SPC. Figure 6C In the support structure SPSb shown in FIG, the support core layer SPC may include a metal-based material. The support spacer layer SSP may be between the support core layer SPC and the stacking mold SMLD so that the support core layer SPC is electrically isolated from the stacking mold SMLD. The support spacer layer SSP may include an insulating material. For example, the support spacer layer SSP may include a nitride, an oxide, an oxynitride, or any combination thereof, but the embodiment is not limited thereto.

[0076] In some embodiments, the supporting core layer SPC may be electrically connected to the upper bonding pad BPD to electrically connect the pad pattern PAD together with the through contact IOMC to the upper bonding pad BPD. Figure 2 The peripheral circuit structure PS shown. For example, the bit line contact BLC, the bit line BL and the upper interconnect structure ITCS may be sequentially located between the support core layer SPC and the upper bonding pad BPD. In other embodiments, similar to Fig. 6AThe support structure SPS shown in Figure 6B In the support structure SPSa shown in FIG. 1 , the support core layer SPC may not be electrically connected to the upper bonding pad BPD, and the bit line contact BLC may not be connected to the lower surface of the support core layer SPC.

[0077] Fig. 7A and 7B is a schematic cross-sectional view of an example nonvolatile memory device according to an embodiment.

[0078] Reference Fig. 7A , the nonvolatile memory device 2a may include a cell region CELL and a peripheral connection region PA adjacent to the cell region CELL. Fig. 7A The peripheral connection area PA shown can be connected with Figure 4A The edge region ER shown is adjacent; that is, in a plan view, the peripheral connection region PA may be disposed between the edge region ER and the cell region CELL. The cell region CELL may include a real cell region RCR and a dummy cell region DCR. The dummy cell region DCR may be between the real cell region RCR and the peripheral connection region PA.

[0079] The pad pattern PAD may extend from the peripheral connection area PA to the dummy cell area DCR in the second horizontal direction (Y direction) so as to be positioned across the peripheral connection area PA and the dummy cell area DCR. The pad pattern PAD may be exposed to the outside of the nonvolatile memory device 2a through the pad opening POP. The stacked mold SMLD and the common source line layer CSL disposed on the stacked mold SMLD may be arranged in the cell area CELL. The stacked mold SMLD and the common source line layer CSL may be arranged in the cell area CELL and may not be arranged in the peripheral connection area PA.

[0080] The common source line layer CSL may have at least one common source opening CSLO. A plurality of cell channel structures CHS may be arranged in the real cell region RCR, and a plurality of dummy structures DCS may be arranged in the dummy cell region DCR. The plurality of cell channel structures CHS may penetrate the stack mold SMLD and extend in a vertical direction (Z direction) so as to be connected to the common source line layer CSL. Some dummy structures DCS may penetrate the stack mold SMLD and extend in a vertical direction (Z direction) so as to be connected to the common source line layer CSL, and other dummy structures DCS may penetrate the stack mold SMLD and extend into at least one common source opening CSLO. At least some of the dummy structures DCS may overlap with the pad pattern PAD in the vertical direction (Z direction). Other dummy structures DCS that penetrate the stack mold SMLD and extend into at least one common source opening CSLO may perform Fig. 6AThe function of the supporting structure SPS shown. Other dummy structures DCS performing the function of the supporting structure SPS may overlap the pad pattern PAD in the vertical direction (Z direction).

[0081] In some embodiments, the nonvolatile memory device 2a may further include a word line cutting region WLC penetrating the stacked mold SMLD. The word line cutting region WLC may be spaced apart from the cell channel structure CHS. In some embodiments, the word line cutting region WLC may extend between the cell channel structures CHS adjacent to each other along the second horizontal direction (Y direction) in the first horizontal direction (X direction). The word line cutting region WLC may include an oxide layer, a nitride layer, or any combination thereof, but the embodiment is not limited thereto.

[0082] In some embodiments, at least a portion of the unit channel structure CHS and at least a portion of the dummy structure DCS may be formed together by the same manufacturing process. For example, the dummy structure DCS may have a structure that is the same as or substantially similar to the unit channel structure CHS. In some embodiments, all dummy structures DCS or other dummy structures DCS that perform the function of the support structure SPS may have a structure that is the same as or substantially similar to the unit channel structure CHS. Fig. 6A The support structure SPS shown in Figure 6B The support structure SPSa shown in Figure 6C The support structure SPSb and Fig.6D An identical structure to the one in the support structure SPSc shown in .

[0083] In some embodiments, other dummy structures DCS performing the function of the support structure SPS may not be electrically connected to the upper bonding pads BPD. For example, the bit line contacts BLC may not be connected to the lower surface of other dummy structures DCS performing the function of the support structure SPS.

[0084] In some embodiments, when the dummy structure DCS has Figure 6C The support structure SPSb shown or Fig.6D When the support structure SPSc is the same as shown, the dummy structure DCS can be electrically connected to the upper bonding pad BPD to electrically connect the pad pattern PAD together with the through contact IOMC to the Figure 2 The peripheral circuit structure PS is shown.

[0085] Reference Figure 7B , the nonvolatile memory device 2 b may include a cell region CELL and a peripheral connection region PA adjacent to the cell region CELL. Figure 7B The peripheral connection area PA shown can be connected with Figure 4A The edge regions ER are shown to be adjacent. The cell region CELL may include a real cell region RCR and a dummy cell region DCR.

[0086] The pad pattern PAD may extend from the peripheral connection region PA to the real cell region RCR through the dummy cell region DCR so as to be positioned across the peripheral connection region PA, the dummy cell region DCR, and the real cell region RCR. The pad pattern PAD may be exposed to the outside of the nonvolatile memory device 2b through the pad opening POP. The stacked mold SMLD and the common source line layer CSL disposed on the stacked mold SMLD may be arranged in the cell region CELL.

[0087] The common source line layer CSL may have at least one common source opening CSLO. A plurality of cell channel structures CHS may be arranged in the real cell region RCR, and a plurality of dummy structures DCS may be arranged in the dummy cell region DCR. Some cell channel structures CHS may penetrate the stack mold SMLD and extend in a vertical direction (Z direction) so as to be connected to the common source line layer CSL. Some dummy structures DCS may penetrate the stack mold SMLD and extend in a vertical direction (Z direction) so as to be connected to the common source line layer CSL. Other cell channel structures CHS and other dummy structures DCS may each penetrate the stack mold SMLD and extend into at least one common source opening CSLO. Some cell channel structures CHS and at least some dummy structures DCS may overlap with the pad pattern PAD in the vertical direction (Z direction). Each of the other cell channel structures CHS and other dummy structures DCS that penetrate the stack mold SMLD and extend into at least one common source opening CSLO may perform Fig. 6A The function of the supporting structure SPS shown. Other cell channel structures CHS and other dummy structures DCS that perform the function of the supporting structure SPS may overlap the pad pattern PAD in a vertical direction (Z direction).

[0088] In some embodiments, the other cell channel structures CHS and other dummy structures DCS performing the function of the support structure SPS may not be electrically connected to the upper bonding pad BPD. For example, the bit line contact BLC may not be connected to the lower surface of each of the other cell channel structures CHS and other dummy structures DCS performing the function of the support structure SPS.

[0089] In some embodiments, at least a portion of the unit channel structure CHS and at least a portion of the dummy structure DCS may be formed together by the same manufacturing process. For example, the dummy structure DCS may have a structure that is the same as or substantially similar to the unit channel structure CHS. In some embodiments, all dummy structures DCS or other unit channel structures CHS and other dummy structures DCS that perform the function of the support structure SPS may have a structure that is the same as or substantially similar to the unit channel structure CHS. Fig. 6A The support structure SPS shown in Figure 6B The support structure SPSa shown in Figure 6C The support structure SPSb and Fig.6D An identical structure to the one in the support structure SPSc shown in .

[0090] Fig. 8A and 8B is a schematic layout diagram of a nonvolatile memory device 3 according to one or more embodiments.

[0091] Reference Fig. 8A , in a plan view, the nonvolatile memory device 3 may include a cell region CELL and an edge region ER surrounding the cell region CELL. The peripheral connection region PA may be between the cell region CELL and the edge region ER. In some embodiments, the peripheral connection region PA may extend between the cell region CELL and the edge region ER in the second horizontal direction (Y direction) and in the first horizontal direction (X direction), and may extend between the cell region CELL and the edge region ER in the first horizontal direction (X direction) and in the second horizontal direction (Y direction). Therefore, in a plan view, the peripheral connection region PA may surround the cell region CELL. The cell connection region EXT may be between the cell region CELL and the peripheral connection region PA. In some embodiments, the cell connection region EXT may extend between the cell region CELL and the peripheral connection region PA in the second horizontal direction (Y direction) and in the first horizontal direction (X direction), and may extend between the cell region CELL and the peripheral connection region PA in the first horizontal direction (X direction) and in the second horizontal direction (Y direction). Therefore, in a plan view, the cell connection region PA may surround the cell region CELL. For example, the cell connection region EXT may surround the cell region CELL in a plan view, the peripheral connection region PA may surround the cell connection region EXT in a plan view, and the edge region ER may surround the peripheral connection region PA in a plan view.

[0092] The nonvolatile memory device 3 may include a plurality of pad patterns PAD. In some embodiments, the pad pattern PAD may be arranged adjacent to both sides of the edge region ER opposite to each other in the second horizontal direction (Y direction) and the edge region ER opposite to each other in the first horizontal direction (X direction). For example, the pad pattern PAD may be arranged to surround the cell region CELL in a plan view. In some embodiments, the pad pattern PAD may be arranged only adjacent to both sides of the edge region ER opposite to each other in the second horizontal direction (Y direction), or may be arranged only adjacent to both sides of the edge region ER opposite to each other in the first horizontal direction (X direction). The pad pattern PAD may be arranged to form a row along the peripheral connection region PA. In some embodiments, the pad pattern PAD may be arranged to form a row in the first horizontal direction (X direction), or may be arranged to form a row in the second horizontal direction (Y direction). Each of the pad patterns PAD may be positioned across the peripheral connection region PA and the cell connection region EXT, or may be positioned across at least a portion of the peripheral connection region PA, the cell connection region EXT, and the cell region CELL.

[0093] Also refer to Fig. 8A and Figure 8B , the nonvolatile memory device 3 may include a cell array structure CS. The nonvolatile memory device 3 may be Figure 1 The nonvolatile memory device 10 shown in FIG. 1 may include a cell array structure CS. Figure 2 The cell array structure CS is shown.

[0094] The cell array structure CS may include a plurality of memory cell blocks BLK1, BLK2, BLK3, and BLK4. Each of the memory cell blocks BLK1, BLK2, BLK3, and BLK4 may include a cell region CELL and a cell connection region EXT. In some embodiments, each of the memory cell blocks BLK1, BLK2, BLK3, and BLK4 may include one cell region CELL and a cell connection region EXT surrounding the one cell region CELL in a plan view. A pair of cell connection regions EXT may extend from two (opposite) sides of one cell region CELL in a first horizontal direction (X direction) along a second horizontal direction (Y direction), and may extend from opposite sides of one cell region CELL in a second horizontal direction (Y direction) along a first horizontal direction (X direction).

[0095] In some embodiments, each of the memory cell blocks BLK1, BLK2, BLK3, and BLK4 may further include a peripheral connection region PA. The peripheral connection region PA may be arranged to surround the cell region CELL and the cell connection region EXT in a plan view, but the inventive concept is not limited thereto. For example, the peripheral connection region PA may be arranged on two (opposite) sides of the cell region CELL in the second horizontal direction (Y direction), or may be arranged on both sides of the cell region CELL in the first horizontal direction (X direction).

[0096] 9A to 9C is a schematic cross-sectional view of a nonvolatile memory device according to an embodiment.

[0097] Reference Fig.9A , the nonvolatile memory device 3a may include a cell region CELL, a peripheral connection region PA, and a cell connection region EXT between the cell region CELL and the peripheral connection region PA. Fig.9A The peripheral connection area PA shown in FIG. Fig. 8A The cell region CELL may include a real cell region RCR and a dummy cell region DCR adjacent to the real cell region RCR. The dummy cell region DCR may be between the real cell region RCR and the cell connection region EXT.

[0098] The pad pattern PAD may extend from the peripheral connection area PA to the cell connection area EXT in a first horizontal direction (X direction) so as to extend laterally (i.e., in a horizontal direction) across at least a portion of the peripheral connection area PA and the cell connection area EXT. At least a portion of the pad pattern PAD may be exposed to the outside of the nonvolatile memory device 3a through the pad opening POP. The stacked mold SMLD and the common source line layer CSL disposed on the stacked mold SMLD may be arranged in the cell area CELL and the cell connection area EXT. The stacked mold SMLD and the common source line layer CSL may be arranged in the cell area CELL and the cell connection area EXT, and may not be arranged in the peripheral connection area PA. The stacked mold SMLD may form a stepped structure in the vertical direction (Z direction) in the cell connection area EXT.

[0099] The common source line layer CSL may have at least one common source opening CSLO. A plurality of cell channel structures CHS may be arranged in the real cell region RCR, and a plurality of dummy structures DCS may be arranged in the dummy cell region DCR and the cell connection region EXT. A plurality of cell channel structures CHS may penetrate the stacked mold SMLD and extend in a vertical direction (Z direction) so as to be connected to the common source line layer CSL. The dummy structure DCS arranged in the dummy cell region DCR may penetrate the stacked mold SMLD and extend in a vertical direction (Z direction) so as to be connected to the common source line layer CSL. Some of the dummy structures DCS arranged in the cell connection region EXT may penetrate the stacked mold SMLD and extend in a vertical direction (Z direction) so as to be connected to the common source line layer CSL, and other dummy structures DCS therein may penetrate the stacked mold SMLD and extend into at least one common source opening CSLO. The dummy structure DCS arranged in the cell connection region EXT may overlap with the pad pattern PAD in a vertical direction (Z direction). The dummy structure DCS penetrating the stacked mold SMLD and extending into at least one common source opening CSLO may perform Fig. 6A Function of the support structure SPS shown.

[0100] although Fig.9A The cell region CELL, the cell connection region EXT, and the peripheral connection region PA are shown to be arranged in the first horizontal direction (X direction), but the inventive concept is not limited thereto. For example, the cell region CELL, the cell connection region EXT, and the peripheral connection region PA may be arranged in the second horizontal direction (Y direction).

[0101] In some embodiments, at least a portion of the unit channel structure CHS and at least a portion of the dummy structure DCS may be formed together by the same manufacturing process. For example, the dummy structure DCS may have a structure that is the same as or substantially similar to the unit channel structure CHS. In some embodiments, all dummy structures DCS or dummy structures DCS that perform the function of the support structure SPS may have a structure that is the same as or substantially similar to the unit channel structure CHS. Fig. 6A The support structure SPS shown in Figure 6B The support structure SPSa shown in Figure 6C The support structure SPSb and Fig.6D An identical structure to the one in the support structure SPSc shown in .

[0102] although Fig.9AIt is shown that the dummy structure DCS arranged in the dummy cell region DCR is electrically connected to the upper bonding pad BPD, and the dummy structure DCS arranged in the cell connection region EXT is not electrically connected to the upper bonding pad BPD, but the inventive concept is not limited thereto. In some embodiments, none of the dummy structures DCS arranged in the dummy cell region DCR and the cell connection region EXT may be electrically connected to the upper bonding pad BPD. In some embodiments, the dummy structure DCS performing the function of the support structure SPS may not be electrically connected to the upper bonding pad BPD, and the remaining dummy structures DCS may be electrically connected to the upper bonding pad BPD.

[0103] Reference Fig. 9B , the nonvolatile memory device 3b may include a cell region CELL, a peripheral connection region PA, and a cell connection region EXT between the cell region CELL and the peripheral connection region PA. The cell region CELL may be adjacent to the cell connection region EXT, and the cell connection region EXT may be adjacent to the peripheral connection region PA.

[0104] The pad pattern PAD may extend from the peripheral connection area PA to the dummy cell area DCR in a first horizontal direction (X direction), extending across the cell connection area EXT so as to be located above the peripheral connection area PA, the cell connection area EXT, and the dummy cell area DCR. At least a portion of the pad pattern PAD may be exposed to the outside of the nonvolatile memory device 3b through the pad opening POP.

[0105] The common source line layer CSL may have at least one common source opening CSLO. A plurality of cell channel structures CHS may be arranged in the real cell region RCR, and a plurality of dummy structures DCS may be arranged in the dummy cell region DCR and the cell connection region EXT. The dummy structure DCS arranged in the dummy cell region DCR may be referred to as a cell dummy structure, and the dummy structure DCS arranged in the cell connection region EXT may be referred to as a connection dummy structure. A plurality of cell channel structures CHS may extend through the stack mold SMLD in a vertical direction (Z direction) so as to be connected to the common source line layer CSL. Some of the dummy structures DCS arranged in the dummy cell region DCR and the cell connection region EXT may extend through the stack mold SMLD in a vertical direction (Z direction) so as to be connected to the common source line layer CSL, and other dummy structures DCS therein may extend through the stack mold SMLD in a vertical direction (Z direction) and extend into at least one common source opening CSLO. At least some of the dummy structures DCS may overlap with the pad pattern PAD in a vertical direction (Z direction). The dummy structure DCS penetrating the stacked mold SMLD and extending into at least one common source opening CSLO may perform Fig. 6AFunction of the support structure SPS shown. The stacked mold SMLD can form a step structure in the vertical direction (Z direction) in the cell connection region EXT.

[0106] In some embodiments, the dummy structures DCS arranged in the dummy cell region DCR that do not perform the function of the support structure SPS may be electrically connected to the upper bonding pad BPD, but the inventive concept is not limited thereto. For example, the bit line contact BLC may not be connected to the lower surface of each dummy structure DCS, so that all dummy structures DCS are not electrically connected to the upper bonding pad BPD.

[0107] In some embodiments, at least a portion of the unit channel structure CHS and at least a portion of the dummy structure DCS may be formed together by the same manufacturing process. For example, the dummy structure DCS may have a structure that is the same as or substantially similar to the unit channel structure CHS. In some embodiments, all dummy structures DCS or dummy structures DCS that perform the function of the support structure SPS may have a structure that is the same as or substantially similar to the unit channel structure CHS. Fig. 6A The support structure SPS shown in Figure 6B The support structure SPSa shown in Figure 6C The support structure SPSb and Fig.6D An identical structure to the one in the support structure SPSc shown in .

[0108] Reference Fig. 9C The nonvolatile memory device 3c may include a cell region CELL, a peripheral connection region PA, and a cell connection region EXT between the cell region CELL and the peripheral connection region PA. The cell region CELL may be laterally adjacent to the cell connection region EXT, and the cell connection region EXT may be laterally adjacent to the peripheral connection region PA.

[0109] The pad pattern PAD may extend from the peripheral connection region PA to the real cell region RCR through the cell connection region EXT and the dummy cell region DCR along the first horizontal direction (X direction) so as to extend across at least a portion of the peripheral connection region PA, the cell connection region EXT, the dummy cell region DCR, and the real cell region RCR. At least a portion of the pad pattern PAD may be exposed to the outside of the nonvolatile memory device 3c through the pad opening POP.

[0110] The common source line layer CSL may have a common source opening CSLO.A plurality of cell channel structures CHS may be arranged in the real cell region RCR, and a plurality of dummy structures DCS may be arranged in the dummy cell region DCR and the cell connection region EXT.

[0111] Some dummy structures DCS and some cell channel structures CHS arranged in the dummy cell region DCR and the cell connection region EXT may penetrate the stack mold SMLD and extend in the vertical direction (Z direction) so as to be connected to the common source line layer CSL, and other cell channel structures CHS and other dummy structures DCS arranged in the dummy cell region DCR and the cell connection region EXT may penetrate the stack mold SMLD and extend into at least one common source opening CSLO. Some cell channel structures CHS and at least some dummy structures DCS may overlap with the pad pattern PAD in the vertical direction (Z direction). The cell channel structures CHS and dummy structures DCS that pass through the stack mold SMLD and extend into at least one common source opening CSLO may perform Fig. 6A Function of the support structure SPS shown. The stacked mold SMLD can form a step structure in the vertical direction (Z direction) in the cell connection region EXT.

[0112] In some embodiments, the cell channel structure CHS and the dummy structure DCS performing the function of the support structure SPS may not be electrically connected to the upper bonding pad BPD. For example, the bit line contact BLC may not be connected to the lower surface of each of the cell channel structure CHS and the dummy structure DCS performing the function of the support structure SPS.

[0113] Fig. 10A and 10B is a schematic cross-sectional view of an example nonvolatile memory device according to an embodiment. Specifically, Fig. 10B yes Fig. 10A An enlarged cross-sectional view of region XB.

[0114] Reference Fig. 10A , the nonvolatile memory device 100 may include a peripheral circuit structure PS and a cell array structure CS on the peripheral circuit structure PS in a vertical direction (Z direction) (eg, bonded to each other). The peripheral circuit structure PS and the cell array structure CS may also be referred to as a first structure and a second structure, or as a lower structure and an upper structure. The peripheral circuit structure PS may include a reference Figure 1 The peripheral circuit 30 described above, the cell array structure CS may include reference Figure 1 The memory cell array 20 described. The cell array structure CS may include memory cells arranged in three dimensions. The cell array structure CS may include a cell region CELL and a peripheral connection region PA laterally adjacent to the cell region CELL. The cell region CELL may include a real cell region RCR and a dummy cell region DCR. Components for electrically connecting the cell region CELL to the peripheral circuit structure PS, including components for electrically connecting the common source line layer 210 to the peripheral circuit structure PS, may be arranged in the peripheral connection region PA.

[0115] The peripheral circuit structure PS may include a substrate 110 on which a peripheral circuit 120 is disposed, a lower interconnect structure 130 electrically connected to the peripheral circuit 120, a lower bonding pad 150 electrically connected to the peripheral circuit 120 through the lower interconnect structure 130, and a lower insulating structure 140 on the substrate 110 and the peripheral circuit 120.

[0116] The substrate 110 may include, for example, a semiconductor material such as a group IV semiconductor material, a group III-V semiconductor material, a group II-VI semiconductor material, or a group II-VI oxide semiconductor material. The group IV semiconductor material may include, for example, silicon (Si), germanium (Ge), or silicon-germanium (Si-Ge). The group III-V semiconductor material may include, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimony (InSb), or indium gallium arsenide (InGaAs). The group II-VI semiconductor material may include, for example, zinc telluride (ZnTe) or cadmium sulfide (CdS). The substrate 110 may be provided as a bulk wafer or an epitaxial layer. In another embodiment, the substrate 110 may include a silicon on insulator (SOI) substrate or a germanium on insulator (GeOI) substrate. The active region AC may be defined in the substrate 110 by a device isolation layer 112, and a plurality of peripheral circuits 120 may be formed on the active region AC. The peripheral circuit 120 may include a peripheral circuit gate 122 and source / drain regions 124 arranged in portions of the substrate 110 on both sides of the peripheral circuit gate 122 in the second horizontal direction (Y direction).

[0117] The lower interconnect structure 130 may include a plurality of peripheral circuit wiring layers 132 and a plurality of peripheral circuit contacts 134. The lower interconnect structure 130 may include a conductive material such as copper (Cu), aluminum (Al), tungsten (W), silver (Ag), gold (Au), or any combination thereof. A lower bonding pad 150 may be disposed on the lower interconnect structure 130 and electrically connected to the peripheral circuit 120 and / or the substrate 110 through the lower interconnect structure 130. The lower insulating structure 140 may surround the peripheral circuit 120, the lower interconnect structure 130, and the lower bonding pad 150 on the substrate 110. The lower bonding pad 150 may have an upper surface disposed on the same plane as the upper surface of the lower insulating structure 140 (i.e., coplanar with the upper surface of the lower insulating structure 140).

[0118] In some embodiments, the lower insulating structure 140 may include an insulating material including silicon oxide, silicon nitride, a low-k material, or any combination thereof. The low-k material is a material having a lower dielectric constant than silicon oxide, and may include, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), organic silicate glass (OSG), spin-on glass (SOG), spin-on polymer, or any combination thereof, but the embodiment is not limited thereto. In some embodiments, the lower insulating structure 140 may include an ultra-low k (ULK) layer having an ultra-low dielectric constant K of about 2.2 to about 2.4. The ULK layer may include, for example, SiOC or SiCOH. The lower bonding pad 150 may include a conductive material including copper (Cu), gold (Au), silver (Ag), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), or any combination thereof, but the embodiment is not limited thereto.

[0119] The cell array structure CS may include a common source line layer 210, a cell stack 220 disposed below the common source line layer 210, an upper interconnect structure 240 electrically connected to the cell stack 220, an upper bonding pad 260 electrically connected to the upper interconnect structure 240, and an upper insulating structure 250 covering the cell stack 220 below the cell stack 220 and surrounding the bit line contact BLC, the bit line BL, the upper interconnect structure 240, and the upper bonding pad 260. The upper bonding pad 260 may have a lower surface disposed on the same plane as a lower surface of the upper insulating structure 250.

[0120] The nonvolatile memory device 100 may further include a base insulating layer 202 covering the common source line layer 210 on the cell stack 220, a pad pattern 330 disposed on the base insulating layer 202, and a protective insulating layer 350 covering a portion of the pad pattern 330 on the base insulating layer 202. The protective insulating layer 350 may have a pad opening 350O that exposes the upper surface of the remaining portion of the pad pattern 330 without covering the upper surface of the remaining portion of the pad pattern 330. The base insulating layer 202 may include the same insulating material. The pad pattern 330 may extend from the peripheral connection area PA to the dummy cell area DCR so as to be positioned across the peripheral connection area PA and the dummy cell area DCR.

[0121] The common source line layer 210 may be FIG. 5A to FIG. 7B and 9A to 9C The common source line layer CSL shown in FIG. The cell stack 220, the upper interconnect structure 240, and the upper bonding pad 260 may be respectively FIG. 6A to FIG. 7B and 9A to 9C The stacked mold SMLD, the upper interconnect structure ITCS and the upper bonding pad BPD shown in FIG.

[0122] although Fig. 10A It is shown that the upper interconnect structure 240 includes only a plurality of contacts, but this is only an example and the inventive concept is not limited thereto. For example, similar to the lower interconnect structure 130 including the peripheral circuit wiring layer 132 and the peripheral circuit contact 134, the upper interconnect structure 240 may include a plurality of wiring layers and a plurality of contacts. The upper interconnect structure 240 and the upper insulating structure 250 may include the same or similar materials as the lower interconnect structure 130 and the lower insulating structure 140, respectively.

[0123] The upper insulating structure 250 may contact the lower insulating structure 140, and the upper bonding pad 260 may contact the corresponding lower bonding pad 150, and then, bonding may be performed so that the cell array structure CS is bonded to the peripheral circuit structure PS. For example, the peripheral circuit structure PS may also be bonded to the cell array structure CS by a metal oxide hybrid bonding method. Therefore, the upper interconnect structure 240 included in the cell array structure CS may be electrically connected to the peripheral circuit 120 included in the peripheral circuit structure PS.

[0124] The cell stack 220 may include a plurality of gate electrodes 222 and a plurality of insulating layers 224, which are alternately stacked in a vertical direction (Z direction) below the common source line layer 210. The gate electrode 222 may include tungsten (W), copper (Cu), silver (Ag), gold (Au), aluminum (Al), or any combination thereof, but may include a conductive material not limited thereto. The insulating layers 224 may each include an insulating material, which may include silicon oxide, a low-k material, or any combination thereof, but the embodiment is not limited thereto.

[0125] The buffer insulating layer 212 may be between the common source line layer 210 and the cell stack 220. For example, the buffer insulating layer 212 may be between the common source line layer 210 and the gate electrode 222 at the top of the cell stack 220. The buffer insulating layer 212 may include an insulating material such as an oxide. The buffer insulating layer 212 may have a thickness of tens to hundreds of nanometers (nm) in the vertical direction (Z direction). The thickness of the gate electrode 222 in the vertical direction may also be greater than or equal to the thickness of the insulating layer 224. For example, the gate electrode 222 may have a thickness of about 10 nm to about 20 nm, and the insulating layer 224 may have a thickness of about 10 nm to about 15 nm.

[0126] A plurality of cell channel structures 230 vertically extending through the cell stack 220 including the gate electrode 222 and the insulating layer 224 may be provided in the actual cell region RCR. A memory cell string including a plurality of memory cells may be provided along each of the cell channel structures 230 (see Figure 3Each cell channel structure 230 may extend through the cell stack 220 and the buffer insulating layer 212 in the vertical direction (Z direction) into the common source line layer 210. For example, a portion of the upper side of each cell channel structure 230 may protrude (i.e., extend) from the upper surface of the buffer insulating layer 212 in the vertical direction (Z direction) and may be arranged in the common source line layer 210. The cell channel structure 230 may be FIG. 6A to FIG. 7B and 9A to 9C The unit channel structure CHS is shown.

[0127] In some embodiments, the nonvolatile memory device 100 may further include a word line cut region WLC extending vertically in the cell stack 220. The word line cut region WLC may penetrate the cell stack 220 and extend vertically into the common source line layer 210. The word line cut region WLC may be separated from the cell channel structure 230. In some embodiments, the word line cut region WLC may extend between the cell channel structures 230 adjacent to each other in the second horizontal direction (Y direction) in the first horizontal direction (X direction). The word line cut region WLC may include an oxide layer, a nitride layer, or any combination thereof.

[0128] The common source line layer 210 may be used as a source region configured to supply current to memory cells formed in the cell array structure CS. The common source line layer 210 may correspond to Figure 3 The common source line CSL shown. The common source line layer 210 may include a semiconductor material, such as a group IV semiconductor material, a group III-V semiconductor material, or a group II-VI semiconductor material. For example, the common source line layer 210 may include at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or any mixture thereof, but the embodiment is not limited thereto. In addition, the common source line layer 210 may include a semiconductor doped with n-type impurities. In addition, the common source line layer 210 may have a crystal structure including at least one structural type selected from single crystal, amorphous, and polycrystalline structures. In some embodiments, the common source line layer 210 may include a carbon-free semiconductor material. For example, the common source line layer 210 may include polycrystalline silicon. In some embodiments, the common source line layer 210 may include carbon-free polycrystalline silicon. In some examples, the common source line layer 210 may include polycrystalline silicon doped with n-type impurities.

[0129] The common source line layer 210 may be disposed such that the cell channel structure 230 penetrates the gate electrode 222 and the insulating layer 224 and contacts the common source line layer 210. The common source line layer 210 may extend along the lower surface of the base insulating layer 202 and may surround a portion of the upper side of each cell channel structure 230.

[0130] In some embodiments, the gate electrode 222 may correspond to a Figure 3 At least one ground selection line GSL, word lines WL (WL1, WL2, ..., WLn-1, WLn) and at least one string selection line SSL of the memory cell string MS described in the embodiment. For example, the gate electrode 222 (e.g., the uppermost gate electrode 222) arranged closest to the common source line layer 210 in the vertical direction can be used as the ground selection line GSL, at least two gate electrodes 222 (e.g., the two lowermost gate electrodes 222) arranged farthest from the common source line layer 210 in the vertical direction can be used as the string selection line SSL, and the remaining gate electrodes 222 can be used as the word lines WL. Therefore, a memory cell string MS can be provided, wherein Figure 3 The ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MC1, MC2, ..., MCn-1, and MCn therebetween are connected in series.

[0131] In some embodiments, at least one of the gate electrodes 222 may be used as a dummy word line. For example, at least one gate electrode 222 used as an additional dummy word line may be between the gate electrode 222 used as the ground selection line GSL and the common source line layer 210, at least one gate electrode 222 used as an additional dummy word line may be between the gate electrode 222 used as the ground selection line GSL and the gate electrode 222 used as the word line WL, and at least one gate electrode 222 used as an additional dummy word line may be between the gate electrode 222 used as the word line WL and the gate electrode 222 used as the string selection line SSL.

[0132] The unit channel structures 230 may be spaced apart from each other at intervals in a first horizontal direction (X direction), a second horizontal direction (Y direction), and a third horizontal direction (e.g., an oblique direction relative to the first horizontal direction (X direction) and the second horizontal direction (Y direction)). The unit channel structures 230 may be arranged in a zigzag shape or a staggered shape. The unit channel structures 230 may each include a conductive plug 238. The conductive plug 238 may be arranged at one end of each unit channel structure 230 opposite to the common source line layer 210.

[0133] The cell channel structure 230 may be arranged in a plurality of channel holes CHH in the real cell region RCR. The channel holes CHH may extend vertically (ie, in the Z direction) through the buffer insulating layer 212 and the cell stack 220 including the gate electrode 222 and the insulating layer 224, and partially extend into the common source line layer 210. The channel holes CHH may be defined by the gate electrode 222 and the insulating layer 224 within the cell stack 220, and may be defined by the common source line layer 210.

[0134] Each of the unit channel structures 230 may include a gate insulating layer 232, a channel layer 234, a buried insulating layer 236, and a conductive plug 238. Fig. 10A and Fig. 10B As shown. The gate insulating layer 232 and the channel layer 234 may be sequentially disposed on the inner wall of the channel hole CHH. For example, the gate insulating layer 232 may conformally cover the inner wall (side wall) of the cell stack 220 including the insulating layer 224 and the channel hole CHH penetrating the buffer insulating layer 212, and the channel layer 234 may conformally cover the inner wall and the top (i.e., upper) surface of the channel hole CHH. The channel layer 234 may cover the inner wall and the top surface of the channel hole CHH extending into the common source line layer 210 so as to contact the common source line layer 210. The gate insulating layer 232 may not extend into the common source line layer 210. For example, the top surface of the gate insulating layer 232 may contact the lower surface of the common source line layer 210, so that the top surface of the gate insulating layer 232 may be coplanar with the lower surface of the common source line 210 relative to the upper surface of the substrate 110 as a reference layer. The channel layer 234 may extend into the common source line layer 210 along the inner wall of the channel hole CHH extending into the common source line layer 210. For example, the top of the channel layer 234 may be located at a vertical level higher than the lower surface of the common source line layer 210 relative to the upper surface of the substrate 110. The lower surface of the common source line layer 210 refers to the lowermost surface of the common source line layer 210, excluding the inner wall and the top surface of the channel hole CHH extending into the common source line layer 210.

[0135] A buried insulating layer 236 filling the remaining space of the channel hole CHH may be disposed on the channel layer 234. A conductive plug 238 contacting the channel layer 234 and blocking the entrance of the channel hole CHH may be disposed on the lower side of the channel hole CHH. In some embodiments, the buried insulating layer 236 may be omitted, and the channel layer 234 may be formed in a pillar shape to fill the remaining portion of the channel hole CHH.

[0136] The gate electrode 222 may include a metal (such as tungsten, nickel, cobalt, and tantalum), a conductive metal nitride (such as titanium nitride, tantalum nitride, and tungsten nitride), a metal silicide (such as tungsten silicide, nickel silicide, cobalt silicide, and tantalum silicide), doped polysilicon, or any combination thereof, but the embodiment is not limited thereto. In some embodiments, a dielectric liner may be between the gate electrode 222 and the insulating layer 224. The dielectric liner may include a high dielectric constant (high-k) material, such as aluminum oxide.

[0137] The gate insulating layer 232 may have a structure including a tunneling dielectric layer 232A, a charge storage layer 232B, and a blocking dielectric layer 232C, which are sequentially disposed in the stated order on the outer wall of the channel layer 234. The relative thicknesses of the tunneling dielectric layer 232A, the charge storage layer 232B, and the blocking dielectric layer 232C constituting the gate insulating layer 232 are not limited to Fig. 10B The thickness is shown and various modifications may be made.

[0138] The tunneling dielectric layer 232A may include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, etc., but the embodiment is not limited thereto. The charge storage layer 232B is a region where electrons passing through the tunneling dielectric film 232A from the channel layer 234 can be stored, and may include silicon nitride, boron nitride, silicon boron nitride, or polysilicon doped with impurities. The blocking dielectric layer 232C may include, for example, silicon oxide, silicon nitride, or a metal oxide having a dielectric constant higher than that of silicon oxide. The metal oxide may include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or any combination thereof, but the embodiment is not limited thereto.

[0139] The bit lines BL may extend apart from each other in a first horizontal direction (X direction), but the inventive concept is not limited thereto. For example, the bit lines BL may extend apart from each other in a second horizontal direction (Y direction). The bit lines BL may be electrically connected to the cell channel structure 230 through the bit line contacts BLC. The bit line contacts BLC may be connected to the conductive plug 238.

[0140] A plurality of dummy structures 230D may be arranged within the channel hole CHH in the dummy cell region DCR. The dummy structure 230D may be formed to prevent tilting or bending of the gate electrode 222 and to ensure structural stability during the process of manufacturing the nonvolatile memory device 100. In some embodiments, the dummy structure 230D may have a structure and shape substantially the same as or similar to the cell channel structure 230. When the dummy structure 230D has a structure and shape substantially the same as or similar to the cell channel structure 230, the cell channel structure 230 may be referred to as a real cell channel structure, and the dummy structure 230D may be referred to as a dummy cell channel structure. For example, the dummy structure 230D may include a gate insulating layer 232, a channel layer 234, and a buried insulating layer 236, but may not include a conductive plug 238. In other embodiments, the cell channel structure 230 and the dummy structure 230D may have different structures and shapes. The dummy structure 230D may be FIG. 6A to FIG. 7B and 9A to 9C The fictitious structure DCS is shown.

[0141] The filling insulating layer 228 filling the portion corresponding to the cell stack 220 may be arranged in the peripheral connection area PA. The upper insulating structure 250 may cover the cell stack 220 and the filling insulating layer 228. In some embodiments, the upper insulating structure 250 may include a plurality of insulating layers. Each of the insulating layers may be arranged to cover the bit line contact BLC, the bit line BL, and the upper interconnect structure 240. A through contact plug IOMC that penetrates the filling insulating layer 228 and is electrically connected to the peripheral circuit 120 through the upper interconnect structure 240 and the lower interconnect structure 130 may be arranged in the peripheral connection area PA. The through contact plug IOMC may extend into the base insulating layer 202.

[0142] In some embodiments, the cell channel structure 230, the dummy structure 230D, and the through contact plug IOMC may each have a tapered shape in which a horizontal width thereof increases while extending downward in a vertical direction (Z direction) from the common source line layer 210 and the base insulating layer 202 toward the peripheral circuit structure PS.

[0143] The common source line layer 210 may have a common source opening 210O. The common source opening 210O may be FIG. 5A to FIG. 7B and 9A to 9C . In some embodiments, the common source opening 210O may not be located in the peripheral connection area PA, and may be located only in the cell area CELL. The pad pattern 330 may extend from the peripheral connection area PA to the common source opening 210O in the second horizontal direction (Y direction). In some embodiments, the common source opening 210O may be located in the dummy cell region DCR, and may not be located in the real cell region RCR. The basic insulating layer 202 may at least partially fill the common source opening 210O.

[0144] Some dummy structures 230D may penetrate the cell stack 220 and extend in the vertical direction (Z direction) to be connected to the common source line layer 210, and other dummy structures 230D may penetrate the cell stack 220 and extend into the base insulating layer 202 filling the common source opening 210O. At least some of the dummy structures 230D may overlap the pad pattern 330 in the vertical direction (Z direction). Other dummy structures 230D that penetrate the cell stack 220 and extend into the common source opening 210O may perform the function of the support structure SPS.

[0145] The pad connection path 325 may be located between the pad pattern 330 and the through contact plug IOMC in the vertical direction (Z direction). The upper surface and the lower surface of the pad connection path 325 may contact the lower surface of the pad pattern 330 and the upper surface of the through contact plug IOMC, respectively. The pad support path 328 may be between the pad pattern PAD and the dummy structure 230D that performs the function of the support structure SPS in the vertical direction. The upper surface and the lower surface of the pad support path 328 may contact the lower surface of the pad pattern 330 and the upper surface of the dummy structure 230D that performs the function of the support structure SPS, respectively. The pad connection path 325 and the pad support path 328 may penetrate the base insulating layer 202. The pad connection path 325 and the pad support path 328 may be FIG. 6A to FIG. 7B and 9A to 9C The pad connection via PCOT and the pad support via SCOT shown in FIG.

[0146] The cell channel structure 230 and the through contact plug IOMC may be electrically connected to the upper bonding pad 260. The cell channel structure 230 and the through contact plug IOMC may be electrically connected to the peripheral circuit 120 included in the peripheral circuit structure PS through the upper bonding pad 260. The cell channel structure 230 and the through contact plug IOMC may be electrically connected to the bit line BL. The cell channel structure 230 and the through contact plug IOMC may be electrically connected to the bit line BL through the bit line contact BLC. The bit line BL may be electrically connected to the upper bonding pad 260 through the upper interconnect structure 240. For example, the bit line contact BLC, the bit line BL, and the upper interconnect structure 240 may be sequentially arranged between each of the cell channel structure 230 and the through contact plug IOMC and the upper bonding pad 260.

[0147] The dummy structure 230D performing the function of the support structure SPS may not be electrically connected to the upper bonding pad BPD. The dummy structure 230D performing the function of the support structure SPS may not be electrically connected to the bit line BL. For example, the bit line contact BLC may be connected to the lower surface of each of the cell channel structure 230 and the through contact contact IOMC, but the bit line contact BLC may not be connected to the lower surface of the dummy structure 230D performing the function of the support structure SPS. In some embodiments, the upper insulating structure 250 may cover the lower surface of the dummy structure 230D performing the function of the support structure SPS.

[0148] Fig.11 is a cross-sectional view of a nonvolatile memory device according to an embodiment.

[0149] Reference Fig.11, the nonvolatile memory device 100a may include a peripheral circuit structure PS and a cell array structure CS on the peripheral circuit structure PS in a vertical direction (Z direction) (e.g., bonded to each other). The cell array structure CS may include a cell region CELL and a peripheral connection region PA laterally adjacent to the cell region CELL. The cell region CELL may include a real cell region RCR and a dummy cell region DCR laterally adjacent to the real cell region RCR.

[0150] The pad pattern 330 may extend from the peripheral connection region PA to the real cell region RCR in the second horizontal direction (Y direction) through the dummy cell region DCR so as to extend across (ie, extend over) the peripheral connection region PA, the dummy cell region DCR, and the real cell region RCR.

[0151] The common source line layer 210 may have one or more common source openings 210O. The common source opening 210O may not be located in the peripheral connection area PA, and may be located only in the cell area CELL. In some embodiments, the common source opening 210O may be located in the real cell area RCR and the dummy cell area DCR. The basic insulating layer 202 may at least partially fill the common source opening 210O.

[0152] Some of the cell channel structures 230 may penetrate the cell stack 220 and extend in the vertical direction (Z direction) to be connected to the common source line layer 210, and other cell channel structures 230 may penetrate the cell stack 220 and extend into the base insulating layer 202 filling the common source opening 210O. Some of the dummy structures 230D may penetrate the cell stack 220 and extend in the vertical direction (Z direction) to be connected to the common source line layer 210, and other dummy structures 230D may penetrate the cell stack 220 and extend into the common source opening 210O.

[0153] Some of the cell channel structures 230 and at least some of the dummy structures 230D may overlap with the pad pattern 330 in the vertical direction (Z direction). Other cell channel structures 230 and other dummy structures 230D (each of which extends vertically through the cell stack 220 and extends into the common source opening 210O) may be connected to the pad support path 328 and perform the function of the support structure SPS. The cell channel structure 230 and the dummy structure 230D that perform the function of the support structure SPS may not be electrically connected to the upper bonding pad BPD. The bit line contact BLC may not be connected to the lower surface of the cell channel structure 230 and the lower surface of the dummy structure 230D (which performs the function of the support structure SPS). In some embodiments, the upper insulating structure 250 may cover the lower surface of the cell channel structure 230 and the lower surface of the dummy structure 230D (which performs the function of the support structure SPS).

[0154] FIG. 12A to FIG. 12C is a schematic cross-sectional view of an example nonvolatile memory device according to an embodiment.

[0155] Reference Fig. 12A , the nonvolatile memory device 200 may include a peripheral circuit structure PS and a cell array structure CS on the peripheral circuit structure PS in a vertical direction (Z direction) (e.g., bonded to each other). The cell array structure CS may include a cell region CELL, a cell connection region EXT laterally adjacent to the cell region CELL, and a peripheral connection region PA laterally adjacent to the cell connection region EXT. The cell region CELL may include a real cell region RCR and a dummy cell region DCR. The dummy cell region DCR may be between the real cell region RCR and the cell connection region EXT.

[0156] The pad pattern 330 may extend from the peripheral connection area PA to the cell connection area EXT in the first horizontal direction (X direction) so as to extend laterally across the peripheral connection area PA and the cell connection area EXT. At least a portion of the pad pattern 330 may be exposed to the outside of the nonvolatile memory device 200 through a pad opening 350O provided in the protective insulating layer 350 on the upper surface of the memory device 200. The cell stack 220 and the common source line layer 210 disposed on the cell stack 220 may be arranged in the cell area CELL and in at least a portion of the cell connection area EXT. The cell stack 220 and the common source line layer 210 may be arranged in the cell area CELL and the cell connection area EXT, but may not be arranged in the peripheral connection area PA.

[0157] The cell stack 220 may form a staircase structure in the vertical direction in the cell connection region EXT. A plurality of gate electrodes 222 may be stacked on the cell region CELL to be separated from each other in the vertical direction (Z direction), and may extend from the cell region CELL to the cell connection region EXT at different lengths in the first horizontal direction (X direction) to form a staircase structure. The gate electrodes 222 may be arranged in the first horizontal direction (X direction) to have a staircase structure between adjacent gate electrodes 222 in the vertical direction (Z direction), but the inventive concept is not limited thereto. For example, the gate electrodes 222 may be arranged to have a staircase structure in the second horizontal direction (Y direction), or may be arranged to have a staircase structure in each of the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0158] Due to the stepped structure, each gate electrode 222 may have a portion extending longer in the first horizontal direction (X direction) than other gate electrodes 222 adjacent in the vertical direction (Z direction), and each portion may be referred to as a gate pad portion. In some embodiments, in each gate electrode 222, the gate pad portion may include an end portion in the first horizontal direction (X direction).

[0159] The common source line layer CSL may have at least one common source opening CSLO. A plurality of cell channel structures 230 may be arranged in the real cell region RCR, and a plurality of dummy structures may be arranged in the dummy cell region DCR and the cell connection region EXT. In order to distinguish between the dummy structure arranged in the dummy cell region DCR and the dummy structure arranged in the cell connection region EXT, the dummy structure arranged in the dummy cell region DCR may be referred to as a cell dummy structure 230D, and the dummy structure arranged in the cell connection region EXT may be referred to as a connection dummy structure 270D.

[0160] The connection dummy structure 270D may be arranged in a plurality of dummy channel holes DCH penetrating the gate electrode 222, a plurality of insulating layers 224 disposed between adjacent gate electrodes 222, and the buffer insulating layer 212, and extend in the vertical direction (Z direction). The connection dummy structure 270D may be arranged around a plurality of gate contact plugs 270. Each of the gate contact plugs 270 may extend through the gate electrode 222 in the vertical direction (Z direction) in the cell connection region EXT, and may be electrically connected to a gate pad portion of a corresponding one of the gate electrodes 222. An insulating spacer 280S may be between the gate electrode 222 and the gate contact plug 270 that are not electrically connected among the gate electrode 222 and the gate contact plug 270. Each of the gate contact plugs 270 may be electrically connected to the upper bonding pad 260.

[0161] A filling insulating layer 228 covering a portion of the gate electrode 222 constituting a gate pad portion and surrounding the gate contact plug 270 may be disposed in the cell connection region EXT. The filling insulating layer 228 may also be disposed in the peripheral connection region PA. An upper insulating structure 250 may cover the cell stack 220 and the filling insulating layer 228.

[0162] Some of the connection dummy structures 270D arranged in the cell connection region EXT may penetrate the cell stack 220 and extend in the vertical direction (Z direction) so as to be connected to the common source line layer 210, and other connection dummy structures therein may penetrate the cell stack 220 and extend into at least one common source opening 210O. At least some of the connection dummy structures 270D may overlap the pad pattern 330 in the vertical direction (Z direction). The connection dummy structures 270D that penetrate the cell stack 220 and extend into at least one common source opening 210O may be connected to the pad support via 328 and perform Fig.9A The connection dummy structure 270D performing the function of the support structure SPS may not be electrically connected to the upper bonding pad BPD. In some embodiments, the upper insulating structure 250 may cover the lower surface of each connection dummy structure 270D performing the function of the support structure SPS.

[0163] although Fig. 12A The cell channel structure 230 and the cell dummy structure 230D are shown to have the same or substantially similar structure, and the gate contact plug 270 and the connection dummy structure 270D have the same or substantially similar structure, but this is only an example and the inventive concept is not limited thereto. For example, each of the cell dummy structure 230D and the connection dummy structure 270D may have the same or substantially similar structure. Fig. 6A The support structure SPS shown, Figure 6B The support structure SPSa shown, Figure 6C The support structure SPSb and Fig.6D An identical structure is shown in the support structure SPSc.

[0164] Reference Fig. 12B The nonvolatile memory device 200a may include a cell region CELL, a peripheral connection region PA, and a cell connection region EXT between the cell region CELL and the peripheral connection region PA in a first horizontal direction (X direction). The pad pattern 330 may extend from the peripheral connection region PA to the dummy cell region DCR through the cell connection region EXT so as to be positioned across the peripheral connection region PA, the cell connection region EXT, and the dummy cell region DCR.

[0165] The common source line layer CSL may have a common source opening CSLO. A plurality of cell channel structures CHS may be arranged in the real cell region RCR, a plurality of cell dummy structures 230D may be arranged in the dummy cell region DCR, and a plurality of connection dummy structures 270D may be arranged in the cell connection region EXT.

[0166] Some of the cell dummy structures 230D and some of the connection dummy structures 270D may penetrate the cell stack 220 and extend in the vertical direction (Z direction) so as to be connected to the common source line layer 210, and other cell dummy structures 230D and other connection dummy structures 270D may penetrate the cell stack 220 and extend into at least one common source opening 210O. At least some of the cell dummy structures 230D and at least some of the connection dummy structures 270D may overlap the pad pattern 330 in the vertical direction (Z direction). Other cell dummy structures 230D and other connection dummy structures 270D, each of which penetrates the cell stack 220 and extends into the common source opening 210O, may be connected to the pad support via 328 and perform Fig. 9B The function of the support structure SPS shown. The other unit dummy structures 230D and other connection dummy structures 270D that perform the function of the support structure SPS may not be electrically connected to the upper bonding pad 260. In some embodiments, the upper insulating structure 250 may cover the lower surfaces of the other unit dummy structures 230D and other connection dummy structures 270D that perform the function of the support structure SPS.

[0167] Reference Fig. 12C , the nonvolatile memory device 200b may include a cell region CELL, a peripheral connection region PA, and a cell connection region EXT between the cell region CELL and the peripheral connection region PA in a first horizontal direction (X direction). The pad pattern 330 may extend from the peripheral connection region PA to the real cell region RCR through the cell connection region EXT and the dummy cell region DCR so as to be positioned across the peripheral connection region PA, the cell connection region EXT, the dummy cell region DCR, and the real cell region RCR. At least a portion of the pad pattern 330 may be exposed to the outside of the nonvolatile memory device 200b through the pad opening 350O.

[0168] The common source line layer 210 may have a common source opening 2100. A plurality of cell channel structures 230 may be arranged in the real cell region RCR, a plurality of cell dummy structures 230D may be arranged in the dummy cell region DCR, and a plurality of connection dummy structures 270D may be arranged in the cell connection region EXT.

[0169] Some of the cell channel structures 230, some of the cell dummy structures 230D, and some of the connection dummy structures 270D may extend through the cell stack 220 and extend in the vertical direction (Z direction) so as to be connected to the common source line layer 210, and other of the cell channel structures 230, other of the cell dummy structures 230D, and other of the connection dummy structures 270D may penetrate the cell stack 220 and extend into at least the common source opening 210O. At least some of the cell channel structures 230, at least some of the cell dummy structures 230D, and at least some of the connection dummy structures 270D may overlap with the pad pattern 330 in the vertical direction (Z direction). Other of the cell channel structures 230, other of the cell dummy structures 230D, and other of the connection dummy structures 270D, each of which penetrates the cell stack 220 and extends into the common source opening 210O, may be connected to the pad support via 328 and perform Fig. 9C The other cell channel structures 230, other cell dummy structures 230D, and other connection dummy structures 270D that perform the function of the support structure SPS may not be electrically connected to the upper bonding pad 260. In some embodiments, the upper insulating structure 250 may cover the lower surfaces of the other cell channel structures 230, other cell dummy structures 230D, and other connection dummy structures 270D that perform the function of the support structure SPS.

[0170] Fig.13 is a diagram schematically illustrating a memory system including a nonvolatile memory device according to one or more embodiments.

[0171] refer to Fig.13 , the memory system 1000 may include at least one memory device 1100 and a memory controller 1200 electrically connected to the at least one memory device 1100. The memory system 1000 may be, for example, a solid state drive (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device, which includes at least one memory device 1100, but the embodiment is not limited thereto.

[0172] The memory device 1100 may be a nonvolatile memory device. For example, the memory device 1100 may be a NAND flash memory device, which includes any one of the nonvolatile memory devices 1, 1-1, 1-2, 1-3, 1a, 1b, 1c, 1d, 2a, 2b, 3, 3a, 3b, 3c, 100, 100a, 200, 200a, 200b described with reference to FIGS. 4 to 12C, or any combination thereof. At least one memory device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. The first structure 1100F may correspond to Fig. 10A , Fig.11 , Fig. 12A , Fig. 12B and Fig. 12C The peripheral circuit structure PS is shown. Fig. 10A , Fig.11 , Fig. 12A , Fig. 12B and Fig. 12C The peripheral circuit 120 shown may include a row decoder 1110 , a page buffer 1120 , and a logic circuit 1130 .

[0173] The second structure 1100S may correspond to FIG. 6A to FIG. 7B The nonvolatile memory devices 1a, 1b, 1c, 1d, 2a and 2b shown in FIG. 9A to 9C The nonvolatile memory devices 3a, 3b and 3c shown and Fig. 10A , Fig.11 , Fig. 12A , Fig. 12B and Fig. 12C Any one of the cell array structures CS shown. The second structure 1100S may include one or more bit lines BL, a common source line CSL, a plurality of word lines WL, a first string selection line UL1 and a second string selection line UL2, a first ground selection line LL1 and a second ground selection line LL2, and a plurality of memory cell strings CSTR located between the bit lines BL and the common source line CSL. Fig. 10A , Fig.11 , Fig. 12A , Fig. 12B and Fig. 12C The cell channel structure 230 and the gate electrode 222 shown in FIG. 2 may form a memory cell string CSTR.

[0174] In the second structure 1100S, the memory cell strings CSTR may each include ground selection transistors LT1 and LT2 adjacent to the common source line CSL, string selection transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT between the ground selection transistors LT1 and LT2 and the string selection transistors UT1 and UT2. The number of the ground selection transistors LT1 and LT2 and the number of the string selection transistors UT1 and UT2 may be variously changed according to the embodiment. Fig. 10A , Fig.11 , Fig. 12A , Fig. 12B and Fig. 12C One of the illustrated cell channel structures 230 and one of the gate electrodes 222 may form one of the transistors LT1 , LT2 , UT1 , UT2 , and MCT.

[0175] In some embodiments, ground selection lines LL1 and LL2 may be electrically connected to gate electrodes of ground selection transistors LT1 and LT2, respectively. Word line WL may be electrically connected to gate electrodes of memory cell transistors MCT. String selection lines UL1 and UL2 may be electrically connected to gate electrodes of string selection transistors UT1 and UT2, respectively.

[0176] The common source line CSL, the ground selection lines LL1 and LL2, the word lines WL, and the string selection lines UL1 and UL2 may be electrically connected to the row decoder 1110. The bit lines BL may be electrically connected to the page buffer 1120.

[0177] The memory device 1100 may communicate with the memory controller 1200 through at least one external connection pad 1101 electrically connected to the logic circuit 1130. The external connection pad 1101 may be electrically connected to the logic circuit 1130. The external connection pad 1101 may correspond to Figure 4A , FIG. 5A to FIG. 7B , Fig. 8A and 9A to 9C The pad pattern PAD and Fig. 10A , Fig.11 , Fig. 12A , Fig. 12B and Fig. 12C The pad pattern 330 is shown. The memory device 1100 can be connected by a connection structure (see Fig.14 2400 ) (such as a bonding wire connected to the external connection pad 1101 ) is electrically connected to the memory controller 1200 .

[0178] The memory controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface (I / F) 1230. In some embodiments, the memory system 1000 may include a memory device 1100. In this case, the memory controller 1200 may control the memory device 1100.

[0179] The processor 1210 may control the overall operation of the memory system 1000 including the memory controller 1200. The processor 1210 may operate according to certain firmware, and may control the NAND controller 1220 to access the memory device 1100. The NAND controller 1220 may include a NAND interface 1221 that handles communication with the memory device 1100. A control command for controlling the memory device 1100, data to be recorded on the memory cell transistors MCT of the memory device 1100, and data to be read from the memory cell transistors MCT of the memory device 1100 may be transmitted through the NAND interface 1221. The host interface 1230 may provide a communication function between the memory system 1000 and an external host. After receiving a control command from the external host through the host interface 1230, the processor 1210 may control the memory device 1100 in response to the control command.

[0180] Fig.14 is a perspective view schematically illustrating a memory system including a nonvolatile memory device according to an embodiment.

[0181] Reference Fig.14 , a memory system 2000 according to an embodiment may include a main board 2001, a memory controller 2002 disposed on the main board 2001, at least one semiconductor package 2003, and a dynamic random access memory (DRAM) 2004. The at least one semiconductor package 2003 and the DRAM 2004 may be connected to the memory controller 2002 through a plurality of wiring patterns 2005 formed on the main board 2001.

[0182] The mainboard 2001 may include a connector 2006 including a plurality of pins to be connected to an external host. The number and arrangement of the pins in the connector 2006 may vary according to the communication interface between the storage system 2000 and the external host. In some embodiments, the storage system 2000 may communicate with the external host according to one or more interfaces, such as M-Phy for Universal Flash Storage (UFS), Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), and Serial Advanced Technology Attachment (SATA), but the embodiment is not limited thereto. In some embodiments, the storage system 2000 may operate using power supplied from an external host through the connector 2006. The storage system 2000 may also include a power management integrated circuit (PMIC) (not explicitly shown) that distributes the power supplied from the external host to the storage controller 2002 and at least one semiconductor package 2003.

[0183] The memory controller 2002 may write data to or read data from at least one semiconductor package 2003 , and may increase the operation speed of the memory system 2000 .

[0184] The DRAM 2004 may be a buffer memory that mitigates the speed difference between the at least one semiconductor package 2003 as a data storage space and an external host. The DRAM 2004 included in the memory system 2000 may operate as a cache memory and may provide a space for temporarily storing data during a control operation of the at least one semiconductor package 2003. When the memory system 2000 includes the DRAM 2004, the memory controller 2002 may further include a DRAM controller that controls the DRAM 2004 and a NAND controller that controls the at least one semiconductor package 2003.

[0185] At least one semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other on a main board 2001. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package board 2100, a plurality of semiconductor chips 2200 on the package board 2100, an adhesive layer 2300 on a lower surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 to the package board 2100, and a molding layer 2500 covering the semiconductor chip 2200 and the connection structure 2400 on the package board 2100.

[0186] Each semiconductor chip 2200 may include the semiconductor chips shown in FIG. 4 to FIG. Fig. 12C At least one of the nonvolatile memory devices 1, 1-1, 1-2, 1-3, 1a, 1b, 1c, 1d, 2a, 2b, 3, 3a, 3b, 3c, 100, 100a, 200, 200a, and 200b described above. Each semiconductor chip 2200 may include an input / output (I / O) pad 2210. The I / O pad 2210 may correspond to Figure 4A , FIG. 5A to FIG. 7B , Fig. 8A and 9A to 9C The pad pattern PAD shown in , and Fig. 10A , Fig.11 , Fig. 12A , Fig. 12B and Fig. 12C The pad pattern 330 shown in FIG. The package board 2100 may be a printed circuit board including a plurality of package pads 2130 .

[0187] In some embodiments, the connection structure 2400 may be a bonding wire that electrically connects the I / O pad 2210 to the package upper pad 2130. Therefore, in the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other by a bonding wire method and may be electrically connected to the package upper pad 2130 of the package board 2100.

[0188] In some embodiments, the memory controller 2002 and the semiconductor chip 2200 may be included in a single package. In an embodiment, the memory controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer board different from the main board 2001, and the memory controller 2002 and the semiconductor chip 2200 may be connected to each other through wiring formed on the interposer board.

[0189] Fig.15 is a schematic diagram showing a method according to one or more embodiments Fig.14 Schematic cross-sectional view of an example semiconductor package 2003 is shown in FIG.

[0190] Reference Fig.15 The package board 2100 in the semiconductor package 2003 may be a printed circuit board. The package board 2100 may include a package board main body 2120, a plurality of package upper pads (see FIG. Fig.14 2130), a plurality of lower pads 2125 disposed on or exposed through the lower surface of the package board main body portion 2120, and a package upper pad (see Fig.14 2130) is electrically connected to a plurality of internal wirings 2135 of the lower pads 2125 in the package board main body portion 2120. Fig.14 As shown, the upper pad 2130 of the package can be electrically connected to the connection structure 2400. The lower pad 2125 can be connected to the Fig.14 Each semiconductor chip 2200 may include a wiring pattern 2005 on the main board 2001 of the storage system 2000 described in FIG. Fig. 12C At least one of the nonvolatile memory devices 1, 1-1, 1-2, 1-3, 1a, 1b, 1c, 1d, 2a, 2b, 3, 3a, 3b, 3c, 100, 100a, 200, 200a, and 200b is described.

[0191] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

[0192] CROSS-REFERENCE TO RELATED APPLICATIONS

[0193] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0133771 filed in the Korean Intellectual Property Office on October 6, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A nonvolatile memory device, comprising: a peripheral circuit structure comprising a peripheral circuit, a lower insulating structure on the peripheral circuit, and a plurality of lower bonding pads on an upper surface of the lower insulating structure and electrically connected to the peripheral circuit; A cell array structure having a cell region and a peripheral connection region, and comprising an upper insulating structure contacting the lower insulating structure, an upper bonding pad on a lower surface of the upper insulating structure and contacting the plurality of lower bonding pads, a cell stack in the cell region on the upper insulating structure, a common source line layer on the cell stack and having a common source opening, a plurality of cell channel structures extending at least partially through the cell stack in a vertical direction and extending into the common source line layer, and a support structure extending at least partially through the cell stack in the vertical direction and extending into the common source opening; and A pad pattern extends from the peripheral connection region to the cell region in a horizontal direction perpendicular to the vertical direction on the cell array structure and overlaps the support structure in the vertical direction.

2. The nonvolatile memory device according to claim 1 , wherein the plurality of unit channel structures are electrically connected to some of the plurality of upper bonding pads, and The support structure is not electrically connected to the plurality of upper bond pads.

3. The nonvolatile memory device according to claim 1 , wherein the cell array structure comprises a plurality of bit line contacts electrically connected to the plurality of upper bonding pads, the upper insulating structure extending around the plurality of bit line contacts, Some of the plurality of bit line contacts are in contact with lower surfaces of the plurality of cell channel structures, respectively, and The upper insulating structure is located on the lower surface of the supporting structure.

4. The nonvolatile memory device according to claim 3, wherein the cell array structure further comprises a filling insulating layer on the cell stack on the upper insulating structure, and a through contact plug electrically connected to the pad pattern through the filling insulating layer in the peripheral connection region, and A lower surface of the through contact plug contacts one of the plurality of bit line contacts.

5. The nonvolatile memory device according to claim 4, further comprising a pad connection via electrically connecting the through contact plug to the pad pattern and a pad support via electrically connecting the support structure to the pad pattern, Wherein the pad connecting via and the pad supporting via comprise the same material.

6. The nonvolatile memory device according to claim 1 , wherein the cell region includes a real cell region and a dummy cell region between the real cell region and the peripheral connection region in the horizontal direction, The support structure is in the dummy cell region, and The pad pattern extends from the peripheral connection region to the dummy cell region in the horizontal direction.

7. The nonvolatile memory device according to claim 1 , wherein the cell region includes a real cell region and a dummy cell region between the real cell region and the peripheral connection region in the horizontal direction, a plurality of support structures are located in each of the dummy cell region and the real cell region, and The pad pattern extends in the horizontal direction from the peripheral connection region through the dummy cell region to the real cell region. 8 . The nonvolatile memory device of claim 1 , wherein the support structure has the same structure as each of the plurality of unit channel structures. 9 . The nonvolatile memory device of claim 1 , wherein the support structure comprises polysilicon or a carbon-containing material. 10 . The nonvolatile memory device of claim 1 , wherein the support structure comprises a metal, a conductive metal nitride, a metal silicide, or any combination thereof.

11. A nonvolatile memory device, comprising: a peripheral circuit structure comprising a peripheral circuit, a lower insulating structure on the peripheral circuit, and a plurality of lower bonding pads on an upper surface of the lower insulating structure and electrically connected to the peripheral circuit; A cell array structure having a cell region and a peripheral connection region, and comprising: an upper insulating structure in contact with the lower insulating structure; an upper bonding pad on the lower surface of the upper insulating structure and in contact with the plurality of lower bonding pads; a cell stack in the cell region on the upper insulating structure; a common source line layer in the cell region and having a common source opening on the cell stack; a filling insulating layer on the upper insulating structure on the cell stack; a basic insulating layer at least partially filling the common source opening and on the common source line layer and the filling insulating layer; a plurality of cell channel structures extending in a vertical direction in the cell stack and extending into the common source line layer; a support structure extending in the vertical direction in the cell stack, extending into the basic insulating layer, and not electrically connected to the plurality of upper bonding pads; and a through contact plug extending in the vertical direction in the filling insulating layer, extending into the basic insulating layer, and connected to one of the plurality of upper bonding pads in the peripheral connection region; a pad pattern extending from the peripheral connection region to the cell region in a horizontal direction perpendicular to the vertical direction on the cell array structure, overlapping with the support structure and the through contact plug in the vertical direction, and electrically connected to the through contact plug; and A pad connection via and a pad support via extend in the vertical direction in the base insulating layer and connect between the through contact plug and the pad pattern and between the support structure and the pad pattern, the pad connection via and the pad support via comprising the same material.

12. The nonvolatile memory device according to claim 11, wherein: In a plan view, the common source opening is located at an edge of the common source line layer, and A plurality of support structures extend in the vertical direction in the cell stack and the base insulating layer.

13. The nonvolatile memory device according to claim 11, wherein a plurality of common source openings are spaced apart from an edge of the common source line layer and are spaced apart from each other in the horizontal direction, and At least one of a plurality of support structures extends in the vertical direction in the cell stack and the basic insulating layer.

14. The nonvolatile memory device according to claim 11, wherein the cell region includes a real cell region and a dummy cell region between the real cell region and the peripheral connection region in the horizontal direction, and The common source opening is in the dummy cell region.

15. The nonvolatile memory device according to claim 11, wherein the cell region includes a real cell region and a dummy cell region between the real cell region and the peripheral connection region in the horizontal direction, The common source opening is in the dummy cell region and the real cell region, and At least one of a plurality of support structures extends in the vertical direction in the cell stack in each of the dummy cell region and the real cell region and extends into the foundation insulating layer.

16. The nonvolatile memory device according to claim 11, wherein the cell array structure further comprises an upper interconnect structure, a bit line, and a bit line contact, which are sequentially located on each of the plurality of upper bonding pads, the upper insulating structure extends around the upper interconnect structure, the bit line, and the bit line contact, and A lower surface of each of the plurality of cell channel structures and a lower surface of the through contact plug are in contact with the bit line contact. 17 . The nonvolatile memory device of claim 16 , wherein a lower surface of the support structure is not in contact with the bit line contact, and the upper insulating structure is on the lower surface of the support structure.

18. A storage system comprising: A nonvolatile memory device, comprising: a peripheral circuit structure including a peripheral circuit, a lower insulating structure on the peripheral circuit, and a plurality of lower bonding pads on an upper surface of the lower insulating structure and electrically connected to the peripheral circuit; a cell array structure contacting the peripheral circuit structure and having a cell region and a peripheral connection region; and a pad pattern extending from the peripheral connection region to the cell region on the cell array structure; and a memory controller electrically connected to the nonvolatile memory device through a bonding wire connected to the pad pattern and configured to control the nonvolatile memory device, The cell array structure comprises: an upper insulating structure in contact with the lower insulating structure; an upper bonding pad on the lower surface of the upper insulating structure and in contact with the plurality of lower bonding pads; a cell stack in the cell region on the upper insulating structure; a common source line layer in the cell region and having a common source opening on the cell stack; a filling insulating layer on the upper insulating structure on the cell stack; a base insulating layer at least partially filling the common source opening and on the common source line layer and the filling insulating layer; a plurality of cell channel structures extending through the cell stack in a vertical direction and extending into the common source line layer; a support structure extending through the cell stack in the vertical direction, extending into the base insulating layer, and not electrically connected to the plurality of upper bonding pads; a through contact plug extending in the vertical direction in the filling insulating layer in the peripheral connection region and extending into the base insulating layer, and electrically connecting the pad pattern to one of the plurality of upper bonding pads; and a pad connection path and a pad support path, each of which extends in the base insulating layer in the vertical direction and connects between the through contact plug and the pad pattern and between the support structure and the pad pattern. 19 . The memory system of claim 18 , wherein the pad connecting via and the pad supporting via each contact a lower surface of the pad pattern and include a same material, the material including metal.

20. The memory system of claim 18, wherein the cell array structure further comprises an upper interconnect structure, a bit line, and a bit line contact, which are sequentially located on each of the plurality of upper bonding pads and surrounded by the upper insulating structure, A lower surface of each of the plurality of unit channel structures and a lower surface of the through contact plug are in contact with the bit line contact, and A lower surface of the support structure is not in contact with the bit line contact, and the upper insulating structure is located on the lower surface of the support structure.

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