Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and is applied to the technical field of semiconductors. According to the invention, the first insulating structure is a composite structure, and the gaps and / or gaps are formed in the plurality of insulating layers contained in the first insulating structure, so that the efficiency and the reliability of the semiconductor device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Dynamic random access memory (DRAM) is a type of volatile memory, including an array area consisting of multiple memory cells and a peripheral area consisting of a control circuit. Each memory cell is composed of a transistor and a capacitor electrically connected to the transistor, and the transistor controls the storage or release of the charge in the capacitor to achieve the purpose of storing data. The control circuit can address each memory cell to control the access of data to each memory cell through word lines (WL) and bit lines (BL) that span the array area and are electrically connected to each memory cell. However, due to the limitations of process technology, the existing dynamic random access memory still has many defects, and further improvements are needed to effectively enhance the performance and reliability of related memory components. Summary of the invention

[0003] The object of the present invention is to provide a semiconductor device and a manufacturing method thereof, so as to improve the performance and reliability of the semiconductor device.

[0004] In a first aspect, in order to solve the above technical problems, the present invention provides a semiconductor device, which may at least include:

[0005] substrate;

[0006] A plurality of first insulating structures are disposed on the substrate in a mutually separated manner, and the first insulating structures include a first insulating layer and a second insulating layer, wherein the first insulating layer and the second insulating layer of at least one of the first insulating structures include a first gap and a second gap respectively;

[0007] A plurality of first contact structures are located between adjacent first insulating structures.

[0008] Optionally, the first insulating layer and the second insulating layer of at least one of the first insulating structures define a gap, and a width of the gap in the horizontal direction may be greater than a width of the first gap in the first insulating layer in the horizontal direction.

[0009] Optionally, the gap contacts the first gap and / or the second gap.

[0010] Optionally, a top surface of the gap may be higher than a top surface of the first contact structure.

[0011] Optionally, the semiconductor device may further include:

[0012] A plurality of word line structures are mutually separated and arranged in the substrate and are located opposite to the first insulating structure. At least one of the word line structures comprises an insulating cover layer having a third gap, and the first insulating layer extends into the insulating cover layer in a vertical direction and directly contacts the insulating cover layer.

[0013] Optionally, the first insulating structure may further include: a third insulating layer located on two outer side walls of the first insulating layer.

[0014] Optionally, the third insulating layer of at least one of the first insulating structures is further located between the first insulating layer and the second insulating layer, and the third insulating layer and the first insulating layer define a gap, and the gap contacts the first gap.

[0015] Optionally, the first slit in the first insulating layer may be aligned with the second slit in the second insulating layer in the same vertical direction.

[0016] Optionally, the first gap in the first insulating layer may be connected to the second gap in the second insulating layer.

[0017] Optionally, the third gap of the insulating cap layer of at least one of the word line structures is aligned with the first gap in the first insulating layer and / or the second gap in the second insulating layer in the same vertical direction.

[0018] Optionally, the second insulating layer may also extend to cover a portion of the side walls of the third insulating layer located on two outer side walls of the first insulating layer.

[0019] Optionally, the semiconductor device may further include:

[0020] A plurality of second contact structures are located on the first contact structure and extend in a horizontal direction to cover a portion of the top surface of the first insulating structure.

[0021] Optionally, the semiconductor device may further include:

[0022] A plurality of second insulating structures are located between adjacent second contact structures and directly contact the first insulating structure through the second contact structures.

[0023] Optionally, at least one of the second insulating structures is in direct contact with the gap in the first insulating structure.

[0024] Optionally, at least one of the second insulating structures is in direct contact with the second gap in the second insulating layer of the first insulating structure.

[0025] In a second aspect, based on the same inventive concept, the present invention also provides a method for manufacturing a semiconductor device, which may at least include the following steps:

[0026] providing a substrate;

[0027] forming a plurality of first insulating structures, which are disposed on the substrate in a spaced manner, and the first insulating structures include a first insulating layer and a second insulating layer, wherein the first insulating layer and the second insulating layer of at least one of the first insulating structures include a first gap and a second gap respectively;

[0028] A plurality of first contact structures are formed and located between adjacent first insulating structures.

[0029] Optionally, the step of forming the first insulating structure may include:

[0030] forming a sacrificial layer having a plurality of through holes on the substrate;

[0031] Forming a first insulating layer to fill the through hole, wherein a first gap exists in the first insulating layer;

[0032] etching back to remove a portion of the first insulating layer to form a recess on the top of the first insulating layer, the bottom of which contacts the first slit;

[0033] A second insulating layer is formed to fill the recess and extend to cover a portion of the height of the two side walls of the first insulating layer, and a second gap exists in the second insulating layer.

[0034] Optionally, the first insulating layer and the second insulating layer of at least one of the first insulating structures define a gap, and a width of the gap in the horizontal direction may be greater than a width of the first gap in the first insulating layer in the horizontal direction.

[0035] Optionally, before forming the second insulating layer, the method may further include:

[0036] A third insulating layer is formed on two outer side walls of the first insulating layer.

[0037] Optionally, the third insulating layer may also be located between the first insulating layer and the second insulating layer in the recess of at least one of the first insulating structures, and the third insulating layer and the first insulating layer define a gap, and the gap contacts the first gap.

[0038] In the present invention, multiple first insulating structures may include at least a first insulating layer and a second insulating layer, wherein gaps are respectively arranged in the first insulating layer and the second insulating layer of at least one first insulating structure, for example, a first gap in the first insulating layer and a second gap in the second insulating layer, and the first insulating layer and the second insulating layer in at least one first insulating structure define a gap, that is, by setting the first insulating structure as a composite structure and providing gaps and / or gaps in the multiple insulating layers it contains, a new structure of the first insulating structure and a semiconductor device containing the new structure are formed, thereby improving the performance and reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application but do not constitute a limitation to the present application. In the accompanying drawings:

[0040] Figure 1 to Figure 14 The figure is a schematic diagram of the structure of a semiconductor device during the preparation process provided in one embodiment of the present invention.

[0041] Wherein, the accompanying drawings are marked as follows:

[0042] 100-substrate, 110-trench isolation, 120-word line structure, 121-gate dielectric layer, 122-work function layer, 123-conductive layer, 124-insulating cap layer, 124.1-gap in the insulating cap layer (third gap), 130-isolation layer, 140-sacrificial layer, 101-through hole, 151-first insulating layer, 102-gap in the first insulating layer (first gap), 103-recess, 103'-gap defined by the first insulating layer and the second insulating layer, 104-third insulating layer and the first insulating layer define gap, 152-third insulating layer, 105-gap in the third insulating layer, 106-first contact groove, 160-first contact material layer, 161-first contact structure, 153-second insulating layer, 107-gap in the second insulating layer (second gap), 162-silicide layer, 163-second contact structure, 171-first insulating structure, 172-second insulating structure, 180-capacitor, 181-lower electrode, 182-capacitor dielectric, 183-upper electrode, BL-bit line structure, ACT-active area.

[0043] In the drawings, the same reference numerals are used for the same components, and the drawings are not drawn to scale. DETAILED DESCRIPTION

[0044] In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0045] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the accompanying drawings are all in very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It is understood that the meanings of "on", "above" and "above" in the present invention should be interpreted in the broadest way, so that "on" not only means that it is "on" something and there are no intervening features or layers (i.e. directly on something), but also includes the meaning of being "on" something and having intervening features or layers.

[0046] For ease of understanding, a horizontal direction and a vertical direction are defined below, wherein the horizontal direction is a direction parallel to the surface of the substrate 100 ; and the vertical direction is a direction perpendicular to the surface of the substrate 100 .

[0047] Please refer to Fig.13 , which is a cross-sectional schematic diagram of a semiconductor device in the first embodiment of the present invention. The semiconductor device of the present invention can be used to manufacture dynamic random access memory (DRAM), and the present invention can also be applied to other types of memory without departing from the spirit of the present invention.

[0048] like Fig.13As shown, the semiconductor device includes a substrate 100, a plurality of word line structures 120, a plurality of first contact structures 161, a silicide layer 162, a plurality of second contact structures 163, a plurality of first insulating structures 171, a plurality of second insulating structures 172 and a plurality of capacitors 180. The substrate 100 is any suitable substrate material known in the art, for example, a silicon substrate, a silicon-containing substrate (such as SiC, SiGe) or a silicon-on-insulator substrate or a substrate composed of other suitable materials, etc., but not limited thereto. A plurality of trench isolations 110 are further provided in the substrate 100 to define a plurality of active regions (not shown) extending in the same direction (not shown) in the substrate 100. In one embodiment, the trench isolation 110 may be in the shape of a long strip and arranged in sequence along the horizontal direction; the trench isolation 110 may include a single layer or multiple layers of dielectric material, and applicable dielectric materials may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, nitrogen-doped silicon carbide, low dielectric constant dielectric materials such as fluorosilicate glass, carbon silicon oxide, spin-on silicon glass, porous low dielectric constant dielectric materials, organic polymer dielectric materials, or a combination of the above materials, but not limited thereto. The multiple word line structures 120 are arranged in the multiple trench isolations 110, and can also be arranged in a horizontal direction and separated from each other and in the shape of long strips extending in the vertical direction. The details may include a gate dielectric layer 121 (the material is, for example, a high dielectric constant), a work function layer 122 (the material is, for example, titanium nitride), a conductive layer 123 (the material is, for example, metal tungsten) and an insulating cap layer 124 (the material is, for example, an oxide or a nitride), but the present invention is not limited thereto. The insulating cap layer 124 of at least one of the multiple word line structures 120 may also have a gap, i.e., a third gap 124.1, but the present invention is not limited thereto.

[0049] The plurality of first insulating structures 171 are disposed on the substrate 100 in a horizontal direction and spaced from each other and are in the shape of long strips extending in the vertical direction, and each of the plurality of first insulating structures 171 includes at least a first insulating layer 151 and a second insulating layer 153. In one embodiment, the first insulating layer 151 and the second insulating layer 153 may be in an upper and lower positional relationship as a whole in the vertical direction, such as the first insulating layer 151 is located below the second insulating layer 153, and the second insulating layer 153 may be located at the top of the first insulating layer 151 and embedded in the first insulating layer 151, and further extends to cover a portion of the height of the two outer side walls of the first insulating layer 151 in each of the first insulating structures 171, such as the upper part of the two outer side walls of the first insulating layer 151, so that the top surface of the second insulating layer 153 in each of the first insulating structures 171 is flush with the top surfaces of the first insulating layer 151 located on both sides of the first insulating structure 171. Furthermore, at least one of the plurality of first insulating structures 171 has a gap respectively disposed in the first insulating layer 151 and the second insulating layer 153 , such as a first gap 102 disposed in the first insulating layer 151 and a second gap 107 disposed in the second insulating layer 153 .

[0050] It should be particularly noted that, in the embodiment of the present invention, the first slit 102 in the first insulating layer 151 has a longer extension length in the vertical direction, while the second slit 107 in the second insulating layer 153 is not subject to this limitation, that is, the bottom of the second slit 107 may be at the same level as the bottom of the second insulating layer 153 in which it is located, or may be higher in the vertical direction than the bottom of the second insulating layer 153 in which it is located. Furthermore, the length of the second insulating layer 153 in the vertical direction may be set to be different in different first insulating structures 171, so that the bottom of the second insulating layer 153 located in part of the first insulating structure 171 is in direct contact with the first slit 102 of the first insulating layer 151 in the first insulating structure 171, while the bottom of the second insulating layer 153 located in another part of the first insulating structure 171 is not in direct contact with the first slit 102 of the first insulating layer 151 in the first insulating structure 171, that is, the first insulating layer 151 and the second insulating layer 153 located in another part of the first insulating structure 171 may define a gap at the junction of the two, such as Fig.13The area marked by the reference numeral 103' in the figure. Preferably, the width of the gap defined by the first insulating layer 151 and the second insulating layer 153 in the horizontal direction may be greater than the width of the first gap 102 in the first insulating layer 151 in the horizontal direction, and the top surface of the gap defined by the first insulating layer 151 and the second insulating layer 153 is also higher than the top surface of the first contact structure 161, but the bottom of the gap defined by the first insulating layer 151 and the second insulating layer 153 may be higher, lower or equal to the top surface of the first contact structure 161, but is not limited thereto. Furthermore, the first gap 102 in the first insulating layer 151 of the same first insulating structure 171 can be aligned with the second gap 107 in the second insulating layer 153 in the same vertical direction (i.e., perpendicular direction), and the first gap 102 in the first insulating layer 151 and / or the second gap 107 in the second insulating layer 153 of the same first insulating structure 171 and the third gap 124.1 in the word line structure 120 aligned with the first insulating structure 171 can also be aligned in the same vertical direction, but not limited to this.

[0051] In one embodiment, at least part of the first insulating structure 171 is further provided with a third insulating layer 152; specifically, the third insulating layer 152 may be located on the two outer side walls of the first insulating layer 151 in the first insulating structure 171, or the third insulating layer 152 may be located between the first insulating layer 151 and the second insulating layer 153 in the first insulating structure 171, and extend to cover the two outer side walls of the first insulating layer 151. Under this setting, the part of the second insulating layer 153 covering the two outer side walls of the first insulating layer 151 is actually located on the two outer side walls of the third insulating layer 152; and the third insulating layer 152 and the first insulating layer 151 located in the same first insulating structure 171 may also define a gap such as Fig.13 The area marked by the reference numeral 104 in the figure, and the gap is in direct contact with the first gap 102 in the first insulating layer 151. Of course, in other embodiments, the third insulating layer 152 located in the same first insulating structure 171 may also be in direct contact with the first gap 102 in the first insulating layer 151, without defining a gap (not shown). Similarly, the width of the gap defined by the third insulating layer 152 and the first insulating layer 151 in the horizontal direction may also be greater than the width of the first gap 102 in the first insulating layer 151 in the horizontal direction, and the top surface of the gap defined by the third insulating layer 152 and the first insulating layer 151 may also be higher than the top surface of the first contact structure 161, but the bottom of the gap is not limited, and may be higher, lower or equal to the top surface of the first contact structure 161, but is not limited thereto.

[0052] It should be understood that the materials of the first insulating layer 151, the second insulating layer 153 and the third insulating layer 152 can all be insulating materials, such as silicon oxide, silicon nitride, etc., and the materials of the first insulating layer 151, the second insulating layer 153 and the third insulating layer 152 can be the same or different, but are preferably different insulating materials.

[0053] Furthermore, the plurality of first contact structures 161 are disposed between adjacent first insulating structures 171 in a mutually spaced manner in the horizontal direction, and the top surface of each first contact structure 161 is lower than the top surface of any first insulating structure 171 located on both sides thereof; the silicide layer 162 is located on the top surface of the first contact structure 161, and the plurality of second contact structures 163 are respectively disposed on the first contact structure 161, and extend in the horizontal direction to cover a portion of the top surface of the corresponding first insulating structure 171. The plurality of second insulating structures 172 are respectively disposed between adjacent second contact structures 163, and directly contact the first insulating structure 171 through the second contact structure 163. In the embodiment of the present invention, the extension lengths of the plurality of second insulating structures 172 in the vertical direction may be different, so that some of the second insulating structures 172 may pass through the corresponding first insulating structure 171 in the vertical direction and directly contact the gap therein, that is, some of the second insulating structures 172 may directly contact the gap defined by the first insulating layer 151 and the second insulating layer 153 in the corresponding first insulating structure 171 (the position marked by the reference numeral 103'), such as Fig.13 As shown; or, it may also be in direct contact with the gap (the position marked by the figure mark 104) defined by the first insulating layer 151 and the third insulating layer 152 in the corresponding first insulating structure 171 (not shown); or, part of the second insulating structure 172 is in direct contact with the second gap 107 in the second insulating layer 153 in the corresponding first insulating structure 171, but is not limited to this.

[0054] In one embodiment, the material of the first contact structure 161 may include single crystal silicon (crystalline silicon), polycrystalline silicon (poly silicon), amorphous silicon (amorphous silicon), doped silicon (doped silicon), silicon germanium (SiGe), or other suitable silicon-containing semiconductor materials, but not limited thereto. Exemplarily, the material of the first contact structure 161 is phosphorus-doped silicon (SiP). The second contact structure 163 may be a single-layer structure or a multi-layer structure, and its material may include conductive barrier materials such as titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN), and preferably titanium nitride (TiN), or a metal material such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), nitrides, silicides, alloys, and / or composite layers of the above materials, and preferably tungsten (W), but not limited thereto. The material of the second insulating structure 172 may be an insulating material, such as nitride, silicon oxide, etc., but not limited thereto.

[0055] In addition, the plurality of capacitors 180 are respectively located on the second contact structure 163; in detail, the capacitor 180 may include a lower electrode 181, a capacitor dielectric layer 182 and an upper electrode 183. The lower electrode 181 is disposed on the second contact structure 163, the upper electrode 183 is disposed on the lower electrode 181, and the capacitor dielectric layer 182 is disposed between the upper electrode 181 and the lower electrode 183.

[0056] A person skilled in the art of the present invention should be able to easily understand that, in order to meet the actual product requirements, the semiconductor device of the present invention may also have other aspects and is not limited to the above. Other embodiments or variations of the semiconductor device of the present invention will be further described below. In order to simplify the description, the following description mainly describes the differences between the embodiments, and does not repeat the same aspects. In addition, the same components in the embodiments of the present invention are marked with the same reference numerals to facilitate comparison between the embodiments.

[0057] Please refer to Fig.14, which is a cross-sectional schematic diagram of a semiconductor device in a second embodiment of the present invention. The structure of the semiconductor device in this embodiment is substantially the same as that of the semiconductor device in the first embodiment, such as the semiconductor device also includes a plurality of word line structures 120, a plurality of first contact structures 161, a silicide layer 162, a plurality of second contact structures 163, a plurality of first insulating structures 171, a plurality of second insulating structures 172 and a plurality of capacitors 180; wherein at least one first insulating structure 171 includes a first insulating layer 151 and a second insulating layer 153, and at least one first insulating structure 171 includes a first insulating layer 151, a second insulating layer 153 and a third insulating layer 152, and a gap is also provided in each of the first insulating layer 151 and the second insulating layer 153, such as a first gap 102 provided in the first insulating layer 151 and a second gap 107 provided in the second insulating layer 153, etc., and the same parts are not repeated here. The main difference between the semiconductor device of this embodiment and the aforementioned first embodiment is that the first gap 102 in the first insulating layer 151 in at least one first insulating structure 171 among the multiple first insulating structures 171 is connected with the second gap 107 in the corresponding second insulating layer 153; and / or the first gap 102 in the first insulating layer 151 in at least one first insulating structure 171 among the multiple first insulating structures 171 is in direct contact with the gap 103' defined at the junction of the first insulating layer 151 and the corresponding second insulating layer 153, so that the first gap 102, the gap 103' and the second gap 107 in a first insulating structure 171 are connected, but not limited to this.

[0058] Further, based on the same concept, an embodiment of the present invention also provides a method for preparing the semiconductor device, which may include at least the following steps:

[0059] Step S100, providing a substrate 100;

[0060] Step S200, forming a plurality of first insulating structures 171, which are disposed on the substrate 100 in a spaced manner, and the first insulating structures 171 include a first insulating layer 151 and a second insulating layer 153, wherein the first insulating layer 151 and the second insulating layer 153 of at least one of the first insulating structures 171 include a first gap 102 and a second gap 107, respectively;

[0061] Step S300 , forming a plurality of first contact structures 161 located between adjacent first insulating structures 171 .

[0062] In order to enable a person skilled in the art to which the present invention relates to easily understand the method for manufacturing a semiconductor device in an embodiment of the present invention, the method for manufacturing a semiconductor device proposed in the present invention will be further described below in conjunction with various structural schematic diagrams of the manufacturing method during the preparation process.

[0063] Please refer to Figure 1 to Figure 14 As shown, what is depicted is a schematic diagram of the structure of the semiconductor device manufacturing method provided in an embodiment of the present invention during the manufacturing process. Figure 1 The one shown is Figure 2 to Figure 14 A top view of a partial structure of a semiconductor device is shown, so as to distinguish the positional relationship of some different components and / or devices of the semiconductor device in the embodiment of the present invention. Figure 2 to Figure 14 The one shown is Figure 1 The AA cut line shown is a cross-sectional view of the local structure of some different components of the semiconductor device and / or the device during the manufacturing process.

[0064] like Figure 1 As shown, the semiconductor device provided in the embodiment of the present invention may include a plurality of word line structures 120 and a plurality of bit line structures BL arranged alternately therewith, and a plurality of active areas ACT arranged in the substrate 100, and the AA cut line is located between any two adjacent bit line structures BL and the extension direction of the AA cut line is the same as the extension direction of any bit line structure BL, so in Figure 2 to Figure 14 The bit line structure BL is not shown in the partial structural cross-sectional view.

[0065] like Figure 2As shown, the above step S100 is performed: firstly, a substrate 100 (eg, a silicon substrate) is provided, and then a plurality of trench isolations 110 and word line structures 120 located in the trench isolations 110 are formed in the substrate 100 . In one embodiment, the process of forming the trench isolation 110 and the word line structure 120 may include: using at least one of an etching process such as a dry etching process or a wet etching process to form a plurality of trenches arranged in sequence along a horizontal direction in the substrate 100, and then using at least one of a deposition process such as a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process to fill the plurality of trenches with an insulating material (such as silicon oxide, silicon nitride, etc.) to form the trench isolation 110; the plurality of trench isolations 110 define a plurality of active areas ACT in the substrate 100; and then using a deposition process to sequentially form a gate dielectric layer 121 (such as a high dielectric constant), a work function layer 122 (such as titanium nitride), a conductive layer 123 (such as metal tungsten) and an insulating cap layer 124 (such as oxide or nitride) having a third gap 124.1 therein in the trench isolation 110, thereby forming the word line structure 120. It should be understood that the third gap 124 . 1 may be located in the insulating capping layer 124 of each of the word line structures 120 , or may be located in the insulating capping layer 124 of some of the word line structures 120 , but is not limited thereto.

[0066] Next, an isolation layer 130 may be further formed on the surface of the substrate 100. In one embodiment, the isolation layer 130 may be a single-layer structure (eg Figure 2 It may be a silicon oxide layer or a silicon nitride layer, or may be a composite layer (not shown), such as an ONO composite layer composed of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer, but is not limited thereto.

[0067] like Figure 3 As shown, following the above step S100, a deposition process such as at least one of a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process may be further used to form a sacrificial layer 140 having a certain thickness on the isolation layer 130 of the substrate 100. In one embodiment, the material of the sacrificial layer 140 may be a single-layer or multi-layer oxide material, such as silicon oxide, boro-phospho-silicate-glass (BPSG) or other sacrificial materials, but is not limited thereto.

[0068] like Figure 4As shown, following the above step S100, an etching process such as a dry etching process can be used to form a plurality of through holes 101 arranged in sequence and spaced apart from each other along a horizontal direction in the sacrificial layer 140; in one embodiment, the number of the through holes 101 can be the same as the number of the word line structures 120, and one of the through holes 101 is located opposite to one of the word line structures 120. It should be particularly noted that each of the through holes 101 in the embodiment of the present invention not only penetrates the sacrificial layer 140 in the vertical direction, but also further penetrates the isolation layer 130 below the sacrificial layer 140 and a portion of the height of the insulating cover layer 124 in the word line structure 120 aligned therewith in the vertical direction, so that the bottom of the through hole 101 exposes the remaining insulating cover layer 124, that is, the bottom surface of the through hole 101 is lower than the bottom surface of the substrate 100 or the isolation layer 130, so that the bottom of the first insulating layer 151 subsequently filled in the through hole 101 can be in direct contact with the remaining insulating cover layer 124 in each word line structure 120, but is not limited to this.

[0069] like Figure 5 As shown, the above step S200 is performed: a deposition process such as a chemical vapor deposition process may be used to first form a first insulating layer 151 having a first gap 102 inside on the substrate 100. At this time, the material of the first insulating layer 151 having the first gap 102 is not only filled into each of the through holes 101, but also extends laterally in the horizontal direction to cover the top surface of the sacrificial layer 140 exposed between adjacent through holes 101. In one embodiment, the material of the first insulating layer 151 may be silicon oxide or silicon nitride, but is not limited thereto; the shape of the first gap 102 located in the first insulating layer 151 may be a gate-shaped gap extending in the vertical direction, and the length of the long side of the first gap 102 in the vertical direction is much greater than the length of the short side in the horizontal direction, for example, its long side may be N times the length of its short side, where N≥3. It should be understood that Figure 5 The first insulating layer 151 shown in each through hole 101 is provided with a first gap 102, while in other embodiments, the first insulating layer 151 located in some of the through holes 101 may also be provided with a first gap 102, that is, at least one first insulating layer 151 located in the through hole 101 is not provided with a first gap 102 (not shown), but it is not limited to this.

[0070] like Figure 6As shown, the above step S200 is performed: the first insulating layer 151 extending laterally and covering the top surface of the sacrificial layer 140 exposed between adjacent through holes 101 is etched back, for example, a dry etching process is performed to remove the material of the first insulating layer 151 exceeding the top surface of the sacrificial layer 140, and at the same time, the first insulating layer 151 located in one or more through holes 101 is partially removed in height to form a recess 103 at the top of the first insulating layer 151 located in the through hole 101; in one embodiment, the bottom of the recess 103 located in a through hole 101 can be in direct contact with the first gap 102 in the remaining first insulating layer 151 in the through hole 101. Furthermore, the bottom of the recess 103 located at the top of the first insulating layer 151 in different through holes 101 (which can also be understood as the lowest point of the bottom surface contour) is located at different horizontal heights, that is, the bottoms of the multiple recesses 103 have a height difference in the vertical direction, and this height difference will also cause the shapes of the multiple recesses 103 to have partial differences, but is not limited to this.

[0071] like Figure 7 and Figure 8 As shown, the above step S200 is performed: the sacrificial layer 140 between the adjacent through holes 101 can be removed first to expose the two outer side walls of the first insulating layer 151 located in the through holes 101, as shown in FIG. Figure 7 As shown; then, a third insulating layer 152 is formed on the substrate 100 to fill the recess 103 and the two outer side walls of the first insulating layer 151. In one embodiment, since the recesses 103 in different through holes 101 have different depths in the vertical direction, the third insulating layer 152 filled in different recesses 103 will also have gaps in at least part of the third insulating layer 152 in the recess 103, such as Figure 8 In the area marked by reference numeral 105, there is also a gap defined at the junction of the third insulating layer 152 filled in part of the through hole 101 and the first insulating layer 151 located in the same through hole 101, such as Figure 8 The area marked by the reference numeral 104 in the figure; wherein the bottoms of the gaps 105 in the third insulating layer 152 located in different recesses 103 may be located at the same level or at different levels, and the top surfaces and / or bottom surfaces of the gaps 104 defined by the third insulating layer 152 and the first insulating layer 151 located in different through holes 101 may also be the same or different. In addition, the materials of the third insulating layer 152 and the first insulating layer 151 may both be insulating materials, such as silicon oxide or silicon nitride, but not limited thereto, and the materials of the two may be the same or different, but preferably different.

[0072] like Fig. 9 and Fig.10As shown, the above step S300 is performed: then an etching process such as a dry etching process can be used to remove the isolation layer 130 outside the first insulating layer 151 and the third insulating layer 152 aligned with the word line structure 120 and a portion of the height of the substrate 100 below the isolation layer 130 in the vertical direction to form a plurality of first contact grooves 106 for subsequent preparation of the first contact structure 161, and then a deposition process is used to fill the first contact grooves 106 with a first contact material layer 160 (such as single crystal silicon or polycrystalline silicon); the first contact material layer 160 formed at this time not only fills the first contact grooves 106, but also extends horizontally in the horizontal direction to cover the top surface and side walls of the first insulating layer 151 and the third insulating layer 152 to bury the film layer structure on the substrate 100.

[0073] like Fig.11 and Fig.12 As shown, the above step S300 is performed: the first contact material layer 160 extending laterally and covering the top surface and part of the side wall of the first insulating layer 151 and the third insulating layer 152 can be further etched back to remove, so as to form a first contact structure 161 whose top surface is lower than the top surface of the first insulating layer 151 or the top surface of the third insulating layer 152. In this etch-back removal process, since the third insulating layer 152 located in the recess 103 is not shielded, part of its height will also be removed, and the third insulating layer 152 located in the recesses 103 with different depths will also be removed at different heights in this step. For example, part of the third insulating layer 152 in the recess 103 with a deeper depth in the vertical direction will remain after performing this step, while the third insulating layer 152 in the recess 103 with a shallower depth in the vertical direction can be completely removed, but this is not limited to it. Then, a second insulating layer 153 (made of, for example, silicon nitride) may be further formed in the remaining space of the recess 103 and on the exposed side walls of the third insulating layer 152 by a deposition process, and a gap, such as the second gap 107, may also exist in the second insulating layer 153 in the remaining space of the recess 103. Thus, a first insulating structure 171 consisting of the first insulating layer 151, the second insulating layer 153 and the third insulating layer 152, or the first insulating layer 151 and the third insulating layer 152, is formed.

[0074] It should be understood that, since the depths of different recesses 103 along the vertical direction are different (i.e., the extension lengths along the vertical direction are different), and the third insulating layer 152 formed in some of the deeper recesses 103 may also have a gap at the junction with the corresponding first insulating layer 151, such as Fig.12 The area is marked with the reference numeral 103', but the present invention is not limited thereto.

[0075] Furthermore, when the second insulating layer 153 having the second gap 107 is formed by this step, there will also be Fig.14 The first gap 102 in the first insulating layer 151 in at least one first insulating structure 171 among the multiple first insulating structures 171 formed as shown is connected with the second gap 107 in the corresponding second insulating layer 153; and / or the first gap 102 in the first insulating layer 151 in at least one first insulating structure 171 among the multiple first insulating structures 171 is in direct contact with the gap 103' defined at the junction of the first insulating layer 151 and the corresponding second insulating layer 153, so that the first gap 102, the gap 103' and the second gap 107 in a first insulating structure 171 are connected.

[0076] like Fig.13 or Fig.14 As shown, following the above step S300: then, a deposition and etching process can be further utilized to form a silicide layer 162 located on the top surface of the first contact structure 161, and then a plurality of second contact structures 163 (materials such as titanium nitride and / or metal tungsten) are formed, which are arranged between adjacent first insulating structures 171 and separated from each other in the horizontal direction and are located on the silicide layer 162, and the second contact structures 163 also extend in the horizontal direction to cover part of the top surface of the corresponding first insulating structure 171; then, a plurality of second insulating structures 172 (materials such as silicon oxide or silicon nitride) are formed, which are located between adjacent second contact structures 163 and pass through the second contact structures 163 to directly contact the first insulating structure 171. In one embodiment, the extension lengths of the plurality of second insulating structures 172 in the vertical direction may be different, so that some of the second insulating structures 172 may pass through the corresponding first insulating structure 171 in the vertical direction and directly contact the gap therein, that is, some of the second insulating structures 172 may directly contact the gap defined by the first insulating layer 151 and the second insulating layer 153 in the corresponding first insulating structure 171 (the position marked by the reference numeral 103'), such as Fig.13 or Fig.14 As shown; or, it may also be in direct contact with the gap (the position marked by the figure mark 104) defined by the first insulating layer 151 and the third insulating layer 152 in the corresponding first insulating structure 171 (not shown); or, part of the second insulating structure 172 is in direct contact with the second gap 107 in the second insulating layer 153 in the corresponding first insulating structure 171, but is not limited to this.

[0077] Next, a capacitor 180 is formed on the second contact structure 163. In one embodiment, the capacitor 180 may include a lower electrode 181, a capacitor dielectric layer 182 and an upper electrode 183. The materials of the lower electrode 181 and the upper electrode 183 may be conductive materials, such as doped silicon, tungsten, copper, titanium nitride or others, but not limited thereto. The material of the capacitor dielectric layer 182 may be a high dielectric constant material layer, such as TaOO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, BST((Ba,Sr)TiO), STO(SrTiO), BTO(BaTiO), PZT(Pb(Zr,Ti)O), (Pb,La)(Zr,Ti)O, Ba(Zr,Ti)OO, Sr(Zr,Ti)O, combinations of the above materials or other suitable dielectric materials, and the material of the upper electrode 183 may include titanium nitride, tantalum nitride, SiGe, combinations of the above materials or other suitable conductive materials, but not limited thereto.

[0078] It should be understood that the "common shape" in the present invention refers to constructing a continuous structural shape by utilizing the morphological similarities and correlations between two or more shapes.

[0079] To summarize, in the present invention, multiple first insulating structures may include at least a first insulating layer and a second insulating layer, wherein the first insulating layer and the second insulating layer of at least one first insulating structure are respectively provided with gaps, for example, a first gap in the first insulating layer and a second gap in the second insulating layer, and the first insulating layer and the second insulating layer in at least one first insulating structure define a gap, that is, by setting the first insulating structure as a composite structure and providing gaps and / or voids in the multiple insulating layers it contains, a new structure of the first insulating structure and a semiconductor device protecting the new structure are formed, and the performance and reliability of the semiconductor device can also be improved.

[0080] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: substrate; A plurality of first insulating structures are disposed on the substrate in a mutually separated manner, and the first insulating structures include a first insulating layer and a second insulating layer, wherein the first insulating layer and the second insulating layer of at least one of the first insulating structures include a first gap and a second gap respectively; A plurality of first contact structures are located between adjacent first insulating structures.

2. The semiconductor device according to claim 1, wherein The first insulating layer and the second insulating layer of at least one of the first insulating structures define a gap, and a width of the gap in the horizontal direction is greater than a width of the first gap in the first insulating layer in the horizontal direction.

3. The semiconductor device according to claim 2, wherein: The gap contacts the first gap and / or the second gap.

4. The semiconductor device according to claim 2, wherein: A top surface of the gap is higher than a top surface of the first contact structure.

5. The semiconductor device according to claim 1, wherein: Also includes: A plurality of word line structures are mutually separated and arranged in the substrate and are located opposite to the first insulating structure. At least one of the word line structures comprises an insulating cover layer having a third gap, and the first insulating layer extends into the insulating cover layer in a vertical direction and directly contacts the insulating cover layer.

6. The semiconductor device according to claim 1, wherein: The first insulating structure further includes: a third insulating layer located on two outer side walls of the first insulating layer.

7. The semiconductor device according to claim 6, wherein: The third insulating layer of at least one of the first insulating structures is also located between the first insulating layer and the second insulating layer, and the third insulating layer and the first insulating layer define a gap, and the gap contacts the first gap.

8. The semiconductor device according to claim 1, wherein The first slit in the first insulating layer is aligned with the second slit in the second insulating layer in the same vertical direction.

9. The semiconductor device according to claim 8, characterized in that The first gap in the first insulating layer is connected to the second gap in the second insulating layer.

10. The semiconductor device according to claim 5, wherein: The third slit of the insulating cap layer of at least one of the word line structures is aligned with the first slit in the first insulating layer and / or the second slit in the second insulating layer in the same vertical direction.

11. The semiconductor device according to claim 7, wherein: The second insulating layer also extends to cover a portion of the side walls of the third insulating layer located on two outer side walls of the first insulating layer.

12. The semiconductor device according to claim 11, wherein Also includes: A plurality of second contact structures are located on the first contact structure and extend in a horizontal direction to cover a portion of the top surface of the first insulating structure.

13. The semiconductor device according to claim 12, wherein: Also includes: A plurality of second insulating structures are located between adjacent second contact structures and directly contact the first insulating structure through the second contact structures.

14. The semiconductor device according to claim 13, wherein: At least one of the second insulating structures is in direct contact with the gap in the first insulating structure.

15. The semiconductor device according to claim 13, wherein: At least one second insulating structure is in direct contact with a second gap in the second insulating layer of the first insulating structure.

16. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate; forming a plurality of first insulating structures, which are disposed on the substrate in a spaced manner, and the first insulating structures include a first insulating layer and a second insulating layer, wherein the first insulating layer and the second insulating layer of at least one of the first insulating structures include a first gap and a second gap respectively; A plurality of first contact structures are formed and located between adjacent first insulating structures.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: The step of forming the first insulating structure comprises: forming a sacrificial layer having a plurality of through holes on the substrate; Forming a first insulating layer to fill the through hole, wherein a first gap exists in the first insulating layer; Etching back to remove a portion of the first insulating layer to form a recess on the top of the first insulating layer, the bottom of which contacts the first gap; A second insulating layer is formed to fill the recess and extend to cover a portion of the height of the two side walls of the first insulating layer, and a second gap exists in the second insulating layer.

18. The semiconductor device according to claim 17, wherein: The first insulating layer and the second insulating layer of at least one of the first insulating structures define a gap, and a width of the gap in the horizontal direction is greater than a width of the first gap in the first insulating layer in the horizontal direction.

19. The method for manufacturing a semiconductor device according to claim 17, wherein: Before forming the second insulating layer, the method further includes: A third insulating layer is formed on two outer side walls of the first insulating layer.

20. The method for manufacturing a semiconductor device according to claim 19, wherein: The third insulating layer is also located between the first insulating layer and the second insulating layer in the recess of at least one of the first insulating structures, and the third insulating layer and the first insulating layer define a gap, and the gap contacts the first gap.

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