Semiconductor device and method for manufacturing semiconductor device

Abstract

The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device may include: a gate structure including alternately stacked gate lines and insulating layers; a channel structure extending through the gate structure and including a channel layer and a channel pad connected to the channel layer; a dummy gate structure including stacked dummy gate lines; a dummy channel structure extending through the dummy gate structure and including a dummy channel layer and a dummy channel pad connected to the dummy channel layer; an isolation insulating layer disposed between the gate structure and the dummy gate structure; and a dummy pad disposed on the isolation insulating layer between the gate structure and the dummy gate structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an electronic device, and more particularly, to a semiconductor device and a method of manufacturing the semiconductor device. Background Art

[0002] The integration degree of a semiconductor device is mainly determined by the area occupied by a unit memory cell. Recently, as the improvement of the integration degree of a semiconductor device in which a memory cell is formed as a single layer on a substrate has reached a limit, a three-dimensional semiconductor device in which memory cells are stacked on a substrate is being proposed. In addition, in order to improve the operational reliability of the semiconductor device, various structures and manufacturing methods are being developed. Summary of the invention

[0003] According to an embodiment of the present disclosure, a semiconductor device may include: a gate structure including alternately stacked gate lines and insulating layers; a channel structure extending through the gate structure and including a channel layer and a channel pad connected to the channel layer; a dummy gate structure including stacked dummy gate lines; a dummy channel structure extending through the dummy gate structure and including a dummy channel layer and a dummy channel pad connected to the dummy channel layer; an isolation insulating layer disposed between the gate structure and the dummy gate structure; and a dummy pad disposed on the isolation insulating layer between the gate structure and the dummy gate structure.

[0004] According to an embodiment of the present disclosure, a semiconductor device may include: a gate structure including alternately stacked gate lines and insulating layers; a dummy gate structure including stacked dummy gate lines; an isolation insulating structure disposed between the gate structure and the dummy gate structure and including a stacked horizontal portion and a vertical portion extending through the horizontal portion; and a dummy pad disposed on the isolation insulating structure between the gate structure and the dummy gate structure.

[0005] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device may include the following steps: forming a stack including alternately stacked first material layers and second material layers; forming a first opening in the stack; etching the first material layer exposed through the first opening to form a second opening interconnecting the first opening; forming an insulating layer in the first opening and the second opening; etching the insulating layer to form an isolation insulating layer; and forming a dummy pad on the isolation insulating layer.

[0006] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device may include the following steps: forming a stack including a block edge region, a block central region, and a boundary region arranged between the block edge region and the block central region; forming an opening in the stack; forming a channel material layer in the opening; etching a portion of the channel material layer arranged in the boundary region to separate the channel material layer into a dummy channel layer arranged in the block edge region and a channel layer arranged in the block central region; forming an isolation trench in the boundary region; forming an insulating layer in the isolation trench, the channel layer, and the dummy channel layer; forming a third opening by partially etching the insulating layer; and forming a pad in the third opening.

[0007] These and other features and advantages will become apparent from the following drawings and detailed description of example embodiments of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A and Figure 1B is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure.

[0009] FIG. 2A to FIG. 2D is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0010] FIG. 3A to FIG. 9A as well as FIG. 3B to FIG. 9B is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0011] Embodiments of the present disclosure provide a semiconductor device having a stable structure and improved characteristics and a method of manufacturing the semiconductor device.

[0012] The integration degree of a semiconductor device can be increased by stacking memory cells in three dimensions. In addition, a semiconductor device having a stable structure and improved reliability can be provided.

[0013] Hereinafter, embodiments according to the technical spirit of the present disclosure are described with reference to the accompanying drawings.

[0014] Figure 1A and Figure 1B is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure. Figure 1B yes Figure 1A A-A' cross-sectional view.

[0015] Reference Figure 1A and Figure 1B, the semiconductor device may include a gate structure GST, a channel structure CH, a dummy gate structure DGST, a dummy channel structure DCH, an isolation insulating layer 17, a dummy pad 18 and a slit structure SLS. The semiconductor device may be a chip and may include a plurality of planes. Each plane may include a plurality of memory blocks MB. Each memory block MB may include a block central region BCR, a block edge region BER, and a border region BR disposed between the block central region BCR and the block edge region BER. The block central region BCR and the block edge region BER may be adjacent to each other in a first direction I, and the block edge region BER may be disposed closer to the edge of the plane than the block central region BCR. When two features are referred to as being adjacent in a certain direction as the term is used herein, this means that the two features are close to or proximate to each other, but they are not necessarily in direct contact with each other. Thus, for example, the block central region BCR and the block edge region BER are close to each other in the first direction, but they are separated by the border region BR. More specifically, the border region BR may be disposed at the border between the block central region BCR and the block edge region BER. A portion including the border may be defined as a border region BR, and the border region BR may be disposed between the block central region BCR and the block edge region BER.

[0016] The gate structure GST may be disposed in the block central region BCR. The gate structure GST may include alternately stacked gate lines 11G and an insulating layer 12. The gate line 11G may be a word line, a source selection line, a drain selection line, etc. The gate line 11G may include a conductive material such as polysilicon, tungsten, or molybdenum. The insulating layer 12 may insulate the stacked gate lines 11G from each other. An insulating material suitable for the insulating layer 12 may include an oxide or a nitride. However, the insulating layer 12 may also include a void and / or a combination of an insulating material and a void.

[0017] The channel structure CH may extend through the gate structure GST. The channel structure CH may include a channel layer 13 and a channel pad 16 connected to the channel layer 13. The channel layer 13 may include a semiconductor material such as silicon or germanium. The channel pad 16 may be formed in the channel layer 13 and may be in direct contact with the channel layer 13. The channel pad 16 may be used as a pad for connecting the channel layer to a line such as a bit line. The channel pad 16 may include a conductive material and a junction doped with N-type or P-type impurities. In some embodiments, the channel pad 16 may include polysilicon.

[0018] The channel structure CH may further include at least one of a memory layer 14 surrounding the channel layer 13 and an insulating core 15 in the channel layer 13. The memory layer 14 may include a floating gate, polysilicon, a charge trap material, a nitride, a variable resistance material, etc. For reference, some of the channel structures CH passing through the gate structure GST may be dummy channel structures. In some embodiments, among the channel structures CH, the channel structure CH disposed adjacent to the isolation insulating layer 17 may be a dummy channel structure.

[0019] The dummy gate structure DGST may be disposed in the block edge region BER. The dummy gate structure DGST may include stacked dummy gate lines 11D. The dummy gate lines 11D may be disposed at a height corresponding to the gate lines 11G. The insulating layer 12 may extend between the dummy gate lines 11D, and the dummy gate lines 11D and the insulating layer 12 may be alternately stacked. The dummy gate lines 11D may include a conductive material such as polysilicon, tungsten, or molybdenum.

[0020] The dummy channel structure DCH may extend through the dummy gate structure DGST. The dummy channel structure DCH may have a structure similar to the channel structure CH. The dummy channel structure DCH may include a dummy channel layer 13D and a dummy channel pad 16D connected to the dummy channel layer 13D. The dummy channel pad 16D may be formed in the dummy channel layer 13D and may be in direct contact with the dummy channel layer 13D. The dummy channel pad 16D may include a conductive material and a junction doped with N-type or P-type impurities. In some embodiments, the dummy channel pad 16D may include polysilicon. The dummy channel structure DCH may also include at least one of a dummy memory layer 14D and a dummy insulating core 15D. The dummy memory layer 14D may include a floating gate, polysilicon, a charge trap material, a nitride, a variable resistance material, etc.

[0021] The isolation insulating layer 17 may be disposed in the boundary region BR. The isolation insulating layer 17 may be disposed between the gate structure GST and the dummy gate structure DGST adjacent to each other in the first direction I. The isolation insulating layer 17 may electrically isolate the gate structure GST from the dummy gate structure DGST. The isolation insulating layer 17 may include an insulating material such as oxide or nitride.

[0022] The isolation insulating layer 17 may include a horizontal portion 17H and a vertical portion 17V. The horizontal portion 17H may be stacked between the gate structure GST and the dummy gate structure DGST. The horizontal portion 17H may be provided to correspond to the gate line 11G and the dummy gate line 11D, and may be provided between the gate line 11G and the dummy gate line 11D. The thickness Td of the horizontal portion 17H may be substantially the same as the thickness T1 of the gate line 11G and the thickness T2 of the dummy gate line 11D. The insulating layer 12 may extend between the horizontal portions 17H, and the horizontal portions 17H and the insulating layer 12 may be alternately stacked.

[0023] The vertical portion 17V may extend through the horizontal portion 17H. The vertical portion 17V may have substantially the same shape as the channel structure CH and the dummy channel structure DCH. At the same height, the width of the vertical portion 17V may be substantially the same as the width of the channel structure CH and the width of the dummy channel structure DCH.

[0024] The dummy pad 18 may be disposed on the isolation insulating layer 17 between the gate structure GST and the dummy gate structure DGST. The dummy pad 18 may be formed together when the channel pad 16 and / or the dummy channel pad 16D are formed. The dummy pad 18 may be disposed between the channel pad 16 and the dummy channel pad 16D, and may be disposed at substantially the same height as the channel pad 16 and the dummy channel pad 16D. In some embodiments, the upper surface of the dummy pad 18 may be disposed at substantially the same height as the upper surface of the channel pad 16. The upper surface of the dummy pad 18 may be disposed at substantially the same height as the upper surface of the dummy channel pad 16D.

[0025] Compared to the channel pad 16 and the dummy channel pad 16D, the dummy pad 18 may have a larger size. The width Wd of the dummy pad 18 may be greater than the width W1 of the channel pad 16 and the width W2 of the dummy channel pad 16D. The height Hd of the dummy pad 18 may be greater than the height H1 of the channel pad 16 and the height H2 of the dummy channel pad 16D.

[0026] The dummy pad 18 may include a groove 18G on a sidewall. The channel structure CH and the dummy channel structure DCH disposed adjacent to the dummy pad 18 may protrude toward the dummy pad 18, and the channel structure CH or the dummy channel structure DCH may be disposed in the groove 18G.

[0027] The dummy pad 18 may include the same material as the channel pad 16 and the dummy channel pad 16D. For example, in some embodiments, the dummy pad 18, the channel pad 16, and the dummy channel pad 16D may include polysilicon.

[0028] The slit structure SLS may be disposed between adjacent memory blocks MB in the second direction II. Here, the second direction II may be a direction intersecting the first direction I, for example, the second direction II may be orthogonal to the first direction I. The slit structure SLS may be disposed between the gate structures GST, and may extend between the isolation insulating structures and between the dummy gate structures DGST. The slit structure SLS may extend along the first direction I. The slit structure SLS may extend from the block central region BCR to the boundary region BR and the block edge region BER. Adjacent gate structures GST in the second direction II may be insulated from each other by the slit structure SLS. The slit structure SLS may include at least one of an insulating material, a semiconductor material, and a conductive material.

[0029] According to the above structure, the isolation insulating layer 17 and the dummy pad 18 may be disposed between the gate structure GST and the dummy gate structure DGST adjacent to each other in the first direction I. Therefore, the gate structure GST and the dummy gate structure DGST may be separated from each other by the isolation insulating layer 17 and the dummy pad 18 .

[0030] The pattern density of the dummy channel structure DCH set in the block edge region BER and the pattern density of the channel structure CH set in the block central region CER may be substantially the same or similar to each other. Therefore, during the manufacturing process, the bending of the stack, slits, etc. in the area with relatively low pattern density can be reduced. In order to compensate for the pattern density difference, the shape of the slit structure SLS may not be changed, and the slit structure SLS may have a uniform width. In addition, the occurrence of wafer warpage can be reduced by positioning the gate structure GST in the block central region BCR and positioning the dummy gate structure DGST in the block edge region BER.

[0031] FIG. 2A to FIG. 2D 2 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Hereinafter, descriptions overlapping with the above contents may be omitted.

[0032] Reference Figure 2A , a stacked body ST may be formed by alternately stacking first material layers 21 and second material layers 22. The first material layer 21 may be used to form a gate line, and the second material layer 22 may be used to insulate the stacked gate lines from each other. The first material layer 21 may include a material having a high etching selectivity relative to the second material layer 22. The first material layer 21 may include a sacrificial material such as a nitride, or may include a conductive material such as polysilicon, tungsten, or molybdenum. The second material layer 22 may include an insulating material such as an oxide or a nitride.

[0033] Reference Figure 2B, at least one first opening OP1 may be formed in the stack body ST. The first opening OP1 may extend vertically through the stack body ST. Subsequently, a second opening OP2 (also referred to as a lateral opening, a lateral extension opening, or a horizontal opening) may be formed. The second opening OP2 may be formed by etching the first material layer 21 exposed by the first opening OP1. Adjacent first openings OP1 may be connected to each other through the second opening OP2.

[0034] Reference Figure 2C , an insulating layer 23 may be formed. In some embodiments, the insulating layer 23 may be formed in the first opening OP1 and the second opening OP2. The insulating layer 23 may include an insulating material such as an oxide, a nitride, or the like. In a variation of this embodiment, a void may be formed in a region shown as being covered by the insulating layer 23.

[0035] Reference Figure 2D , the isolation insulating layer 23A may be formed by partially etching the insulating layer 23. When etching the insulating layer 23, the second material layer 22 may be partially etched. The third opening OP3 may be formed in the portion where the insulating layer is etched. The isolation insulating layer 23A may include a horizontal portion 23H and a vertical portion 23V. The vertical portion 23V may be disposed in the first opening OP1, and the horizontal portion 23H may be disposed in the second opening OP2.

[0036] Subsequently, a dummy pad 24 may be formed in the third opening OP3. The dummy pad 24 may be disposed on the isolation insulating layer 23A. In some embodiments, the dummy pad 24 may include polysilicon. For example, the dummy pad 24 may be a doped polysilicon layer including N-type or P-type impurities.

[0037] Subsequently, the first material layer 21 may be replaced with a third material layer. In some embodiments, after removing the first material layer 21, the conductive layer may be formed as a third material layer. Thus, a gate structure GST including alternately stacked gate lines 21G and second material layers 22 may be formed. At this time, the gate structure GST may be formed on one side of the isolation insulating layer 23A, and a dummy gate structure DGST may be formed on the other side. The dummy gate structure DGST may include alternately stacked dummy gate lines 21D and second material layers 22.

[0038] For reference, when the first material layer 21 includes a conductive material, the replacement process may be omitted. In this case, the first material layer 21 may be used as the gate line 21G and the dummy gate line 21D, and the stacked body ST may be used as the gate structure GST.

[0039] According to the above-mentioned manufacturing method, before replacing the first material layer 21 with the third material layer, the isolation insulating layer 23A and the dummy pad 24 may be formed in the stacked body ST. Therefore, the replacement process may be performed in a state where the stacked body ST is separated into one side and the other side of the isolation insulating layer 23A, and the gate structure GST and the dummy gate structure DGST may be naturally separated. The gate structure GST and the dummy gate structure DGST may be formed in a form separated from each other, and a separation process for separating the gate structure GST and the dummy gate structure DGST may be omitted.

[0040] FIG. 3A to FIG. 9A as well as FIG. 3B to FIG. 9B 1 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Each numbered A figure is a plan view, and each numbered B figure is a BB' cross-sectional view of Figure A. In the following, descriptions repeated with the above content may be omitted.

[0041] Reference Figure 3A and Figure 3B , a first sub-stack body ST1 may be formed. The first sub-stack body ST1 may include first material layers 31 and second material layers 32 that are alternately stacked. The first material layer 31 may be used to form a gate line, and the second material layer 32 may be used to insulate the stacked gate lines from each other. The first material layer 31 may include a material having a high etching selectivity relative to the second material layer 32. The first material layer 31 may include a sacrificial material such as a nitride or include a conductive material such as polysilicon or a metal. The second material layer 32 may include an insulating material such as an oxide or a nitride.

[0042] The first sub-stack body ST1 may include a block central region BCR, a block edge region BER, and a boundary region BR. The boundary region BR may be disposed between the block central region BCR and the block edge region BER.

[0043] Subsequently, the first sub-opening OPA may be formed in the first sub-stack body ST1. The first sub-opening OPA may extend through the first sub-stack body ST1. The first sub-opening OPA may be arranged in a first direction I and a second direction II intersecting the first direction I. The first sub-opening OPA may be disposed in the block central region BCR, the block edge region BER, and the boundary region BR. The first sub-opening OPA may not be formed in the slit region SLR where the slit is to be formed in a subsequent process.

[0044] Subsequently, a sacrificial layer 33 may be formed inside the first sub-opening OPA to fill the first sub-opening OPA to the top of the first sub-opening OPA. The sacrificial layer 33 may include a material having a high etching selectivity with respect to the first material layer 31 and the second material layer 32.

[0045] Reference Figure 4A and Figure 4B , a second sub-stack ST2 including alternately stacked first material layers 31 and second material layers 32 may be formed on the first sub-stack ST1. The second sub-stack ST2 may include a block central region BCR, a block edge region BER, and a boundary region BR. Thus, a stack ST including the first sub-stack ST1 and the second sub-stack ST2 may be formed.

[0046] Subsequently, a second sub-opening OPB may be formed in the second sub-stack body ST2. The second sub-opening OPB may be connected to the first sub-opening OPA. The second sub-opening OPB may not be formed in the slit region SLR. Each of the first sub-openings OPA may be connected to a corresponding one of the second sub-openings OPB to form a single continuous opening OP. The opening OP may provide a channel hole for forming a channel structure, or may provide a dummy channel hole for forming a dummy channel structure. Each opening OP may provide a portion of an isolation trench for forming an isolation insulating layer.

[0047] Subsequently, a memory material layer 34 and a channel material layer 35 may be formed. More specifically, the memory material layer 34 may be first formed along the inner surface of the opening OP, and then, after the memory material layer 34 is formed, the channel material layer 35 may be formed on the memory material layer 34. The memory material layer 34 may be conformally formed to form a layer having a substantially constant thickness on the inner surface of the opening OP and also on the top surface of the second material layer 32 at the top. The channel material layer 35 may be conformally formed on the memory material layer 34 to form a layer having a substantially constant thickness. The memory material layer 34 and the channel material layer 35 may be formed with a thickness that the memory material layer 34 and the channel material layer 35 do not completely fill the opening OP. The memory material layer 34 may be a multilayer structure including at least one of a barrier layer 34A, a data storage layer 34B, and a tunneling layer 34C. In the illustrated embodiment, the memory material layer 34 includes a barrier layer 34A, a data storage layer 34B, and a tunneling layer 34C. The barrier layer 34A may include a high-k material. The data storage layer 34B may include a floating gate, polysilicon, a charge trap material, a nitride, a variable resistance material, etc. The tunnel layer 34C may include an oxide. The channel material layer 35 may include a semiconductor material such as, for example, polysilicon.

[0048] Reference Figure 5A and Figure 5B, a mask pattern 36 may be formed on the stacked body ST. The mask pattern 36 may cover the block central region BCR and the block edge region BER, and may expose the boundary region BR. The mask pattern 36 may include a photoresist. The mask pattern 36 may be formed to fill the opening OP of the block central region BCR and the block edge region BER.

[0049] Subsequently, the channel material layer 35 and the memory material layer 34 may be etched using the mask pattern 36 as an etching barrier. A portion of the memory material layer 34 may be etched. In some embodiments, the data storage layer 34B may be exposed by etching the channel material layer 35 and the tunneling layer 34C. By etching a portion of the channel material layer 35 formed in the boundary region BR, the channel material layer 35 may be separated into a channel layer 35R disposed in the block central region BCR and a dummy channel layer 35D disposed in the block edge region BER. By etching a portion of the tunneling layer 34C formed in the boundary region BR, the tunneling layer 34C may be separated into a tunneling layer 34CR disposed in the block central region BCR and a dummy tunneling layer 34CD disposed in the block edge region BER.

[0050] Subsequently, the mask pattern 36 may be removed. In some embodiments, a strip process may be used to remove the photoresist, and a cleaning process may be performed.

[0051] Reference Fig. 6A and Figure 6B , the data storage layer 34B of the boundary region BR may be etched to expose the barrier layer 34A. By etching the portion of the data storage layer 34B formed in the boundary region BR, the data storage layer 34B may be separated into the data storage layer 34BR disposed in the block central region BCR and the dummy data storage layer 34BD disposed in the block edge region BER. Subsequently, the barrier layer 34A of the boundary region BR may be etched to expose the first material layer 31 and the second material layer 32. By etching the portion of the barrier layer 34A formed in the boundary region BR, the barrier layer 34A may be separated into the barrier layer 34AR disposed in the block central region BCR and the dummy barrier layer 34AD disposed in the block edge region BER.

[0052] Thus, the portion of the memory material layer 34 disposed in the boundary region BR may be selectively etched. The portion of the memory material layer 34 disposed in the block edge region BER and the block central region BCR is covered by the channel layer 35R and the dummy channel layer 35D, and thus the portion of the memory material layer 34 disposed in the block edge region BER and the block central region BCR may not be etched. Therefore, the memory material layer 34 may be separated into the memory layer 34R disposed in the block central region BCR and the dummy memory layer 34D disposed in the block edge region BER.

[0053] As the memory material layer 34 is etched, the first opening OP1 may be formed in the boundary region BR. Among the openings OP, the opening OP disposed in the boundary region BR may be reopened to form the first opening OP1. The first opening OP1 may be disposed between the channel layer 35R and the dummy channel layer 35D. The first material layer 31 and the second material layer 32 may be exposed through the first opening OP1.

[0054] Subsequently, a second opening OP2 (also referred to as a lateral opening or a horizontal opening) can be formed by etching the first material layer 31 exposed by the first opening OP1. The first material layer 31 can be selectively etched to form the second opening OP2. Adjacent first openings OP1 can be connected to each other through the second opening OP2. Thus, an isolation trench IST can be formed in the boundary region BR. The first material layer 31 of the block edge region BER and the first material layer 31 of the block central region BCR can be separated from each other by the isolation trench IST.

[0055] Reference Fig. 7A and Figure 7B , an insulating layer 37 may be formed. The insulating layer 37 may be formed in the isolation trench IST. The insulating layer 37 may be formed in the channel layer 35R of the block central region BCR and the dummy channel layer 35D of the block edge region BER. The insulating layer 37 may include an insulating material such as oxide, nitride, or the like. In some embodiments, the insulating layer 37 may include a void.

[0056] Reference Fig. 8A and Figure 8B , an isolation insulating layer 37A may be formed in the isolation trench IST. The isolation insulating layer 37A may be formed by etching the insulating layer 37. In some embodiments, the insulating layer 37 may be etched in a dry etching process.

[0057] The insulating core 37R may be formed by etching a portion of the insulating layer 37 formed in the block central region BCR. The insulating core 37R may be disposed in the channel layer 35R. The dummy insulating core 37D may be formed by etching the insulating layer 37 formed in the block edge region BER. The dummy insulating core 37D may be disposed in the dummy channel layer 35D. When the isolation insulating layer 37A is formed, at least one of the insulating core 37R and the dummy insulating core 37D may be formed together.

[0058] The second material layer 32 of the boundary region BR may be etched. In the process of etching the insulating layer 37, the second material layer 32 of the boundary region BR may be exposed, and the second material layer 32 may be etched together. When etching the insulating layer 37, since the second material layer 32 of the block edge region BER and the block central region BCR is not exposed, the second material layer 32 of the boundary region BR may be selectively etched. The third opening OP3A disposed in the boundary region BR may be formed by etching the insulating layer 37 and the second material layer 32 of the boundary region BR. The third opening OP3R disposed in the block central region BCR may be formed by partially etching the insulating layer 37 of the block central region BCR. The third opening OP3D disposed in the block edge region BER may be formed by partially etching the insulating layer 37 of the block edge region BER. The third opening OP3R and the third opening OP3D may be formed when the third opening OP3A is formed.

[0059] The third openings OP3A, OP3R and OP3D can be used to form pads in subsequent processes. The third openings OP3A, OP3R and OP3D can be set higher than the upper surface of the first material layer 31 on the uppermost side. The third openings OP3A, OP3R and OP3D can have the same thickness or different thicknesses. In some embodiments, the third opening OP3A can have a wider width than the third opening OP3R and the third opening OP3D, and the third opening OP3A can be formed to have a depth greater than the third opening OP3R and the third opening OP3D. The depth Dd can be greater than the depth D1 and the depth D2.

[0060] Reference Fig. 9A and Fig. 9B , the dummy pad 38 may be formed on the isolation insulating layer 37A. In some embodiments, the dummy pad 38 may be formed by forming a conductive layer in the third opening OP3A and planarizing the conductive layer until the upper surface of the stack ST is exposed. Thus, the dummy pad 38 may be formed in the third opening OP3A. The dummy pad 38 may include polysilicon. During planarization, the conductive layer, the channel layer 35R, the dummy channel layer 35D, the memory layer 34R, and the dummy memory layer 34D may be planarized together.

[0061] Channel pad 38R and dummy channel pad 38D may be formed when forming dummy pad 38. Channel pad 38R may be connected to channel layer 35R and may be disposed on insulating core 37R. Dummy channel pad 38D may be connected to dummy channel layer 35D and may be disposed on dummy insulating core 37D.

[0062] Through the above operations, a channel structure CH disposed in the block central region BCR may be formed. The channel structure CH may include a channel layer 35R, an insulating core 37R, and a channel pad 38R. A dummy channel structure DCH may be formed in the block edge region BER when the channel structure CH is formed. The dummy channel structure DCH may include a dummy channel layer 35D, a dummy insulating core 37D, and a dummy channel pad 38D. An isolation insulating layer 37A and a dummy pad 38 may be formed in the boundary region BR when the channel structure CH is formed.

[0063] Subsequently, the first material layer 31 may be replaced with a third material layer. In some embodiments, a slit SL extending through the stacked body ST in the first direction I may be formed. Subsequently, the first material layer 31 may be etched through the slit SL, and then a conductive layer may be formed. Thus, a gate structure GST including alternately stacked gate lines 31G and second material layers 32 in the block central region BCR may be formed. A dummy gate structure DGST may be formed in the block edge region BER. The dummy gate structure DGST may include alternately stacked dummy gate lines 31D and second material layers 32.

[0064] When the first material layer 31 is etched through the slit SL, the first material layer 31 of the boundary region BR may have been removed and the isolation insulating layer 37A may be formed. Therefore, the first material layer 31 of the block central region BCR and the block edge region BER may be etched, and the gate line 31G of the block central region BCR and the dummy gate line 31D of the block edge region BER may be naturally separated by the isolation insulating layer 37A. A process for separating the gate line 31G and the dummy gate line 31D may not be additionally performed.

[0065] Subsequently, a slit structure SLS may be formed in the slit SL. The slit structure SLS may include at least one of an insulating material, a semiconductor material, and a conductive material. In some embodiments, the slit structure SLS may be a gap filling layer including an insulating material or a semiconductor material. The slit structure SLS may include a conductive contact plug and an insulating spacer.

[0066] According to the above-described manufacturing method, the isolation insulating layer 17 and the dummy pad 18 may be formed using the process of forming the channel structure CH. Therefore, the cost associated with the additional process of forming the isolation insulating layer 17 and the dummy pad 18 may be reduced.

[0067] Before replacing the first material layer 31 with the third material layer, an isolation insulating layer 37A and a dummy pad 38 may be formed in the boundary region BR. Therefore, the block central region BCR and the block edge region BER may be separated by the isolation insulating layer 37A and the dummy pad 38, and the gate structure GST and the dummy gate structure DGST may be separated from each other.

[0068] Although the embodiments according to the technical spirit of the present disclosure have been described with reference to the accompanying drawings, this is only used to describe the embodiments according to the concept of the present disclosure, and the present disclosure is not limited to the above-mentioned embodiments. Within the scope of the technical spirit of the present disclosure, technicians in the field to which the present disclosure belongs can make various forms of replacement, modification and change to the embodiments, and these also belong to the scope of the present disclosure. In addition, these embodiments can be combined to form other embodiments.

[0069] CROSS-REFERENCE TO RELATED APPLICATIONS

[0070] This application claims priority to Korean Patent Application No. 10-2023-0131624, filed on October 4, 2023, which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: A gate structure, the gate structure comprising alternately stacked gate lines and insulating layers; a channel structure extending through the gate structure, the channel structure comprising a channel layer and a channel pad connected to the channel layer; a dummy gate structure, the dummy gate structure comprising stacked dummy gate lines; a dummy channel structure extending through the dummy gate structure, the dummy channel structure comprising a dummy channel layer and a dummy channel pad connected to the dummy channel layer; an isolation insulating layer, wherein the isolation insulating layer is disposed between the gate structure and the dummy gate structure; as well as A dummy pad is provided on the isolation insulating layer between the gate structure and the dummy gate structure.

2. The semiconductor device according to claim 1, wherein The isolation insulating layer includes stacked horizontal portions and vertical portions extending through the horizontal portions.

3. The semiconductor device according to claim 2, wherein: The horizontal portion is disposed to correspond to the gate line and the dummy gate line.

4. The semiconductor device according to claim 2, wherein: The insulating layer extends between the horizontal portions and between the dummy gate lines.

5. The semiconductor device according to claim 1, wherein The channel pad, the dummy channel pad, and the dummy pad are disposed at substantially the same height.

6. The semiconductor device according to claim 1, wherein The height of the dummy pad is greater than the height of the channel pad and the height of the dummy channel pad, and The width of the dummy pad is greater than the width of the channel pad and the width of the dummy channel pad.

7. The semiconductor device according to claim 1, wherein In a memory block, the dummy gate structure is disposed in a block edge region, the gate structure is disposed in a block central region, the isolation insulating structure is disposed in a boundary region, and the boundary region is disposed between the block edge region and the block central region.

8. The semiconductor device according to claim 1, wherein The dummy pad includes polysilicon.

9. A semiconductor device, comprising: A gate structure, the gate structure comprising alternately stacked gate lines and insulating layers; a dummy gate structure, the dummy gate structure comprising stacked dummy gate lines; an isolation insulating structure, the isolation insulating structure being disposed between the gate structure and the dummy gate structure, the isolation insulating structure comprising a stacked horizontal portion and a vertical portion extending through the horizontal portion; as well as A dummy pad is provided on the isolation insulating structure between the gate structure and the dummy gate structure.

10. The semiconductor device according to claim 9, wherein The horizontal portion is disposed to correspond to the gate line and the dummy gate line.

11. The semiconductor device according to claim 9, wherein The insulating layer extends between the horizontal portions and between the dummy gate lines.

12. The semiconductor device according to claim 9, further comprising: a channel structure extending through the gate structure, the channel structure comprising a channel layer and a channel pad connected to the channel layer; as well as A dummy channel structure extends through the dummy gate structure, the dummy channel structure comprising a dummy channel layer and a dummy channel pad connected to the dummy channel layer.

13. The semiconductor device according to claim 12, wherein: The channel pad, the dummy channel pad, and the dummy pad are disposed at substantially the same height.

14. The semiconductor device according to claim 12, wherein: The height of the dummy pad is greater than the height of the channel pad and the height of the dummy channel pad, and The width of the dummy pad is greater than the width of the channel pad and the width of the dummy channel pad.

15. The semiconductor device according to claim 9, wherein: In a memory block, the dummy gate structure is disposed in a block edge region, the gate structure is disposed in a block central region, the isolation insulating structure is disposed in a boundary region, and the boundary region is disposed between the block edge region and the block central region.

16. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a stack including alternately stacked first material layers and second material layers; forming a first opening in the stack; etching the first material layer exposed through the first openings to form second openings interconnecting the first openings; forming an insulating layer in the first opening and the second opening; etching the insulating layer to form an isolation insulating layer; as well as A dummy pad is formed on the isolation insulating layer.

17. The method according to claim 16, wherein: The step of forming the first opening comprises the following steps: forming openings in a block central region, a block edge region, and a border region of the stack; forming a channel material layer in the opening; and The first opening is formed by removing a channel material layer formed in the boundary region.

18. The method according to claim 17, wherein: The step of forming the first opening includes the step of separating the channel material layer into a channel layer disposed in the block central region and a dummy channel layer disposed in the block edge region.

19. The method according to claim 18, wherein: The first opening is disposed between the channel layer and the dummy channel layer.

20. The method according to claim 18, wherein: An insulating core disposed in the channel layer and a dummy insulating core disposed in the dummy channel layer are formed when the isolation insulating layer is formed.

21. The method according to claim 18, wherein: When forming the dummy pad, a channel pad connected to the channel layer and a dummy channel pad connected to the dummy channel layer are formed.

22. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a stacked body including a block edge region, a block central region, and a boundary region disposed between the block edge region and the block central region; forming an opening in the stack; forming a channel material layer in the opening; etching a portion of the channel material layer disposed in the boundary region to separate the channel material layer into a dummy channel layer disposed in the block edge region and a channel layer disposed in the block central region; forming an isolation trench in the boundary region; forming an insulating layer in the isolation trench, the channel layer, and the dummy channel layer; forming a third opening by partially etching the insulating layer; as well as A pad is formed in the third opening.

23. The method according to claim 22, further comprising the steps of: forming a memory material layer in the opening; forming a mask pattern exposing the boundary region on the channel material layer; as well as The channel material layer and the memory material layer are etched using the mask pattern as an etch barrier.

24. The method according to claim 23, wherein: The step of etching the channel material layer and the memory material layer comprises the following steps: etching the channel material layer using the mask pattern as an etching barrier; etching a tunneling layer of the memory material layer using the mask pattern as an etch barrier; removing the mask pattern; etching the data storage layer of the memory material layer; and The barrier layer of memory material is etched.

25. The method according to claim 22, wherein: The step of forming the isolation trench comprises the following steps: forming a first opening by etching a portion of the channel layer disposed in the boundary region; and The second material layer among the first material layer and the second material layer included in the stacked body is selectively etched through the first opening.

26. The method of claim 22, wherein: The step of forming the third opening includes the step of forming an insulating core in the channel layer by etching a portion of the insulating layer formed in the block central region.

27. The method of claim 22, wherein: The step of forming the third opening includes the step of forming a dummy insulating core in the dummy channel layer by etching a portion of the insulating layer formed in the block edge region.

28. The method of claim 22, wherein: The step of forming the third opening includes the step of forming an isolation insulating layer in the isolation trench by etching a portion of the insulating layer formed in the boundary region.

29. The method according to claim 28, wherein: The step of forming the pad includes the following steps: forming a dummy pad disposed on the isolation insulating layer.

30. The method of claim 29, wherein: The step of forming the pad further comprises the following steps: forming a channel pad connected to the channel layer; and A dummy channel pad connected to the dummy channel layer is formed.

31. The method according to claim 30, wherein: The channel pad and the dummy channel pad are formed when the dummy pad is formed.

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